Cascaded Programming Circuits using AT17(A) Configurators with Atmel, Xilinx® and Altera® FPGAs Atmel AT17A (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable Gate Arrays (FPGAs) or Field Programmable System Level Integrated Circuits (FPSLIC™) devices. This application note provides circuits showing how to perform In-System Programming (ISP) on two cascaded AT17(A) devices, as well as how to use these devices to configure Atmel, Xilinx and Altera FPGAs. The A2 input of cascaded configurators must be used as an address pin (set to logic level “0” for one configurator and logic level “1” for the other). Each configurator responds only to messages from the programming interface bearing its unique address. AT17(A) Series FPGA Configuration Memory Application Note The A2 pin of the AT17LVXXX and AT17LVXXXA series configurator has internal weak pull-down circuitry. However, the A2 pin of the AT17FXXX an AT17FXXXA series configurator has internal weak pull-up resistor. This default setting of the A2 pin requires the appropriate A2 bit level setting in the message of the programming software. To enter programming mode, the SER_EN pin has to be set to logic Low. For in-system programming, this is accomplished by connecting the 10-pin ISP connector to the ISP cable. Since pin 10 of the ISP cable is connected to GND, SER_EN is grounded automatically. For drop-in/stand-alone programming, the SER_EN pin is set to logic Low by the programmer. In configuration mode, the SER_EN pin has to be set to logic High. For In-system programming, this can be achieved by releasing the ISP cable to allow the external pullup resistor to pull the SER_EN pin to VCC (High). For stand-alone and drop-in programming, the SER_EN pin can be directly connected to VCC. 1. AT17(A) = AT17/AT17A AT17 = AT17LV/FXXX AT17A = AT17LV/FXXXA AT17NXXX series configurators should not be used in the cascaded circuits of this document. Rev. 3034C–CNFG–05/2004 1 The In-System Programming (ISP) circuit diagrams are shown in Figures 1 through 4. Atmel ATDH2200E or ATDH2225 ISP download cable is recommended to use for the ISP circuit. Refer to the ATDH2200E or ATDH2225 user guides, available on the Atmel web site, for the ISP programming procedure. Figure 1. ISP of AT17LVXXXA Series Devices for Altera FPGA Applications, Internal Oscillator and Cascaded Arrangement VCC VCC 1 kΩ VCC VCC VCC APEX II, EP20K, EP1K, EPF10K, EPF6K 1 kΩ nCONFIG 22 µF GND nCE MSEL0 MSEL1 (3) DATA0 DCLK CONF_DONE nSTATUS 1 kΩ 1 kΩ 1 kΩ DATA 1 SCLK 3 2 5 6 7 8 9 10 4 VCC GND AT17LVXXXA Series Device 1 SER_EN (4) DATA SER_EN DCLK nCS nCASC (A2)(5) RESET/OE(1) VCC GND AT17LVXXXA Series Device 2 4.7 kΩ DATA SER_EN DCLK nCS nCASC (A2)(5) RESET/OE(1) READY(2) Notes: 2 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by ISP programmer. 2. Use of the READY pin is optional. 3. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used. 4. The internal oscillator of the second cascaded configurator must be disabled by the programmer. 5. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to low for ISP access to Series Device 1, and set to high for Series Device 2. Cascaded Circuits for Atmel, Altera and Xilinx FPGAs 3034C–CNFG–05/2004 Cascaded Circuits for Atmel, Altera and Xilinx FPGAs Figure 2. ISP of AT17FXXXA Series Devices for Altera FPGA Applications, Internal Oscillator and Cascaded Arrangement VCC VCC 1 kΩ VCC VCC VCC APEX II, EP20K, EP1K, EPF10K, EPF6K 1 kΩ nCONFIG 22 µF GND nCE MSEL0 MSEL1 1 kΩ (2) DATA0 DCLK CONF_DONE nSTATUS GND 1 kΩ 1 kΩ DATA 1 SCLK 3 2 5 6 7 8 9 10 4 VCC GND AT17FXXXA Series Device 1 SER_EN (4) DATA SER_EN DCLK nCS nCASC (A2)(3) RESET/OE AT17FXXXA Series Device 2 DATA SER_EN DCLK nCS nCASC (A2)(3) (1) RESET/OE READY 4.7 kΩ Note: 1. Use of the READY pin is optional. 2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used. 3. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to high for ISP access to Series Device 1, and set to low for Series Device 2. 3 3034C–CNFG–05/2004 Figure 3. ISP of AT17LVXXX Series for Xilinx/Lattice® FPGA Applications, Cascaded Arrangement VCC VCC 4.7 kΩ 4.7 kΩ DATA 1 SCLK 3 2 5 6 7 8 9 10 4 VCC VCC GND 4.7 kΩ ORCA, VIRTEX-II, VIRTEX-E, VIRTEX, SPARTAN, SPARTAN II, XC5000, XC4000, XC3000 PROGRAM PROGRAM M2 M1 M0 (4) DIN CCLK DONE(3) INIT AT17LVXXX Series Device 1 VCC AT17LVXXX Series Device 2 GND Notes: 4 SER_EN SER_EN DATA CLK CEO(A2)(5) CE (1) RESET/OE 4.7 kΩ DATA SER_EN CLK CE CEO(A2)(5) (1) RESET/OE READY(2) 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by ISP programmer. 2. Use of the READY pin is optional. 3. A 330Ω external pull-up resistor on the DONE pin is required for Virtex® and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin. 4. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA® FPGAs can use PRGM instead of the PROGRAM pin. 5. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to low for ISP access to Series Device 1, and set to high for Series Device 2. Cascaded Circuits for Atmel, Altera and Xilinx FPGAs 3034C–CNFG–05/2004 Cascaded Circuits for Atmel, Altera and Xilinx FPGAs Figure 4. ISP of AT17FXXX Series for Xilinx/Lattice® FPGA Applications, Cascaded Arrangement VCC VCC 4.7 kΩ 4.7 kΩ DATA 1 SCLK 3 2 5 6 7 8 9 10 4 VCC VCC GND 4.7 kΩ ORCA, VIRTEX-II, VIRTEX-E, VIRTEX, SPARTAN, SPARTAN II, XC5000, XC4000, XC3000 (3) PROGRAM PROGRAM M2 M1 M0 DIN CCLK (2) DONE INIT AT17FXXX Series Device 1 SER_EN DATA CLK CEO(A2)(4) CE (1) RESET/OE SER_EN AT17FXXX Series Device 2 GND DATA SER_EN CLK CE CEO(A2)(4) RESET/OE READY(1) 4.7 kΩ Notes: 1. Use of the READY pin is optional. 2. A 330Ω external pull-up resistor on the DONE pin is required for Virtex® and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin. 3. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA® FPGAs can use PRGM instead of the PROGRAM pin. 4. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to high for ISP access to Series Device 1, and set to low for Series Device 2. 5 3034C–CNFG–05/2004 The Drop-in/stand-alone programming circuit diagrams are displayed in Figure 5 and Figure 6. Atmel ATDH2200E programming kit and many other third-party programmers can be used to program the configuration bitstream to the EEPROMs, before the parts are placed into the drop-in/stand-alone programming circuits. Figure 5. Drop-In Replacement of AT17A Devices for Altera FPGAs, Internal Oscillator and Cascaded Arrangement VCC VCC VCC VCC 1 kΩ 1 kΩ (2) APEX II, EP20K, EP1K, EPF10K, EPF6K nCONFIG(2) 0.1 µF GND nCE MSEL0 MSEL1 DATA0 DCLK(3) CONF_DONE nSTATUS 1 kΩ AT17A Series Device 1 DATA SER_EN DCLK nCS nCASC (A2) (1) RESET/OE VCC GND AT17A Series Device 2 DATA SER_EN DCLK nCS RESET/OE(1) READY Notes: 6 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by programmer if AT17LVXXXA series configurators are used. 2. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used. 3. If AT17LVXXXA series configurators are used, the internal oscillator of the DCLK pin of the second configurator must be disabled to avoid clock contention. Cascaded Circuits for Atmel, Altera and Xilinx FPGAs 3034C–CNFG–05/2004 Cascaded Circuits for Atmel, Altera and Xilinx FPGAs Figure 6. Drop-In Replacement of AT17 Series Devices for Xilinx and Lattice Applications, Cascaded Arrangement VCC ORCA, VIRTEX-II, VIRTEX-E, VIRTEX, SPARTAN, SPARTAN II, XC5000, XC4000, XC3000 PROGRAM(4) PROGRAM M2 M1 M0 GND Notes: DIN CCLK (2) DONE INIT 4.7 kΩ AT17 Series Device 1 VCC SER_EN DATA CLK CEO/A2 CE (1) RESET/OE AT17 Series Device 2 SER_EN DATA CLK CE (3) (1) RESET/OE READY 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by programmer if AT17LVXXX series configurators are used. 2. A 330Ω external pull-up resistor on the DONE pin is required for Virtex and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin. 3. Use of the READY pin is optional. 4. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA FPGAs can use PRGM instead of the PROGRAM pin. 7 3034C–CNFG–05/2004 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof, are the registered trademarks and FPSLIC ™ is the trademark of Atmel Corporation or its subsidiaries. Xilinx ®, Spartan ® and Virtex® are the registered trademarks of Xilinx, Inc.; Altera ® is the registered trademark, and APEX ™ and APEX ™ II are the trademarks of Altera Corporation; Lattice® and ORCA ® are the registered trademarks of Lattice Semiconductor Corporation. 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