View detail for Drop-In/Stand-alone Programming Circuits for AT17A Series Configurators with Altera® FPGAs

Drop-In/Stand-alone Programming Circuits for
AT17A Series Configurators with Altera® FPGAs
Atmel AT17A (1) series configurators use a simple serial-access procedure to configure
one or more Field Programmable Gate Arrays (FPGAs) or programmable logic
devices.
This application note provides the drop-in/stand-alone programming circuits for AT17A
series devices Altera FPGAs. For Drop-In/Stand-alone Programming, the configurator
is programmed before dropping into the circuit that will configure the FPGA, see Figure 1.
Application
Note
Figure 1. ATDH2200E Stand-alone Device Programming
Parallel
Cable
DB-25M
Parallel
Port
PC
AT17A Series
FPGA
Configuration
Memory
ATDH2200E
25
DB-25F
AT17A Series
Device
Socket
1.
AT17A=AT17LV/FXXXA
AT17=AT17LV/FXXX
Rev. 3033C–CONFG–3/04
1
Figure 2, Figure 3 and Figure 4 show the configurator connection for different families of Altera FPGAs.
Figure 2. Drop-In Replacement of AT17A Series Devices for Altera EPF8K FPGA Applications
VCC
VCC VCC
VCC
1 kΩ
EPF8K
1 kΩ
1 kΩ
(4)
AT17A Series Device
nCONFIG
(2)
22 µF
GND
nS/P
MSEL0
MSEL1
DATA0
DCLK
CONF_DONE
nSTATUS
DATA
DCLK(3)
nCS
(1)
OE
SER_EN
1 kΩ
GND
Notes:
1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by a programmer.
2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. (nCONFIG can instead be connected
to an active Low system reset signal).
3. For AT17LV512A/010A/002A devices, the internal oscillator of the DCLK pin must be disabled to avoid clock contention.
4. AT17 Series devices could also be used.
Figure 3. Drop-In Replacement of AT17A Series Devices for Altera FPGA Applications, Internal Oscillator Arrangement
VCC
VCC
VCC
VCC
1 kΩ
APEX II, EP20K, EP1K,
EPF10K, EPF6K
nCONFIG
(3)
0.1 µF
GND
nCE
MSEL0
MSEL1
DATA0
DCLK
CONF_DONE
nSTATUS
1 kΩ
1 kΩ
AT17A Series Device
DATA
DCLK
nCS
OE(1)
SER_EN
READY(2)
GND
Notes:
2
1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by a programmer if an AT17LVXXXA series
configurator is used.
2. Use of the READY pin is optional.
3. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected
to an active Low system reset signal).
4. For Altera’s EDF6K FPGA, MSEL is used instead of MSEL0 and MSEL1.
Drop-In/Stand-alone Circuits for Altera FPGAs
3033C–CONFG–3/04
Drop-In/Stand-alone Circuits for Altera FPGAs
Figure 4. Drop-In Replacement of AT17A Series Devices for Altera FPGA Applications
VCC
VCC
1 kΩ APEX
II, EP20K, EP1K,
EPF10K, EPF6K
0.1 µF
nCONFIG
(2)
DATA0
DCLK
CONF_DONE
nSTATUS
GND
1 kΩ
VCC
EXT_CLK
VCC
1 kΩ
AT17A Series Device
DATA
(3)
DCLK
nCS
OE
SER_EN
nCE
MSEL
GND
Notes:
1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by a programmer if an AT17LVXXXA series
configurator is used.
2. RC filter recommended for input to nCONFIG to delay configuration until VCC is stable. (nCONFIG can instead be connected
to an active Low system reset signal).
3. For AT17LV512A/010A/002A devices, the internal oscillator of the DCLK pin must be disabled to avoid clock contention.
4. AT17 series devices could also be used.
3
3033C–CONFG–3/04
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