AT93C56B/66B - Complete

AT93C56B and AT93C66B
3-wire Serial EEPROM
2K (256 x 8 or 128 x 16) and 4K (512 x 8 or 256 x 16)
DATASHEET
Features

Low-voltage Operation
̶

VCC = 1.7V to 5.5V
User-selectable Internal Organization
̶
2K: 256 x 8 or 128 x 16
4K: 512 x 8 or 256 x 16
̶





3-wire Serial Interface
Sequential Read Operation
2MHz Clock Rate (5V)
Self-timed Write Cycle (5ms Max)
High Reliability
̶
̶

Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and
8-ball VFBGA packages
Description
The Atmel® AT93C56B/66B provides 2,048/4,096 bits of Serial Electrically
Erasable Programmable Read-Only Memory (EEPROM) organized as 128/256
words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words
of 8 bits each (when the ORG pin is tied to ground). The device is optimized for
use in many industrial and commercial applications where low-power and lowvoltage operations are essential. The AT93C56B/66B is available in space-saving
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and 8-ball
VFBGA packages.
The AT93C56B/66B is enabled through the Chip Select pin (CS) and accessed
via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and
Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded,
and the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C56B/66B operates from 1.7V to 5.5V.
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Configurations
8-lead SOIC
8-lead TSSOP
Pin Name
Function
CS
Chip Select
CS
1
8
VCC
SK
Serial Data Clock
SK
2
7
NC
6
Serial Data Input
DI
3
DI
ORG
DO
4
5
GND
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
NC
No Connect
8-pad UDFN/XDFN
8
7
6
5
VCC
NC
ORG
GND
Top View
8-ball VFBGA
VCC 8
1
CS
NC 7
2
SK
ORG 6
3
DI
GND 5
4
DO
GND
Note:
VCC
8
1
CS
NC
7
2
SK
ORG
6
3
DI
5
4
DO
Bottom View
Drawings are not to scale.
Absolute Maximum Ratings*
Operating Temperature  55C to +125C
Storage Temperature 65C to +150C
Voltage on any pin
with respect to ground 1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
1
2
3
4
Top View
Bottom View
2.
CS
SK
DI
DO
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
VCC
GND
Memory Array
ORG
256/512 x 8
or
128/256 x 16
Address
Decoder
Data
Register
Output
Buffer
DI
CS
SK
Note:
Mode Decode
Logic
Clock
Generator
DO
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground,
the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input
beyond the capability of the internal 1M pull-up resistor, then the x16 organization is selected.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
3
4.
Memory Organization
4.1
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
4.2
1.
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
This parameter is characterized, and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Unit
1.7
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
VCC = 5.0V
Min
Typ
ISB1
Standby Current
ISB2
Read at 1.0MHz
0.5
2.0
mA
Write at 1.0MHz
0.5
2.0
mA
VCC = 1.7V
CS = 0V
0.4
1.0
μA
Standby Current
VCC = 2.5V
CS = 0V
6.0
10.0
μA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
μA
IIL
Input Leakage
VIN = 0V to VCC
0.1
3.0
μA
IOL
Output Leakage
VIN = 0V to VCC
0.1
3.0
μA
VIL1(1)
Input Low Voltage
2.5V VCC  5.5V
0.6
0.8
V
VIH1(1)
Input High Voltage
2.5V VCC  5.5V
2.0
VCC + 1
V
VIL2(1)
Input Low Voltage
1.7V  VCC  2.5V
0.6
VCC x 0.3
V
VIH2(1)
Input High Voltage
1.7V  VCC  2.5V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
2.5V  VCC  5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
2.5V  VCC  5.5V
IOH = 0.4mA
VOL2
Output Low Voltage
1.7V  VCC  2.5V
IOL = 0.15mA
VOH2
Output High Voltage
1.7V  VCC  2.5V
IOH = 100μA
Note:
4
Test Condition
1.
VIL min and VIH max are reference only, and are not tested.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
2.4
V
0.2
VCC  0.2
V
V
4.3
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to + 85°C, VCC = as specified, CL = 1 TTL gate and 100pF
(unless otherwise noted).
Symbol
Parameter
fSK
SK Clock Frequency
Test Condition
Min
Max
Units
4.5V  VCC  5.5V
0
2
MHz
2.5V  VCC  5.5V
0
1
MHz
1.7V  VCC  5.5V
0
250
kHz
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
2.5V  VCC  5.5V
50
ns
1.7V  VCC  5.5V
200
ns
2.5V  VCC  5.5V
100
ns
1.7V  VCC  5.5V
400
ns
0
ns
2.5V  VCC  5.5V
100
ns
1.7V  VCC  5.5V
400
ns
tSKH
SK High Time
tSKL
SK Low Time
tCS
Minimum CS Low Time
tCSS
CS Setup Time
Relative to SK
tDIS
DI Setup Time
Relative to SK
tCSH
CS Hold Time
Relative to SK
tDIH
DI Hold Time
Relative to SK
tPD1
Output Delay to 1
AC Test
tPD0
Output Delay to 0
AC Test
tSV
CS to Status Valid
AC Test
tDF
CS to DO in
High-impedance
tWP
Write Cycle Time
Endurance(1)
5.0V, 25°C
Note:
1.
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
2.5V  VCC  5.5V
250
ns
1.7V  VCC  5.5V
1000
ns
AC Test
2.5V  VCC  5.5V
150
ns
CS = VIL
1.7V  VCC  5.5V
400
ns
1.7V  VCC  5.5V
5
ms
1,000,000
Write Cycles
This parameter is characterized, and is not 100% tested.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
5
5.
Functional Description
The AT93C56B/66B is accessed via a simple and versatile 3-wire serial communication interface. Device
operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising
edge of CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory
address location.
Table 5-1.
AT93C56B/66B Instruction Set
Address
Data
SB
Opcode
x8(1)
x16(1)
READ
1
10
A8 – A0
A7 – A0
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
11
A8 – A0
A7 – A0
WRITE
1
01
A8 – A0
A7 – A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
Instruction
Note:
1.
x8
x16
Comments
Reads data stored in memory at
specified address.
Write Enable must precede all
programming modes.
Erases memory location AN – A0.
D7 – D0
D15 – D0
Writes memory location AN – A0.
Erases all memory locations.
Valid only at VCC3 (Section 4.2, “DC
Characteristics” on page 4).
D7 – D0
D15 – D0
Writes all memory locations.
Valid only at VCC3 (Section 4.2) and
Disable Register cleared.
Disables all programming
instructions.
The Xs in the address field represent don’t care values, and must be clocked.
READ: The READ instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the Serial Output
pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be
noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C56B/66B supports
sequential Read operations. The device will automatically increment the internal address pointer and clock out
the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not
be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out.
Note:
6
Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or VCC
power is removed from the part.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The selftimed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 1 at the
DO pin indicates that the selected memory location has been erased, and the part is ready for another
instruction.
WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at Serial Data Input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of tCS. A
Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction, and the part is ready for
further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the end of the
self-timed programming cycle, tWP.
Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought
high after being kept low for a minimum of tCS. The ERAL instruction is valid only at VCC3 (Section 4.2, “DC
Characteristics” on page 4).
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of tCS. The WRAL instruction is valid only at VCC3 (Section 4.2).
Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
7
6.
Timing Diagrams
Figure 6-1.
Synchronous Data Timing
CS
SK
VIH
VIL
tSKL
VIL
tDIH
VIH
VIL
tPD0
DO (Read)
tCSH
VIH
tDIS
DI
tSKH
tCSS
tDF
tPD1
VOH
VOL
tDF
tSV
DO (Program)
VOH
Status Valid
VOL
Table 6-1.
Organization Key for Timing Diagrams
AT93C56B (2K)
Notes:
AT93C66B (4K)
I/O
x8
x16
x8
x16
AN
A8(1)
A7(2)
A8
A7
DN
D7
D15
D7
D15
1.
2.
Figure 6-2.
A8 is a don’t-care value, but the extra clock is required.
A7 is a don’t-care value, but the extra clock is required.
READ Timing
tCS
CS
SK
DI
DO
8
1
1
0
AN
A0
High-impedance
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
0
DN
D0
Figure 6-3.
EWEN Timing
tCS
CS
SK
DI
Figure 6-4.
1
0
0
1
...
1
ERASE Timing
tCS
Standby
Check
Status
CS
SK
DI
1
1
1
AN
AN-1 AN-2
...
A0
tDF
tSV
DO
High-impedance
High-impedance
Busy
Ready
tWP
Figure 6-5.
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
High-impedance
Busy
Ready
tWP
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
9
Figure 6-6.
ERAL Timing(1)
tCS
Standby
Check
Status
CS
SK
1
DI
0
0
1
0
tDF
tSV
High-impedance
DO
High-impedance
Busy
Ready
tWP
Note:
1.
Figure 6-7.
Valid only at VCC3 (Section 4.2).
WRAL Timing(1)
tCS
CS
SK
1
DI
0
0
0
1
...
DN
...
D0
High-impedance
DO
Busy
tWP
Note:
1.
Figure 6-8.
Valid only at VCC3 (Section 4.2).
EWDS Timing
tCS
CS
SK
DI
10
1
0
0
0
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
0
...
Ready
7.
Ordering Code Detail
AT 9 3 C 5 6 B - S S H M - B
Atmel Designator
Product Family
93C = Microwire-compatible
3-Wire Serial EEPROM
Shipping Carrier Option
B or Blank = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
Operating Voltage
M = 1.7V to 5.5V
Device Density
56 = 2k
66 = 4k
Device Revision
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
U = Green, Matte Sn Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS = JEDEC SOIC
X
= TSSOP
MA = UDFN
ME = XDFN
C
= VFBGA
WWU = Wafer Unsawn
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
11
8.
Ordering Information
Delivery Information
Atmel Ordering Code
Lead Finish
Package
Form
Quantity
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
100 per Tube
Tape and Reel
5,000 per Reel
Tape and Reel
5,000 per Reel
Tape and Reel
15,000 per Reel
8ME1
Tape and Reel
5,000 per Reel
8U3-1
Tape and Reel
5,000 per Reel
AT93C56B-SSHM-B
Operation
Range
8S1
AT93C56B-SSHM-T
AT93C56B-XHM-B
AT93C56B-XHM-T
8X
NiPdAu
(Lead-free/Halogen-free)
AT93C56B-MAHM-T
8MA2
AT93C56B-MAHM-E
AT93C56B-MEHM-T
AT93C56B-CUM-T
SnAgCu
(Lead-free/Halogen-free)
AT93C56B-WWU11M(1)
N/A
Wafer Sale
Industrial
Temperature
(-40C to 85C)
Note 1
AT93C66B-SSHM-B
Bulk (Tubes)
100 per Tube
Tape and Reel
4,000 per Reel
Bulk (Tubes)
100 per Tube
Tape and Reel
5,000 per Reel
Tape and Reel
5,000 per Reel
Tape and Reel
15,000 per Reel
8ME1
Tape and Reel
5,000 per Reel
8U3-1
Tape and Reel
5,000 per Reel
8S1
AT93C66B-SSHM-T
AT93C66B-XHM-B
AT93C66B-XHM-T
8X
NiPdAu
(Lead-free/Halogen-free)
AT93C66B-MAHM-T
8MA2
AT93C66B-MAHM-E
AT93C66B-MEHM-T
AT93C66B-CUM-T
SnAgCu
(Lead-free/Halogen-free)
AT93C66B-WWU11M(1)
Note:
1.
N/A
Wafer Sale
Note 1
For wafer sales, please contact Atmel sales.
Package Type
12
8S1
8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8X
8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
8ME1
8-pad, 1.80mm x 2.20mm body, Extra Thin Dual No Lead (XDFN)
8U3-1
8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Small Die Ball Grid Array (VFBGA)
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
Industrial
Temperature
(-40C to 85C)
9.
Part Markings
AT93C56B and AT93C66B: Package Marking Information
8-lead TSSOP
8-lead SOIC
8-pad UDFN
2.0 x 3.0 mm Body
###
H%@
YXX
ATHYWW
###% @
AAAAAAA
ATMLHYWW
###%
@
AAAAAAAA
8-pad XDFN
8-ball VFBGA
1.8 x 2.2 mm Body
1.5 x 2.0 mm Body
###
YXX
###U
YMXX
PIN 1
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT93C56B
Truncation Code ###: 56B
AT93C66B
Truncation Code ###: 66B
Date Codes
Y = Year
3: 2013
4: 2014
5: 2015
6: 2016
Voltages
7: 2017
8: 2018
9: 2019
0: 2020
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
M: 1.7V min
Grade/Lead Finish Material
U: Industrial/Matte Tin/SnAgCu
H: Industrial/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/22/13
TITLE
Package Mark Contact:
[email protected]
93C56-66BSM, AT93C56B and AT93C66B Package Marking
Information
DRAWING NO.
REV.
93C56-66BSM
B
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
13
10.
Packaging Information
10.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
14
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
GPC
SWB
DRAWING NO.
REV.
8S1
G
10.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
D
SYMBOL
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
REV.
E
15
10.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
A1
E2
b (8x)
8
7
1
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b
0.18
0.25
0.30
C
L
3
1.52 REF
0.30
e
K
NOTE
0.35
0.40
0.50 BSC
0.20
-
-
11/26/14
Package Drawing Contact:
[email protected]
16
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
GPC
DRAWING NO.
REV.
YNZ
8MA2
G
10.4
8ME1 — 8-pad XDFN
D
7
8
6
5
E
PIN #1 ID
2
1
3
4
A1
Top View
A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
0.10
PIN #1 ID
0.15
b
e
e
0.40 TYP
e1
1.20 REF
L
End View
0.26
0.30
NOTE
0.35
9/10/2012
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
REV.
8ME1, 8-pad (1.80mm x 2.20mm body)
Extra Thin DFN (XDFN)
DTP
8ME1
B
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
17
10.5
8U3-1 — 8-ball VFBGA
E
D
2. b
PIN 1 BALL PAD CORNER
A1
A2
TOP VIEW
A
SIDE VIEW
PIN 1 BALL PAD CORNER
3
1
2
4
d
(d1)
8
7
6
5
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
MIN
NOM
MAX
BOTTOM VIEW
A
0.73
0.79
0.85
8 SOLDER BALLS
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
Notes:
b
0.20
0.25
0.30
1. This drawing is for general information only.
D
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
6/11/13
Package Drawing Contact:
[email protected]
18
TITLE
GPC
DRAWING NO.
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GXU
8U3-1
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
REV.
F
11.
Revision History
Rev. No.
Date
8735C
01/2015
Comments
Add the UDFN extended quantity option and update package outline drawings.
Update the 8MA2 package drawing.
Correct Synchronous Data Timing figure and remove note.
8735B
04/2013
Update TSSOP package option from 8A2 to 8X.
Update UDFN package option from 8Y6 to 8MA2.
Update template and Atmel logos.
8735A
01/2011
Initial document release.
AT93C56B/66B [DATASHEET]
Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015
19
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© 2015 Atmel Corporation. / Rev.: Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015.
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