AT83C5111/AT87C5111 - Mature

Features
• 80C51 Compatible
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
– Three I/O Ports
– Two 16-bit Timer/Counters
– 256 Bytes RAM
4K Bytes ROM/OTP Program Memory with 64 Bytes Encryption Array and 3 Security
Levels
High-Speed Architecture
– 33 MHz at 5V (66 MHz Equivalent)
– 20 MHz at 3V (40 MHz Equivalent)
– X2 Speed Improvement Capability (6 Clocks/Machine Cycle)
10-bit, 8 Channels A/D Converter
Hardware Watchdog Timer
Programmable I/O Mode: Standard C51, Input Only, Push-pull, Open Drain
Asynchronous Port Reset
Full Duplex Enhanced UART with Baud Rate Generator
SPI, Master Mode
Dual System Clock
– Crystal or Ceramic Oscillator (33/40 MHz)
– Internal RC Oscillator (12 MHz)
– Programmable Prescaler
Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width
Modulation and Watchdog Timer Capabilities
Interrupt Structure
– 8 Interrupt Sources
– 4 Interrupt Priority Levels
Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
Power Supply: 2.7 - 5.5V
Temperature Range: Industrial (-40 to 85oC)
Package: SO24, DIL24, SSOP24
Low Pin Count
8-bit
Microcontroller
with A/D
Converter
AT83C5111
AT87C5111
Description
The AT8xC5111 is a high-performance ROM/OTP version of the 80C51 8-bit microcontroller in low pin count package.
The AT8xC5111 retains all the features of the standard 80C51 with 4K Bytes
ROM/OTP program memory, 256 bytes of internal RAM, an 8-source, 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The AT8xC5111 is dedicated for analog interfacing applications. For this, it has a 10bit, 8 channels A/D converter and a five-channel Programmable Counter Array.
In addition, the AT8xC5111 has a Hardware Watchdog Timer, a versatile serial channel that facilitates multiprocessor communication (EUART) with an independent baud
rate generator, an SPI serial bus controller and a X2 speed improvement mechanism.
The X2 feature permits keeping the same CPU power at an oscillator frequency
divided by two. The prescaler allows to decrease CPU and peripherals clock
frequency.
The fully static design of the AT8xC5111 can reduce system power consumption by
bringing the clock frequency down to any value, even DC, without loss of data.
The AT8xC5111 has 3 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the peripherals
are still operating. In the quiet mode, only the A/D converter is operating.
Rev. 4190B–8051–02/08
In the power-down mode, the RAM is saved and all other functions are inoperative. Two
oscillator sources, crystal and RC, provide a versatile power management.
The AT8xC5111 is proposed in low-pin count packages. Port 0 and Port 2 (address/data
buses) are not available .
(1) (1)
(2) (2)
Xtal
Osc
C51
CORE
(2) (3)
MISO
MOSI
SPSCK
SS
SPI
Watch
Dog
IB-bus
INT
Ctrl
Parallel I/O Ports
A/D
Converter
Port 1 Port 3 Port 4
(2) (3)
P4
P3
P1
T1
(3)
T0
RST/VPP
(2)
2
PCA
4K *8
CPU
Timer 0
Timer 1
Notes:
ROM /OTP
RAM
256
x8
AIN0-7
RC
Osc
EUART
BRG
VREF
(2)
INT1
XTAL2
(3)(3)(3) (3)
(2)
INT0
XTAL1
CEX0-4
ECI
Vss
Vcc
TxD
RxD
Block Diagram
1. Alternate function of Port 1.
2. Alternate function of Port 3.
3. Alternate function of Port 4.
AT8xC5111
4190B–8051–02/08
AT8xC5111
SFR Mapping
The Special Function Registers (SFRs) of the AT8xC5111 belong to the following
categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•
I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
•
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
•
Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON,
CKRL
•
Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
•
Watchdog Timer: WDTRST, WDTPRG
•
SPI: SPCON, SPSTA, SPDAT
•
PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H,
CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3,
CCAPM4, CL, CH, CMOD, CCON
•
ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
3
4190B–8051–02/08
Table 1. SFR Addresses and Reset Values
0/8
F8h
F0h
1/9
72/A
3/B
4/C
5/D
6/E
CH
0000 0000
CCAP0H
XXXX XXXX
CCAP1H
XXXX XXXX
CCAP2H
XXXX XXXX
CCAP3H
XXXX XXXX
CCAP4H
XXXX XXXX
FFh
F7h
B
0000 0000
CL
0000 0000
E8h
E0h
ACC
0000 0000
D8h
CCON
00X0 0000
D0h
PSW
0000 0000
ADCLK
ADCON
0000 0000
0000 0000
ADDL
XXXXXX00
ADDH
0000 0000
ADCF
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAP2L
XXXX XXXX
CCAP3L
XXXX XXXX
CCAP4L
XXXX XXXX
P3M2
0000 0000
P4M2
0000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
P1M1
P3M1
0000 0000
P4M1
0000 0000
D7h
P1M2
0000 0000
CMOD
X000 0000
7/F
CCAPM0
00XX X000
CCAPM1
X000 0000
0000 0000
CONF
E7h
C8h
CFh
C0h
P4
1111 1111
B8h
IPL0
0000 0000
SADEN
0000 0000
B0h
P3
1111 1111
0000 0000
A8h
IE0
0000 0000
SADDR
0000 0000
SPCON
0001 0100
IE1
90h
88h
SPSTA
SPDAT
XXXXXXXX
XXXX XXXX
SCON
0000 0000
SBUF
XXXX XXXX
C7h
BFh
IPL1
0000 0000
IPH1
0000 0000
AUXR1
XXXXXXX0
A0h
98h
EFh
BRL
0000 0000
WDRST
0000 0000
IPH0
X000 0000
B7h
CKCON1
XXXX XXX0
AFh
WDTPRG
0000 0000
A7h
BDRCON
9Fh
0000 0000
P1
CKRL
1111 1111
1111 1111
TCON
0000 0000
80h
0/8
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
1/9
2/A
3/B
TH0
0000 0000
4/C
TH1
0000 0000
CKCON0
X000X000
PCON
CKSEL
XXXX XXX1
OSCCON
XXXX XX01
00X1 0000
5/D
6/E
7/F
97h
8Fh
87h
Reserved
4
AT8xC5111
4190B–8051–02/08
AT8xC5111
Pin Configuration
P4.4/MISO/AIN4
1
24
P4.3/INT1/AIN3
P4.4/MISO/AIN4
1
24
P4.3/INT1/AIN3
P4.5/MOSI/AIN5
2
P4.2/SS/AIN2
P4.5/MOSI/AIN5
2
3
4
21
P4.1/AIN1/T1
P4.0/AIN0
3
4
VSS
6
SO24
20
19
P3.0/RxD
P3.1/TxD
P4.6/SPSCK/AIN6
VREF
VSS
23
22
P4.2/SS/AIN2
P4.6/SPSCK/AIN6
P4.7/AIN7
VREF
23
22
6
VCC
RST/VPP
XTAL2
XTAL1
7
8
DIL24
18
17
P1.2/ECI
AVSS
9
16
P1.4/CEX1
10
AVCC
VCC
RST/VPP
XTAL2
XTAL1
5
P1.3/CEX0
21
P4.1/AIN1/T1
P4.0/AIN0
20
19
P3.0/RxD
P3.1/TxD
7
8
18
17
P1.2/ECI
9
16
P1.4/CEX1
10
15
14
P1.5/CEX2
13
P3.3/T0
5
SSOP24
P1.3/CEX0
15
14
P1.5/CEX2
11
12
13
P3.3/T0
Mnemonic
Type
Name and Function
VSS
I
Ground: 0V reference
VCC
I
Power Supply: This is the power supply voltage for normal, idle and power-down operation.
VREF
I
VREF: A/D converter positive reference input
I
RST/VPP: Reset/Programming Supply Voltage:
A low on this pin for two machine cycles while the oscillator is running, resets the device. This pin
has no pull-up. In order to use the internal power-on reset, an external pull-up resistor must be
connected.
This pin also receives the 12V programming pulse which will start the EPROM programming and the
manufacturer test modes.
XTAL1
I
XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits
XTAL2
O
XTAL2 : Output from the inverting oscillator amplifier
I/O
Port 1: Port 1 is an 6-bit programmable I/O port . See Section “Ports”, page 18 for a description of
I/O ports.
Alternate functions for Port 1 include:
I/O
ECI (P1.2): External Clock for the PCA
I/O
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
I/O
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
I/O
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
I/O
CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
I/O
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
I/O
Port 3: Port 3 is an 6-bit programmable I/O port with internal pull-ups. See Section "Ports", page 18
for a description of I/O ports.
Port 3 also serves the special features of the 80C51 family, as listed below.
I/O
RXD (P3.0): Serial input port
I/O
TXD (P3.1): Serial output port
P1.7/CEX4
P1.6/CEX3
P3.2/INT0
P1.6/CEX3
11
12
P3.2/INT0
Pin Descriptions
RST/VPP
P1.2 - P1.7
P3.0 - P3.3
5
4190B–8051–02/08
Mnemonic
Type
I/O
INT0 (P3.2): External interrupt 0
I/O
T0 (P3.3): Timer 0 external input
I/O
Port 4: Port 4 is an 8-bit programmable I/O port with internal pull-ups. See Section "Ports", page 18
for a description of I/O ports.
Port 4 is also the input port of the analog-to-digital converter.
I/O
AIN0 (P4.0): A/D converter input 0
I/O
AIN1 (P4.1): A/D converter input 1
T1: Timer 1 external input
I/O
AIN2 (P4.2): A/D converter input 2
SS: Slave select input of the SPI controllers
I/O
AIN3 (P4.3): A/D converter input 3
INT1: External interrupt 1
I/O
AIN4 (P4.4): A/D converter input 4
MISO: Master IN, Slave OUT of the SPI controllers
I/O
AIN5 (P4.5): A/D converter input 5
MOSI: Master OUT, Slave IN of the SPI controllers
I/O
AIN6 (P4.6): A/D converter input 6
SPSCK: Clock I/O of the SPI controllers
I/O
AIN7 (P4.7): A/D converter input 7
P4.0 - P4.7
6
Name and Function
AT8xC5111
4190B–8051–02/08
AT8xC5111
Clock System
The AT8xC5111 oscillator system provides a reliable clocking system with full mastering
of speed versus CPU power trade off. Several clock sources are possible:
•
External clock input
•
High-speed crystal or ceramic oscillator
•
Integrated high-speed RC oscillator
The selected clock source can be divided by 2 - 512 before clocking the CPU and the
peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle.
Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL.
Blocks Description
Crystal Oscillator: OSCA
The AT8xC5111 includes the following oscillators:
•
Crystal oscillator
•
Integrated high-speed RC oscillator, with typical frequency of 12 MHz
The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.
Both crystal and ceramic resonators can be used. An oscillator source on XTAL1 is
mandatory to start the product.
OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input.
Integrated High-speed RC
Oscillator: OSCB
The high-speed RC oscillator typical frequency is 12 MHz. Note that the on chip oscillator has a ±50% frequency tolerance and may not be suitable for use in some
applications.
OSCBEN in OSCCON register is an enable signal for the high-speed RC oscillator.
Clock Selector
CKS bit in CKS register is used to select from crystal to RC oscillator.
OSCBEN bit in OSCCON register is used to enable the RC oscillator.
OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external
oscillator input.
Clock Prescaler
Before supplying the CPU and the peripherals, the main clock is divided by a factor of 2
to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows:
•
to accept any cyclic ratio to be accepted on XTAL1 input.
•
to reduce the CPU power consumption.
The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock
periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on
XTAL1 must have a cyclic ratio between 40 to 60%.
7
4190B–8051–02/08
Functional Block Diagram
Timer 0 Clock
: 128
ResetB
Sub Clock
Reload
WD Clock
Ckrl
Xtal1
Xtal_Osc
OSCA
Xtal2
OSCAEN
OSCBEN
1
0
A/D Clock
Mux
+
Filter
PwdOsc
OscOut
8-bit
Prescaler-Divider
CkAdc
0
1
CkOut
Peripherals Clock
CkIdle
CKS
RC_Osc
OSCB
CPU Clock
X2
Ck
PwdRC
Quiet Pwd Idle
Operating Modes
Functional Modes
Normal Modes
Idle Modes
8
•
CPU and Peripheral clocks depend on the software selection using CKCON0,
CKCON1, CKSEL and CKRL registers.
•
CKS bit selects either Xtal_Osc or RC_Osc.
•
CKRL register determines the frequency of the selected clock, unless X2 bit is set.
In this case the prescaler/divider is not used, so CPU core needs only 6 clock
periods per machine cycle. According to the value of the peripheral X2 individual bit,
each peripheral needs 6 or 12 clock periods per instruction.
•
It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc,
and vice versa by changing CKS bit, a synchronization cell allowing to avoid any
spike during transition.
•
IDLE modes are achieved by using any instruction that writes into PCON.0 sfr
•
IDLE modes A and B depend on previous software sequence, prior to writing into
PCON.0 register:
–
IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)
–
IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)
•
The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing
OSCAEN or OSCBEN, respectively.
•
Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt.
•
In both cases, PCON.0 is cleared by hardware.
AT8xC5111
4190B–8051–02/08
AT8xC5111
Power-down Modes
•
Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and
CKS unchanged.
•
POWER-DOWN modes are achieved by using any instruction that writes into
PCON.1 sfr
•
Exit from POWER-DOWN mode is achieved either by a hardware Reset, or by an
external interruption.
•
By RST signal: The CPU will restart on OSCA.
•
By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN,
OSCBEN and CKS will not be changed, so the selected oscillator before entering
into Power-down will be activated.
Table 1. Power Modes
Prescaler Divider
•
•
PD
IDLE
CKS
OSCBEN
OSCAEN Selected Mode
Comment
0
0
1
X
1
NORMAL MODE A OSCA: XTAL clock
X
X
1
X
0
INVALID
0
0
0
1
X
NORMAL MODE B OSCB: high-speed RC clock
X
X
0
0
X
INVALID
0
1
1
X
1
IDLE MODE A
The CPU is off, OSCA supplies the
peripherics
0
1
0
1
X
IDLE MODE B
The CPU is off, OSCB supplies the
peripherics
1
X
X
X
X
TOTAL POWERDOWN
The CPU is off, OSCA and OSCB are
stopped
No active clock
An hardware RESET selects the prescaler divider:
–
CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature)
–
X2 = 0,
After Reset, any value between FFh down to 00h can be written by software into
CKRL sfr in order to divide frequency of the selected oscillator:
–
CKRL = 00h: minimum frequency = OscOut/512
–
CKRL = FFh: maximum frequency = OscOut/2
The frequency of the CPU and peripherals clock CkOut is related to the frequency of the
main oscillator OscOut by the following formula:
FCkOut = FOscOut/(512 - 2*CKRL)
Some examples can be found in the table below:
FOscOut
•
MHz
X2
CKRL
FCkOut (Mhz)
12
0
FF
6
12
0
FE
3
12
1
x
12
A software instruction which sets X2 bit de-activates the prescaler/divider, so the
internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit.
9
4190B–8051–02/08
Timer 0: Clock Inputs
CkIdle
:6
T0 pin
0
Timer 0
1
0
Control
1
Sub Clock
C/T
TMOD
SCLKT0
OSCCON
Gate
INT0
TR0
The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This
allows to perform a Real-Time Clock function.
SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode).
SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input.
When the subclock input is selected for Timer 0 and the crystal oscillator is selected for
CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order
to assure a proper count on Timer 0.
With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256
seconds to perform a Real-Time Clock (RTC) function. The power consumption will be
very low as the CPU is in idle mode at 32 kHz most of the time. When more CPU power
is needed, the internal RC oscillator is activated and used by the CPU and the others
peripherals.
Registers
Clock Control Register
10
The clock control register is used to define the clock system behavior.
Table 2. OSCCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
-
-
-
-
SCLKT0
OSCBEN
OSCAEN
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Description
AT8xC5111
4190B–8051–02/08
AT8xC5111
Bit
Bit
Number
Mnemonic
2
SCLKT0
Description
Sub Clock Timer0
Cleared by software to select T0 pin
Set by software to select T0 Sub Clock
1
OSCBEN
Enable RC oscillator
This bit is used to enable the high-speed RC oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
0
OSCAEN
Enable crystal oscillator
This bit is used to enable the crystal oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
Reset value = 0XXX X001b
Not bit addressable
Clock Selection Register
The clock selection register is used to define the clock system behavior
Table 3. CKSEL - Clock Selection Register (85h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
CKS
Bit
Bit
Number
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
CKS
Description
Active oscillator selection
This bit is used to select the active oscillator.
1: The crystal oscillator is selected.
0: The high-speed RC oscillator is selected.
Reset value = XXXX XXX 1 b
Not bit addressable
11
4190B–8051–02/08
Clock Prescaler Register
This register is used to reload the clock prescaler of the CPU and peripheral clock.
Table 4. CKRL - Clock Prescaler Register (97h)
7
6
5
4
3
2
1
0
M
Bit
Bit
Number
Mnemonic
7: 0
CKRL
Description
0000 0000b: Division factor equal 512
1111 1111b: Division factor equal 2
M: Division factor equal 2*(256-M)
Reset value = 1111 1111b
Not bit addressable
Clock Control Register
This register is used to control the X2 mode of the CPU and peripheral clock.
Table 5. CKCON0 Register (8Fh)
7
6
5
4
3
2
1
0
-
WdX2
PcaX2
SiX2
-
T1X2
T0X2
X2
Bit
Number
7
6
Bit
Mnemonic Description
-
WdX2
Reserved
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
PcaX2
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4
SiX2
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3
2
-
T1X2
Reserved
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1
T0X2
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
12
AT8xC5111
4190B–8051–02/08
AT8xC5111
Bit
Bit
Number
Mnemonic Description
CPU clock
0
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals.
X2
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Reset value = X000 0000b
Not bit addressable
Table 6. CKCON1 Register (AFh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
BRGX2
SPIX2
Bit
Bit
Number
Mnemonic
7
-
Reserved
6
-
Reserved
5
-
Reserved
4
-
Reserved
3
-
Reserved
2
-
Reserved
1
BRGX2
Description
BRG clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0
SPIX2
SPI clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reset value = XXXX XX00b
Not bit addressable
13
4190B–8051–02/08
AT8xC5111
Reset and Power
Management
The power monitoring and management can be used to supervise the Power Supply
(VDD) and to start up properly when AT8xC5111 is powered up.
It consists of the features listed below and explained hereafter:
•
Power-off flag
•
Idle mode
•
Power-down mode
•
Reduced EMI mode
All these features are controlled by several registers, the Power Control register (PCON)
and the Auxiliary register (AUXR) detailed at the end of this section.
AUX register not available on all versions.
Functional Description
Figure 1 shows the block diagram of the possible sources of microcontroller reset.
Figure 1. Reset Sources
RST Pin(1)
Hardware WD
Reset
RST Pin(2)
PCA WD
Notes:
Power-off Flag
1. RST pin available only on 48 and 52 pins versions.
2. RST pin available only on LPC versions.
When the power is turned off or fails, the data retention is not guaranteed. A Power-off
Flag (POF, Table 8 on page 15) allows to detect this condition. POF is set by hardware
during a reset which follows a power-up or a power-fail. This is a cold reset. A warm
reset is an external or a watchdog reset without power failure, hence which preserves
the internal memory content and POF. To use POF, test and clear this bit just after
reset. Then it will be set only after a cold reset.
14
4190B–8051–02/08
Registers
PCON: Power Configuration
Register
Table 1. PCON Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
–
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1
Double Baud Rate bit
Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is
selected in SCON register.
6
SMOD0
SCON Select bit
When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write
accesses to SCON.6 are to SM1 bit.
When set, read/write accesses to SCON.7 are to FE bit and read/write
accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register.
5
–
Description
Reserved
Must be cleared.
4
POF
Power-off flag
Set by hardware when VDD rises above VRET+ to indicate that the Power Supply
has been set off.
Must be cleared by software.
3
GF1
General Purpose flag 1
One use is to indicate wether an interrupt occurred during normal operation or
during Idle mode.
2
GF0
General Purpose flag 0
One use is to indicate wether an interrupt occurred during normal operation or
during Idle mode.
PD
Power-down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
1
0
Reset value = 0000 0000b
Port Pins
The value of port pins in the different operating modes is shown on Table 9.
Table 2. Pin Conditions in Special Operating Modes
15
Mode
Program Memory
Port 1 Pins
Port 3 Pins
Port 4 Pins
Reset
Don’t care
Weak High
Weak High
Weak High
Idle
Internal
Data
Data
Data
Power-down
Internal
Data
Data
Data
AT8xC5111
4190B–8051–02/08
AT8xC5111
Hardware Watchdog
Timer (WDT)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock
periods) and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). The T0 bit of the WDTPRG register is used to select the
overflow after 10 or 14 bits. When WDT overflows, it will generate an internal reset. It
will also drive an output RESET HIGH pulse at the emulator RST-pin. The length of the
reset pulse is 24 clock periods of the WD clock.
Using the WDT
To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to
01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when
it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. When WDT is
enabled, it will increment every machine cycle while the oscillator is running. This means
the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the
user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The
WDT counter cannot be read or written. When WDT overflows, it will generate an output
RESET pulse at the RST pin. The RESET pulse duration is 96 x TOSC, where TOSC =
1/FOSC . To make the best use of the WDT, it should be serviced in those sections of
code that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s at FOSC = 12 MHz and T0 = 0. To manage this feature, refer to WDTPRG register description, Table 11 (SFR0A7h).
Table 1. WDTRST Register
WDTRST Address (0A6h)
Reset value
7
6
5
4
3
2
1
X
X
X
X
X
X
X
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
16
4190B–8051–02/08
Table 2. WDTPRG Register
WDTPRG Address (0A7h)
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Number
Bit
Mnemonic
7
T4
6
T3
5
T2
4
T1
3
T0
Description
Reserved
Do not try to set this bit.
WDT overflow select bit
0: Overflow after 14 bits
1: Overflow after 10 bits
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out with T0 = 0
(214 - 1) machine cycles, 16.3 ms at 12 MHz
(215 - 1) machine cycles, 32.7 ms at 12 MHz
(216 - 1) machine cycles, 65.5 ms at 12 MHz
(217 - 1) machine cycles, 131 ms at 12 MHz
(218 - 1) machine cycles, 262 ms at 12 MHz
(219 - 1) machine cycles, 542 ms at 12 MHz
(220 - 1) machine cycles, 1.05 s at 12 MHz
(221 - 1) machine cycles, 2.09 s at 12 MHz
Reset value = XXX0 0000
Write only register
WDT During Power-down and
Idle
Power-down
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as normal whenever the AT8xC5111 is
reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held
low long enough for the oscillator to stabilize. When the interrupt is brought high, the
interrupt is serviced. To prevent the WDT from resetting the device while the interrupt
pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested
that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is best to reset the WDT just before entering power-down.
In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT8xC5111 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
Idle Mode
17
AT8xC5111
4190B–8051–02/08
AT8xC5111
Ports
The low pin count versions of the AT8xC5111 has 3 I/O ports, port 1, port 3, and port 4.
All port1, port3 and port4 I/O port pins on the AT8xC5111 may be software configured to
one of four types on a bit-by-bit basis, as shown in Table 13. These are: quasi bi-directional (standard 80C51 port outputs), push-pull, open drain, and input only. Two
configuration registers for each port choose the output type for each port pin.
Table 1. Port Output Configuration Settings Using PxM1 and PxM2 Registers
PxM1.y Bit
PxM2.y Bit
Port Output Mode
0
0
Quasi bidirectional
0
1
Push-pull
1
0
Input Only (High Impedance)
1
1
Open Drain
Port Types
Quasi Bi-directional Output
Configuration
The default port output configuration for standard AT8xC5111 I/O ports is the quasi bidirectional output that is common on the 80C51 and most of its derivatives. This output
type can be used as both an input and output without the need to reconfigure the port.
This is possible because when the port outputs a logic high, it is weakly driven, allowing
an external device to pull the pin low. When the pin is pulled low, it is driven strongly and
able to sink a fairly large current. These features are somewhat similar to an open drain
output except that there are three pull-up transistors in the quasi-bidirectional output that
serve different purposes. One of these pull-ups, called the "very weak" pull-up, is turned
on whenever the port latch for the pin contains a logic 1. The very weak pull-up sources
a very small current that will pull the pin high if it is left floating. A second pull-up, called
the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the
pin itself is also at a logic 1 level. This pull-up provides the primary source current for a
quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low
by an external device, the weak pull-up turns off, and only the very weak pull-up remains
on. In order to pull the pin low under these conditions, the external device has to sink
enough current to overpower the weak pull-up and take the voltage on the port pin
below its input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi bi-directional port pin when the port latch changes
from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time,
two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The quasi bi-directional port configuration is shown in Figure 2.
18
4190B–8051–02/08
Figure 1. Quasi bi-directional Output
2 CPU
CLOCK DELAY
P
Strong
N
Port Latch
Data
P
Very
Weak
P
Weak
Pin
Input
Data
Open-drain Output
Configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi bi-directional
mode. The open-drain port configuration is shown in Figure 3.
Figure 2. Open-drain Output
N
Port Latch
Data
Pin
Input
Data
Push-pull Output
Configuration
19
The push-pull output configuration has the same pull-down structure as both the open
drain and the quasi bi-directional output modes, but provides a continuous strong pullup when the port latch contains a logic 1. The push-pull mode may be used when more
source current is needed from a port output. The push-pull port configuration is shown in
Figure 4.
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 3. Push-pull Output
P
Strong
Pin
N
Port latch
Data
Input
Data
The input only configuration is a pure input with neither pull-up nor pull-down.
Input Only Configuration
The input only configuration is shown in Figure 5.
Figure 4. Input only
Input
Data
Pin
Ports Description
Ports P1, P3 and P4
Every output on the AT8xC5111 may potentially be used as a 20 mA sink LED drive output. However, there is a maximum total output current for all ports which must not be
exceeded. All port pins of the AT8xC5111 have slew rate controlled outputs. This is to
limit noise generated by quickly switching output signals. The slew rate is factory set to
approximately 10 ns rise and fall times.
The inputs of each I/O port of the AT8xC5111 are TTL level Schmitt triggers with
hysteresis.
Ports P0 and P2
The high pin-count version of the AT8xC5111 has standard address and data ports P0
and P2. These ports are standard C51 ports (Quasi bi-directional I/O). The control lines
are provided on the pins: ALE, PSEN, EA, Reset; RD and WR signals are on the bits
P1.1 and P1.0 .
20
4190B–8051–02/08
Registers
Table 2. P1M1 Address (D4h)
7
6
5
4
3
2
1
0
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
Bit Number
Bit
Mnemonic
Description
7:0
P1M1.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value = 0000 00XX
Table 3. P1M2 Address (E2h)
7
6
5
4
3
2
1
0
P1M2.7
P1M2.6
P1M2.5
P1M2.4
P1M2.3
P1M2.2
P1M2.1
P1M2.0
Bit Number
Bit
Mnemonic
Description
7:0
P1M2.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value = 0000 00XX
Table 4. P3M1 Address (D5h)
7
6
5
4
3
2
1
0
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
Bit Number
Bit
Mnemonic
Description
7:0
P3M1.x
Port Output configuration bit
See Table 10 for configuration definition
Reset value = 0000 0000
Table 5. P3M2 Address (E4h)
7
6
5
4
3
2
1
0
P3M2.7
P3M2.6
P3M2.5
P3M2.4
P3M2.3
P3M2.2
P3M2.1
P3M2.0
Bit
Bit
Number
Mnemonic
7:0
P3M2.x
Description
Port Output configuration bit
See Table 10 for configuration definition
Reset value = 0000 0000
21
AT8xC5111
4190B–8051–02/08
AT8xC5111
Table 6. P4M1 Address (D6h)
7
6
5
4
3
2
1
0
P4M1.7
P4M1.6
P4M1.5
P4M1.4
P4M1.3
P4M1.2
P4M1.1
P4M1.0
Bit Number
Bit
Mnemonic
Description
7:0
P4M1.x
Port Output configuration bit
See Table 10. for configuration definition.
Reset value = 0000 0000
Table 7. P4M2 Address (E5h)
7
6
5
4
3
2
1
0
P4M2.7
P4M2.6
P4M2.5
P4M2.4
P4M2.3
P4M2.2
P4M2.1
P4M2.0
Bit Number
Bit
Mnemonic
Description
7:0
P4M2.x
Port Output configuration bit
See Table 10. for configuration definition.
Reset value = 0000 0000
22
4190B–8051–02/08
AT8xC5111
Dual Data Pointer
Register
The additional data pointer can be used to speed up code execution and reduce code
size in a number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1/bit0 (see Table 19) that allows the program code to switch between them (See Figure 6).
Figure 1. Use of Dual Pointer
7
External Data Memory
0
DPS
DPTR1
AUXR1(A2H)
DPTR0
DPH(83H) DPL(82H)
Table 1. AUXR1: Auxiliary Register 1
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DPS
Bit
Number
Note:
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
23
4190B–8051–02/08
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,atDPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX atDPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
24
AT8xC5111
4190B–8051–02/08
AT8xC5111
Serial I/O Ports
Enhancements
The serial I/O ports in the AT8xC5111 are compatible with the serial I/O port in the
80C52.
They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex
modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.
Serial I/O ports include the following enhancements:
Framing Error Detection
•
Framing error detection
•
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 7).
Figure 1. Framing Error Block Diagram
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
SCON for UART (98h) (SCON_1 for UART_1 (C0h))
RI
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)
SM0 to UART mode control (SMOD0 = 0 for UART)
SMOD1
SMOD0
POF
-
GF1
GF0
PD
PCON for UART (87h) (SMOD bits for UART_1
are located in BDRCON_1)
IDL
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (see Table 25) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (see Figure 8 and Figure 9).
Figure 2. UART Timings in Mode 1
D0
RXD
Start
Bit
D1
D2
D3
D4
D5
Data Byte
D6
D7
Stop
Bit
RI
SMOD0 = X
FE
SMOD0 = 1
25
4190B–8051–02/08
Figure 3. UART Timings in Modes 2 and 3
D0
D1
D2
D3
RXD
Start
Bit
D4
D5
Data Byte
D6
D7
D8
Ninth Stop
Bit Bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
Automatic Address
Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect).
Each UART has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
26
AT8xC5111
4190B–8051–02/08
AT8xC5111
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0
set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast
= SADDR OR SADEN1111 111Xb
The use of don’t care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR = 1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
Baud Rate Selection for
UART for Modes 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
27
4190B–8051–02/08
Figure 4. Baud Rate Selection
TIMER1_BRG
0
/ 16
1
Rx Clock
INT_BRG
RBCK
TIMER1_BRG
0
/ 16
1
Tx Clock
INT_BRG
TBCK
Table 1. Baud Rate Selection Table for UART
Internal Baud Rate Generator
(BRG)
TBCK
RBCK
Clock Source for UART Tx
Clock Source
UART Rx
0
0
Timer 1
Timer 1
1
0
INT_BRG
Timer 1
0
1
Timer 1
INT_BRG
1
1
INT_BRG
INT_BRG
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the X2 bit in CKON0 register, the
value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in
PCON register (for UART).
Figure 5. Internal Baud Rate Generator
SMOD1
/2
0
Peripheral Clock
/6
0
Auto Reload Counter
BRG
Overflow
1
INT_BRG
1
BRL
SPD
BRR
28
AT8xC5111
4190B–8051–02/08
AT8xC5111
for UART:
Baud_Rate =
(BRL) = 256 -
2SMOD1 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)]
2SMOD1 x 2X2 x FXTAL
2 x 2 x 6(1-SPD) x 16 x Baud_Rate
Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1
Baud Rates
FXTAL = 16.384 MHz
FXTAL = 24 MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
-
-
Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0
Baud Rates
FOSC = 16.384 MHz
FOSC = 24 MHz
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (See Figure 10), but also for mode
0 for both UARTs, thanks to the bit SRC located in BDRCON register (see Table 27).
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4190B–8051–02/08
UART Registers
Table 2. SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
1
0
2
1
0
2
1
0
Reset value = 0000 0000b
Table 3. SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
Reset value = 0000 0000b
Table 4. SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
Reset value = XXXX XXXXb
Table 5. BRL - Baud Rate Reload Register for the Internal Baud Rate Generator, UART
- UART(9Ah)
7
6
5
4
3
2
1
0
Reset value = 0000 0000b
30
AT8xC5111
4190B–8051–02/08
AT8xC5111
Table 6. SCON Register
SCON - Serial Control Register for UART (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number Mnemonic Description
7
FE
Framing Error bit (SMOD0 = 1) for UART
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial Port Mode bit 0 (SMOD0 = 0) for UART
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial Port Mode bit 1 for UART
SM0 SM1 Mode Description Baud Rate
6
SM1
0
0
1
1
0
1
0
1
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
FXTAL/12 (FXTAL/6 X2 mode)
Variable
FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode)
Variable
5
SM2
Serial Port Mode 2 bit/Multiprocessor Communication Enable bit for UART
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
4
REN
Reception Enable bit for UART
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 for UART.
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3 for UART
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
0
TI
Transmit Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
RI
Receive Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 8 and Figure 9
in the other modes.
Reset value = 0000 0000b
Bit addressable
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4190B–8051–02/08
Table 7. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
RSTD
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic Description
7
SMOD1
Serial Port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial Port Mode bit 0 for UART
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
RSTD
Reset Detector Disable Bit
Clear to disable PFD.
Set to enable PFD.
4
POF
Power-off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
3
GF1
General-purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General-purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-down Mode bit
Cleared by hardware when reset occurs.
Set to enter Power-down mode.
0
IDL
Idle Mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset value = 0001 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
32
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AT8xC5111
Table 8. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
Baud Rate Run Control bit
Clear to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3
TBCK
Transmission Baud rate Generator Selection bit for UART
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK
Reception Baud Rate Generator Selection bit for UART
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
0
SRC
Description
Baud Rate Speed Control bit for UART
Clear to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source Select bit in Mode 0 for UART
Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset value = XXX0 0000b
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4190B–8051–02/08
AT8xC5111
Serial Port Interface
(SPI)
The Serial Peripheral Interface (SPI) module which allows full-duplex, synchronous,
serial communication between the MCU and peripheral devices, including other MCUs.
Features
Features of the SPI module include the following:
Signal Description
•
Full-duplex, three-wire synchronous transfers
•
Master operation
•
Eight programmable Master clock rates
•
Serial clock with programmable polarity and phase
•
Master Mode fault error flag with MCU interrupt capability
•
Write collision flag protection
Figure 12 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices:
Figure 1. Typical SPI bus
Slave 4
MISO
MOSI
SCK
SS
Slave 1
VDD
Slave 3
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
0
1
2
3
MISO
MOSI
SCK
SS
PORT
Master
MISO
MOSI
SCK
SS
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one byte on the serial lines.
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
drive the network. The Master may select each Slave device by software through port
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4190B–8051–02/08
pins (see Figure 12). To prevent bus conflicts on the MISO line, only one slave should
be selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error Conditions).
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128, or an external clock.
Table 28 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 1. SPI Master Baud Rate Selection
35
SPR2:SPR1:SPR0
Clock Rate
Baud Rate Divisor (BD)
000
FCkIdle /2
2
001
FCkIdle /4
4
010
FCkIdle/8
8
011
FCkIdle/16
16
100
FCkIdle /32
32
101
FCkIdleH /64
64
110
FCkIdle /128
128
111
External clock
Output of BRG
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 13 shows a detailed structure of the SPI module.
Functional Description
Figure 2. SPI Module Block Diagram
Internal Bus
SPDAT
Shift Register
CkIdle
Clock
Divider
7
/2
/4
/8
/16
/32
/64
/128
6
5
4
2
1
0
Receive Data Register
Pin
Control
Logic
Clock
Logic
Clock
Select
External Clk
3
MOSI
MISO
M
S
SCK
SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI
Control
SPI Interrupt Request
8-bit Bus
1-bit Signal
SPSTA
SPIF WCOL
Operating Modes
-
MODF
-
-
-
-
The Serial Peripheral Interface can be configured as Master mode only. The configuration and initialization of the SPI module is made through one register:
•
The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
•
SPCON
•
The Serial Peripheral STAtus register (SPSTA)
•
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO).
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 14).
36
4190B–8051–02/08
Figure 3. Full-Duplex Master-slave Interconnection
8-bit Shift register
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SS
8-bit Shift register
SCK
SS
VDD
Master MCU
VSS
Slave MCU
The SPI operates in Master mode. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the
Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under
the control of the serial clock, SCK. Simultaneously, another byte shifts in from the
Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral
transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes
set, the received byte from the Slave is transferred to the receive data register in
SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA)
with the SPIF bit set, and then reading the SPDAT.
Master Mode
When the pin SS is pulled down during a transmission, the data is interrupted and when
the transmission is established again, the data present in the SPDAT is present.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL (1) ) and the Clock PHAse
(CPHA(1)). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 15 and Figure 16).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
Figure 4. Data Transmission Format (CPHA = 0)
SCK Cycle Number
1
2
3
4
5
6
7
8
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
Capture Point
1.
37
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 16 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 17). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
Figure 5. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
MOSI (from Master)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
MISO (from Slave)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to Slave)
Capture Point
Figure 15 shows the first SCK edge is the MSB capture strobe. Therefore, the Slave
must begin driving its data before the first SCK edge, and a falling edge on the SS pin is
used to start the transmission. The SS pin must be toggled high and then low between
each byte transmitted (Figure 17).
Figure 6. CPHA/SS Timing
MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
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4190B–8051–02/08
Error Conditions
The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
•
An SPI receiver/error CPU interrupt request is generated.
•
The SPEN bit in SPCON is cleared. This disables the SPI.
•
The MSTR bit in SPCON is cleared.
The MODF flag is set when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master is attempting to drive the network. In this case, clearing the MODF bit is accomplished by a read of SPSTA register
with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be
restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition
An overrun condition occurs when the Master device tries to send several data bytes
and the Slave device has not cleared the SPIF bit issuing from the previous data byte
transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
Interrupts
Two SPI status flags can generate a CPU interrupt request:
Table 2. SPI Interrupts
Flag
Request
SPIF (SP data transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF generates receiver/error CPU interrupt
requests.
39
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 18 gives a logical view of the above statements.
Figure 7. SPI Interrupt Requests Generation
SPIF
SPI Transmitter
CPU Interrupt Request
MODF
SPI
CPU Interrupt Request
SPI Receiver/Error
CPU Interrupt Request
SSDIS
40
4190B–8051–02/08
Registers
There are three registers in the module that provide control, status and data storage
functions. These registers are described in the following paragraphs.
Serial Peripheral Control
Register (SPCON)
The Serial Peripheral Control Register does the following:
•
Selects one of the Master clock rates
•
Selects serial clock polarity and phase
•
Enables the SPI module
Table 30 describes this register and explains the use of each bit:
Table 3. Serial Peripheral Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
–
–
CPOL
CPHA
SPR1
SPR0
Bit
Number
Bit
Mnemonic
R/W Mode
Description
7
SPR2
RW
6
SPEN
RW
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate
Serial Peripheral Enable
Clear to disable the SPI interface
Set to enable the SPI interface
5
-
RW
4
-
RW
3
CPOL
RW
Reserved
Leave this Bit at 0.
Reserved
Leave this Bit at 1.
Clock Polarity
Clear to have the SCK set to ’0’ in idle state
Set to have the SCK set to ’1’ in idle low
Clock Phase
2
CPHA
RW
Clear to have the data sampled when the SPSCK leaves the idle
state (see CPOL)
Set to have the data sampled when the SPSCK returns to idle
state (see CPOL)
Serial Peripheral Rate (SPR2:SPR1:SPR0)
000: FCkIdle /2
1
SPR1
RW
001: FCkIdle /4
010: FCkIdle /8
011: FCkIdle /16
100: FCkIdle /32
0
SPR0
RW
101: FCkIdle /64
110: FCkIdle /128
111: External clock, output of BRG
Reset value = 00010100b
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4190B–8051–02/08
AT8xC5111
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions.
•
Data transfer complete
•
Write collision
•
Inconsistent logic level on SS pin (mode fault error)
Table 31 describes the SPSTA register and explains the use of every bit in the register:
Table 4. Serial Peripheral Status and Control Register
7
6
5
4
3
2
1
0
SPIF
WCOL
-
MODF
-
-
-
-
Bit
Number
Bit
Mnemonic
R/W
Mode
Description
Serial Peripheral data transfer flag
7
SPIF
R
Cleared by hardware to indicate data that transfer is in progress or has
been approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
6
WCOL
R
Cleared by hardware to indicate that no collision has occurred or has
been approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5
-
RW
Reserved
The value read from this bit is indeterminate. Do not set this bit
Mode Fault
4
MODF
R
Cleared by hardware to indicate that the SS pin is at appropriate logic
level, or has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic
level
3
-
RW
2
-
RW
1
-
RW
0
-
RW
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reset value = 00X0XXXXb
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4190B–8051–02/08
Serial Peripheral Data Register
(SPDAT)
The Serial Peripheral Data Register (Table 32) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer
is available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 5. Serial Peripheral Data Register
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset value = XXXX XXXXb
R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
43
•
Do not change SPR2, SPR1 and SPR0
•
Do not change CPHA and CPOL
•
Do not change MSTR
•
Clearing SPEN would immediately disable the peripheral
•
Writing to the SPDAT will cause an overflow
AT8xC5111
4190B–8051–02/08
AT8xC5111
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•
Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
•
Oscillator frequency ÷ 4 (÷ 2 in X2 mode)
•
Timer 0 overflow
•
External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•
rising and/or falling edge capture
•
software timer
•
high-speed output
•
pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA PWM
Mode", page 53).
When the compare/capture modules are programmed in the capture mode, software
timer, or high-speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
PCA Component
External I/O Pin
16-bit Counter
P1.2/ECI
16-bit Module 0
P1.3/CEX0
16-bit Module 1
P1.4/CEX1
16-bit Module 2
P1.5/CEX2
16-bit Module 3
P1.6/CEX3
16-bit Module 4
P1.7/CEX4
The PCA timer is a common time base for all five modules (see Figure 19). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see
Table 33) and can be programmed to run at:
•
1/12 the oscillator frequency. (Or 1/6 in X2 Mode).
•
1/4 the oscillator frequency. (Or 1/2 in X2 Mode).
•
The Timer 0 overflow.
•
The input on the ECI pin (P1.2).
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4190B–8051–02/08
Figure 1. PCA Timer/Counter
To PCA
Modules
Fosc /12
Fosc/4
CH
T0 OVF
overflow
CL
It
16-bit Up/Down Counter
P1.2
CIDL
WDTE
CF
CR
CPS1 CPS0
ECF
CMOD
0xD9
CCF2 CCF1
CCF0
CCON
0xD8
Idle
CCF4 CCF3
Table 1. CMOD: PCA Counter Mode Register - CMOD Address 0D9H
7
6
5
4
3
2
1
0
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
7
CIDL
6
WDTE
5
-
Not implemented, reserved for future use. (1)
4
-
Not implemented, reserved for future use.
3
-
Not implemented, reserved for future use.
Description
Counter Idle control:
CIDL = 0 programs the PCA Counter to continue functioning during idle Mode.
CIDL = 1 programs it to be gated off during idle.
Watchdog Timer Enable:
WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1
enables it.
CPS1
2
CPS1
1
CPS0
0
ECF
CPS0
Selected PCA input (2)
0
0
Internal clock fosc/12 ( Or fosc/6 in X2 Mode).
0
1
Internal clock fosc/4 ( Or fosc/2 in X2 Mode).
1
0
Timer 0 Overflow
1
1
External clock at ECI/P1.2 pin (max rate = fosc/ 8)
PCA Count Pulse Select bit 0.
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to
generate an interrupt. ECF = 0 disables that function of CF.
Reset value = 00XXX00
1.
2.
45
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1.The value read from a reserved bit is
indeterminate.
fosc = oscillator frequency
AT8xC5111
4190B–8051–02/08
AT8xC5111
The CMOD SFR includes three additional bits associated with the PCA (See Figure 19
and Table 33).
•
The CIDL bit which allows the PCA to stop during idle mode.
•
The WDTE bit which enables or disables the watchdog function on module 4.
•
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer
(CF) and each module (see Table 34).
•
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
Table 2. CCON: PCA Counter Control Register
CCON Address OD8H
7
6
5
4
3
2
1
0
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
1.
Bit
Mnemonic Description
7
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or
software but can only be cleared by software.
6
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be
cleared by software to turn the PCA counter off.
5
-
4
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
3
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
2
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
1
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
0
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs.
Must be cleared by software.
Not implemented, reserved for future use (1).
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
The watchdog timer function is implemented in module 4 (see Figure 22).
46
4190B–8051–02/08
The PCA interrupt system is shown in Figure 20 below.
Figure 2. PCA Interrupt System
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
PCA Timer/Counter
Module 0
Module 1
To Interrupt
priority decoder
Module 2
Module 3
Module 4
CMOD.0
ECF
ECCFn CCAPMn.0
IE.6
EC
IE.7
EA
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•
16-bit Capture, positive-edge triggered
•
16-bit Capture, negative-edge triggered
•
16-bit Capture, both positive and negative-edge triggered
•
16-bit Software Timer
•
16-bit High-speed Output
•
8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 35). The
registers contain the bits that control the mode that each module will operate in.
47
•
The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•
PWM (CCAPMn.1) enables the pulse width modulation mode.
•
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
•
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
AT8xC5111
4190B–8051–02/08
AT8xC5111
•
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
Table 35 shows the CCAPMn settings for the various PCA functions.
Table 3. CCAPMn: PCA Modules Compare/Capture Control Registers
CAPMn Address n = 0 - 4
7
6
5
4
3
2
1
0
-
ECOMn
CAPPn
CAPn
MATn
TOGn
PWMm
ECCFn
Bit
Number
Bit
Mnemonic
7
-
6
ECOMn
Enable Comparator. ECOMn = 1 enables the comparator function.
5
CAPPn
Capture Positive, CAPPn = 1 enables positive edge capture.
4
CAPNn
Capture Negative, CAPNn = 1 enables negative edge capture.
3
MATn
Match. When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
2
TOGn
Toggle. When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the CEXn pin to toggle.
1
PWMn
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a
pulse width modulated output.
0
ECCFn
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register
to generate an interrupt.
Description
Not implemented, reserved for future use. (1)
Reset value = X000000
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
Table 4. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn
CAPNn
MATn
TOGn
PWMm
ECCFn Module Function
0
0
0
0
0
0
0
No Operation
X
1
0
0
0
0
X
16-bit capture by a positive-edge
trigger on CEXn
X
0
1
0
0
0
X
16-bit capture by a negative trigger
on CEXn
X
1
1
0
0
0
X
16-bit capture by a transition on
CEXn
1
0
0
1
0
0
X
16-bit Software Timer/Compare
mode.
1
0
0
1
1
0
X
16-bit High-speed Output
1
0
0
0
0
1
0
8-bit PWM
1
0
0
1
X
0
X
Watchdog Timer (module 4 only)
48
4190B–8051–02/08
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (See Table 37 &
Table 38)
Table 5. CCAPnH: PCA Modules Capture/Compare Registers High
CCAPnH Address
n=0-4
CCAP0H = 0FAH
CCAP1H = 0FBH
CCAP2H = 0FCH
CCAP3H = 0FDH
CCAP4H = 0FEH
Reset value
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 6. CCAPnL: PCA Modules Capture/Compare Registers Low
CCAPnL Address
n=0-4
CCAP0L = 0EAH
CCAP1L = 0EBH
CCAP2L = 0ECH
CCAP3L = 0EDH
CCAP4L = 0EEH
Reset value
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Table 7. CH: PCA Counter High
CH
Address 0F9H
Reset value
Table 8. CL: PCA Counter Low
CL
Address 0E9H
Reset value
49
AT8xC5111
4190B–8051–02/08
AT8xC5111
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(see Figure 21).
Figure 3. PCA Capture Mode
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0 CCON
0xD8
PCA IT
PCA Counter/Timer
Cex.n
CH
CL
CCAPnH
CCAPnL
Capture
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4
0xDA to 0xDE
50
4190B–8051–02/08
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 22).
16-bit Software Timer/
Compare Mode
Figure 4. PCA Compare Mode and PCA Watchdog Timer
CCON
CF
Write to
CCAPnL
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
Match
16-bit Comparator
CH
RESET (1)
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CIDL
Note:
WDTE
CPS1 CPS0
ECF
CCAPMn, n = 0 to 4
0xDA to 0xDE
CMOD
0xD9
1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
51
AT8xC5111
4190B–8051–02/08
AT8xC5111
High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (see Figure 23).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
Figure 5. PCA High-speed Output Mode
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
Enable
CCAPnL
16-bit Comparator
CH
Match
CEXn
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn
MATn
TOGn
PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
Pulse Width Modulator
Mode
All of the PCA modules can be used as PWM outputs. Figure 24 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than, the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
52
4190B–8051–02/08
Figure 6. PCA PWM Mode
Overflow
CCAPnH
CCAPnL
“0”
Enable
8-bit Comparator
CEXn
<
>
“1”
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn
MATn
TOGn
PWMn ECCFn
CCAPMn, n = 0 to 4
0xDA to 0xDE
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 22 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer
2. Periodically change the PCA timer value so it will never match the compare values or
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
53
AT8xC5111
4190B–8051–02/08
AT8xC5111
Analog-to-Digital
Converter (ADC)
This section describes the on-chip 10-bit analog-to-digital converter of the
T89C51RB2/RC2. Eight ADC channels are available for sampling of the external
sources AN0 to AN7. An analog multiplexer allows the single ADC to select one of the 8
ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC.
Three kind of conversions are available:
•
Standard conversion (7-8 bits).
•
Precision conversion (8-9 bits).
•
Accurate conversion (10 bits).
For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start
the conversion. The chip is in a pseudo-idle mode, the CPU doesn’t run but the peripherals are always running. This mode allows digital noise to be lower, to ensure precise
conversion.
For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start
the conversion. The chip is in a quiet mode, the AD is the only peripheral running. This
mode allows digital noise to be as low as possible, to ensure high precision conversion.
For these modes it is necessary to work with end of conversion interrupt, which is the
only way to wake up the chip.
If another interrupt occurs during the precision conversion, it will be treated only after
this conversion is ended.
Features
ADC I/O Functions
•
8 channels with multiplexed inputs
•
10-bit cascaded potentiometric ADC
•
Conversion time down to 10 micro-seconds
•
Zero Error (offset) ± 2 LSB max
•
External Positive Reference Voltage Range 2.4 to VCC
•
ADCIN Range 0 to VCC
•
Integral non-linearity typical 1 LSB, max. 2 LSB (with 0.9*VCC<VREF<VCC)
•
Differential non-linearity typical 0.5 LSB, max. 1 LSB (with 0.9*VCC<VREF<VCC)
•
Conversion Complete Flag or Conversion Complete Interrupt
•
Selected ADC Clock
AINx are general I/Os that are shared with the ADC channels. The channel select bits in
ADCF register define which ADC channel pin will be used as ADCIN. The remaining
ADC channels pins can be used as general purpose I/Os or as the alternate function
that is available. Writes to the port register which aren’t selected by the ADCF will not
have any effect.
54
4190B–8051–02/08
Figure 1. ADC Description
ADCON.5
ADCON.3
ADEN
ADSST
ADC
Interrupt
Request
ADCON.4
ADEOC
CONTROL
CONV_CK
EADC
AIN0/P4.0
000
AIN1/P4.1
001
AIN2/P4.2
010
AIN3/P4.3
011
AIN4/P4.4
100
AIN5/P4.5
101
AIN6/P4.6
110
AIN7/P4.7
111
IE1.1
ADCIN
8
ADDH
2
ADDL
+
SAR
-
AVSS
Sample and Hold
10
R/2R DAC
VAGND
ADCON.5
SCH2
SCH1
SCH0
ADCON.2
ADCON.1
ADCON.0
ADEN
Vref
VADREF
Figure 26 shows the timing diagram of a complete conversion. For simplicity, the figure
depicts the waveforms in idealized form and does not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC
Characteristics” of the AT8xC5111 datasheet.
Figure 2. Timing Diagram
CONV_CK
ADEN
TSETUP
ADSST
TCONV
ADEOC
Note:
55
Tsetup = 4 µs
AT8xC5111
4190B–8051–02/08
AT8xC5111
ADC Operation
Before starting a conversion, the A/D converter must be enabled, by setting the ADEN
bit, for at least Tsetup (four microseconds).
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
From the ADSST set, the first full CONV_CK period will be the sampling period for the
ADC; during this period, the switch is closed and the capacitor is being charged. At the
end of the first period, the switch opens and the capacitor is no longer being charged.
During the next 10 CONV_CK periods, the sample and hold will be in hold mode during
the conversion. The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the A/D conversion, it is cleared by hardware. When
a conversion is running, this flag can be read only, a write has no effect.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an
interrupt occur when flag ADEOC is set (see Figure 28). Clear this flag for re-arming the
interrupt.
From this point, if you keep starting a new conversion by resetting ADSST without
changing ADEN, it is not necessary to wait Tsetup.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Before starting normal power reduction modes the ADC conversion has to be completed.
Table 1. Selected Analog Input
Voltage Conversion
SCH2
SCH1
SCH0
Selected Analog Input
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
When the ADCIN is equal to VAREF, the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range.
56
4190B–8051–02/08
Clock Selection
The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in
the AC characteristics section. A prescaler is featured (ADCCLK) to generate the
CONV_CK clock from the oscillator frequency.
Figure 3. A/D Converter Clock
CONV_CK
CKADC
/2
Prescaler ADCLK
A/D
Converter
The conversion frequency CONV_CK is derived from the oscillator frequency with the
following formulas:
FCkAdc = FOscOut/(512 - 2*CKRL) , if X2 = 0
= FOscOut
, if X2 = 1
and
FCONV_CK = FCkAdc/(2*PRS), if PRS > 0
FCONV_CK = FCkAdc/256, if PRS = 0
Some examples can be found in the table below:
ADC Standby Mode
FOscOut
FCkAdc
FCONV_CK
MHz
X2
CKRL
Mhz
ADCLK
khz
Conversion
time µs
16
0
FF
8
12
333
33
16
1
NA
16
32
250
44
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register.
In this mode the power dissipation is about 1 µW.
Voltage Reference
The Vref pin is used to enter the voltage reference for the A/D conversion.
Best accuracy is obtained with 0.9 VCC < VREF < VCC.
IT ADC Management
An interrupt end-of-conversion will occur when the bit ADEOC is activated and the bit
EADC is set. To re-arm the interrupt the bit ADEOC must be cleared by software.
Figure 4. ADC Interrupt Structure
ADCI
ADEOC
ADCON.2
EADC
IE1.1
57
AT8xC5111
4190B–8051–02/08
AT8xC5111
Registers
Table 2. ADCON Register
ADCON (S:F3h)
ADC Control Register
7
6
5
4
3
2
1
0
QUIETM
PSIDLE
ADEN
ADEOC
ADSST
SCH2
SCH1
SCH0
Bit Number
Bit Mnemonic
Description
7
QUIETM
Pseudo Idle mode (best precision)
Set to put in quiet mode during conversion.
Cleared by hardware after completion of the conversion.
6
PSIDLE
Pseudo Idle mode (good precision)
Set to put in idle mode during conversion.
Cleared by hardware after completion of the conversion.
5
ADEN
Enable/Standby Mode
Set to enable ADC.
Clear for Standby mode (power dissipation 1 µW).
4
ADEOC
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can
generate an interrupt.
Must be cleared by software.
3
ADSST
Start and Status
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion.
2-0
SCH2:0
Selection of channel to convert
See Table 41.
Reset value = X000 0000b
Table 3. ADCLK Register
ADCLK (S:F2h)
ADC Clock Prescaler
7
6
5
4
3
2
1
0
-
PRS 6
PRS 5
PRS 4
PRS 3
PRS 2
PRS 1
PRS 0
Bit Number
Bit Mnemonic
7
–
6-0
PRS6:0
Description
Reserved
Leave this bit at 0.
Clock Prescaler
fCONV_CK = fCkADC/(2 * PRS)
if PRS = 0, fCONV_CK = fCkADC/256
Reset value = 0000 0000b
58
4190B–8051–02/08
Table 4. ADDH Register
ADDH (S:F5h Read Only)
ADC Data High byte register
7
6
5
4
3
2
1
0
ADAT 9
ADAT 8
ADAT 7
ADAT 6
ADAT 5
ADAT 4
ADAT 3
ADAT 2
Bit Number
Bit Mnemonic Description
7-0
ADC result
Bits 9 - 2
ADAT9:2
Read only register
Reset value = 00h
Table 5. ADDL Register
ADDL (S:F4h Read Only)
ADC Data Low byte register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ADAT 1
ADAT 0
Bit Number
Bit Mnemonic
7-6
-
1-0
ADAT1:0
Description
Reserved
The value read from these bits are indeterminate. Do not set these bits.
ADC result
Bits 1 - 0
Read only register
Reset value = xxxx xx00b
Table 6. ADCF Register
ADCF (S:F6h)
ADC Input Select Register
7
6
5
4
3
2
1
0
SEL7
SEL6
SEL5
SEL4
SEL3
SEL2
SEL1
SEL0
Bit Number Bit Mnemonic Description
7-0
59
SEL7 - 0
Select Input 7 - 0
Set to select bit 7 - 0 as possible input for A/D
Cleared to leave this bit free for other function
AT8xC5111
4190B–8051–02/08
AT8xC5111
Interrupt System
The AT8xC5111 has a total of 8 interrupt vectors: two external interrupts (INT0 and
INT1), two timer interrupts (timers 0, 1), serial port interrupt, PCA, SPI and A/D. These
interrupts are shown in Figure 29.
Figure 1. Interrupt Control System
High Priority
Interrupt
IPH, IP
3
INT0
IE0
0
3
TF0
0
Interrupt
Polling
Sequence
3
INT1
IE1
0
3
TF1
0
CF
3
PCA
0
CCFx
RI
TI
3
0
3
NC
0
3
SPI
0
3
ADC
0
Individual
Enable
Global
Disable
Low Priority
Interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 49). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority register (See Table 51) and in the
Interrupt Priority High register (see Table 53). Table 47 shows the bit values and priority
levels associated with each combination.
60
4190B–8051–02/08
Table 1. Priority Bit Level Values
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 2. Address Vectors
61
Interrupt Name
Interrupt Address Vector
Priority Number
External Interrupt (INT0)
0003h
1
Timer0 (TF0)
000Bh
2
External Interrupt (INT1)
0013h
3
Timer1 (TF1)
001Bh
4
PCA (CF or CCFn)
0033h
5
UART (RI or TI)
0023h
6
SPI
004Bh
8
ADC
0043h
9
AT8xC5111
4190B–8051–02/08
AT8xC5111
Table 3. IE0 Register
IE0 - Interrupt Enable Register (A8H)
7
6
5
4
3
2
1
0
EA
EC
-
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
7
EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
6
EC
PCA Interrupt Enable
Clear to disable the the PCA interrupt.
Set to enable the the PCA interrupt.
5
-
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset value = 00X0 0000b
Bit addressable
62
4190B–8051–02/08
Table 4. IE1 Register
IE1 (S:B1H) - Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
-
-
-
ESPI
EADC
-
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
ESPI
SPI Interrupt Enable bit
Clear to disable the SPI interrupt.
Set to enable the SPI interrupt.
1
EADC
A/D Interrupt Enable bit
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset value = XXXX X00Xb
No Bit addressable
63
AT8xC5111
4190B–8051–02/08
AT8xC5111
Table 5. IPL0 Register
IPL0 - Interrupt Priority Register (B8H)
7
6
5
4
3
2
1
0
-
PPC
-
PS
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
7
-
6
PPC
5
-
4
PS
Serial port Priority bit
Refer to PSH for priority level.
3
PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Counter Interrupt Priority bit
Refer to PPCH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset value = X0X0 0000b
Bit addressable.
64
4190B–8051–02/08
Table 6. IPL1 Register
IPL1 - Interrupt Priority Low Register 1 (S:B2H)
7
6
5
4
3
2
1
0
-
-
-
-
-
PSPI
PADC
-
Bit
Number
Bit
Mnemonic Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
-
6
-
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
PSPI
SPI Interrupt Priority level less significant bit.
Refer to PSPIH for priority level.
1
PADC
ADC Interrupt Priority level less significant bit.
Refer to PADCH for priority level.
0
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset value = XXXX X00Xb
Not Bit addressable.
65
AT8xC5111
4190B–8051–02/08
AT8xC5111
Table 7. IPH0 Register
IPH0 - Interrrupt Priority High Register
7
6
5
4
3
2
1
0
-
PPCH
-
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
7
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Counter Interrupt Priority level most significant bit
6
5
PPCH
-
PPCH
PPC
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority High bit
PS Priority Level
PSH
4
PSH
0
0
0
1
1
1
0
1
Lowest
Highest
Timer 1 overflow interrupt Priority High bit
3
PT1H
PT1H
PT1
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
External interrupt 1 Priority High bit
PX1
Priority Level
PX1H
2
PX1H
0
0
0
1
1
1
0
1
Lowest
Highest
Timer 0 overflow interrupt Priority High bit
1
PT0H
PT0H
PT0
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
External interrupt 0 Priority High bit
0
PX0H
PX0H
PT0
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
Reset value = X0X0 0000b
Not bit addressable
66
4190B–8051–02/08
Table 8. IPH1 Register
IPH1 - Interrupt High Register 1 (B3H)
7
6
5
4
3
2
1
0
-
-
-
-
-
PSPIH
PADCH
-
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Priority level most significant bit
2
PSPIH
PSP1H
PSP1
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
ADC Interrupt Priority level most significant bit
1
0
PADCH
-
PADCH
PADC
Priority Level
0
0
Lowest
0
1
1
1
0
1
Highest
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset value = XXXX X00Xb
Not bit addressable
67
AT8xC5111
4190B–8051–02/08
AT8xC5111
ROM
The AT83C5112 ROM memory is divided in three different arrays:
ROM Structure
•
The code array: ................................................................................4K Bytes
•
The encryption array: .......................................................................64 bytes
•
The signature array:..........................................................................4 bytes
•
ROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Within the ROM array there are 64 bytes of encryption array. Every time a byte is
addressed during program verify, 6 address lines are used to select a byte of the
encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the
unprogrammed state, will return the code in its original, unmodified form.
Encryption Array
When using the encryption array, one important factor needs to be considered. If a byte
has the value FFh, verifying the byte will produce the encryption byte value. If a large
block (>64 bytes) of code is left unprogrammed, a verification routine will display the
content of the encryption array. For this reason all the unused code bytes should be programmed with random values.
The configuration byte is a special register. Its content, described in paragraph
Section “Registers”, page 10 is defined by the diffusion mask in the ROM version or written by the OTP programmer in the OTP version.
Configuration Byte
The lock bits when programmed according to Table 55 will provide different levels of
protection for the on-chip code and data.
Table 1. Program Lock Bits
Program Lock Bits
Security
Level
LB1
LB2
1
U
U
No program lock features enabled. Code verify will still be encrypted by the encryption array if
programmed. MOVC instruction returns non encrypted data.
2
P
U
Same as 1
3
U
P
Notes:
Protection Description
Same as 2, also verify is disabled.
This security level is available because ROM integrity will be verified thanks to another method*.
1. U: unprogrammed
2. P: programmed
*Warning: When security bit is set, ROM contend cannot be verified. Only the CRC is verified.
Signature Bytes
The T80C5111 contains 4 factory programmed signatures bytes. To read these bytes,
perform the process described in Section “Signature Bytes Content”, page 69.
Verify Algorithm
Refer to Section “Verify Algorithm”, page 68.
Program Code Mapping
As there is no external capability in LPC packages, the code size is limited to 4K Bytes.
Any access above 4K will be mapped in the first 4K segment (0XXXh).
68
4190B–8051–02/08
AT8xC5111
EPROM
EPROM Programming
Specific algorithm is implemented, use qualified device programmers from third party
vendors.
EPROM Erasure
(Windowed Packages
Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality.
Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an
integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of
12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient.
An exposure of 1 hour is recommended with most of standard erasers.
Erasure leaves all the EPROM cells in a 1’s state (FF).
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have
wavelengths in this range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this type of exposure, it is suggested
that an opaque label be placed over the window.
Signature Bytes
Signature Bytes Content
The AT8xC5111 has four signature bytes in location 30h, 31h, 60h and 61h. To read
these bytes follow the procedure for EPROM signature bytes reading. Table 56. shows
the content of the signature byte for the AT8xC5111.
Table 1. Signature Bytes Content
Location
Contents
Comment
30h
58h
Manufacturer Code: Atmel
31h
57h
Family Code: C51 X2
60h
2Eh
Product name: AT8xC5111 4K ROM version
60h
AEh
Product name: AT8xC5111 4K OTP version
61h
EFh
Product revision number: AT8xC5111 Rev.0
69
4190B–8051–02/08
Configuration Byte
The configuration byte is a special register. Its content is defined by the diffusion mask
in the ROM version or is read or written by the OTP programmer in the OTP version.
This register can also be accessed as a read only register.
Table 2. Configuration Byte - CONF (EFh)
7
6
5
4
3
2
1
0
LB1
LB2
LB3
1
1
1
1
1
Bit Number
7:5
4
3
2
1
0
Bit Mnemonic Description
-
Program memory lock bits
See previous chapter for the definition of these bits.
-
Reserved
Leave this bit at 1.
-
Reserved
Leave this bit at 1.
-
Reserved
Leave this bit at 1.
-
Reserved
Leave this bit at 1.
-
Reserved
Leave this bit at 1.
Reset value = 1111 111X
70
AT8xC5111
4190B–8051–02/08
AT8xC5111
Electrical Characteristics
Absolute Maximum Ratings (1)
C = Commercial.................................................... 0°C to 70°C
Notes:
I = Industrial ....................................................... -40°C to 85°C
Storage Temperat ure .................................... -65°C to +150°C
Voltage on VCC to VSS ...........................................-0.5V to +7V
Voltage on VPP to VSS .........................................-0.5V to +13V
Voltage on Any Pin to VSS...................................... -0.5V to VCC +0.5V
1. Stresses at or above those listed under “ Absolute
Maximum Rat ings” may cause permanent damage to the device. This is a stress rat ing only and
functional operat ion of the device at these or any
other conditions above those indicat ed in the
operat ional sections of this specificat ion is not
implied. Exposure to absolute maximum rat ing
conditions may affect device reliability.
2. This value is based on the maximum allowable
die temperat ure and the thermal resistance of the
package.
Power Dissipat ion .......................................................... 1 W(2)
Power Consumption
Measurement
Since the introduction of the first C51 devices, every manufacturer made operat ing ICC
measurements under reset, which made sense for the designs were the CPU was running under reset. In our new devices, the CPU is no longer active during reset, so the
power consumption is very low but is not really representat ive of what will happen in the
customer system. That ’s why, while keeping measurements under Reset, we present a
new way to measure the operat ing ICC:
Using an internal test ROM, the following code is executed:
Label:
SJMP Label (80 FE)
Ports 1, 3, 4 are disconnected, RST = VCC, XTAL2 is not connected and XTAL1 is driven
by the clock.
This is much more representat ive of the real operat ing ICC.
71
4190B–8051–02/08
DC Parameters for Standard Voltage
Table 1. DC Parameters in Standard Voltage
TA = -40°C to +85°C; VSS = 0 V; VCC = 5V ± 10%
Symbol
Parameter
Min
VIL
Input Low Voltage
-0.5
0.2 VCC - 0.1
V
VIH
Input High Voltage except XTAL1, RST
0.2 VCC +
0.9
VCC + 0.5
V
VIH1
Input High Voltage, XTAL1, RST
0.7 VCC
VCC + 0.5
V
0.3
V
VOL
Output Low Voltage, ports 1, 3, 4.(6)
0.45
V
IOL = 1.6 mA
1.0
V
IOL = 3.5 mA
VOH
Output High Voltage, ports 1, 3, 4.(6)
mode pseudo bidirectionnel
Output High Voltage, ports 1, 3, 4.(6)
VOH2
Mode Push pull
Logic 0 Input Current ports 1, 3 and 4
ILI
Unit
V
VCC - 0.7
V
VCC - 1.5
V
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
6
RST Pullup Resistor
IIL
Max
VCC - 0.3
Off impedance, ports 1, 3, 4.
RRST
Typ
50
90 (5)
Test Conditions
IOL = 100 µA
IOH = -10 µA
IOH = -30 µA
IOH = -60 µA
VCC = 5V ± 10%
IOH = -100 µA
IOH = -1.6 mA
IOH = -3.2 mA
VCC = 5V ± 10%
MΩ
200
-50
kΩ
VIN = 0.45V, port 1 & 3
TBD
µA
Input Leakage Current
±10
µA
0.45V < VIN < VCC
ITL
Logic 1 to 0 Transition Current, ports 1, 3, 4
-650
µA
VIN = 2.0 V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power-down Current
20 (5)
50
µA
2.0V < VCC < 5.5V (3)
to be
confirmed
3+ 0.4 Freq
(MHz)
5.8 at 12 MHz
to be
confirmed
ICC
under
Power Supply Current Maximum values, X1 mode
(7)
RESET
7.4 at 16 MHz
ICC
operat
ing
ICC
idle
Power Supply Current Maximum values, X1 mode
to be
confirmed
(7)
3 + 0.6 Freq
(MHz)
10.2 at 12 MHz
mA
mA
12.6 at 16 MHz
Power Supply Current Maximum values, X1 mode
to be
confirmed
(7)
3 + 0.3 Freq
(MHz)
3.9 at 12 MHz
mA
VIN = 0.45V, port 4
VCC = 5.5V (1)
VCC = 5.5V(8)
VCC = 5.5V(2)
5.1 at 16 MHz
ICC
operat
ing
VRET
72
to be
confirmed
Power Supply Current OSCB
Supply voltage during power-down mode
2
6
VCC = 5.5V(8),
mA
at 12 MHz
V
AT8xC5111
4190B–8051–02/08
AT8xC5111
DC Parameters for Low Voltage
Table 2. DC Parameters in Standard Voltage
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 to 5.5V
Symbol
Parameter
Min
VIL
Input Low Voltage
-0.5
0.2 VCC - 0.1
V
VIH
Input High Voltage except XTAL1, RST
0.2 VCC +
0.9
VCC + 0.5
V
VIH1
Input High Voltage, XTAL1, RST
0.7 VCC
VCC + 0.5
V
0.3
V
IOL = 100 µA
VOL
Output Low Voltage, ports 1, 3, 4.(6)
0.45
V
IOL = 0.8mA
1.0
V
IOL = 1.6mA
VCC - 0.3
V
IOH = -10 µA
VCC - 0.7
V
IOH = -30 µA
VCC - 1.5
V
IOH = -60 µA
VCC - 0.3
V
IOH = -100 µA
VCC - 0.7
V
IOH = -0.8 mA
VCC - 1.5
V
IOH = -1.6 mA
VOH
VOH2
Output High Voltage, ports 1, 3, 4.(6)
mode pseudo bi-directionnal
Output High Voltage, ports 1, 3, 4.(6)
Mode Push pull
Off impedance, ports 1, 3, 4.
RRST
RST Pullup Resistor
IIL
Logic 0 Input Current ports 1, 3 and 4
ILI
Typ
Max
6
50
90
Unit
Test Conditions
MΩ
(5)
200
-50
kΩ
VIN = 0.45V, port 1 & 3
TBD
µA
Input Leakage Current
±10
µA
0.45V < VIN < VCC
ITL
Logic 1 to 0 Transition Current, ports 1, 3, 4
-650
µA
VIN = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 1 MHz
TA = 25°C
IPD
Power-down Current
20(5)
50
µA
2.0V < VCC < 5.5V (3)
TBD
1.5+ 0.2 Freq (MHz)
3.4 at 12 MHz
to be
confirmed
ICC
under
Power Supply Current Maximum values, X1 mode(7)
4.2 at 16 MHz
RESET
ICC
operat
ing
ICC
idle
Power Supply Current Maximum values, X1 mode(7)
TBD
1.5 + 0.3 Freq (MHz)
5.1 at 12 MHz
6.3 at 16 MHz
Power Supply Current Maximum values, X1 mode(7)
TBD
1.5 + 0.15 Freq (MHz)
2 at 12 MHz
2.6 at 16 MHz
mA
mA
mA
ICC
operat
ing
VRET
Notes:
Power Supply Current OSCB
Supply voltage during power-down mode
TBD
2
3
VIN = 0.45V, port 4
VCC = 3.3v (1)
VCC = 3.3V(8)
VCC = 3.3V(2)
VCC = 3.3V(8),
mA
at 12MHz
V
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 34.), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; VPP = RST = VCC. ICC would be slightly higher if a crystal oscillat or used
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; VPP = RST = VSS (see Figure 32.).
3. Power-down ICC is measured with all output pins disconnected; VPP = VSS; XTAL2 NC.; RST = VSS (see Figure 33.).
4. Not Applicable.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperat ure and
5V.
73
4190B–8051–02/08
6. If IOL exceeds the test condition, VOL may exceed the relat ed specificat ion. Pins are not guaranteed to sink current great er
than the listed test conditions.
7. For other values, please contact your sales office.
8. Operat ing ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 34.), VIL =
VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; RST/VPP = VCC;. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be
slightly higher if a crystal oscillat or is used. Measurements are made with OTP products when possible, which is the worst
case.
Figure 1. ICC Test Condition, Under Reset
VCC
ICC
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 2. Operat ing ICC Test Condition
VCC
ICC
Reset = VSS after a high pulse
during at least 24 clock cycles
VCC
VCC
RST
(NC)
CLOCK
SIGNAL
74
XTAL2
XTAL1
VSS
All other pins are disconnected.
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 3. ICC Test Condition, Idle Mode
VCC
ICC
VCC
Reset = VSS after a high pulse
during at least 24 clock cycles
VCC
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
Figure 4. ICC Test Condition, Power-Down Mode
VCC
ICC
Reset = VSS after a high pulse
during at least 24 clock cycles
VCC
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 5. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.7VCC
0.45V
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
75
4190B–8051–02/08
DC Parameters for A/D
Converter
TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 5.5V .
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7V to 5.5V .
Table 3. DC Parameters
Symbol Parameter
Min
Resolution
AVIN
Analog input voltage
RREF
Resistance between VREF
and Vss
Cai
Analog input Capacitance
60
Integral non-linearity
1
0.5
Offset error
Input source impedance
Max
10
Vss - 0.2
13
Differential non-linearity
76
Typ
-2
18
Unit
Test Conditions
bit
Vcc + 0.2
V
24
kΩ
pF
During sampling
2
lsb
0.9 Vcc< VREF <
Vcc
1
lsb
0.9 Vcc< VREF <
Vcc
2
lsb
0.9 Vcc< VREF <
Vcc
1
kΩ
For 10-bit
resolution at
maximum speed
AT8xC5111
4190B–8051–02/08
AT8xC5111
AC Parameters
Explanat ion of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “t” (that stands for
Time). The other characters, depending on their positions, stand for the name of a signal or the logical stat us of that signal. The following is a list of all the characters and
what they stand for.
Example:TXHDV = Time from clock rising edge to input dat a valid.
TA = -40°C to +85°C (industrial temperat ure range); VSS = 0V; 2.7V < VCC < 5.5V ; -L
range.
Table 61. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings
will be guaranteed if these capacitances are respected. Higher capacitance values can
be used, but timings will then be degraded.
Table 4. Load Capacitance Versus Speed Range, in pF
-L
Port 1, 3 & 4
80
Table 63 gives the description of each AC symbols.
Table 64. gives for each range the AC parameter.
Table 65. gives the frequency derat ing formula of the AC parameter. To calculat e each
AC symbols, take the x value corresponding to the speed grade you need ( -L) and
replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 5. Max frequency for Derat ing Formula Regarding the Speed Grade
-L X1 Mode, VCC = 5V -L X2 Mode, VCC = 5V -L X1 Mode, VCC = 3V -L X2 Mode, VCC = 3V
Freq (MHz)
40
33
40
20
T (ns)
25
30
25
50
Example:
TXHDV in X2 mode for a -L part at 20 MHz (T = 1/20E6 = 50 ns):
x = 133 (Table 65)
T = 50 ns
TXHDV = 5T - x = 5 x 50 - 133 = 117 ns
77
4190B–8051–02/08
Serial Port Timing - Shift
Register Mode
Table 6. Symbol Description
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output dat a set-up to clock rising edge
TXHQX
Output dat a hold after clock rising edge
TXHDX
Input dat a hold after clock rising edge
TXHDV
Clock rising edge to input dat a valid
Table 7. AC Parameters for a Fix Clock
-L (VCC = 5V)
-L (VCC = 5V)
-L (VCC = 3V)
-L (VCC = 3V)
X2 mode
Standard Mode
40 MHz
X2 Mode
Standard Mode
40 MHz
33 MHz
Speed
33 MHz
66 MHz equiv.
Symbol
Min
TXLXL
180
300
300
300
ns
TQVHX
100
200
200
200
ns
TXHQX
10
30
30
30
ns
TXHDX
0
0
0
0
ns
TXHDV
Max
66 MHz equiv.
Min
Max
17
Min
117
Max
Min
Max
17
Units
117
ns
Table 8. AC Parameters for a Variable Clock: Derat ing Formula
78
Symbol
Type
Standard
Clock
X2 Clock
-L (Vcc =
5V)
-L (Vcc =
3V)
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
ns
TXHDX
Min
x
x
0
0
ns
TXHDV
Max
10 T - x
5 T- x
133
133
ns
Units
ns
AT8xC5111
4190B–8051–02/08
AT8xC5111
Shift Register Timing
Waveforms
Figure 6. Shift Register Timing Waveforms
0
INSTRUCTION
1
2
3
4
5
6
7
8
TXLXL
CLOCK
TQVXH
TXHQX
0
OUTPUT DATA
WRITE to SBUF
INPUT DATA
1
2
3
4
5
6
7
TXHDX
TXHDV
VALID
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Table 9. External Clock Drive Characteristics (XTAL1)
Symbol
Parameter
Min
Max
Units
TCLCL
Oscillat or Period
25
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
TCHCX/TCLCX
Cyclic ratio in X2 mode
40
External Clock Drive
Waveforms
Figure 7. External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1 V
TCHCL
TCLCX
TCLCL
TCHCX
TCLCH
79
4190B–8051–02/08
A/D Converter
Symbol
Parameter
Min
TConv
Conversion time
TSetup
Setup time
FConv_Ck
Max
4
Clock Conversion frequency
10
Units
Clock periods (1 for
sampling, 10 for
conversion)
11
Sampling frequency
Notes:
Typ
µs
1100(1)
kHz
100
kHz
1. For 10 bits resolution
AC Testing Input/Output
Waveforms
Figure 8. AC Testing Input/Output Waveforms
VCC-0.5V
INPUT/OUTPUT
0.2VCC+0.9
0.2VCC-0.1
0.45V
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Figure 9. Float Waveforms
FLOAT
VOH-0.1 V
VOL+0.1 V
VLOAD
VLOAD+0.1 V
VLOAD-0.1 V
For timing purposes as port pin is no longer float ing when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20mA.
Clock Waveforms
80
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2
divided by two.
AT8xC5111
4190B–8051–02/08
AT8xC5111
Figure 10. Clock Waveforms
TXD (MODE 0)
SERIAL PORT SHIFT CLOCK
(INCLUDES INT0, INT1, TO, T1)
MOV DEST PORT (P1, P3, P4)
RXD SAMPLED
RXD SAMPLED
P1, P3, P4 PINS
SAMPLED
P1, P3, P4 PINS
SAMPLED
OLD DATA
NEW DATA
PORT OPERATION
XTAL2
CLOCK
INTERNAL
P1P2
STATE4
P1P2
STATE5
P1P2
STATE6
P1P2
STATE1
P1P2
STATE2
P1P2
STATE3
P1P2
STATE4
P1P2
STATE5
Figure 39 indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagat
ion also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximat ely 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
81
4190B–8051–02/08
AT8xC5111
Ordering Information
Table 1. Maximum Clock Frequency
Code
-L (Vcc = 5V)
-L (Vcc = 3V)
Standard Mode, oscillator frequency
40
Standard Mode, internal frequency
40
40
40
33
20
66
40
X2 Mode, oscillator frequency
X2 Mode, internal equivalent
frequency
Unit
MHz
MHz
Table 2. Possible Order Entries
Part Number
Memory Size
(Bytes)
Supply Voltage
Temperature
Range
Max
Frequency
(MHz)
Package
Packing
AT87C5111-3ZSIL
AT87C5111-TDSIL
AT87C5111-TDRIL
AT87C5111-ICSIL
AT87C5111-ICRIL
AT83C5111-3ZSIL
OBSOLETE
AT83C5111-TDSIL
AT83C5111-TDRIL
AT83C5111-ICSIL
AT83C5111-ICRIL
82
4190B–8051–02/08
Package Drawings
DIL24
83
AT8xC5111
4190B–8051–02/08
AT8xC5111
SO24
84
4190B–8051–02/08
SSOP24
85
AT8xC5111
4190B–8051–02/08
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4190B–8051–02/08
/xM