8/16-bit Atmel XMEGA A3BUMicrocontroller ATxmega256A3BU Features ® ® ® z High-performance, low-power Atmel AVR XMEGA 8/16-bit Microcontroller z Nonvolatile program and data memories 256KBytes of in-system self-programmable flash 8KBytes boot section z 4KBytes EEPROM z 16KBytes internal SRAM z z z Peripheral features z z z z z z z z z z z z z z z z Four-channel DMA controller Eight-channel event system Seven 16-bit timer/counters z Four timer/counters with four output compare or input capture channels z Three timer/counters with two output compare or input capture channels z High resolution extension on all timer/counters z Advanced waveform extension (AWeX) on one timer/counter One USB device interface z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant z 32 Endpoints with full configuration flexibility Six USARTs with IrDA support for one USART Two two-wire interfaces with dual address match (I2C and SMBus compatible) Two serial peripheral interfaces (SPIs) AES and DES crypto engine CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator 32-bit real time counter (RTC) with separate oscillator and battery backup system Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters One two-channel, 12-bit, 1msps Digital to Analog Converter Four Analog Comparators with window compare function, and current sources External interrupts on all general purpose I/O pins Programmable watchdog timer with separate on-chip ultra low power oscillator QTouch® library support z Capacitive touch buttons, sliders and wheels z Special microcontroller features Power-on reset and programmable brown-out detection Internal and external clock options with PLL and prescaler z Programmable multilevel interrupt controller z Five sleep modes z Programming and debug interfaces z JTAG (IEEE 1149.1 compliant) interface, including boundary scan z PDI (Program and Debug Interface) z z z I/O and packages 47 programmable I/O pins 64-lead TQFP z 64-pad QFN z z z Operating voltage z 1.6 – 3.6V z Operating frequency z z 0 – 12MHz from 1.6V 0 – 32MHz from 2.7V Atmel-8362 G-AVR-ATxmega-07/2014 1. Ordering Information Ordering code Flash (bytes) EEPROM (bytes) SRAM (bytes) Speed (MHz) Power supply Package (1)(2)(3) 256K + 8K 4K 16K 32 1.6 - 3.6V 64A Temp. ATxmega256A3BU-AU ATxmega256A3BU-AUR (4) -40°C-85°C ATxmega256A3BU-MH ATxmega256A3BU-MHR (4) Notes: 1. 2. 3. 4. 256K + 8K 4K 16K 32 1.6 - 3.6V 64M2 This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. For packaging information, see “Packaging information” on page 67. Tape and reel. Package type 64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 64M2 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN) Typical Applications Industrial control Climate control Low power battery applications Factory automation RF and ZigBee® Power tools Building control USB connectivity HVAC Board control Sensor control Utility metering White goods Optical Medical applications XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 2 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout. Power Ground Programming, debug, test PA3 RESET/PDI PDI PF7 PF6 VCC GND VBAT PF4 PF3 56 55 54 53 52 51 50 49 GND 60 57 AVCC 61 PR0 PA0 62 58 PA1 63 PR1 PA2 64 59 External clock / Crystal pins General Purpose I /O Digital function Analog function / Oscillators Port R 1 48 PF2 47 PF1 46 PF0 45 VCC 44 GND 43 TOSC1 42 TOSC2 41 PE5 40 PE4 39 PE3 38 PE2 37 PE1 36 PE0 35 VCC 34 GND 33 PD7 XOSC 2 PA5 3 PA6 4 PA7 5 DATA BUS OSC/CLK Control Internal oscillators Watchdog oscillator Power Supervision Sleep Controller Real Time Counter Watchdog Timer Reset Controller Event System Controller Crypto / CRC OCD Prog/Debug Interface AREF Port A PA4 ADC AC0:1 Notes: TOSC USART0 TC0:1 32 PD6 29 PD3 31 28 PD2 PD5 27 PD1 30 26 PD0 PD4 TWI USART0 TC0:1 SPI USB 25 Port F VCC Port E 24 Port D GND Port C USART0:1 TC0:1 16 23 PC0 PC7 15 22 VCC EVENT ROUTING NETWORK PC6 14 DATA BUS 21 GND Battery Backup PC5 13 SRAM 20 PB7 EEPROM PC4 12 FLASH IRCOM PB6 JTAG 19 11 AC0:1 PC3 PB5 DMA Controller CPU 18 10 Internal references DAC PC2 PB4 Port B 9 ADC 17 PB3 1. 2. AREF 8 BUS matrix PC1 PB2 Interrupt Controller SPI 7 TWI PB1 USART0:1 6 TC0:1 PB0 For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 3 3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device achieves CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A3BU devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmable multilevel interrupt controller; 47 general purpose I/O lines; 32-bit real-time counter (RTC) with battery backup system; seven flexible 16-bit Timer/Counters with compare modes and PWM; one full speed USB 2.0 interface; six USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16channel, 12-bit ADCs with programmable gain; one 2-channel 12-bit DAC; four analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip debug and programming. The XMEGA A3BU devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 4 3.1 Block Diagram Figure 3-1. XMEGA A3BU block diagram. PR[0..1] Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock XTAL1 General purpose I/O XTAL2 Oscillator Circuits/ Clock Generation PORT R (2) Watchdog Oscillator DATA BUS PA[0..7] PORT A (8) Watchdog Timer Event System Controller Oscillator Control DMA Controller ADCA AREFA Sleep Controller GND RESET/ PDI_CLK PDI Prog/Debug Controller BUS Matrix VCC Power Supervision POR/BOD & RESET SRAM ACA PDI_DATA VCC/10 Int. Refs. AES Tempref JTAG OCD AREFB PORT B DES Interrupt Controller CPU ADCB CRC ACB USARTF0 PORT B (8) Flash TCF0 EEPROM DACB IRCOM PORT F (7) NVM Controller PF[0..4,6..7] DATA BUS PC[0..7] PORT D (8) PD[0..7] TWIE TCE0:1 USARTE0 USB SPID TCD0:1 USARTD0:1 SPIC PORT C (8) TWIC TCC0:1 EVENT ROUTING NETWORK USARTC0:1 PB[0..7]/ JTAG Real Time Counter Battery Backup Controller 32.768 kHz XOSC VBAT Power Supervision VBAT PORT E (6) PE[0..5] TOSC1 TOSC2 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 5 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading z Atmel AVR XMEGA AU manual z XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentations are available from www.atmel.com/avr. 5. Capacitive touch sensing The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide also available for download from the Atmel website. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 6 6. AVR CPU 6.1 Features z 8/16-bit, high-performance Atmel AVR RISC CPU z z 142 instructions Hardware multiplier z 32x8-bit registers directly connected to the ALU z Stack in RAM z Stack pointer accessible in I/O memory space z Direct addressing of up to 16MB of program memory and 16MB of data memory z True 16/24-bit access to 16/24-bit I/O registers z Efficient support for 8-, 16-, and 32-bit arithmetic z Configuration change protection of system-critical features 6.2 Overview All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel Interrupt Controller” on page 28. 6.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 6-1. Block diagram of the AVR CPU architecture. Register File R31 (ZH) R29 (YH) R27 (XH) R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 R30 (ZL) R28 (YL) R26 (XL) R24 R22 R20 R18 R16 R14 R12 R10 R8 R6 R4 R2 R0 Program Counter Flash Program Memory Instruction Register Instruction Decode Data Memory Stack Pointer Status Register ALU XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 7 The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory. 6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: z Multiplication of unsigned integers z Multiplication of signed integers z Multiplication of a signed integer with an unsigned integer z Multiplication of unsigned fractional numbers z Multiplication of signed fractional numbers z Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 8 6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 6.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 13. 6.8 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes: z One 8-bit output operand and one 8-bit result input z Two 8-bit output operands and one 8-bit result input z Two 8-bit output operands and one 16-bit result input z One 16-bit output operand and one 16-bit result input XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 9 Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. 7. Memories 7.1 Features z Flash program memory z z z z z z z z One linear address space In-system programmable Self-programming and boot loader support Application section for application code Application table section for application code or data storage Boot section for application code or boot loader code Separate read/write protection lock bits for all sections Built in fast CRC check of a selectable flash program memory section z Data memory z z z z z z z One linear address space Single-cycle access from CPU SRAM EEPROM z Byte and page accessible z Optional memory mapping for direct load and store I/O memory z Configuration and status registers for all peripherals and modules z 16 bit-accessible general purpose registers for global variables or flags Bus arbitration z Deterministic priority handling between CPU, DMA controller, and other bus masters Separate buses for SRAM, EEPROM and I/O memory z Simultaneous bus access for CPU and DMA controller z Production signature row memory for factory programmed data ID for each microcontroller device type Serial number for each device z Calibration bytes for factory calibrated peripherals z z z User signature row One flash page in size Can be read and written from software z Content is kept after chip erase z z 7.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 10 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash Program Memory (Hexadecimal address). Word Address 0 Application Section (256K) ... 1EFFF 7.3.1 1F000 Application Table Section 1FFFF (8K) 20000 Boot Section 20FFF (8K) Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 7.3.2 Application Table Section The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 7.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. 7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 11 corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics” on page 69. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes for Atmel AVR XMEGA A3BU devices. Device ATxmega256A3BU 7.3.5 Device ID bytes Byte 2 Byte 1 Byte 0 43 98 1E User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 Fuses and Lock bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, JTAG enable, and JTAG user ID. The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 7.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 12 Figure 7-2. Data memory map (Hexadecimal address). Byte Address ATxmega256A3BU 0 FFF I/O Registers (4K) 1000 EEPROM (4K) 1FFF 7.6 2000 Internal SRAM 5FFF (16K) EEPROM XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. 7.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules in XMEGA A3BU is shown in the “Peripheral Module Address Map” on page 60. 7.7.1 General Purpose I/O Registers The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing. 7.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 13 7.11 JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins. 7.12 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.13 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 7-2 on page 14 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 7-2. Devices ATxmega256A3B U Number of words and pages in the flash. PC size Flash size Page size [bits] [bytes] [words] 18 256K + 8K 256 FWORD Z[8:1] FPAGE Z[18:9] Application Boot Size No of pages Size No of pages 256K 512 8K 16 Table 7-3 on page 14 shows EEPROM memory organization. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Devices ATxmega256A3BU Number of bytes and pages in the EEPROM. EEPROM Page size size [bytes] 4K 32 E2BYTE E2PAGE No of pages ADDR[4:0] ADDR[11:5] 128 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 14 8. DMAC – Direct Memory Access Controller 8.1 Features z Allows high speed data transfers with minimal CPU intervention from data memory to data memory from data memory to peripheral z from peripheral to data memory z from peripheral to peripheral z z z Four DMA channels with separate transfer triggers interrupt vectors z addressing modes z z z Programmable channel priority z From 1 byte to 16MB of data in a single transaction z z Up to 64KB block transfers with repeat 1, 2, 4, or 8 byte burst transfers z Multiple addressing modes Static Incremental z Decremental z z z Optional reload of source and destination addresses at the end of each Burst Block z Transaction z z z Optional interrupt on end of transaction z Optional connection to CRC generator for CRC on DMA data 8.2 Overview The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers. The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM. Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger DMA transfers. The four DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the DMA controller detects an error on a DMA channel. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 15 9. Event System 9.1 Features z System for direct peripheral-to-peripheral communication and signaling z Peripherals can directly send, receive, and react to peripheral events CPU and DMA controller independent operation 100% predictable signal timing z Short and guaranteed response time z z z Eight event channels for up to eight different and parallel signal routing configurations z Events can be sent and/or used by most peripherals, clock system, and software z Additional functions include z z Quadrature decoders Digital filtering of I/O pin state z Works in active mode and idle sleep mode 9.2 Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules. A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure 9-1 on page 17 shows a basic diagram of all connected peripherals. The event system can directly connect together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be generated from software and the peripheral clock. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 16 Figure 9-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network ADC AC clkPER Prescaler Real Time Counter Event System Controller Timer / Counters DAC USB Port pins IRCOM The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 17 10. System Clock and Clock options 10.1 Features z Fast start-up time z Safe run-time clock switching z Internal oscillators: 32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator z 32.768kHz calibrated oscillator z 32kHz ultra low power (ULP) oscillator with 1kHz output z z z External clock options 0.4MHz - 16MHz crystal oscillator 32.768kHz crystal oscillator z External clock z z z PLL with 20MHz - 128MHz output frequency z z Internal and external clock options and 1x to 31x multiplication Lock detector z Clock prescalers with 1x to 2048x division z Fast peripheral clocks running at two and four times the CPU clock z Automatic run-time calibration of internal oscillators z External oscillator and PLL lock failure detection with optional non-maskable interrupt 10.2 Overview Atmel AVR XMEGA A3BU devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 10-1 on page 19 presents the principal clock system in the XMEGA A3BU family of devices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 21 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 18 Figure 10-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkPER2 clkCPU clkPER4 USB clkUSB Brown-out Detector System Clock Prescalers Watchdog Timer Prescaler clkSYS clkRTC System Clock Multiplexer (SCLKSEL) USBSRC DIV1024 PLL PLLSRC 32.768kHz Int. OSC 32.768kHz TOSC 0.4 – 16MHz XTAL 32MHz Int. Osc 2MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 10.3 DIV4 DIV32 DIV32 32kHz Int. ULP XOSCSEL Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 19 10.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 10.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock. 10.3.4 0.4 - 16MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz. 10.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 10.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB clock source. 10.3.7 External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz crystal oscillator. 10.3.8 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 20 11. Power Management and Sleep Modes 11.1 Features z Power management for adjusting power consumption and functions z Five sleep modes Idle Power down z Power save z Standby z Extended standby z z z Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 11.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 11.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will wake the device. 11.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 21 11.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 11.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 22 12. System Control and Reset 12.1 Features z Reset the microcontroller and set it to initial state when a reset source goes active z Multiple reset sources that cover different situations z z z z z z Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset z Asynchronous operation z No running system clock in the device is required for reset z Reset status register for reading the reset source from the application code 12.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 12.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again: z Reset counter delay z Oscillator startup z Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. 12.4 Reset Sources 12.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 23 12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 12.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25. 12.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 12.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 24 13. WDT – Watchdog Timer 13.1 Features z Issues a device reset if the timer is not reset before its timeout period z Asynchronous operation from dedicated oscillator z 1kHz output of the 32kHz ultra low power oscillator z 11 selectable timeout periods, from 8ms to 8s z Two operation modes: z z Normal mode Window mode z Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 25 14. Battery Backup System 14.1 Features z Battery Backup voltage supply from dedicated VBAT power pin for: One Ultra Low-power 32-bit Real Time Counter (RTC) One 32.768kHz crystal oscillator with failure detection monitor z Two Backup Registers z z z Typical power consumption of 500nA with Real Time Counter running z Automatic switching from main power to battery backup power at: z Brown-Out Detection (BOD) reset z Automatic switching from battery backup power to main power: z z 14.2 Device reset after Brown-Out Reset (BOR) is released Device reset after Power-On Reset (POR) and BOR is released Overview Atmel AVR XMEGA family is already running in an ultra low leakage process with power-save current consumption below 2µA with RTC, BOD and watchdog enabled. Still, for some applications where time keeping is important, the system would have one main battery or power source used for day to day tasks, and one backup battery power for the time keeping functionality. The Battery Backup System includes functionality that enable automatic power switching between main power and a battery backup power. Figure 14-1 on page 27 shows an overview of the system. The Battery Backup Module support connection of a backup battery to the dedicated VBAT power pin. This will ensure power to the 32-bit Real Time Counter, a 32.768kHz crystal oscillator with failure detection monitor and two backup registers, when the main battery or power source is unavailable. Upon main power loss the device will automatically detect this and the Battery Backup Module will switch to be powered from the VBAT pin. After main power has been restored and both main POR and BOR are released, the Battery Backup Module will automatically switch back to be powered from main power again. The 32-bit real time counter (RTC) must be clocked from the 1Hz output of a 32.768kHz crystal oscillator connected between the TOSC1 and TOSC2 pins when running from VBAT. For more details on the 32-bit RTC refer to the “RTC32 – 32-bit Real-Time Counter” on page 39“. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 26 Figure 14-1. Battery Backup Module and its power domain implementation. VBAT VBAT power supervisor Power switch Main power supervision Watchdog w/ Oscillator OCD & Programming Interface Oscillator & sleep controller VDD XTAL1 XTAL2 TOSC1 Crystal Oscillator TOSC2 RTC Level shifters / Isolation Failure monitor CPU & Peripherals Internal RAM GPIO FLASH, EEPROM & Fuses Backup Registers XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 27 15. Interrupts and Programmable Multilevel Interrupt Controller 15.1 Features z Short and predictable interrupt response time z Separate interrupt configuration and vector address for each interrupt z Programmable multilevel interrupt controller Interrupt prioritizing according to level and vector address Three selectable interrupt levels for all interrupts: low, medium and high z Selectable, round-robin priority scheme within low-level interrupts z Non-maskable interrupts for critical functions z z z Interrupt vectors optionally placed in the application section or the boot loader section 15.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 15.3 Interrupt vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA A3BU devices are shown in Table 15-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 15-1. The program address is the word address. Table 15-1. Reset and interrupt vectors. Program address (base address) Source 0x000 RESET 0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI) 0x004 PORTC_INT_base Port C interrupt base 0x008 PORTR_INT_base Port R interrupt base 0x00C DMA_INT_base DMA controller interrupt base 0x014 RTC32_INT_base 32-bit Real Time Counter interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on Port C interrupt base Interrupt description XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 28 Program address (base address) Source Interrupt description 0x028 TCC1_INT_base Timer/Counter 1 on Port C interrupt base 0x030 SPIC_INT_vect SPI on Port C interrupt vector 0x032 USARTC0_INT_base USART 0 on Port C interrupt base 0x038 USARTC1_INT_base USART 1 on Port C interrupt base 0x03E AES_INT_vect AES interrupt vector 0x040 NVM_INT_base Non-Volatile Memory interrupt base 0x044 PORTB_INT_base Port B interrupt base 0x048 ACB_INT_base Analog Comparator on Port B interrupt base 0x04E ADCB_INT_base Analog to Digital Converter on Port B interrupt base 0x056 PORTE_INT_base Port E interrupt base 0x05A TWIE_INT_base Two-Wire Interface on Port E interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on Port E interrupt base 0x06A TCE1_INT_base Timer/Counter 1 on Port E interrupt base 0x074 USARTE0_INT_base USART 0 on Port E interrupt base 0x080 PORTD_INT_base Port D interrupt base 0x084 PORTA_INT_base Port A interrupt base 0x088 ACA_INT_base Analog Comparator on Port A interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on Port D interrupt base 0x0A6 TCD1_INT_base Timer/Counter 1 on Port D interrupt base 0x0AE SPID_INT_vector SPI on Port D interrupt vector 0x0B0 USARTD0_INT_base USART 0 on Port D interrupt base 0x0B6 USARTD1_INT_base USART 1 on Port D interrupt base 0x0D0 PORTF_INT_base Port F interrupt base 0x0D8 TCF0_INT_base Timer/Counter 0 on Port F interrupt base 0x0EE USARTF0_INT_base USART 0 on Port F interrupt base 0x0FA USB_INT_base USB on Port D interrupt base XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 29 16. I/O Ports 16.1 Features z 47 general purpose input and output pins with individual configuration z Output driver with configurable driver and pull settings: Totem-pole Wired-AND z Wired-OR z Bus-keeper z Inverted I/O z z z Input with synchronous and/or asynchronous sensing with interrupts and events Sense both edges Sense rising edges z Sense falling edges z Sense low level z z z Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations z Optional slew rate control z Asynchronous pin change sensing that can wake the device from all sleep modes z Two port interrupts with pin masking per I/O port z Efficient and safe access to port pins Hardware read-modify-write through dedicated toggle/clear/set registers Configuration of multiple pins in a single operation z Mapping of port registers into bit-accessible I/O memory space z z z Peripheral clocks output on port pin z Real-time counter clock output to port pin z Event channels can be output on port pin z Remapping of digital peripheral pin functions z Selectable USART, SPI, and timer/counter input/output pin locations 16.2 Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF and PORTR. 16.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 30 16.3.1 Push-pull Figure 16-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 16.3.2 Pull-down Figure 16-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 16.3.3 Pull-up Figure 16-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 16.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 31 Figure 16-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 16.3.5 Others Figure 16-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 16-6. I/O configuration - Wired-AND with optional pull-up. INn Pn OUTn 16.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 16-7 on page 33. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 32 Figure 16-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 16.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 33 17. TC0/1 – 16-bit Timer/Counter Type 0 and 1 17.1 Features z Seven 16-bit timer/counters Four timer/counters of type 0 Three timer/counters of type 1 z Split-mode enabling two 8-bit timer/counter from each timer/counter type 0 z z z 32-bit Timer/Counter support by cascading two timer/counters z Up to four compare or capture (CC) channels z z Four CC channels for timer/counters of type 0 Two CC channels for timer/counters of type 1 z Double buffered timer period setting z Double buffered capture or compare channels z Waveform generation: Frequency generation Single-slope pulse width modulation z Dual-slope pulse width modulation z z z Input capture: Input capture with noise cancelling Frequency capture z Pulse width capture z 32-bit input capture z z z Timer overflow and error interrupts/events z One compare match or input capture interrupt/event per CC channel z Can be used with event system for: Quadrature decoding Count and direction control z Capture z z z Can be used with DMA and to trigger DMA transactions z High-resolution extension z Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) z Advanced waveform extension: z Low- and high-side output with programmable dead-time insertion (DTI) z Event controlled fault protection for safe disabling of drivers 17.2 Overview Atmel AVR XMEGA devices have a set of seven flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 34 Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details. The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution Extension” on page 38 for more details. Figure 17-1. Overview of a Timer/Counter and closely related peripherals. Timer/Counter Base Counter Timer Period Counter Prescaler Control Logic clkPER Event System Buffer Capture Control Waveform Generation DTI Dead-Time Insertion Pattern Generation Fault Protection PORT Comparator AWeX Hi-Res clkPER4 Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 35 18. TC2 – Timer/Counter Type 2 18.1 Features z Eight eight-bit timer/counters z z Four Low-byte timer/counter Four High-byte timer/counter z Up to eight compare channels in each Timer/Counter 2 z z Four compare channels for the low-byte timer/counter Four compare channels for the high-byte timer/counter z Waveform generation z Single slope pulse width modulation z Timer underflow interrupts/events z One compare match interrupt/event per compare channel for the low-byte timer/counter z Can be used with the event system for count control z Can be used to trigger DMA transactions 18.2 Overview There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels. The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down. PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2), TCD2, TCE2 and TCF2, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 36 19. AWeX – Advanced Waveform Extension 19.1 Features z Waveform output with complementary output from each compare channel z Four dead-time insertion (DTI) units 8-bit resolution Separate high and low side dead-time setting z Double buffered dead time z Optionally halts timer during dead-time insertion z z z Pattern generation unit creating synchronised bit pattern across the port pins z z Double buffered pattern generation Optional distribution of one compare channel output across the port pins z Event controlled fault protection for instant and predictable fault triggering 19.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. The AWeX is available for TCC0. The notation of this is AWEXC. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 37 20. Hi-Res – High Resolution Extension 20.1 Features z Increases waveform generator resolution up to 8x (three bits) z Supports frequency, single-slope PWM, and dual-slope PWM generation z Supports the AWeX when this is used for the same timer/counter 20.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 38 21. RTC32 – 32-bit Real-Time Counter 21.1 Features z 32-bit resolution z One 32-bit Compare register z One 32-bit Period register z Clear Timer on overflow z Optional Interrupt/ Event on overflow and compare match z Selectable clock reference z z 1.024kHz 1Hz z Isolated VBAT power domain with dynamic switch over from/to VCC power domain’ 21.1.1 Overview The 32-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is generated from a high accuracy 32.768kHz crystal, and the design is optimized for low power consumption. The RTC typically operate in low power sleep modes, keeping track of time and waking up the device at regular intervals. The RTC input clock can be taken from a 1.024kHz or 1Hz prescaled output from the 32.768kHz reference clock. The RTC will give a compare interrupt request and/or event when the counter value equals the Compare register value. The RTC will give an overflow interrupt request and/or event when the counter value equals the Period register value. Counter overflow will also reset the counter value to zero. The 32-bit Real Time Counter (RTC) must be clocked from the 1Hz output of a 32.768kHz crystal oscillator connected between the TOSC1 and TOSC2 pins when running from VBAT. Figure 21-1. Real Time Counter overview. PER TOSC1 TOSC2 32.768kHz Crystal Osc = Overflow = Compare Match 1.024kHz DIV32 DIV1024 CNT COMP XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 39 22. USB – Universal Serial Bus Interface 22.1 Features z One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface z Integrated on-chip USB transceiver, no external components needed z 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints z z One input endpoint per endpoint address One output endpoint per endpoint address z Endpoint address transfer type selectable to Control transfers Interrupt transfers z Bulk transfers z Isochronous transfers z z z Configurable data payload size per endpoint, up to 1023 bytes z Endpoint configuration and data buffers located in internal SRAM z z Configurable location for endpoint configuration data Configurable location for each endpoint's data buffer z Built-in direct memory access (DMA) to internal SRAM for: z z Endpoint configurations Reading and writing endpoint data z Ping-pong operation for higher throughput and double buffered operation z z Input and output endpoint data buffers used in a single direction CPU/DMA controller can update data buffer during transfer z Multipacket transfer for reduced interrupt load and software intervention z z Data payload exceeding maximum packet size is transferred in one continuous transfer No interrupts or software interaction on packet transaction level z Transaction complete FIFO for workflow management when using multiple endpoints z Tracks all completed transactions in a first-come, first-served work queue z Clock selection independent of system clock source and selection z Minimum 1.5MHz CPU clock required for low speed USB operation z Minimum 12MHz CPU clock required for full speed operation z Connection to event system z On chip debug possibilities during USB transactions 22.2 Overview The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface. The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data payloads up to 1023 bytes. No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 40 Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB. Notation of this is USB. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 41 23. TWI – Two-Wire Interface 23.1 Features z Two Identical two-wire interface peripherals z Bidirectional, two-wire communication interface Phillips I2C compatible z System Management Bus (SMBus) compatible z z Bus master and slave operation supported Slave operation Single bus master operation z Bus master in multi-master bus environment z Multi-master arbitration z z z Flexible slave address match functions 7-bit and general call address recognition in hardware 10-bit addressing supported z Address mask register for dual address match or address range masking z Optional software address recognition for unlimited number of addresses z z z Slave can operate in all sleep modes, including power-down z Slave address match can wake device from all sleep modes z 100kHz and 400kHz bus frequency support z Slew-rate limited output drivers z Input filter for bus noise and spike suppression z Support arbitration between start/repeated start and data bit (SMBus) z Slave arbitration allows support for address resolve protocol (ARP) (SMBus) 23.2 Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 42 24. SPI – Serial Peripheral Interface 24.1 Features z Two identical SPI peripherals z Full-duplex, three-wire synchronous data transfer z Master or slave operation z Lsb first or msb first data transfer z Eight programmable bit rates z Interrupt flag at the end of transmission z Write collision flag to indicate data collision z Wake up from idle sleep mode z Double speed master mode 24.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 43 25. USART 25.1 Features z Six identical USART peripherals z Full-duplex operation z Asynchronous or synchronous operation z z Synchronous clock rates up to 1/2 of the device clock frequency Asynchronous clock rates up to 1/8 of the device clock frequency z Supports serial frames with 5, 6, 7, 8, or 9 data bits and one or two stop bits z Fractional baud rate generator z z Can generate desired baud rate from any system clock frequency No need for external oscillator with certain frequencies z Built-in error detection and correction schemes Odd or even parity generation and parity check Data overrun and framing error detection z Noise filtering includes false start bit detection and digital low-pass filter z z z Separate interrupts for Transmit complete Transmit data register empty z Receive complete z z z Multiprocessor communication mode z z Addressing scheme to address a specific devices on a multidevice bus Enable unaddressed devices to automatically ignore all frames z Master SPI mode z z Double buffered operation Operation up to 1/2 of the peripheral clock frequency z IRCOM module for IrDA compliant pulse modulation/demodulation 25.2 Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps. PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0 and USARTF0, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 44 26. IRCOM – IR Communication Module 26.1 Features z Pulse modulation/demodulation for infrared communication z IrDA compatible for baud rates up to 115.2Kbps z Selectable pulse modulation scheme 3/16 of the baud rate period Fixed pulse period, 8-bit programmable z Pulse modulation disabled z z z Built-in filtering z Can be connected to and used by any USART 26.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 45 27. AES and DES Crypto Engine 27.1 Features z Data Encryption Standard (DES) CPU instruction z Advanced Encryption Standard (AES) crypto module z DES Instruction Encryption and decryption DES supported z Encryption/decryption in 16 CPU clock cycles per 8-byte block z z z AES crypto module Encryption and decryption Supports 128-bit keys z Supports XOR data load mode to the state memory z Encryption/decryption in 375 clock cycles per 16-byte block z z 27.2 Overview The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage. DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block. The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 46 28. CRC – Cyclic Redundancy Check Generator 28.1 Features z Cyclic redundancy check (CRC) generation and checking for Communication data Program or data in flash memory z Data in SRAM and I/O memory space z z z Integrated with flash memory, DMA controller and CPU Continuous CRC on data going through a DMA channel Automatic CRC of the complete or a selectable range of the flash memory z CPU can load data to the CRC generator through the I/O interface z z z CRC polynomial software selectable to z z CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.3) z Zero remainder detection 28.2 Overview A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRCCCITT) and CRC-32 (IEEE 802.3). z z CRC-16: Polynomial: x16+x12+x5+1 Hex value: 0x1021 CRC-32: Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 47 29. ADC – 12-bit Analog to Digital Converter 29.1 Features z Two Analog to Digital Converters (ADCs) z 12-bit resolution z Up to two million samples per second Two inputs can be sampled simultaneously using ADC and 1x gain stage Four inputs can be sampled within 1.5µs z Down to 2.5µs conversion time with 8-bit resolution z Down to 3.5µs conversion time with 12-bit resolution z z z Differential and single-ended input Up to 16 single-ended inputs 16x4 differential inputs without gain z 8x4 differential input with gain z z z Built-in differential gain stage z 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options z Single, continuous and scan conversion options z Four internal inputs Internal temperature sensor DAC output z AVCC voltage divided by 10 z 1.1V bandgap voltage z z z Four conversion channels with individual input control and result registers z Enable four parallel configurations and results z Internal and external reference options z Compare function for accurate monitoring of user defined thresholds z Optional event triggered conversion for accurate timing z Optional DMA transfer of conversion results z Optional interrupt/event on compare result 29.2 Overview The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to two million samples per second (msps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at a low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started while other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay. The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control. The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high data throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 48 Figure 29-1. ADC overview. ADC0 Compare • • • ADC15 ADC0 Internal signals VINP CH0 Result • •• ADC7 ADC4 ADC ½x - 64x • • • ADC7 Int. signals Internal signals < > CH1 Result Threshold (Int Req) CH2 Result CH3 Result VINN ADC0 • •• ADC3 Int. signals Internal 1.00V Internal AVCC/1.6V Internal AVCC/2 AREFA AREFB Reference Voltage Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the application. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs for 12-bit to 2.5µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 49 30. DAC – 12-bit Digital to Analog Converter 30.1 Features z One Digital to Analog Converter (DAC) z 12-bit resolution z Two independent, continuous-drive output channels z Up to one million samples per second conversion rate per DAC channel z Built-in calibration that removes: z z Offset error Gain error z Multiple conversion trigger sources z z On new available data Events from the event system z High drive capabilities and support for Resistive loads Capacitive loads z Combined resistive and capacitive loads z z z Internal and external reference options z DAC output available as input to analog comparator and ADC z Low-power mode, with reduced drive strength z Optional DMA transfer of data 30.2 Overview The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in calibration system can remove offset and gain error when loaded with calibration values from software. Figure 30-1. DAC overview. DMA req (Data Empty) CH0DATA 12 D A T A Select Trigger AVCC Internal 1.00V AREFA AREFB Reference voltage CTRLB Trigger CH1DATA 12 D A T A Output Driver DAC0 Enable CTRLA Select DAC1 Int. driver To AC/ADC Internal Output enable Enable Output Driver DMA req (Data Empty) XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 50 A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC. The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, as well as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or ADC. PORTB has one DAC. Notation of this peripheral is DACB. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 51 31. AC – Analog Comparator 31.1 Features z Four Analog Comparators (AC) z Selectable propagation delay versus current consumption z Selectable hysteresis No Small z Large z z z Analog comparator output available on pin z Flexible input selection All pins on the port Output from the DAC z Bandgap reference voltage z A 64-level programmable voltage scaler of the internal AVCC voltage z z z Interrupt and event generation on: Rising edge Falling edge z Toggle z z z Window function interrupt and event generation on: Signal above window Signal inside window z Signal below window z z z Constant current source with configurable output pin selection 31.2 Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of these parameters may be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 52 Figure 31-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis Enable DAC Voltage Scaler ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 31-2. Figure 31-2. Analog comparator window function. + AC0 Upper limit of window Interrupt sensitivity control Input signal Interrupts Events + AC1 Lower limit of window - XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 53 32. Programming and Debugging 32.1 Features z Programming External programming through PDI or JTAG interfaces z Minimal protocol overhead for fast operation z Built-in error detection and handling for reliable operation z Boot loader support for programming through any communication interface z z Debugging z z z z z z Nonintrusive, real-time, on-chip debug system No software or hardware resources required from device except pin connection Program flow control z Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor Unlimited number of user program breakpoints Unlimited number of user data breakpoints, break on: z Data location read, write, or both read and write z Data location content equal or not equal to a value z Data location content is greater or smaller than a value z Data location content is within or outside a range No limitation on device clock frequency z Program and Debug Interface (PDI) Two-pin interface for external programming and debugging Uses the Reset pin and a dedicated pin z No I/O pins required during programming or debugging z z z JTAG interface z z 32.2 Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG) Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std. 1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 54 33. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 33.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 33.1.1 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage VBAT Battery Backup Module supply voltage GND Ground 33.1.2 Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function 33.1.3 Analog functions ACn Analog Comparator input pin n ACnOUT Analog Comparator n Output ADCn Analog to Digital Converter input pin n DACn Digital to Analog Converter output pin n AREF Analog Reference input pin 33.1.4 Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 33.1.5 Communication functions SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 55 RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB 33.1.6 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 33.1.7 Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin TCK JTAG Test Clock TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 56 33.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 33-1. Port A - alternate functions. PORT A PIN # INTERRUPT ADCA POS/ GAINPOS ADCB POS ADCA NEG ADCA GAINNEG ACA POS ACA NEG GND 60 AVCC 61 PA0 62 SYNC ADC0 ADC8 ADC0 AC0 AC0 PA1 63 SYNC ADC1 ADC9 ADC1 AC1 AC1 PA2 64 SYNC/ASYNC ADC2 ADC10 ADC2 AC2 PA3 1 SYNC ADC3 ADC11 ADC3 AC3 PA4 2 SYNC ADC4 ADC12 ADC4 AC4 PA5 3 SYNC ADC5 ADC13 ADC5 AC5 PA6 4 SYNC ADC6 ADC14 ADC6 AC6 PA7 5 SYNC ADC7 ADC15 ADC7 ACA OUT REFA AREF AC3 AC5 AC1OUT AC7 AC0OUT Table 33-2. Port B - alternate functions. PORT B PIN # INTERRUPT ADCA POS ADCB POS/ GAINPOS ADCB NEG ADCB GAINNEG ACB POS ACB NEG PB0 6 SYNC ADC8 ADC0 ADC0 AC0 AC0 PB1 7 SYNC ADC9 ADC1 ADC1 AC1 AC1 PB2 8 SYNC/ASYNC ADC10 ADC2 ADC2 AC2 PB3 9 SYNC ADC11 ADC3 ADC3 AC3 PB4 10 SYNC ADC12 ADC4 ADC4 AC4 PB5 11 SYNC ADC13 ADC5 ADC5 AC5 PB6 12 SYNC ADC14 ADC6 ADC6 AC6 PB7 13 SYNC ADC15 ADC7 ADC7 GND 14 VCC 15 ACB OUT DACB REFB JTAG AREF DAC0 AC3 DAC1 TMS AC5 AC7 TDI AC1OUT TCK AC0OUT TDO XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 57 Table 33-3. Port C - alternate functions. TCC0 USARTC0 PIN # INTERRUPT (1)(2) AWEXC PC0 16 SYNC OC0A OC0ALS PC1 17 SYNC OC0B OC0AHS XCK0 PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 19 SYNC OC0D OC0BHS TXD0 PC4 20 SYNC OC0CLS OC1A PC5 21 SYNC OC0CH S OC1B PC6 22 SYNC PC7 23 SYNC GND 24 VCC 25 PORT C Notes: 1. 2. 3. 4. 5. 6. TCC1 (3) USARTC1 SPIC (4) CLOCKOUT EVENTOUT (5) (6) TWIC SDA SCL SS XCK1 MOSI OC0DLS RXD1 MISO clkRTC OC0DH S TXD1 SCK clkPER USARTD1 SPID EVOUT Pin mapping of all TC0 can optionally be moved to high nibble of port. If TC0 is configured as TC2 all eight pins can be used for PWM output. Pin mapping of all USART0 can optionally be moved to high nibble of port. Pins MOSI and SCK for all SPI can optionally be swapped. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7. Table 33-4. Port D - alternate functions. PORT D PIN # INTERRUPT TCD0 TCD1 USBD USARTD0 PD0 26 SYNC OC0A PD1 27 SYNC OC0B XCK0 PD2 28 SYNC/ASYNC OC0C RXD0 PD3 29 SYNC OC0D TXD0 PD4 30 SYNC OC1A PD5 31 SYNC OC1B PD6 32 SYNC PD7 33 SYNC GND 34 VCC 35 CLOCKOUT EVENTOUT clkPER EVOUT SS XCK1 MOSI D- RXD1 MISO D+ TXD1 SCK XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 58 Table 33-5. Port E - alternate functions. PORT E PIN # INTERRUPT TCE0 TCE1 USARTE0 PE0 36 SYNC OC0A PE1 37 SYNC OC0B XCK0 PE2 38 SYNC/ASYNC OC0C RXD0 PE3 39 SYNC OC0D TXD0 PE4 40 SYNC OC1A PE5 41 SYNC OC1B TOSC2 42 TOSC1 43 GND 44 VCC 45 TWIE SDA SCL Table 33-6. Port F - alternate functions. PORT F PIN # INTERRUPT TCF0 USARTF0 PF0 46 SYNC OC0A PF1 47 SYNC OC0B XCK0 PF2 48 SYNC/ASYN C OC0C RXD0 PF3 49 SYNC OC0D TXD0 PF4 50 SYNC VBAT 51 GND 52 SYNC VCC 53 SYNC PF6 54 PF7 55 Table 33-7. Port R - alternate functions. PORT R PIN # INTERRUPT PDI XTAL PDI 56 PDI_DATA RESET 57 PDI_CLOCK PRO 58 SYNC XTAL2 PR1 59 SYNC XTAL1 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 59 34. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A3BU. For complete register description and summary for each peripheral module, refer to the XMEGA AU Manual. Table 34-1. Peripheral module address map. Base Address Name Description 0x0000 GPIO General purpose IO registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 2 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32MHz internal oscillator 0x0068 DFLLRC2M DFLL for the 2MHz internal oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch-Dog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable Multilevel Interrupt Controller 0x00B0 PORTCFG Port Configuration 0x00C0 AES AES module 0x00D0 CRC CRC generator 0x00F0 VBAT VBAT Battery Backup module 0x0100 DMA DMA Controller 0x0180 EVSYS Event System 0x01C0 NVM Non Volatile Memory (NVM) Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0240 ADCB Analog to Digital Converter on port B 0x0320 DACB Digital to Analog Converter on port B 0x0380 ACA Analog Comparator pair on port A 0x0390 ACB Analog Comparator pair on port B 0x0420 RTC32 32-bit Real Time Counter 0x0480 TWIC Two-wire Interface on port C 0x04A0 TWIE Two-wire Interface on port E 0x04D0 USBD USB Device 0x0600 PORTA Port A 0x0620 PORTB Port B XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 60 Base Address Name Description 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08B0 USARTC1 USART 1 on port C 0x08C0 SPIC Serial Peripheral Interface on port C 0x08F8 IRCOM Infrared Communication Module 0x0900 TCD0 Timer/Counter 0 on port D 0x0940 TCD1 Timer/Counter 1 on port D 0x0990 HIRESD High Resolution Extension on port D 0x09A0 USARTD0 USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A40 TCE1 Timer/Counter 1 on port E 0x0A80 AWEXE Advanced Waveform Extension on port E 0x0A90 HIRESE High Resolution Extension on port E 0x0AA0 USARTE0 USART 0 on port E 0x0B00 TCF0 Timer/Counter 0 on port F 0x0B90 HIRESF High Resolution Extension on port F 0x0BA0 USARTF0 USART 0 on port F XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 61 35. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2 DES K Data Encryption if (H = 0) then R15:R0 else if (H = 1) then R15:R0 ← ← Encrypt(R15:R0, K) Decrypt(R15:R0, K) PC ← PC + k + 1 None 2 1/2 Branch instructions RJMP k Relative Jump IJMP Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 EIJMP Extended Indirect Jump to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 2 JMP k Jump PC ← k None 3 RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3 (1) XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 62 Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 3 (1) call Subroutine PC ← k None 3 / 4 (1) RET Subroutine Return PC ← STACK None 4 / 5 (1) RETI Interrupt Return PC ← STACK I 4 / 5 (1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2/3/4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2/3/4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr None 1 Rd+1:Rd ← Rr+1:Rr None 1 Rd ← K None 1 Rd - Rr Z,C,N,V,S,H 1 Rd - Rr - C Z,C,N,V,S,H 1 Rd - K Z,C,N,V,S,H 1 Data transfer instructions MOV Rd, Rr Copy Register MOVW Rd, Rr Copy Register Pair LDI Rd, K Load Immediate XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 63 Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd ← (k) None 2 (1)(2) LD Rd, X Load Indirect Rd ← (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X ← ← (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) ← ← X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y ← ← (Y) Y+1 None 1 (1)(2) LD Rd, -Y Load Indirect and Pre-Decrement Y Rd ← ← Y-1 (Y) None 2 (1)(2) LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 (1)(2) LD Rd, Z Load Indirect Rd ← (Z) None 1 (1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd Z ← ← (Z), Z+1 None 1 (1)(2) LD Rd, -Z Load Indirect and Pre-Decrement Z Rd ← ← Z - 1, (Z) None 2 (1)(2) LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 (1)(2) STS k, Rr Store Direct to Data Space (k) ← Rd None 2 (1) ST X, Rr Store Indirect (X) ← Rr None 1 (1) ST X+, Rr Store Indirect and Post-Increment (X) X ← ← Rr, X+1 None 1 (1) ST -X, Rr Store Indirect and Pre-Decrement X (X) ← ← X - 1, Rr None 2 (1) ST Y, Rr Store Indirect (Y) ← Rr None 1 (1) ST Y+, Rr Store Indirect and Post-Increment (Y) Y ← ← Rr, Y+1 None 1 (1) ST -Y, Rr Store Indirect and Pre-Decrement Y (Y) ← ← Y - 1, Rr None 2 (1) STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 (1) ST Z, Rr Store Indirect (Z) ← Rr None 1 (1) ST Z+, Rr Store Indirect and Post-Increment (Z) Z ← ← Rr Z+1 None 1 (1) ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z-1 None 2 (1) STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 (1) Load Program Memory R0 ← (Z) None 3 LPM Operation LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd Z ← ← (Z), Z+1 None 3 Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and PostIncrement Rd Z ← ← (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) ← R1:R0 None - Store Program Memory and Post-Increment by 2 (RAMPZ:Z) Z ← ← R1:R0, Z+2 None - SPM SPM Z+ XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 64 Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 1 (1) Pop Register from Stack Rd ← STACK None 2 (1) Z, Rd Exchange RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp Rd (Z) ← ← ← Rd, (Z), ($FFh – Rd) • (Z) None 2 LAT Z, Rd Load and Toggle RAM location Temp Rd (Z) ← ← ← Rd, (Z), Temp ⊕ (Z) None 2 Rd(n+1) Rd(0) C ← ← ← Rd(n), 0, Rd(7) Z,C,N,V,H 1 Rd(n) Rd(7) C ← ← ← Rd(n+1), 0, Rd(0) Z,C,N,V 1 Rd(0) Rd(n+1) C ← ← ← C, Rd(n), Rd(7) Z,C,N,V,H 1 Bit and bit-test instructions LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry Rd(7) Rd(n) C ← ← ← C, Rd(n+1), Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 65 Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Notes: 1. 2. (See specific descr. for BREAK) Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing Internal SRAM. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 66 36. Packaging information 36.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 13.90 14.00 14.10 E1 B 0.30 – Note 2 Note 2 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE 0.80 TYP 2010-10-20 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. TITLE 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64A XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 REV. C 67 36.2 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW 0.20 REF b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 7.50 7.65 7.80 E 8.90 9.00 9.10 E2 7.50 7.65 7.80 e Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. NOTE 0.50 BSC L 0.35 0.40 0.45 K 0.20 0.27 0.40 2014-05-30 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M2, 64-pad, 9 x 9 x 1.0mm Bod y, Lead Pitch 0.50mm , 7.65mm Exposed Pad, Quad Flat No Lead Package (QFN) DRAWING NO. 64M2 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 REV. F 68 37. Electrical Characteristics All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. Note: 37.1 For devices that are not available yet, preliminary values in this datasheet are based on simulations, and/or characterization of similar AVR XMEGA microcontrollers. After the device is characterized the final values will be available, hence existing values can change. Missing minimum and maximum values will be available after the device is characterized. Absolute Maximum Ratings Stresses beyond those listed in Table 37-1 on page 69 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 37-1. Absolute maximum ratings. Symbol 37.2 Parameter Condition Min. Typ. -0.3 Max. Units 4 V VCC Power supply voltage IVCC Current into a VCC pin 200 IGND Current out of a Gnd pin 200 VPIN Pin voltage with respect to Gnd and VCC -0.5 VCC+0.5 V IPIN I/O pin sink/source current -25 25 mA TA Storage temperature -65 150 Tj Junction temperature 150 mA °C General Operating Ratings The device must operate within the ratings listed in Table 37-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 37-2. General operating conditions. Symbol Parameter Condition Min. Typ. Max. VCC Power supply voltage 1.60 3.6 AVCC Analog supply voltage 1.60 3.6 TA Temperature range -40 85 Tj Junction temperature -40 105 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 Units V °C 69 Table 37-3. Operating voltage and frequency. Symbol Parameter ClkCPU Condition CPU clock frequency Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 37-1 on page 70 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 37-1. Maximum frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.6 V XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 70 37.3 Current consumption Table 37-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle Power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and Sampled BOD enabled, T = 25°C WDT and Sampled BOD enabled, T = 85°C Power-save power consumption (2) Reset power consumption Notes: 1. 2. Min. Typ. Max. VCC = 1.8V 120 VCC = 3.0V 270 VCC = 1.8V 350 VCC = 3.0V 697 VCC = 1.8V 658 700 1.1 1.4 10.6 15 VCC = 3.0V µA VCC = 1.8V 4.3 VCC = 3.0V 4.8 VCC = 1.8V 78 VCC = 3.0V 150 VCC = 1.8V 150 350 290 600 4.7 7.0 0.1 1.0 1.8 5.0 1.3 3.0 3.1 7.0 VCC = 3.0V VCC = 3.0V mA µA mA VCC = 3.0V RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.6 2 VCC = 3.0V 0.7 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.8 3 VCC = 3.0V 1.0 3 VCC = 3.0V 250 Current through RESET pin subtracted Units µA All Power Reduction Registers set. Maximum limits are based on characterization, and not tested in production. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 71 Table 37-5. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. ULP oscillator 1.0 32.768kHz int. oscillator 27 2MHz int. oscillator 32MHz int. oscillator PLL BOD Max. Units 85 DFLL enabled with 32.768kHz int. osc. as reference 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog timer ICC Typ. 460 220 µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.2 Internal 1.0V reference 100 Temperature sensor 95 3.0 ADC DAC AC DMA 250ksps CURRLIMIT = LOW 2.6 VREF = Ext ref CURRLIMIT = MEDIUM 2.1 CURRLIMIT = HIGH 1.6 Normal mode 1.9 Low Power mode 1.1 250ksps VREF = Ext ref No load High Speed Mode 330 Low Power Mode 130 615KBps between I/O registers and SRAM 115 Timer/Counter USART 1. µA 16 Rx and Tx enabled, 9600 BAUD Flash memory and EEPROM programming Note: mA 2.5 4 mA All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are givenAll parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external clock without prescaling, T = 25°C unless other conditions are given. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 72 37.4 Wake-up time from sleep modes Table 37-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Max. Units µs The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 37-2. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 37-2. Wake-up time definition. Wakeup time Wakeup request Clock output XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 73 37.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 37-7. I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.7*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3*VCC VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.3*VCC I/O pin source/sink current IOL (2) VIH High level input voltage VIL Low level input voltage VCC = 3.0 - 3.6V High level output voltage 2.4 0.94*VCC IOH = -1mA 2.0 0.96*VCC IOH = -2mA 1.7 0.92*VCC VCC = 3.3V IOH = -8mA 2.6 2.9 VCC = 3.0V IOH = -6mA 2.1 2.6 VCC = 1.8V IOH = -2mA 1.4 1.6 VCC = 3.0 - 3.6V IOL = 2mA 0.05*VCC 0.4 IOL = 1mA 0.03*VCC 0.4 IOL = 2mA 0.06*VCC 0.7 VCC = 3.3V IOL = 15mA 0.4 0.76 VCC = 3.0V IOL = 10mA 0.3 0.64 VCC = 1.8V IOL = 5mA 0.3 0.46 <0.001 0.1 VCC = 2.3 - 2.7V VOL Low level output voltage Typ. IOH = -2mA VCC = 2.3 - 2.7V VOH Min. IIN Input leakage current RP I/O pin Pull/Bus-keeper resistor 25 Reset pin pull-up resistor 25 RRST tr Notes: Rise time T = 25°C No load V 4 slew rate limitation 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA. The sum of all IOH for PORTC, PORTD, PORTE must for each port not exceed 200mA. The sum of all IOH for pins PF[0-4] on PORTF must not exceed 200mA. The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA. 2. The sum of all IOL for PORTA and PORTB must not exceed 100mA. 7 µA kΩ ns The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA. The sum of all IOL for pins PF[0-4] on PORTF must not exceed 200mA. The sum of all IOL for pins PF[6-7] on PORTF, PORTR and PDI must not exceed 100mA. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 74 37.6 ADC characteristics Table 37-8. Symbol Power supply, reference and input range. Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.0 kΩ Cin Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 MΩ CAREF Reference input capacitance Static load 7 pF VIN Input range Conversion range Differential mode, Vinp - Vinn VIN Conversion range Single ended unsigned mode, Vinp ∆V Fixed offset voltage -0.1 AVCC+0.1 -VREF VREF -ΔV VREF-ΔV 190 V LSB Table 37-9. Clock and timing. Symbol ClkADC fclkADC Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of Peripheral clock frequency 100 2000 Measuring internal signals 100 125 Current limitation (CURRLIMIT) off 100 2000 CURRLIMIT = LOW 100 1500 CURRLIMIT = MEDIUM 100 1000 CURRLIMIT = HIGH 100 500 Sampling Time 1/2 ClkADC cycle 0.25 5 µs Conversion time (latency) (RES+2)/2+(GAIN !=0) RES (Resolution) = 8 or 12 5 8 ClkADC cycles Start-up time ADC clock cycles 12 24 After changing reference or input mode 7 7 After ADC flush 1 1 ADC Clock frequency Sample rate ADC settling time XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 kHz ksps ClkADC cycles 75 Table 37-10. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset Error -1 mV Temperature drift <0.01 mV/K Operating voltage drift <0.6 mV/V External reference -1 AVCC/1.6 10 AVCC/2.0 8 Bandgap ±5 Differential mode Gain Error Noise Notes: 1. 2. lsb mV Temperature drift <0.02 mV/K Operating voltage drift <0.5 mV/V Differential mode, shorted input 2msps, VCC = 3.6V, ClkPER = 16MHz 0.4 mV rms Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. Table 37-11. Gain stage characteristics. Symbol Parameter Condition Min. Typ. Max. Units Rin Input resistance Switched in normal mode 4.0 kΩ Cin Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate Sample rate Same as ADC INL (1) Integral Non-Linearity 500ksps 0 VCC- 0.6 ClkADC cycles 1 100 All gain settings ±1.5 V 1000 kHz ±4 lsb XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 76 Symbol Parameter Gain Error Offset Error, input referred Condition Min. Typ. 1x gain, normal mode -0.8 8x gain, normal mode -2.5 64x gain, normal mode -3.5 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 8x gain, normal mode 64x gain, normal mode Note: 1. 37.7 DAC Characteristics Max. Units % mV 0.5 VCC = 3.6V mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. Table 37-12. Power supply, reference and output range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Rchannel Condition Min. Typ. VCC- 0.3 VCC+ 0.3 1.0 VCC- 0.6 DC output impedance Linear output voltage range RAREF Reference input resistance CAREF Reference input capacitance 0.15 Static load Minimum Resistance load Maximum capacitance load Output sink/source Max. Units V 50 Ω AVCC-0.15 V >10 MΩ 7 pF 1 kΩ 1000Ω serial resistance Operating within accuracy specification 100 pF 1 nF AVCC/1000 Safe operation 10 mA Table 37-13. Clock and timing. Symbol Fclk Parameter Conversion rate Condition Fout=Fclk/4, Cload=100pF, maximum step size Min. 0 Typ. Max. Units 1000 ksps XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 77 Table 37-14. Accuracy characteristics. Symbol RES Parameter Condition Min. Typ. Input Resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error Max. Units 12 Bits VCC = 1.6V ±2.0 ±3 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4 VCC = 3.6V ±1.5 ±4 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±1.0 3.5 VCC = 3.6V ±0.6 1.5 VCC = 1.6V ±4.5 VCC = 3.6V ±4.5 After calibration lsb <4 Gain calibration step size 4 Gain calibration drift VREF= Ext 1.0V <0.2 Offset error After calibration <1 Offset calibration step size mV/K lsb 1 Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range. 37.8 Analog Comparator Characteristics Table 37-15. Analog Comparator characteristics. Symbol Parameter Voff Input offset voltage Ilk Input leakage current Condition Input voltage range Hysteresis, None Vhys2 Hysteresis, Small Vhys3 Hysteresis, Large Typ. Max. Units <±10 mV <1 nA -0.1 AC startup time Vhys1 Min. AVCC 100 V µs 0 mode = High Speed (HS) 13 mode = Low Power (LP) 30 mode = HS 30 mode = LP 60 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 mV 78 Symbol Parameter Condition VCC = 3.0V, T= 85°C tdelay Propagation delay Min. mode = HS mode = HS VCC = 3.0V, T= 85°C Max. 30 90 30 mode = LP 130 mode = LP 37.9 Typ. 500 Units ns 130 Current source calibration range Single mode 2 8 Double mode 4 16 64-Level Voltage Scaler Integral non-linearity (INL) 0.3 0.5 µs lsb Bandgap and Internal 1.0V Reference Characteristics Table 37-16. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC or DAC Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V 0.99 1 Units µs 1.5 Bandgap voltage INT1V Typ. 1.01 ±1.0 V % 37.10 Brownout Detection Characteristics Table 37-17. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD VHYST Min. Typ. Max. 1.60 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Detection time Hysteresis Continuous mode Sampled mode 0.4 1000 1.6 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 Units V µs % 79 37.11 External Reset Characteristics Table 37-18. External reset characteristics. Symbol tEXT Parameter Condition Min. Typ. Max. Units 95 1000 ns Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.70*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.30*VCC V 37.12 Power-on Reset Characteristics Table 37-19. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 37.13 Flash and EEPROM Memory Characteristics Table 37-20. Symbol Parameter Endurance and data retention. Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. 25°C 10K 85°C 10K 105°C 2K 25°C 100 85°C 25 105°C 10 25°C 100K 85°C 100K 105°C 30K 25°C 100 85°C 25 105°C 10 Units Cycle Year Cycle Year XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 80 Table 37-21. Symbol Programming time. Parameter Chip Erase 256KB Flash, EEPROM Application Erase Flash EEPROM Notes: 1. 2. Condition (2) Typ. (1) Min. and SRAM Erase Max. Units 105 ms Section erase 6 ms Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 Page Erase 4 Page Write 4 Atomic Page Erase and Write 8 ms ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 37.14 VBAT and Battery Backup Characteristics Table 37-22. VBAT and battery backup characteristics. Symbol Parameter Condition Vbat supply voltage range Vcc Power-down slope range Typ Vbbbod Monotonic falling BOD threshold voltage Vbbbod Min Max Units 3.6 V 0.1 V/ms 1.8 BBBOD threshold voltage 1.7 2.1 BBBOD detection speed 1 2 Current consumption Powering from VBAT pin RTC from Low Power 32kHz TOSC and XOSC Faillure Monitor enabled VBAT pin leackage Powering Battery Backup module from Vcc 0.6 V s µA 50 nA Max. Units 37.15 Clock and Oscillator Characteristics 37.15.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 37-23. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy User calibration accuracy Typ. 32.768 T = 85°C, VCC = 3.0V kHz -0.5 0.5 -0.5 0.5 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 % 81 37.15.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 37-24. 2MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 1.8 Factory calibrated frequency Factory calibration accuracy Typ. Max. 2.2 Units MHz 2.0 T = 85°C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration stepsize 0.22 37.15.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 37-25. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. 55 MHz 32 T = 85°C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration step size 0.23 37.15.4 32kHz Internal ULP Oscillator characteristics Table 37-26. 32kHz internal ULP oscillator characteristics. Symbol Parameter Condition Min. Output frequency Accuracy Typ. 32 -30 kHz 30 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 % 82 37.15.5 Internal Phase Locked Loop (PLL) characteristics Table 37-27. Internal PLL characteristics. Symbol fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 37.15.6 External clock characteristics Figure 37-3. External clock drive waveform. tCH tCH tCR tCF VIH1 VIL1 tCL tCK Table 37-28. External clock used as system clock without prescaling. Symbol Clock frequency(1) 1/tCK tCK Clock period tCH Clock high time tCL Clock low time tCR Rise time (for maximum frequency) tCF Fall time (for maximum frequency) ΔtCK Note: Parameter Change in period from one clock cycle to the next 1. Condition Min. Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.6V 0 32 VCC = 1.6 - 1.8V 83.3 VCC = 2.7 - 3.6V 31.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 Units MHz ns VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 10 % The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 83 Table 37-29. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.8V 1.5 VCC = 2.7 - 3.6V 1.0 VCC = 1.6 - 1.8V 1.5 VCC = 2.7 - 3.6V 1.0 Change in period from one clock cycle to the next 1. 2. Max. 10 ns ns % System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 37.15.7 External 16MHz crystal oscillator and XOSC characteristics Table 37-30. External 16MHz crystal oscillator and XOSC characteristics. Symbol Parameter Cycle to cycle jitter Condition XOSCPWR=0 Min. FRQRANGE=0 <10 FRQRANGE=1, 2, or 3 <1 XOSCPWR=1 Long term jitter XOSCPWR=0 XOSCPWR=0 FRQRANGE=0 FRQRANGE=1, 2, or 3 XOSCPWR=0 XOSCPWR=1 <6 Units ns <0.5 <0.5 FRQRANGE=0 <0.1 FRQRANGE=1 <0.05 FRQRANGE=2 or 3 <0.005 XOSCPWR=1 Duty cycle Max. <1 XOSCPWR=1 Frequency error Typ. <0.005 FRQRANGE=0 40 FRQRANGE=1 42 FRQRANGE=2 or 3 45 % 48 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 84 Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.2k 8MHz crystal 250 9MHz crystal 195 8MHz crystal 360 9MHz crystal 285 12MHz crystal 155 9MHz crystal 365 12MHz crystal 200 16MHz crystal 105 9MHz crystal 435 12MHz crystal 235 16MHz crystal 125 9MHz crystal 495 12MHz crystal 270 16MHz crystal 145 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 305 16MHz crystal 160 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 380 16MHz crystal 205 XOSCPWR=0, FRQRANGE=0 XOSCPWR=0, FRQRANGE=1, CL=20pF XOSCPWR=0, FRQRANGE=2, CL=20pF Negative impedance (1) RQ XOSCPWR=0, FRQRANGE=3, CL=20pF XOSCPWR=1, FRQRANGE=0, CL=20pF XOSCPWR=1, FRQRANGE=1, CL=20pF ESR Min. Typ. SF = safety factor min(RQ)/SF Parasitic capacitance XTAL1 pin 5.2 CXTAL2 Parasitic capacitance XTAL2 pin 6.8 Parasitic capacitance load 2.95 CLOAD 1. Units Ω CXTAL1 Note: Max. kΩ pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 85 37.15.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 37-31. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin 3.0 CTOSC2 Parasitic capacitance TOSC2 pin 2.9 Parasitic capacitance load 2.0 CL Condition Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 capacitance load matched to crystal specification Units kΩ pF 3.0 See Figure 37-4 for definition. Figure 37-4. TOSC input capacitance. CL1 TOSC1 CL2 Device internal External TOSC2 32.768kHz crystal The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 86 37.16 SPI Characteristics Figure 37-5. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 37-6. SPI timing requirements in slave mode. SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data input) tSIH MSB tSOSSS MISO (Data output) tSSCK LSB tSOS MSB tSOSSH LSB XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 87 Table 37-32. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 22-3 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.5*SCK tMOH MOSI hold after SCK Master 1.0 tSSCK Slave SCK Period Slave 4*t ClkPER tSSCKW SCK high/low width Slave 2*t ClkPER tSSCKR SCK Rise time Slave 1600 tSSCKF SCK Fall time Slave 1600 tSIS MOSI setup to SCK Slave 3 tSIH MOSI hold after SCK Slave t ClkPER tSSS SS setup to SCK Slave 21 tSSH SS hold after SCK Slave 20 tSOS MISO setup SCK Slave 8.0 tSOH MISO hold after SCK Slave 13 tSOSS MISO setup after SS low Slave 11 tSOSH MISO hold after SS high Slave 8.0 Units ns XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 88 37.17 Two-Wire Interface Characteristics Table 37-33 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 377. Figure 37-7. Two-Wire Interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;STA tHD;DAT tSU;STO tSU;DAT SDA tBUF Table 37-33. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC+0.5 VIL Input low voltage 0.5 0.3×VCC Vhys Hysteresis of Schmitt Trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O pin CI Capacitance for each I/O pin fSCL SCL clock frequency 0.05VCC (1) 3mA, sink current 10pF < Cb < 400pF (2) 0.1VCC < VI < 0.9VCC fPER (3)>max(10fSCL, 250kHz) Value of pull-up resistor fSCL > 100kHz V 0 0.4 20+0.1Cb (1)(2) 300 20+0.1Cb (1)(2) 250 0 50 -10 10 µA 10 pF 400 kHz 0 fSCL ≤ 100kHz RP Units V CC – 0,4V ---------------------------3mA 100ns --------------Cb 300ns --------------Cb XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 ns Ω 89 Symbol tHD;STA Parameter Hold Time (repeated) START condition tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock Set-up time for a repeated START condition tSU;STA tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Units µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 90 38. Typical Characteristics 38.1 Current consumption 38.1.1 Active mode supply current ICC [µA] Figure 38-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 3.3V 700 3.0V 600 2.7V 500 2.2V 400 1.8V 300 200 100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [MHz] 0.7 0.8 0.9 1.0 Figure 38-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 14 3.3V 12 3.0V 10 ICC [mA] 2.7V 8 6 2.2V 4 1.8V 2 0 0 4 8 12 16 Frequency [MHz] 20 24 28 32 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 91 Figure 38-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 450 -40°C 400 25°C ICC [µA] 350 85°C 300 250 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 38-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 1000 -40°C 25°C 85°C 900 ICC [µA] 800 700 600 500 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 92 Figure 38-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1800 -40°C 1600 25°C 85°C ICC [µA] 1400 1200 1000 800 600 400 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 38-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 6.5 -40°C 25°C 85°C 6.0 5.5 ICC [mA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 93 Figure 38-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 16 -40°C 15 25°C ICC [mA] 14 85°C 13 12 11 10 9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 38.1.2 Idle mode supply current Figure 38-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 180 3.3V 160 3.0V 140 2.7V ICC [µA] 120 100 2.2V 80 1.8V 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 94 Figure 38-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 6 3.3V 5 3.0V 2.7V ICC [mA] 4 3 2.2V 2 1 1.8V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 38-10.Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35 85°C -40°C 34 25°C ICC [µA] 33 32 31 30 29 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 95 Figure 38-11.Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-12.Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 500 -40°C 25°C 85°C 450 ICC [µA] 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 96 Figure 38-13.Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.3 -40°C 25°C 85°C 2.1 I CC [mA] 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-14.Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 6.7 -40°C 6.4 25°C 6.1 85°C ICC [mA] 5.8 5.5 5.2 4.9 4.6 4.3 4.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V CC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 97 38.1.3 Power-down mode supply current Figure 38-15.Power-down mode supply current vs. VCC. All functions disabled. 2.4 85°C 2.1 ICC [µA] 1.8 1.5 1.2 0.9 0.6 0.3 25°C -40°C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-16.Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 3.5 85°C 3.2 ICC [µA] 2.9 2.6 2.3 2.0 1.7 25°C -40°C 1.4 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 98 38.1.4 Power-save mode supply current Figure 38-17.Power-save mode supply current vs. VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.90 0.85 Normal mode ICC [µA] 0.80 0.75 0.70 0.65 Low-power mode 0.60 0.55 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.1.5 Standby mode supply current Figure 38-18.Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 7.5 ICC [µA] 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 99 Figure 38-19.Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 500 16MHz 12MHz 450 ICC [µA] 400 350 8MHz 2MHz 300 250 0.454MHz 200 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 38.2 I/O Pin Characteristics 38.2.1 Pull-up Figure 38-20.I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 80 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V PIN [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 100 Figure 38-21.I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 38-22.I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V PIN [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 101 38.2.2 Output Voltage vs. Sink/Source Current Figure 38-23.I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 0.9 -40°C 0.7 25°C 85°C 0.5 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 IPIN [mA] Figure 38-24.I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 VPIN [V] 2.5 2.0 1.5 1.0 -40°C 0.5 -30 25°C 85°C -25 -20 -15 -10 -5 0 IPIN [mA] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 102 Figure 38-25.I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.0 VPIN [V] 2.5 2.0 1.5 -40°C 1.0 25°C 85°C 0.5 -30 -25 -20 -15 -10 -5 0 I PIN [mA] Figure 38-26.I/O pin output voltage vs. source current. 4.0 3.6V 3.5 3.3V VPIN [V] 3.0 2.7V 2.5 2.2V 2.0 1.8V 1.5 1.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 103 Figure 38-27.I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 0.9 85°C 0.8 25°C -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 38-28.I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 0.9 25°C 85°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 104 Figure 38-29.I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 25°C -40°C VPIN [V] 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 35 IPIN [mA] Figure 38-30.I/O pin output voltage vs. sink current. 1.5 1.8V VPIN [V] 1.2 2.2V 0.9 2.7V 3.3V 3.6V 0.6 0.3 0 0 5 10 15 20 25 IPIN [mA] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 105 38.2.3 Thresholds and Hysteresis Figure 38-31.I/O pin input threshold voltage vs. VCC. T = 25°C. 1.85 1.70 VIH 1.55 VIL VThreshold [V] 1.40 1.25 1.10 0.95 0.80 0.65 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 38-32.I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40°C 25°C 85°C VTHRESHOLD [V] 1.6 1.4 1.2 1.0 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 106 Figure 38-33.I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.7 -40°C 25°C 85°C VTRESHOLD [V] 1.5 1.3 1.1 0.9 0.7 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-34.I/O pin input hysteresis vs. VCC. 350 VHYSTERESIS [mV] 300 250 200 150 -40°C 25°C 85°C 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 107 ADC Characteristics Figure 38-35.INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.7 1.6 1.5 INL [LSB] 1.4 Differential mode 1.3 1.2 Single-ended unsigned mode 1.1 1.0 0.9 Single-ended signed mode 0.8 0.7 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1550 1700 1850 2000 VREF [V] Figure 38-36.INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 1.4 Differential mode 1.3 Single-ended unsigned mode 1.2 INL [LSB] 38.3 1.1 1.0 0.9 Single-ended signed mode 0.8 0.7 500 650 800 950 1100 1250 1400 ADC sample rate [ksps] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 108 Figure 38-37.INL error vs. input code. 2.0 1.5 1.0 INL [LSB] 0.5 0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 ADC input code 2560 3072 3584 4096 Figure 38-38.DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.80 0.75 DNL [LSB] 0.70 Differential mode 0.65 Single-endedsigned mode 0.60 0.55 Single-ended unsigned mode 0.50 0.45 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 109 Figure 38-39.DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. DNL [LSB] 0.70 0.65 Differential mode 0.60 Single-ended signed mode 0.55 0.50 Single-ended unsigned mode 0.45 0.40 0.35 0.50 0.65 0.80 0.95 1.10 1.25 1.40 1.55 1.70 1.85 2.00 Sampling speed [MS/s] Figure 38-40.DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 ADC Input Code 3072 3584 4096 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 110 Figure 38-41.Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 4 Gain error [mV] 2 Single-ended signed mode 0 -2 Single-ended unsigned mode -4 Differential mode -6 -8 -10 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Figure 38-42.Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 3.0 2.5 Gain Error [mV] 2.0 1.5 Single-ended signed mode 1.0 0.5 0 Single-ended unsigned mode -0.5 -1.0 -1.5 -2.0 1.6 Differential mode 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 111 Figure 38-43.Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.1 Offset [mV] -1.2 -1.3 Differential mode -1.4 -1.5 -1.6 1.0 1.2 1.4 1.6 1.8 2.0 VREF [V] 2.2 2.4 2.6 2.8 3.0 Figure 38-44.Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 1 0 1V mode -1 Gain error [mV] -2 1.5V mode -3 -4 2V mode -5 -6 2.5V mode -7 -8 3V mode -9 -10 -11 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 112 Figure 38-45.Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.5 Offset error [mV] -0.6 -0.7 -0.8 Differential mode -0.9 -1.0 -1.1 -1.2 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 38-46.Noise vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.30 Single-ended signed mode Noise [mV RMS] 1.15 Single-ended unsigned mode 1.00 0.85 0.70 0.55 Differential mode 0.40 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 113 Figure 38-47.Noise vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended signed mode Noise [mV RMS] 1.1 1.0 0.9 Single-ended unsigned mode 0.8 0.7 0.6 0.5 Differential mode 0.4 0.3 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] DAC Characteristics Figure 38-48.DAC INL error vs. VREF. VCC = 3.6V. 3.1 2.9 2.7 2.5 INL [LSB] 38.4 2.3 2.1 1.9 1.7 -40°C 1.5 1.3 25°C 1.1 85°C 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 114 Figure 38-49.DNL error vs. VREF. T = 25°C, VCC = 3.6V. 1.4 1.3 DNL [LSB] 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -40°C 0.5 0.4 0.3 25°C 85°C 0.2 0.1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 38-50.DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . 0.183 0.181 Noise [mV RMS] 0.179 0.177 0.175 0.173 0.171 0.169 0.167 0.165 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [ºC] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 115 Analog Comparator Characteristics Figure 38-51.Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 17 85°C -40°C 25°C 16 15 VHYST [mV] 14 13 12 11 10 9 8 7 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-52.Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 35 85°C 34 33 32 VHYST [mV] 38.5 31 25°C 30 29 28 -40°C 27 26 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 116 Figure 38-53.Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 40 85°C 38 25°C -40°C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 38-54.Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 75 85°C VHYST [mV] 70 65 25°C 60 -40°C 55 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 117 Figure 38-55.Analog comparator current source vs. calibration value. Temperature = 25°C. 8 7 I [µA] 6 5 3.3V 3.0V 2.7V 4 3 2.2V 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] Figure 38-56.Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.5 I [µA] 6.0 5.5 5.0 4.5 -40°C 25°C 85°C 4.0 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIB[3..0] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 118 Figure 38-57.Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.100 0.075 INL [LSB] 0.050 0.025 25°C 0 -0.025 -0.050 -0.075 -0.100 0 10 20 30 40 50 60 70 SCALEFAC Internal 1.0V reference Characteristics Figure 38-58.ADC/DAC Internal 1.0V reference vs. temperature. 1.002 3.3V 3.0V 2.7V 1.8V 1.000 Bandgap voltage [V] 38.6 0.998 0.996 0.994 0.992 0.990 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 119 BOD Characteristics Figure 38-59.BOD thresholds vs. temperature. BOD level = 1.6V. 1.632 Rising VCC 1.630 VBOT [V] 1.628 1.626 1.624 1.622 Falling VCC 1.620 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 55 65 75 85 Temperature [°C] Figure 38-60.BOD thresholds vs. temperature. BOD level = 3.0V. 3.08 3.07 Rising VCC 3.06 VBOT [V] 38.7 3.05 3.04 3.03 Falling VCC 3.02 3.01 -45 -35 -25 -15 -5 5 15 25 35 45 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 120 External Reset Characteristics Figure 38-61. Minimum Reset pin pulse width vs. VCC. 147 142 137 tRST [ns] 132 127 122 117 112 107 102 85°C 97 -40°C 25°C 92 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V CC [V] Figure 38-62. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 60 50 IPIN [µA] 38.8 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V PIN [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 121 Figure 38-63. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 130 117 104 IPIN [µA] 91 78 65 52 39 26 -40°C 25°C 85°C 13 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V PIN [V] Figure 38-64. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 126 112 IPIN [µA] 98 84 70 56 42 28 -40°C 25°C 85°C 14 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V PIN [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 122 Figure 38-65. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.1 2.0 1.9 1.8 VThreshold [V] 1.7 1.6 1.5 1.4 1.3 1.2 -40°C 25°C 1.1 85°C 1.0 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 Figure 38-66. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.65 -40°C 25°C 85°C 1.50 1.35 VThreshold [V] 1.20 1.05 0.90 0.75 0.60 0.45 1.6 1.8 2.0 2.2 2.4 2.6 VCC [V] 2.8 3.0 3.2 3.4 3.6 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 123 38.9 Power-on Reset Characteristics Figure 38-67. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 85°C ICC [µA] 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VCC [V] 38.10 Oscillator Characteristics 38.10.1 Ultra Low-Power internal oscillator Figure 38-68. Ultra Low-Power internal oscillator frequency vs. temperature. 32.9 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.8 32.7 32.6 32.5 32.4 32.3 32.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 124 38.10.2 32.768kHz Internal Oscillator Figure 38-69. 32.768kHz internal oscillator frequency vs. temperature. 32.85 3.3V 3.0V 2.7V 2.2V 1.8V Frequency [kHz] 32.80 32.75 32.70 32.65 32.60 32.55 32.50 32.45 32.40 32.35 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 38-70. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 50 Frequency [kHz] 45 40 35 30 25 20 0 50 100 150 200 250 300 RC32KCAL[7..0] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 125 38.10.3 2MHz Internal Oscillator Figure 38-71. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.18 2.16 Frequency [MHz] 2.14 2.12 2.10 2.08 2.06 2.04 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 38-72. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.008 3.0V 3.3V 2.7V 2.2V 1.8V 2.005 2.002 Frequency [MHz] 1.999 1.996 1.993 1.990 1.987 1.984 1.981 1.978 1.975 -45 -35 -25 -15 -5 5 15 25 35 Temperature [°C] 45 55 65 75 85 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 126 Figure 38-73. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.37 0.35 Step size [%] 0.32 0.30 0.27 0.25 0.22 0.20 25°C -40°C 0.17 85°C 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 38.10.4 32MHz Internal Oscillator Figure 38-74. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.5 36.0 Frequency [MHz] 35.5 35.0 34.5 34.0 33.5 33.0 3.3V 32.5 3.0V 2.7V 1.8V 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 127 Figure 38-75. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.0V 3.3V 2.7V 2.2V 1.8V 32.05 32.00 Frequency [MHz] 31.95 31.90 31.85 31.80 31.75 31.70 31.65 31.60 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 38-76. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.39 Step size 0.34 0.29 0.24 25°C 0.19 85°C -40°C 0.14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 128 Figure 38-77. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V. 80 -40°C 75 25°C 85°C 70 Frequency [MHz] 65 60 55 50 45 40 35 30 25 0 10 20 30 40 50 60 70 CALB 38.10.5 32MHz internal oscillator calibrated to 48MHz Figure 38-78. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55 54 Frequency [MHz] 53 52 51 50 3.3V 3.0V 2.7V 2.2V 1.8V 49 48 47 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 129 Figure 38-79. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.15 3.3V 3.0V 2.7V 2.2V 1.8V 48.05 Frequency [MHz] 47.95 47.85 47.75 47.65 47.55 47.45 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 38-80. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.40% Step size 0.35% 0.30% 0.25% 25°C 0.20% 85°C -40°C 0.15% 0 16 32 48 64 80 96 112 128 CALA XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 130 38.11 Two-Wire Interface characteristics Figure 38-81.SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 38-82. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 131 38.12 PDI characteristics fMAX [MHz] Figure 38-83. Maximum PDI frequency vs. VCC. 36 -40°C 31 25°C 85°C 26 21 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 132 39. Errata 39.1 ATxmega256A3BU 39.1.1 Rev. G z AWeX fault protection restore is not done correct in Pattern Generation Mode 1. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTILSBUF register. Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. 39.1.2 Rev. E-F Not sampled 39.1.3 rev. D z ADC unsigned mode non-functional z ADC increased noise when using internal 1.0V reference at low temperature z DAC offset calibration range too small when using AVCC as reference z Register ANAINIT in MCUR will always read as zero z CPU clock frequency limited to 24MHz z CPU clock frequency limited to 20MHz if using both application section and boot section z High active current consumption at low frequency z USB Transfer Complete interrupt generated for each IN packet in Multipacket Mode z Disabling the USART transmitter does not automatically set the TxD pin direction to input z AWeX PWM output after fault restarted with wrong values z TWI inactive bus timeout from BUSY bus state z TOSC32 as RTC32 clock output Non-functional z Pending asynchronous RTC32 interrupts will not wake up device z Pending full asynchronous pin change interrupts will not wake the device 1. ADC Unsigned mode non-functional The ADC Unsigned mode is non-functional. Problem fix/Workaround XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 133 None, use the ADC in signed mode also for single ended conversions. 2. ADC increased noise when using internal 1.0V reference at low temperature When operating at -40°C and using internal 1.0V reference the RMS noise will be up 4LSB. Problem fix/Workaround Use averaging tof multiple samples to remove noise. 3. DAC offset calibration range too small when using AVCC as reference If using AVCC as reference, the DAC offset calibration will not totally remove the offset error. Offset could be up to 100LSB after calibration. Problem fix/Workaround Offset adjustment must be partly handled in software. 4. Register ANAINIT in MCUR will always read as zero The ANAINIT register in the MCUR module will always be read as zero even if written to a different value. The actual content of the register is correct. Problem fix/Workaround Do not use software that reads these registers to get the Analog Initialization configuration. 5. CPU clock frequency limited to 24MHz The CPU clock must never exceed 24MHz for any supply level. Problem fix/Workaround None. 6. CPU clock frequency limited to 20MHz if using both application section and boot section The CPU clock frequency must never exceed 20MHz when jumping between flash application section and boot section or executing code from one section and reading (LPM) from the other. If exceeding this frequency the first instruction/read will be read as NOP/0x00. These conditions occur when: • Executing code in one section and jumping (JMP, CALL, RET, branch) to other section. • Interrupt table is located in different flash section than the code is executed from. • Using LPM reading the other flash section than the code is executed from. • Reading signature rows • Running CRC and the address crosses the boundary between the two sections. Problem fix/Workaround For all conditions except CRC crossing the boundary between the sections, enable the Flash Power Reduction mode and add a NOP after every LPM instruction. For CRC there is no workaround. 7. High active current consumption at low frequency The current consumption in Active mode is higher than specified for all frequencies below 12MHz. The extra current consumption increases with supply level and lower frequency (see Figure 39-1 on page 135). XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 134 Problem fix/Workaround None, avoid running at low frequenices and use higher frequnecies in compination with sleep modes where possible. Figure 39-1. Current consumption increase vs. VCC voltage and CPU clock frequency 3500 3000 Current consumption (µA) 3.6V 2500 3.3V 2000 3.0V 2.7V 1500 2.2V 1000 1.8V 500 0 0 2 4 6 8 10 12 14 Frequency (MHz) 8. USB Transfer Complete interrupt generated for each IN packet in Multipacket Mode When multipacket is used, a Transfer Complete interrupt will be generated for each IN packet transferred on USB line instead of just at the end of the multipacket transfer. Problem fix/Workaround Ignore interrupt until multipacket is complete. 9. Disabling the USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/Workaround The TxD pin direction can be set to input using the Port DIR register. Using Port DIR register to set direction to input only will be immediate and ongoing transmissions will be truncated. 10. AWeX PWM output after fault restarted with wrong values When recovering from fault state, the PWM output will drive wrong values to the port for up to 2x CLKPER + 1 CLKPER4 cycles. Problem fix/Workaround If the glitch can not be tolerated or not filtered out by external components the following sequence can be used in Latched Mode for restaring without glitch: XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 135 1. Disable DTI outputs (Write DTICCxEN to 0). 2. Clear fault flag. 3. Wait for Overflow. 4. Re-enable DTI (Write DTICCxEN to 1). 5. Set pin direction to Output. This will remove the glitch, but the following period will be shorter. In Cycle-by-cycle mode the same procedure can be followed as long as the Pattern Generation Mode is not enabled. For Pattern Generation Mode, there is no workaround. 11. TWI inactive bus timeout from BUSY bus state If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 12. TOSC32 as RTC32 clock output Non-functional Selecting TOSC32 as clock output is Non-functional. Problem fix/Workaround If 32kHz clock output is required, the internal 32.768kHz oscillator can be selected as source for RTC32 and output to pin. 13. Pending asynchronous RTC32-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround In software, read the RTC32 CNT value before executing the SLEEP instruction and check that it will not to generate overflow or compare match interrupt during the last CPU instruction before the SLEEP instruction is executed. In addition check that no previous RTC interrupts are pending. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround Use limited asynchronous pin-change interrupts instead. 39.1.4 rev A-C Not sampled. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 136 40. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revisions in this section are referring to the document revision. 40.1 40.2 40.3 40.4 8362G – 07/2014 1. Changed VCC to AVCC in Section 31. “AC – Analog Comparator” on page 52 and Section 29. “ADC – 12-bit Analog to Digital Converter” on page 48 2. Updated with footer and back page from template dated 2014-0502 8362F – 02/2013 1. Updated the whole contents with an updated template (Atmel new logo, table tags and paragraph tags). 2. Updated Figure 2-1 on page 3. Pin 15 and Pin 25 are VCC and not VDD. 3. Updated Figure 16-7 on page 33, “Input sensing system overview.” 4. Updated Figure 31-1 on page 53, “Analog comparator overview.” 5. Removed TWID from Table 33-4 on page 58, “Port D - alternate functions.” 6. Updated Table 37-30 on page 84. Added ESR parameter in “External 16MHz crystal oscillator and XOSC characteristics.” 8362E – 12/11 1. Updated “Electrical Characteristics” on page 69. 2. Updated “Typical Characteristics” on page 91. 3. Added “Errata” on page 133. 4. Updated “Packaging information” on page 67. 5. Editing and figure updates 6. Tape and reel added in “Ordering Information” on page 2 7. Pin numbers for GND and VCC in Table 33-4 on page 58 have been corrected 8362D - 03/11 1. Preliminary removed from the front page. 2. Updated the datasheet according to the Atmel new brand style guide. 3. Editing update. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 137 40.5 40.6 8362C - 02/11 1. Updated “Electrical Characteristics” on page 69. 2. Added “Typical Characteristics” on page 91 2. Added “Errata” on page 133. 3. Editing update. 8362B - 11/09 1. 40.7 Updated “Ordering Information” on page 2. 8362A - 10/09 1. Initial version. XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-07/2014 138 Table Of Contents Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 12 12 13 13 13 13 13 14 14 14 DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 8.2 9. 7 7 7 8 9 9 9 9 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 10.2 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-Datasheet_07/2014 i 11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.1 11.2 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12.1 12.2 12.3 12.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1 13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14. Battery Backup System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.1 14.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 28 15.1 15.2 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.1 16.2 16.3 16.4 16.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 32 33 17. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 17.1 17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18.1 18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 19. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 19.1 19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 20.1 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 21. RTC32 – 32-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 22. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 22.1 22.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-Datasheet_07/2014 ii 23. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 24. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 25. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25.1 25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 26. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 26.1 26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 27. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 27.1 27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 28. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 28.1 28.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 29. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 29.1 29.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 30. DAC – 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 30.1 30.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 31. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 31.1 31.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 32. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 32.1 32.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 33. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 33.1 33.2 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 34. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 35. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 36. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 36.1 36.2 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 64M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 37. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 37.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-Datasheet_07/2014 iii 37.2 37.3 37.4 37.5 37.6 37.7 37.8 37.9 37.10 37.11 37.12 37.13 37.14 37.15 37.16 37.17 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up time from sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash and EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBAT and Battery Backup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 71 73 74 75 77 78 79 79 80 80 80 81 81 87 89 38. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 38.1 38.2 38.3 38.4 38.5 38.6 38.7 38.8 38.9 38.10 38.11 38.12 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Internal 1.0V reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Two-Wire Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 PDI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 39. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 39.1 ATxmega256A3BU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 40. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 40.1 40.2 40.3 40.4 40.5 40.6 40.7 8362G – 07/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362F – 02/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362E – 12/11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362D - 03/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362C - 02/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362B - 11/09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8362A - 10/09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 137 137 137 138 138 138 Table Of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i XMEGA A3BU [DATASHEET] Atmel-8362 G-AVR-ATxmega-Datasheet_07/2014 iv XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-8362 G-AVR-ATxmega-Datasheet_07/2014. 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