ATA6831C Triple Half-bridge Driver with SPI and PWM DATASHEET Features ● Supply voltage up to 40V ● RDSon typically 0.8 at 25°C, maximum 1.5 at 150°C ● Up to 1.0A output current ● Three half-bridge outputs formed by three high-side and three low-side drivers ● Capable of switching loads such as DC motors, bulbs, resistors, capacitors, and inductors ● PWM capability up to 25kHz for each high-side output controlled by external PWM signal ● No shoot-through current ● Very low quiescent current IVS < 2µA in standby mode over total temperature range ● Outputs short-circuit protected ● Selective overtemperature protection for each switch and overtemperature prewarning ● Undervoltage protection ● Various diagnostic functions such as shorted output, open load, overtemperature and power-supply fail detection ● Serial data interface, daisy chain capable, up to 2MHz clock frequency ● QFN18 package 9215E-AUTO-02/15 1. Description The Atmel® ATA6831C provides fully protected driver interfaces designed in SOI technology. They are used to allow a microcontroller to control up to three different loads in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable of driving currents up to 1.0A. Due to the enhanced PWM signal (up to 25kHz) it is possible to generate a smooth control of, for example, a DC motor without any noise. The drivers are internally connected to form three half-bridges and can be controlled separately from a standard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capacitors and inductors, to be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed with respect to short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. Figure 1-1. Block Diagram S I O S C O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 VS1 11 Input register Ouput register DI 4 P S F I N H O V L n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 Charge pump L S 1 VS2 T P CLK 5 CS 3 Fault detector DO Fault detector UV protection Fault detector 9 7 Control logic PWM 6 VCC Power on reset 8 GND 14 Fault detector Fault detector Fault detector GND Thermal protection 17 GND 18 1 2 OUT3S OUT3F 2 ATA6831C [DATASHEET] 9215E–AUTO–02/15 13 OUT2S 12 OUT2F 16 OUT1S 15 OUT1F GND Pin Configuration Figure 2-1. Pinning QFN18 PGND3 PGND1 OUT1S OUT1F PGND2 OUT2S 2. OUT3S OUT3F CS DI CLK PWM Table 2-1. Pin 1 2 3 4 5 6 18 17 16 15 14 13 12 11 10 9 8 7 OUT2F VS2 VS1 VCC GND DO Pin Description Symbol Function 1 OUT3S Used only for final testing, to be connected to OUT3F 2 OUT3F Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and lowside switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3 CS Chip select input; 5V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4 DI Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control device; DI expects a 16-bit control word with LSB transferred first 5 CLK Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (fmax = 2MHz) 6 PWM PWM input; 5V CMOS logic level input with internal pull-down Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB transferred first); output will remain tristated unless device is selected by CS = low; this allows several ICs to operate on only one data-output line 7 DO 8 GND Ground 9 VCC Logic supply voltage (5V) 10 VS1 Power supply for output stages OUT1 and OUT2; internal supply 11 VS2 Power supply for output stages OUT2 and OUT3; internal supply 12 OUT2F Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and lowside switch 2 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 13 OUT2S Used only for final testing, to be connected to OUT2F 14 PGND2 Power ground OUT2 15 OUT1F Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and lowside switch 1 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 16 OUT1S Used only for final testing, to be connected to OUT1F 17 PGND1 Power ground OUT1 18 PGND3 Power ground OUT3 ATA6831C [DATASHEET] 9215E–AUTO–02/15 3 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer CS DI SRR 0 LS1 1 HS1 LS2 HS2 LS3 HS3 PL1 2 3 4 5 6 7 8 S1H S2L S2H S3H n. u. n. u. PH1 PL2 9 PH2 10 PL3 11 PH3 12 OLD 13 OCS 14 SI 15 CLK DO Table 3-1. 4 TP S1L S3L n. u. n. u. n. u. n. u. OVL INH PSF Input Data Protocol Bit Input Register 0 SRR Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 PL1 Output LS1 additionally controlled by PWM Input 8 PH1 Output HS1 additionally controlled by PWM Input 9 PL2 See PL1 10 PH2 See PH1 11 PL3 See PL1 12 PH3 See PH1 13 OLD Open load detection (low = on) 14 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 15 SI ATA6831C [DATASHEET] 9215E–AUTO–02/15 Function Software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered) Table 3-2. Output Data Protocol Bit Output (Status) Register 0 TP Function Temperature prewarning: high = warning Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 1 2 11 n. u. Not used 12 n. u. Not used 13 OVL Over-load detected: set high, when at least one output is switched off by a shortcircuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch 14 INH Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation 15 PSF Power-supply fail: undervoltage at pin VS detected After power-on reset, the input register has the following status: Bit 15 Bit 14 SI OCS H H Bit 13 OLD Bit 12 PH3 Bit 11 PL3 Bit 10 PH2 Bit 9 PL2 Bit 8 PH1 Bit 7 PL1 Bit 6 HS3 Bit 5 LS3 Bit 4 HS2 Bit 3 LS2 Bit 2 HS1 Bit 1 LS1 Bit 0 SRR H L L L L L L L L L L L L L The following patterns are used to enable internal test modes of the IC. Do not use these patterns during normal operation. Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 Bit 1 Bit 0 (HS1) (LS1) (SRR) H H H H H L L L L L L L L L L L H H H L L H H L L L L L L L L L H H H L L L L H H L L L L L L L ATA6831C [DATASHEET] 9215E–AUTO–02/15 5 3.2 Power-supply Fail If undervoltage is detected at pin VS, the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when the supply voltage returns to the normal operational value. The PSF bit stays high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection (Available for H-Bridge Configuration only) If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch of typically 2.5mA and a pulldown current for each low-side switch of typically 9mA is turned on (open-load detection current IOut1-3). The open load condition of all the outputs is indicated in the SPI output register bit 1-6. Activating an output stage with the OLD bit set to low disables the open-load function for this output. Figure 3-2. Open Load Detection in H-bridge Configuration VS HSx HSy OUTx OUTy LSx M LSy GND Operating open load and short circuit detection in H-Bridge configuration requires the following command sequence: Step #1 a. Low side check Input: HSx = 0, LSx = 1, HSy = 0, LSy = 0, OLD = 0 b. Feedback: LSy = 1 indicates “Motor connected” LSy = 0 indicates “Motor connection fail”, open load Step #2 a. High side check Input: HSx = 1, LSx = 0, HSy = 0, LSy = 0, OLD = 0 b. Feedback: HSy = 1 indicates “Motor connected” HSy = 0 indicates “Motor connection fail”, open load The maximum H-bridge load resistance for proper load detection is 170. Both conditions step #1 and #2 need to be fulfilled. 6 ATA6831C [DATASHEET] 9215E–AUTO–02/15 3.4 Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tjswitch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additionally, the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on, and the SRR bit in the input register is set to high. The hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the overcurrent shutdown bit (OCS) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off, following a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low, the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. 3.6 Inhibit The SI bit in the input register has to be set to zero to inhibit the Atmel® ATA6831C. In this state, all output stages are then turned off but the serial interface remains active. The current consumption is reduced to less than 2µA at pin VS and less than 100µA at pin VCC. The output stages can be reactivated by setting bit SI to “1”. 3.7 PWM Mode The common input for all six outputs is pin PWM (Figure 3-3). The selection of the outputs, which are controlled by PWM, is done by input data register PLx or PHx. In addition to the PWM input register, the corresponding input registers HSx and LSs have to be set. Switching the high side outputs is possible up to 25kHz, low side switches up to 8kHz. Figure 3-3. Output Control by PWM Bit LSx/HSx Pin OUTx Bit PLx/PHx Pin PWM ATA6831C [DATASHEET] 9215E–AUTO–02/15 7 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Pin Symbol Value Unit Supply voltage 10, 11 VVS –0.3 to +40 V Supply voltage t < 0.5s; IVS > –2A 10, 11 VVS –1 V 9 VVCC –0.3 to +7 V 3, 4, 5, 6 VCS, VDI, VCLK, VPWM –0.3 to VVCC + 0.3 V 7 VDO –0.3 to VVCC + 0.3 V 3, 4, 5, 6 ICS, IDI, ICLK, IPWM –10 to +10 mA Output current 7 IDO –10 to +10 mA Output current 2, 12, 15 IOut1, IOut2, IOut3 Internally limited, see output specification Output voltage 2, 12, 15 IOut1, IOut2, IOut3 –0.3 to +40 V Reverse conducting current (tpulse = 150µs) 2, 12, 15 IOut1, IOut2, IOut3 17 A Junction temperature range TJ –40 to +150 °C Storage temperature range TSTG –55 to +150 °C Logic supply voltage Logic input voltage Logic output voltage Input current 5. Thermal Resistance Parameters Test Conditions Thermal resistance from junction to case Thermal resistance from junction to ambient 6. Depends on the PC board Symbol Value Unit RthJC 5 k/W RthJA 40 K/W Operating Range Parameters Symbol Value (1) Unit Supply voltage VVS VUV to 40 V Logic supply voltage VVCC 4.75 to 5.25 V Logic input voltage VCS, VDI, VCLK, VPWM –0.3 to VVCC V Serial interface clock frequency fCLK 2 MHz PWM input frequency fPWM max. 25 kHz Tj –40 to +150 °C Junction temperature range Note: 1. Threshold for undervoltage description 8 ATA6831C [DATASHEET] 9215E–AUTO–02/15 7. Noise and Surge Immunity Parameters Test Conditions Value Conducted interferences ISO 7637-1 Level 4(1) Interference suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) ESD S 5.1 2kV CDM (Charge Device Model) Note: 1. Test pulse 5: Vsmax = 40V ESD STM5.3.1 500V 8. Electrical Characteristics 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions 1 Current Consumption 1.1 Quiescent current VS 1.2 4.75V < VVCC < 5.25V, Quiescent current VCC SI = low VVS < 20V, SI = low Pin Symbol 10, 11 9 Min. Typ. Max. Unit Type* IVS 1 2 µA A IVCC 60 100 µA A IVS 4 6 mA A 350 650 µA A 1.3 Supply current VS VVS < 20V normal operating, all outputs off, 10, 11 input register bit 13 (OLD) = high 1.4 Supply current VCC 4.75V < VVCC < 5.25V, normal operating 9 IVCC 1.5 Discharge current VS VVS = 32.5V, INH = low 10, 11 IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40V, INH = low 10, 11 IVS 2.5 14 mA A 9 VVCC 3.2 3.9 4.4 V A tdPor 30 95 190 µs A 5.6 7.0 V A V A 40 µs A 2 Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold 2.2 Power-on reset delay time 2.3 Undervoltage-detection VVCC = 5V threshold 10, 11 VUv 2.4 Undervoltage-detection VVCC = 5V hysteresis 10, 11 VUv 2.5 Undervoltage-detection delay time 3 After switching on VVCC 0.6 tdUV 10 TjPW set 120 145 170 °C B 105 130 155 °C B K B °C B Thermal Prewarning and Shutdown 3.1 Thermal prewarning set 3.2 Thermal prewarning reset TjPW reset 3.3 Thermal prewarning hysteresis TjPW 3.4 Thermal shutdown off Tj switch off 15 150 175 200 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. ATA6831C [DATASHEET] 9215E–AUTO–02/15 9 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters 3.5 Symbol Min. Typ. Max. Unit Type* Thermal shutdown on Tj switch on 135 160 185 °C B 3.6 Thermal shutdown hysteresis Tj switch off K B 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.2 B 4 4.1 4.2 Test Conditions Pin 15 Output Specification (OUT1 to OUT3) On resistance IOut1-3 = –0.9A 2, 12, 15 RDSon1-3H 1.5 A IOut1-3 = –0.9A 2, 12, 15 RDSon1-3L 1.5 A µA A 300 µA A 2 V A V A 4.3 High-side output leakage current VOut 1-3 H = 0V, output stages off 2, 12, 15 IOut1-3H 4.4 Low-side output leakage current VOut 1-3 L = VVS, output stages off 2, 12, 15 IOut1-3L 4.5 High-side switch reverse diode forward voltage IOut = 1.5A 2, 12, 15 VOut1-3 – VVS 4.6 Low-side switch reverse diode forward voltage IOut 1-3 L = –1.5A 2, 12, 15 VOut1-3L 2 4.7 High-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold 2, 12, 15 IOut1-3 1.0 1.3 1.7 A A 4.8 Low-side overcurrent limitation and shutdown 7.5V < VVS < 20V threshold 2, 12, 15 IOut1-3 –1.7 –1.3 –1.0 A A 4.9 High-side overcurrent limitation and shutdown 20V < VVS < 40V threshold 2, 12, 15 IOut1-3 1.0 1.3 2.0 A A 4.10 Low-side overcurrent limitation and shutdown 20V < VVS < 40V threshold 2, 12, 15 IOut1-3 –2.0 –1.3 –1.0 A A 4.11 Overcurrent shutdown delay time tdSd 10 40 µs A 4.12 High-side open load detection current IOut1-3H 1 2.5 4 mA A VVS – 3.5V VVS – 2.5V VVS – 1V V A High-side open load 4.12a detection threshold level Input register bit 13 (OLD) = low, output off 2, 12, 15 VVS = 13V, VOut 1-3 = 0V Input register bit 13 (OLD) = low, output off 2, 12, 15 VOut1-3_OLD_HTh VVS = 13V, IOut1-3 = 0mA –15 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 10 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. ATA6831C [DATASHEET] 9215E–AUTO–02/15 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin 4.13 Low-side open load detection current Input register bit 13 (OLD) = low, output off 2, 12, 15 VVS = 13V, VOut 1-3 = 13V Symbol Min. Typ. Max. Unit Type* IOut1-3L –6 –9 –11 mA A 0.5 1.5 2.5 V A 2 3 4 Low-side open load 4.13a detection threshold level Input register bit 13 (OLD) = low, output off 2, 12, 15 VOut1-3_OLD_LTh VVS = 13V, IOut1-3 = 0mA 4.14 Open load detection current ratio IOut1-3L/IOut1-3H 4.15 High-side output switch VVS = 13V on delay(1),(2) RLoad = 30 tdon 20 µs A 4.16 Low-side output switch VVS = 13V on delay(1),(2) RLoad = 30 tdon 20 µs A 4.17 High-side output switch VVS =13V off delay(1),(2) RLoad = 30 tdoff 20 µs A 4.18 Low-side output switch VVS =13V off delay(1),(2) RLoad = 30 tdoff 3 µs A 4.19 Dead time between VVS =13V corresponding high-side and low-side RLoad = 30 switches tdon – tdoff µs A 4.20 tdPWM low-side switch(3) VVS = 13V RLoad = 30 tdPWM = tdon – tdoff 20 µs A tdPWM VVS = 13V RLoad = 30 tdPWM = tdon – tdoff -5 5 µs A 0.3 VVCC V A 0.7 VVCC V A 4.21 5 high-side switch(3) 1 Logic Inputs DI, CLK, CS, PWM 5.1 Input voltage low-level threshold 3, 4, 5, 6 VIL 5.2 Input voltage high-level threshold 3, 4, 5, 6 VIH 5.3 Hysteresis of input voltage 3, 4, 5, 6 VI 50 700 mV A 5.4 Pull-down current pins DI, CLK, PWM VDI, VCLK, VPWM = VVCC 4, 5, 6 IPD 10 65 µA A 5.5 Pull-up current pin CS VCS = 0V 3 IPU –65 –10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. ATA6831C [DATASHEET] 9215E–AUTO–02/15 11 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 6 Parameters Test Conditions Pin Symbol Min. Typ. Output-voltage low level IDOL = 2mA 7 VDOL 6.2 Output-voltage high level IDOL = –2mA 7 VDOH VVCC – 0.7V 6.3 Leakage current (tri-state) VCS = VVCC 0V < VDO < VVCC 7 IDO –10 7.1 Unit Type* 0.4 V A V A 10 µA A 100 µs A Serial Interface – Logic Output DO 6.1 7 Max. Inhibit Input – Timing Delay time from standby to normal operation tdINH *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 9. 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. Serial Interface Timing No. 8 Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type* Serial Interface Timing 8.1 DO enable after CS falling edge CDO = 100pF 7 1 tENDO 200 ns D 8.2 DO disable after CS rising edge CDO = 100pF 7 2 tDISDO 200 ns D 8.3 DO fall time CDO = 100pF 7 - tDOf 100 ns D 8.4 DO rise time CDO = 100pF 7 - tDOr 100 ns D 8.5 DO valid time CDO = 100pF 7 10 tDOVal 200 ns D 8.6 CS setup time 3 4 tCSSethl 225 ns D 8.7 CS setup time 3 8 tCSSetlh 225 ns D 8.8 CS high time 3 9 tCSh 500 ns D 8.9 CLK high time 5 5 tCLKh 225 ns D 8.10 CLK low time 5 6 tCLKl 225 ns D 8.11 CLK period time 5 - tCLKp 500 ns D 8.12 CLK setup time 5 7 tCLKSethl 225 ns D 8.13 CLK setup time 5 3 tCLKSetlh 225 ns D 8.14 DI setup time 4 11 tDIset 40 ns D 8.15 DI hold time 4 12 tDIHold 40 ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 12 ATA6831C [DATASHEET] 9215E–AUTO–02/15 Figure 9-1. Serial Interface Timing with Chart Number 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC ATA6831C [DATASHEET] 9215E–AUTO–02/15 13 10. Application Circuit Figure 10-1. Application Circuit VCC VS S I Trigger Reset U5021M Watchdog O S C O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R BYV28 10 VBatt VS1 11 Input register Ouput register DI 4 P S F I N H O V L n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 Charge pump L S 1 13V VS2 + T P CLK 5 Microcontroller CS 3 Fault detector Fault detector VCC UV protection Fault detector VCC 9 DO Control logic 7 PWM 6 VCC Power on reset 5V + 8 GND Fault detector Fault detector 14 Fault detector GND Thermal protection VCC 17 GND 18 1 2 13 OUT3F GND 15 OUT1F M Application Notes ● ● Connect the blocking capacitors at VVCC and VVS as close as possible to the power supply and GND pins. Recommended value for capacitors at VVS: ● Electrolytic capacitor C > 22µF in parallel with a ceramic capacitor C = 100nF. The value for the electrolytic capacitor depends on external loads, conducted interferences, and the reverse conducting current IOut1,2,3. ● Recommended value for capacitors at VVCC: ● To reduce thermal resistance, place cooling areas on the PCB as close as possible to the GND pins and to the die pad. ● 14 16 OUT2F M 10.1 12 Electrolytic capacitor C > 10µF in parallel with a ceramic capacitor C = 100nF. ATA6831C [DATASHEET] 9215E–AUTO–02/15 11. Ordering Information Extended Type Number Package Remarks ATA6831C-PIQW-1 QFN18, 4mm 4mm Pb-free, 6k, taped and reeled Package Information Top View D 18 E 1 PIN 1 ID 6 Dimensions in mm A Side View A3 A1 technical drawings according to DIN specifications Bottom View D2 6 E2 7 1 12 18 COMMON DIMENSIONS 13 (Unit of Measure = mm) e Z Z 10:1 L 12. b Symbol MIN NOM MAX A 0.8 0.85 0.9 A1 A3 0 0.16 0.035 0.21 0.05 0.26 D 3.9 4 4.1 D2 2.6 2.7 2.8 E 3.9 4 4.1 E2 3.075 3.175 3.275 L 0.35 0.4 0.45 b e 0.2 0.25 0.5 0.3 NOTE 05/20/14 TITLE Package Drawing Contact: [email protected] Package: QFN_4x4_18L Exposed pad 2.7x3.175 GPC DRAWING NO. REV. 6.543-5189.01-4 1 ATA6831C [DATASHEET] 9215E–AUTO–02/15 15 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9215E-AUTO-02/15 History Section 11 “Ordering Information” on page 15 updated Section 12 “Package Information” on page 15 updated 9215D-AUTO-11/12 Section 3.3 “Open-load Detection (Available for H-Bridge Configuration only)” on page 6 updated 9215C-AUTO-06/11 Package Information: drawing changed Features on page 1 changed 9215B-AUTO-01/11 Section 3.6 “Inhibit” on page 7 changed Section 8 “Electrical Characteristics” number 1.1 on page 9 changed 16 ATA6831C [DATASHEET] 9215E–AUTO–02/15 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: 9215E–AUTO–02/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. 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