Features • • • • • • • • • • • • Supply Voltage up to 40V RDSon Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C Up to 1.0A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors No Shoot-through Current Outputs Short-circuit Protected Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency QFN18 Package 1. Description The ATA6827 is a fully protected driver IC specially designed for high temperature applications. In mechatronic solutions, for example turbo charger or exhaust gas recirculation systems, many flaps have to be controlled by DC motor driver ICs which are located very close to the hot engine or actuator where ambient temperatures up to 150°C are usual. Due to the advantages of SOI technology junction temperatures up to 200°C are allowed. This enables new cost effective board design possibilities to achieve complex mechatronic solutions. High Temperature Triple Half-bridge Driver with Serial Input Control ATA6827 The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode opens a wide range of applications. Automotive qualification gives added value and enhanced quality for exacting requirements of automotive applications. 4912E–AUTO–02/10 Figure 1-1. Block Diagram n. u. n. u. O S C n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 VS 11 Input register Ouput register DI 4 O P L P S F S C D n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 VS Charge pump L S 1 T P CLK 5 CS 3 Fault detector INH Fault detector UV protection Fault detector 9 8 Control logic DO 7 VCC Power on reset 14 GND 17 Fault detector Fault detector Fault detector GND Thermal protection 18 GND 6 1 OUT3S 2 2 OUT3F 13 OUT2S 12 OUT2F 16 OUT1S 15 GND OUT1F ATA6827 4912E–AUTO–02/10 ATA6827 2. Pin Configuration Pinning QFN18 PGND3 PGND1 OUT1S OUT1F PGND2 OUT2S Figure 2-1. OUT3S OUT3F CS DI CLK GND Table 2-1. 1 2 3 4 5 6 18 17 16 15 14 13 12 11 10 9 8 7 OUT2F VS VS VCC INH DO Pin Description Pin Symbol Function 1 OUT3S Used only for final testing, to be connected to OUT3F 2 OUT3F Half-bridge output 3 3 CS Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 4 DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 5 CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) 6 GND Ground; reference potential 7 DO Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 8 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation 9 VCC Logic supply voltage (5 V) 10 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply 11 VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply 12 OUT2F Half-bridge output 2 13 OUT2S Used only for final testing, to be connected to OUT2F 14 PGND2 Power Ground OUT2 15 OUT1F Half-bridge output 1 16 OUT1S Used only for final testing, to be connected to OUT13F 17 PGND1 PGND3 Power Ground OUT1 and OUT3 18 PGND1 PGND3 Power Ground OUT1 and OUT3 3 4912E–AUTO–02/10 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer CS DI SRR 0 LS1 1 HS1 LS2 HS2 2 3 4 S1H S2L S2H LS3 HS3 n. u. 5 6 7 8 S3H n. u. n. u. n. u. n. u. 9 n. u. 10 n. u. 11 n. u. 12 OCS 13 n. u. 14 n. u. 15 CLK DO TP S1L Table 3-1. Bit 4 S3L n. u. n. u. n. u. n. u. SCD OPL PSF Input Data Protocol Input Register Function 0 SRR Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 14 n. u. Not used 15 n. u. Not used ATA6827 4912E–AUTO–02/10 ATA6827 Table 3-2. Output Data Protocol Output (Status) Register Bit Function 0 TP 1 Status LS1 High = output is on, low = output is off; not affected by SRR Temperature prewarning: high = warning 2 Status HS1 High = output is on, low = output is off; not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 SCD Short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted switch. 14 OPL Open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. 15 PSF Power-supply fail: undervoltage at pin VS detected After power-on reset, the input register has the following status: Bit 15 Bit 14 x x Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) H x x x x x x L L L L Bit 2 Bit 1 (HS1) (LS1) L L Bit 0 (SRR) L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 Bit 1 (HS1) (LS1) Bit 0 (SRR) H H H H H L L L L L L L L L L L H H H L L H H L L L L L L L L L H H H L L L L H H L L L L L L L 5 4912E–AUTO–02/10 3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR (Status Register Reset) bit in the input register. 3.3 Open-load Detection If the current through a high-side or low-side switch in the ON-state stays below the open-load detection threshold, the open-load detection bit (OPL) in the output register is set. The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to be longer than the open-load detection delay time tdSd. 3.4 Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T jPW set , the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit Applying 0V to pin 8 (INH) inhibits the ATA6827. All output switches are then turned off and switched to tri-state. The data in the output register is deleted. The output switches can be activated again by switching pin 8 (INH) to 5V which initiates an internal power-on reset. 6 ATA6827 4912E–AUTO–02/10 ATA6827 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Pin Symbol Value Unit Supply voltage 10, 11 VVS –0.3 to +40 V Supply voltage t < 0.5s; IS > –2A 10, 11 VVS –1 V 9 VVCC –0.3 to +7 V 3, 4, 5, 8 VCS,VDI, VCLK, VINH –0.3 to VVCC + 0.3 V 7 VDO –0.3 to VVCC + 0.3 V 3, 4, 5, 8 ICS, IDI, ICLK, IINH –10 to +10 mA Output current 7 IDO –10 to +10 mA Logic supply voltage Logic input voltage Logic output voltage Input current Output current 2, 12, 15 IOut3, IOut2, IOut1 Internally limited, see output specification Output voltage 2, 12, 15 IOut3, IOut2, IOut1 –0.3 to +40 V Reverse conducting current (tpulse = 150 µs) 2, 12, 15 IOut3, IOut2, IOut1 17 A Junction temperature range Tj –40 to +200 °C Storage temperature range TSTG –55 to +200 °C Ambient temperature range Ta –40 to +150 °C 5. Thermal Resistance Parameters Test Conditions Symbol Junction case Junction ambient Notes: (1) Value Unit Rthjc 5 K/W RthJA 40 K/W 1. Depends on PCB board design 6. Operating Range Parameters Symbol Value Unit Supply voltage VVS VUV(2) to 40 V Logic supply voltage VVCC 4.75 to 5.25 V VCS,VDI, VCLK, VINH –0.3 to VVCC V fCLK 2 MHz Tj –40 to +200 °C Logic input voltage Serial interface clock frequency Junction temperature range Note: Threshold for undervoltage detection 7 4912E–AUTO–02/10 7. Noise and Surge Immunity Parameters Test Conditions Value Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 2 ESD (Human Body Model) ESD S 5.1 2 kV CDM (Charged Device Model) Note: Test pulse 5: Vsmax = 40V ESD STM 5.3.1-1999 all pins 500V Level 4(1) Level 5 8. Electrical Characteristics 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. 1 Parameters Test Conditions Pin Symbol 10, 11 9 Min. Typ. Max. Unit Type* IVS 1 60 µA A IVCC 15 40 µA A Current Consumption 1.1 Quiescent current VS VVS < 20V, INH = low 1.2 Quiescent current VCC 4.75 V < VVCC < 5.25V, INH = low 1.3 Supply current VS VVS < 20V normal 10, 11 operating, all outputs off IVS 4 6 mA A 1.4 Supply current VCC 4.75V < VVCC < 5.25V, normal operating 9 IVCC 350 500 µA A 1.5 Discharge current VS VVS = 32.5V, INH = low 10, 11 IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40V, INH = low 10, 11 IVS 2.0 10 mA A 9 VVCC 3.1 3.9 4.5 V A tdPor 30 95 190 µs A 5.5 7.1 V A V A 40 µs A 2 Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold 2.2 Power-on reset delay time 2.3 Undervoltage-detection VCC = 5V threshold 10, 11 VUv 2.4 Undervoltage-detection VCC = 5V hysteresis 10, 11 ΔVUv 2.5 Undervoltage-detection delay time 3 After switching on VCC 0.6 tdUV 10 TjPW set 170 195 220 °C B 155 180 205 °C B °C B Thermal Prewarning and Shutdown 3.1 Thermal prewarning set 3.2 Thermal prewarning reset TjPW reset 3.3 Thermal prewarning hysteresis ΔTjPW 3.4 Thermal shutdown off Tj switch off 200 225 250 °C B 3.5 Thermal shutdown on Tj switch on 185 210 235 °C B 15 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 8 ATA6827 4912E–AUTO–02/10 ATA6827 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters 3.6 Thermal shutdown hysteresis ΔTj switch off 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.15 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.15 B 4 Test Conditions Pin Symbol Min. Typ. Max. 15 Unit Type* °C B Output Specification (OUT1-OUT3) 4.1 IOut 1-3 = –0.9A 2, 12, 15 RDSOn1-3 1.8 Ω A IOut 1-3 = +0.9A 2, 12, 15 RDSOn1-3 1.8 Ω A µA A On resistance 4.2 4.3 High-side output leakage current VOut 1-3 = 0V, output stages off 2, 12, 15 IOut1-3 4.4 Low-side output leakage current VOut 1-3 = VVS, output stages off 2, 12, 15 IOut1-3 300 µA A 4.5 High-side switch reverse diode forward voltage IOut 1-3 = 1.5A 2, 12, 15 VOut1-3 – VVS 2 V A 4.6 Low-side switch reverse IOut 1-3 = –1.5A diode forward voltage 2, 12, 15 VOut 1-3 –2 V A 4.7 High-side overcurrent limitation and shutdown 7.5V < VS < 20V threshold 2, 12, 15 IOut1-3 1.0 1.3 1.7 AA A 4.8 Low-side overcurrent limitation and shutdown 7.5V < VS < 20V threshold 2, 12, 15 IOut1-3 –1.7 –1.3 –1.0 A A 4.18 High-side overcurrent limitation and shutdown 20V < VS < 40V threshold 2, 12, 15 IOut1-3 1.0 1.3 2.0 AA A 4.19 Low-side overcurrent limitation and shutdown 20V < VS < 40V threshold 2, 12, 15 IOut1-3 –2.0 –1.3 –1.0 A A 4.9 Overcurrent shutdown delay time 2, 12, 15 tdSd 10 40 µs A 4.10 High-side open-load detection threshold 2, 12, 15 IOut1-3 –55 –30 –5 mA A 4.11 Low-side open-load detection threshold 2, 12, 15 IOut1-3 5 30 55 mA A 4.12 Open-load detection delay time tdSd 200 600 µs A –60 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 9 4912E–AUTO–02/10 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Max. Unit Type* 4.13 High-side output switch VVS = 13V RLoad = 30Ω on delay(1) tdon 20 µs A 4.14 Low-side output switch VVS = 13V on delay(1) RLoad = 30Ω tdon 20 µs A 4.15 High-side output switch VVS = 13V off delay(1) RLoad = 30Ω tdoff 20 µs A 4.16 Low-side output switch VVS = 13V off delay(1) RLoad = 30Ω tdoff 3 µs A 4.17 Dead time between corresponding highand low-side switches 5 Test Conditions Pin VVS = 13V RLoad = 30Ω Symbol Min. Typ. tdon – tdoff 1 µs A 0.3 × VVCC V A 0.7 × VVCC V A Logic Inputs DI, CLK, CS, INH 5.1 Input voltage low-level threshold 3, 4, 5, 8 VIL 5.2 Input voltage high-level threshold 3, 4, 5, 8 VIH 5.3 Hysteresis of input voltage 3, 4, 5, 8 ΔVI 50 700 mV B 5.4 Pull-down current pin DI, CLK, INH VDI, VCLK, VINH = VCC 4, 5, 8 IPD 5 70 µA A 5.5 Pull-up current Pin CS VCS = 0V 3 IPU –70 –5 µA A 0.4 V A V A +15 µA A 100 µs A 6 Serial Interface – Logic Output DO 6.1 Output-voltage low level IDOL = 2 mA 7 VDOL 6.2 Output-voltage high level IDOL = –2 mA 7 VDOH VVCC –0.7V 6.3 Leakage current (tri-state) VCS = VCC 0V < VDO < VVCC 7 IDO –15 7 7.1 Inhibit Input - Timing Delay time from standby to normal operation tdINH *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 10 ATA6827 4912E–AUTO–02/10 ATA6827 9. Serial Interface – Timing Pin Timing Chart No.(1) Symbol DO enable after CS CDO = 100 pF falling edge 7 1 8.2 DO disable after CS CDO = 100 pF rising edge 7 8.3 DO fall time CDO = 100 pF 7 8.4 DO rise time CDO = 100 pF 7 8.5 DO valid time CDO = 100 pF 7 8.6 CS setup time 3 4 tCSSethl 8.7 CS setup time 3 8 8.8 CS high time 3 8.9 CLK high time 5 8.10 CLK low time No. Parameters 8.1 Test Conditions Min. Typ. Max. Unit Type* tENDO 200 ns D 2 tDISDO 200 ns D - tDOf 100 ns D - tDOr 100 ns D 10 tDOVal 200 ns D 225 ns D tCSSetlh 225 ns D 9 tCSh 500 ns D 5 tCLKh 225 ns D 5 6 tCLKl 225 ns D 8.11 CLK period time 5 - tCLKp 500 ns D 8.12 CLK setup time 5 7 tCLKSethl 225 ns D 8.13 CLK setup time 5 3 tCLKSetlh 225 ns D 8.14 DI setup time 4 11 tDIset 40 ns D 8.15 DI hold time 4 12 tDIHold 40 ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Serial Interface Timing with Chart Numbers 11 4912E–AUTO–02/10 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 12 ATA6827 4912E–AUTO–02/10 ATA6827 10. Application Circuit Figure 10-1. Application Circuit VCC VS Enable n. u. O S C n. u. n. u. n. u. n. u. n. u. n. u. H n. S u. 3 L S 3 L S 2 H S 2 H S 1 L S 1 S R R 10 VS BYT41D VBatt Trigger Reset U5021M Watchdog 11 Input register Ouput register P S F DI 4 O P L S C D n. u. Serial interface n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 L S 1 13V VS Charge pump + T P CLK 5 CS 3 Microcontroller Fault detector INH Fault detector VCC UV protection Fault detector VCC 9 8 Control logic DO 7 VCC Power on reset 5V + 14 GND Fault detector Fault detector 17 Fault detector GND Thermal protection 18 GND 6 VCC 1 2 13 OUT3F 12 16 OUT2F M GND 15 OUT1F M 11. Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see Section 4. “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins and to the die pad. 13 4912E–AUTO–02/10 12. Ordering Information Extended Type Number Package Remarks ATA6827-PIQW QFN18, 4 mm × 4 mm Taped and reeled, Pb-free 13. Package Information Package: VQFN_4 x 4_18L Exposed pad 2.7 x 3.175 Dimensions in mm Bottom 2.5 Not indicated tolerances ±0.05 Z 0.5 nom. Top 13 18 1 4 7 0.175 6 0.2 1 2.5 3.175±0.15 Pin 1 identification 18 12 6 2.7±0.15 0.9±0.1 Drawing-No.: 6.543-5133.01-4 0.23±0.07 Issue: 1; 26.04.07 0.4±0.1 Z 10:1 technical drawings according to DIN specifications 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 14 Revision No. History 4912E-auto-02/10 • Section 5 “Thermal Resistance” on page 7 changed 4912D-auto-06/07 • • • • • • Put datasheet in a new template Package drawing changed Block diagram changed Pinning drawing changed Pin Description table changed Application circuit drawing changed ATA6827 4912E–AUTO–02/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4912E–AUTO–02/10