Features • Industry-standard Architecture – Emulates Many 24-pin PALs® – Low-cost Easy-to-use Software Tools • High-speed Electrically-erasable Programmable Logic Devices – 7.5 ns Maximum Pin-to-pin Delay • Several Power Saving Options Device ICC, Standby ICC, Active ATF20V8B 50 mA 55 mA ATF20V8BQ 35 mA 40 mA ATF20V8BQL 5 mA 20 mA Highperformance EE PLD • CMOS and TTL Compatible Inputs and Outputs • Input and I/O Pull-up Resistors • Advanced Flash Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts PCI-Compliant Green Package Options (Pb/Halide-free/RoHS Complant) Available • • • • • ATF20V8B ATF20V8BQ ATF20V8BQL Block Diagram TSSOP Pin Configurations CLK/IN IN IN IN IN IN IN IN IN IN IN GND All Pinouts Top View I Logic Inputs I/O Bi-directional Buffers OE Output Enable * No Internal Connection VCC +5V Supply DIP/SOIC CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PLCC VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN IN IN CLK/IN * VCC IN I/O Clock IN IN IN * IN IN IN 4 3 2 1 28 27 26 CLK 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 Function VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN 24 23 22 21 20 19 18 17 16 15 14 13 I/O I/O I/O * I/O I/O I/O Rev. 0407J–07/06 IN IN GND * OE/IN IN I/O Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 1 Description The ATF20V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges. Several low-power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to 7.0V for pulses of less than 20 ns. Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. DC and AC Operating Conditions Operating Temperature (Ambient) VCC Power Supply 2 ATF20V8B(Q)(L) Commercial Industrial 0°C - 70°C -40°C - 85°C 5V ± 5% 5V ± 10% ATF20V8B(Q)(L) DC Characteristics Symbol Parameter Condition IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(Max) IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC Min Typ Max Units -35 -100 µA 10 µA Com. 60 90 mA Ind. 60 100 mA B-15 Com. 60 80 mA B-15 Ind. 60 90 mA B-25 Com. 60 80 mA B-25 Ind. 60 90 mA BQ-10 Com. 35 55 mA BQL-15 Com. 5 10 mA BQL-15 Ind. 5 15 mA BQL-25 Com. 5 10 mA BQL-25 Ind. 5 15 mA Com. 80 110 mA Ind. 80 125 mA B-15 Com. 60 90 mA B-15 Ind. 60 105 mA B-25 Com. 60 90 mA B-25 Ind. 60 105 mA BQ-10 Com. 40 55 mA BQL-15 Com. 20 35 mA BQL-15 Ind. 20 40 mA BQL-25 Com. 20 35 mA BQL-25 Ind. 20 40 mA -130 mA B-7, -10 ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open B-7, -10 ICC2 Clocked Power Supply Current VCC = Max, Outputs Open, f = 15 MHz IOS(1) Output Short Circuit Current VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.75 V 0.5 V VOL Output Low Voltage 0.5 V VOH Notes: Output High Voltage VOUT = 0.5V VIN = VIH or VIL, VCC = Min VIN = VIH or VIL, VCC = Min IOL = 24 mA Com., Ind. IOL = 16 mA IOH = -4.0 mA 2.4 V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. Shaded parts are obsolete with a last time buy date of 19 August 1999. 3 AC Waveforms(1) Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. AC Characteristics(1) -7 -10 -15 -25 Symbol Parameter tPD Input or Feedback to Non-Registered Output tCF Clock to Feedback tCO Clock to Output 2 tS Input or Feedback Setup Time 5 7.5 12 15 ns tH Hold Time 0 0 0 0 ns tP Clock Period 8 12 16 24 ns tW Clock Width 4 6 8 12 ns fMAX 8 outputs switching Min Max Min Max Min Max Min Max Units 3 7.5 3 10 3 15 3 25 ns 7 1 output switching ns 3 5 6 2 7 8 2 10 2 10 ns 12 ns External Feedback 1/(tS + tCO) 100 68 45 37 MHz Internal Feedback 1/(tS + tCF) 125 74 50 40 MHz No Feedback 1/(tP) 125 83 62 41 MHz tEA Input to Output Enable — Product Term 3 9 3 10 3 15 3 20 ns tER Input to Output Disable —Product Term 2 9 2 10 2 15 2 20 ns tPZX OE pin to Output Enable 2 6 2 10 2 15 2 20 ns tPXZ OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns Note: 4 1. See ordering information for valid part numbers and speed grades. 2. Shaded -25 parts are obsolete with a last-time buy date of August 19, 1999. 3. Shaded -7 and -15 parts are obsolete with a last-time buy date of September 30, 2006. ATF20V8B(Q)(L) ATF20V8B(Q)(L) Input Test Waveforms and Measurement Levels Output Test Loads Commercial tR, tF < 5 ns (10% to 90%) Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions CIN 5 8 pF VIN = 0V COUT 6 8 pF VOUT = 0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power-up Reset The registers in the ATF20V8Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR. Preload of Registered Outputs Parameter Description Typ Max Units tPR Power-up Reset Time 600 1,000 ns VRST Power-up Reset Voltage 3.8 4.5 V The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Security Fuse Usage Electronic Signature Word Programming/Erasing There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.” A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 5 Input and I/O Pull-ups All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V CC . This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below). Input Diagram I/O Diagram Functional Logic Diagram Description The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control. The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural 6 ATF20V8B(Q)(L) subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse. ATF20V8B(Q)(L) Compiler Mode Selection Registered Complex Simple Auto Select ABEL, Atmel-ABEL P20V8R P20V8C P20V8 P20V8 CUPL G20V8MS G20V8MA (1) G20V8 (1) G20V8A (1) LOG/iC GAL20V8_R GAL20V8_C7 GAL20V8_C8 GAL20V8 OrCAD-PLD “Registered” “Complex” “Simple” GAL20V8 PLDesigner P20V8 P20V8 P20V8 P20V8 Tango-PLD G20V8 G20V8 G20V8 G20V8 Note: 1. Only applicable for version 3.4 or lower. ATF20V8B Registered Mode PAL Device Emulation/PAL Replacement. The registered mode is used if one or more registers are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 20R8 20RP8 20R6 20RP6 20R4 20RP4 Registered Mode Operation 7 Registered Mode Logic Diagram 8 ATF20V8B(Q)(L) ATF20V8B(Q)(L) ATF20V8B Complex Mode PAL Device Emulation/PAL Replacement. In the complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 20L8 20H8 20P8 Complex Mode Operation ATF20V8B Simple Mode PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can be emulated using this mode: 14L8 14H8 14P8 16L6 18H6 16P6 18L4 18H4 18P4 20L2 20H2 20P2 Simple Mode Option 9 Complex Mode Logic Diagram 10 ATF20V8B(Q)(L) ATF20V8B(Q)(L) Simple Mode Logic Diagram 11 12 ATF20V8B(Q)(L) ATF20V8B(Q)(L) 13 14 ATF20V8B(Q)(L) ATF20V8B(Q)(L) ATF20V8B Ordering Information tPD (ns) tS (ns) tCO (ns) Ordering Code Package 7.5 5 5 ATF20V8B-7JC ATF20V8B-7PC ATF20V8B-7SC ATF20V8B-7XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 10 7.5 7 ATF20V8B-10JC ATF20V8B-10PC ATF20V8B-10SC ATF20V8B-10XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF20V8B-10JI ATF20V8B-10PI ATF20V8B-10SI ATF20V8B-10XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) ATF20V8B-15JC ATF20V8B-15PC ATF20V8B-15SC ATF20V8B-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF20V8B-15JI ATF20V8B-15PI ATF20V8B-15SI ATF20V8B-15XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) 15 Note: 12 10 Operation Range 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006. ATF20V8B Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) tS (ns) tCO (ns) 10 7.5 7 Ordering Code Package ATF20V8B-10JU ATF20V8B-10PU 28J 24P3 Operation Range Industrial (-40°C to 85°C) Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%. Package Type 28J 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 15 ATF20V8BQ and ATF20V8BQL Ordering Information tPD (ns) tS (ns) tCO (ns) 10 7.5 15 15 Note: Ordering Code Package Operation Range 7 ATF20V8BQ-10JC ATF20V8BQ-10PC ATF20V8BQ-10XC 28J 24P3 24X Commercial (0°C to 70°C) 12 10 ATF20V8BQL-15JC ATF20V8BQL-15PC ATF20V8BQL-15SC ATF20V8BQL-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 12 10 ATF20V8BQL-15JI ATF20V8BQL-15PI ATF20V8BQL-15SI ATF20V8BQL-15XI 28J 24P3 24S 24X Industrial (-40°C to 85°C)) 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006. ATF20V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) tS (ns) tCO (ns) 15 12 10 Note: Ordering Code Package ATF20V8BQL-15JU ATF20V8BQL-15PU 28J 24P3 Operation Range Industrial (-40°C to 85°C)) 1. Shaded parts are obsolete with a last-time buy date of September 30, 2006. Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%. Package Type 28J 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 16 ATF20V8B(Q)(L) ATF20V8B(Q)(L) Packaging Information 28J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 12.319 – 12.573 D1 11.430 – 11.582 E 12.319 – 12.573 E1 11.430 – 11.582 D2/E2 9.906 – 10.922 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 28J B 17 24P3 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 31.623 – 32.131 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.651 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 SYMBOL e NOTE Note 2 Note 2 2.540 TYP 6/1/04 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) ATF20V8B(Q)(L) DRAWING NO. 24P3 REV. D ATF20V8B(Q)(L) 24S – SOIC B D1 D PIN 1 ID PIN 1 e E A COMMON DIMENSIONS (Unit of Measure = mm) A1 0º ~ 8º L1 L SYMBOL MIN NOM MAX A – – 2.65 A1 0.10 – 0.30 D 10.00 – 10.65 D1 7.40 – 7.60 E 15.20 – 15.60 B 0.33 – 0.51 L 0.40 – 1.27 L1 0.23 – 0.32 e NOTE 1.27 BSC 06/17/2002 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. REV. 24S B 19 24X – TSSOP Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007) 4.48(0.176) 6.50(0.256) 4.30(0.169) 6.25(0.246) PIN 1 0.65(0.0256)BSC 7.90(0.311) 1.20(0.047)MAX 7.70(0.303) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0º ~ 8º 0.09(0.004) 0.75(0.030) 0.45(0.018) 04/11/2001 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) ATF20V8B(Q)(L) DRAWING NO. REV. 24X A ATF20V8B(Q)(L) Revision History Revision Level – Release Date History J – July 2006 Ordering Information tables updated to reflect obsolete parts. 21 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are ® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 0407J–07/06