AT93C86A - Complete

AT93C86A
3-wire Serial EEPROM
16K (2,048 x 8 or 1,024 x 16)
DATASHEET
Features

Low-voltage Operation
̶
̶

User-selectable Internal Organization
̶






16K: 2,048 x 8 or 1,024 x 16
3-wire Serial Interface
Sequential Read Operation
Schmitt Trigger, Filtered Inputs for Noise Suppression
2MHz Clock Rate (5V)
Self-timed Write Cycle (10ms Max)
High Reliability
̶
̶


VCC = 1.8V to 5.5V
VCC = 2.7V to 5.5V
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT93C86A provides 16,384 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 1,024 words of 16
bits each (when the ORG pin is connected to VCC) and 2,048 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage
operations are essential. The AT93C86A is available in space-saving 8-lead
JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 8-lead PDIP packages.
The AT93C86A is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and
the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C86A operates from 1.8V to 5.5V or from 2.7V to 5.5V.
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Configurations
Pin Name
Function
CS
Chip Select
(Top View)
1
8
VCC
2
7
NC
SK
Serial Data Clock
SK
DI
3
6
ORG
DI
Serial Data Input
DO
4
5
GND
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
NC
No Connect
CS
SK
DI
DO
CS
SK
DI
DO
1
2
3
4
8-pad UDFN
8-lead PDIP
(Top View)
(Top View)
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
VCC
NC
ORG
GND
8
7
6
5
CS
1
8
VCC
SK
2
7
NC
DI
3
6
ORG
DO
4
5
GND
Drawings are not to scale.
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . .-55C to +125C
Storage Temperature . . . . . . . . . . . . .-65C to +150C
Voltage on any pin
with respect to ground . . . . . . . . . . . -1.00V to +7.00V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
8-lead TSSOP
(Top View)
CS
Note:
2.
8-lead SOIC
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
GND
Memory Array
ORG
2,048 x 8
or
1,024 x 16
Address
Decoder
Data
Register
Output
Buffer
DI
CS
SK
Note:
Mode Decode
Logic
Clock
Generator
DO
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground,
the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input
beyond the capability of the internal 1M pull-up resistor, then the x16 organization is selected.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
3
4.
Memory Organization
4.1
Pin Capacitance
Table 4-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
4.2
1.
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
This parameter is characterized, and is not 100% tested.
DC Characteristics
Table 4-2.
DC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Unit
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
VCC = 5.0V
Min
Typ
ISB1
Standby Current
ISB2
Read at 1.0MHz
0.5
2.0
mA
Write at 1.0MHz
0.5
2.0
mA
VCC = 1.8V
CS = 0V
0.4
1.0
μA
Standby Current
VCC = 2.7V
CS = 0V
6.0
10.0
μA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
μA
IIL
Input Leakage
VIN = 0V to VCC
0.1
3.0
μA
IOL
Output Leakage
VIN = 0V to VCC
0.1
3.0
μA
VIL1(1)
Input Low Voltage
2.7V VCC  5.5V
0.6
0.8
V
VIH1(1)
Input High Voltage
2.7V VCC  5.5V
2.0
VCC + 1
V
VIL2(1)
Input Low Voltage
1.8V  VCC  2.7V
0.6
VCC x 0.3
V
VIH2(1)
Input High Voltage
1.8V  VCC  2.7V
VCC x 0.7
VCC + 1
V
VOL1
Output Low Voltage
2.7V  VCC  5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
2.7V  VCC  5.5V
IOH = 0.4mA
VOL2
Output Low Voltage
1.8V  VCC  2.5V
IOL = 0.15mA
VOH2
Output High Voltage
1.8V  VCC  2.7V
IOH = 100μA
Note:
4
Test Condition
1.
VIL min and VIH max are reference only, and are not tested.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
2.4
V
0.2
VCC  0.2
V
V
4.3
AC Characteristics
Table 4-3.
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to + 85°C, CL = 1 TTL gate and 100pF (unless otherwise
noted).
Symbol
Parameter
fSK
SK Clock Frequency
Test Condition
Max
Units
0
2
MHz
2.7V  VCC  5.5V
0
1
MHz
1.8V  VCC  5.5V
0
250
kHz
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
2.7V  VCC  5.5V
50
ns
1.8V  VCC  5.5V
200
ns
2.7V  VCC  5.5V
100
ns
1.8V  VCC  5.5V
400
ns
0
ns
2.7V  VCC  5.5V
100
ns
1.8V  VCC  5.5V
400
ns
SK High Time
tSKL
SK Low Time
tCS
Minimum CS Low Time
tCSS
CS Setup Time
Relative to SK
tDIS
DI Setup Time
Relative to SK
tCSH
CS Hold Time
Relative to SK
tDIH
DI Hold Time
Relative to SK
tPD1
Output Delay to 1
AC Test
tPD0
Output Delay to 0
AC Test
tSV
CS to Status Valid
AC Test
tDF
CS to DO in
High-impedance
tWP
Write Cycle Time
Endurance(1)
5.0V, 25°C
1.
Typ
4.5V  VCC  5.5V
tSKH
Note:
Min
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
2.7V  VCC  5.5V
250
ns
1.8V  VCC  5.5V
1000
ns
AC Test
2.7V  VCC  5.5V
150
ns
CS = VIL
1.8V  VCC  5.5V
400
ns
10
ms
1.8V  VCC  5.5V
0.1
3
1,000,000
Write
Cycles
This parameter is characterized, and is not 100% tested.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
5
5.
Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. Device operation
is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of
CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address
location.
Table 5-1.
AT93C86A Instruction Set
Address
Instruction
Data
Opcode
READ
1
10
A10 – A0
A9 – A0
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
11
A10 – A0
A9 – A0
WRITE
1
01
A10 – A0
A9 – A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
1.
x16
(1)
SB
Note:
x8
(1)
x8
x16
Comments
Reads data stored in memory at
specified address.
Write Enable must precede all
programming modes.
Erases memory location AN – A0.
D7 – D0
D15 – D0
Writes memory location AN – A0.
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
D7 – D0
D15 – D0
Writes all memory locations.
Valid only at VCC = 4.5V to 5.5V and
Disable Register cleared.
Disables all programming
instructions.
The ‘X’ in the address field represent don’t care values, and must be clocked.
READ: The READ instruction contains the address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the Serial Output
pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be
noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C86A supports
sequential Read operations. The device will automatically increment the internal address pointer and clock out
the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not
be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out.
Note:
6
Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or VCC
power is removed from the part.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 1 at the
DO pin indicates that the selected memory location has been erased, and the part is ready for another
instruction.
WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory
location. The self-timed programming cycle, tWP, starts after the last bit of data is received at Serial Data Input
pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of tCS. A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the
memory location at the specified address has been written with the data pattern contained in the instruction, and
the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the
end of the self-timed programming cycle, tWP.
Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought
high after being kept low for a minimum of tCS. The ERAL instruction is valid only at VCC = 5.0V ± 10%.
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of tCS. The WRAL instruction is valid only at VCC = 5.0V ± 10%.
Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
7
6.
Timing Diagrams
Figure 6-1.
Synchronous Data Timing
CS
SK
VIH
1µs (1)
VIL
tSKH
tCSS
tCSH
VIH
VIL
tDIH
tDIS
DI
tSKL
VIH
VIL
tPD0
DO (Read)
tDF
tPD1
VOH
VOL
tDF
tSV
DO (Program)
VOH
Status Valid
VOL
Note:
1.
This is the minimum SK period.
Table 6-1.
Organization Key for Timing Diagrams
AT93C86A (16K)
I/O
x8
x16
AN
A10
A9
DN
D7
D15
Figure 6-2.
ERASE Timing
tCS
Standby
Check
Status
CS
SK
DI
1
1
1
AN
AN-1 AN-2
...
A0
tDF
tSV
DO
High-impedance
High-impedance
Busy
Ready
tWP
8
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
Figure 6-3.
READ Timing
tCS
CS
SK
DI
DO
Figure 6-4.
1
1
0
AN
A0
High-impedance
0
DN
D0
EWEN Timing
tCS
CS
SK
DI
Figure 6-5.
1
0
0
1
...
1
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
High-impedance
Busy
Ready
tWP
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
9
Figure 6-6.
ERAL Timing(1)
tCS
Standby
Check
Status
CS
SK
1
DI
0
0
1
0
tDF
tSV
High-impedance
DO
High-impedance
Busy
Ready
tWP
Note:
1.
VCC = 4.5V to 5.5V.
Figure 6-7.
WRAL Timing(1)
tCS
CS
SK
1
DI
0
0
0
1
...
DN
...
D0
High-impedance
DO
Busy
tWP
Note:
1.
Figure 6-8.
Valid only at VCC = 4.5V to 5.5V.
EWDS Timing
tCS
CS
SK
DI
10
1
0
0
0
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
0
...
Ready
7.
Ordering Code Detail
A T 9 3 C 8 6 A N - 1 0 S U - 1 .8 - E
Atmel Designator
Product Family
93C = Microwire-Compatible
3-Wire Serial EEPROM
Shipping Carrier Option
Blank = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Expanded Quantity Option
Operating Voltage
1.8 or 18 = 1.8V to 5.5V
2.7 = 2.7V to 5.5V
Device Density
86 = 16-Kilobit
Device Revision
Package Variation
(Package Type Dependent)
N = 0.150” width SOIC
Y6 = 2.0x3.0mm body UDFN
Package Device Grade
U = Green, Matte Tin Lead Finish
or SnAgCu Ball
Industrial Temperature Range
(-40°C to +85°C)
H = Green, NiPdAu Lead Finish
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Type
S
T
Y
P
=
=
=
=
JEDEC SOIC
TSSOP
UDFN
PDIP
Speed Type
10 = Default value
Note: This field is not used for
Serial EEPROM products.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
11
8.
Part Markings
AT93C86A: Package Marking Information
8-lead TSSOP
8-lead SOIC
ATMELYWW
93C86A
SU%%
U%
AT###
Note: Lot Number, location of assembly and
YWW date code on the bottom side of
the package.
Note: Lot Number and location of assembly
on the bottom side of the package.
8-pad UDFN
8-lead PDIP
2.0 x 3.0 mm Body
ATMLUYWW
93C86A
PU%%
###
H%
YXX
Note: Lot Number and location of assembly
on the bottom side of the package.
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT93C86A
Truncation Code ###: 86A
Date Codes
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
Voltages
8: 2018
9: 2019
0: 2020
1: 2021
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
3 or 27: 2.7V min
1 or 18: 1.8V min
Grade/Lead Finish Material
H: Industrial/NiPdAu
U: Industrial/Matte Tin/SnAgCu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
6/11/14
TITLE
DRAWING NO.
REV.
93C86ASM
A
93C86ASM, AT93C86A Package Marking Information
Package Mark Contact:
[email protected]
12
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
9.
Ordering Information
Atmel Ordering Code (1)
Lead
Finish
Delivery Information
Package
Voltage
Form
Quantity
1.8V to 5.5V
Tape and Reel
4,000 per Reel
2.7V to 5.5V(1)
Tape and Reel
4,000 per Reel
1.8V to 5.5V
Tape and Reel
5,000 per Reel
AT93C86A-10TU-2.7
2.7V to 5.5V(1)
Tape and Reel
5,000 per Reel
AT93C86A-10PU-1.8
1.8V to 5.5V
Tape and Reel
4,000 per Reel
2.7V to 5.5V(1)
Tape and Reel
4,000 per Reel
Tape and Reel
5,000 per Reel
Tape and Reel
15,000 per Reel
AT93C86A-10SU-1.8
Operation
Range
8S1
AT93C86A-10SU-2.7
AT93C86A-10TU-1.8
NiPdAu
Lead-free
Halogen-free
8X
AT93C86A-10PU-2.7
AT93C86AY6-10YH-1.8
AT93C86AY6-10YH-18-E
AT93C86A-W1.8-11(2)
Notes:
Matte Tin
Lead-free
Halogen-free
8P3
NiPdAu
Lead-free
Halogen-free
8MA2
N/A
Wafer Sale
Industrial
Temperature
(-40C to 85C)
1.8V to 5.5V
1.8V to 5.5V
Note 2
1. For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in Section 4.2, “DC Characteristics”
and 4.3, “AC Characteristics” on page 5.
2. For Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please
contact Atmel sales.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC)
8X
8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP)
8P3
8-lead, 0.300” wide body, Plastic Dual In-line Package (PDIP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
13
10.
Packaging Information
10.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
MIN
NOM
MAX
–
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
SYMBOL
A
D
4.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
NOTE
3/6/2015
Package Drawing Contact:
[email protected]
14
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
GPC
SWB
DRAWING NO.
REV.
8S1
H
10.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
D
SYMBOL
Side View
Notes:
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
NOTE
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
0.65 BSC
L
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
[email protected]
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
REV.
E
15
10.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
C
A1
E2
b (8x)
8
7
1
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.40
1.50
1.60
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
b
0.18
0.25
0.30
C
L
3
0.152 REF
0.35
e
K
NOTE
0.40
0.45
0.50 BSC
0.20
-
-
11/2/15
Package Drawing Contact:
[email protected]
16
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
DRAWING NO.
REV.
YNZ
8MA2
H
10.4
8P3 — 8-lead PDIP
E
1
E1
.381
Gage Plane
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
e
D1
A2 A
A1
b2
b3
b v
4 PLCS
Side View
L
0.254 m C
MIN
NOM
MAX
A
-
-
5.334
A1
0.381
A2
2.921
3.302
4.953
b
0.356
0.457
0.559
5
b2
1.143
1.524
1.778
6
b3
0.762
0.991
1.143
6
c
0.203
0.254
0.356
D
9.017
9.271
10.160
3
D1
0.127
0.000
0.000
3
E
7.620
7.874
8.255
4
E1
6.096
6.350
7.112
3
3.810
2
SYMBOL
-
e
Notes:
2
-
2.540 BSC
eA
L
NOTE
7.620 BSC
2.921
3.302
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
07/31/14
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
8P3, 8-lead, 0.300” Wide Body, Plastic Dual
In-line Package (PDIP)
PTC
8P3
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
REV.
E
17
11.
Revision History
Revision No.
Date
Comments
3408K
12/2015
3408J
01/2015
3408I
08/2014
Update pinouts, 8MA2 package drawing, grammatical changes, document template,
logos, and disclaimer page. No changes to functional specification.
3408H
01/2007
Add “Bottom View” to page 1 Ultra Thin MiniMap package drawing page 4 revise Note 1
added “ensured by characterization”.
Correct Ordering Code Detail and update the 8S1 and 8MA2 package drawings.
Add the UDFN extended quantity option and update the ordering information section.
Update the 8MA2 and 8P3 package drawings.
Revision history implemented.
3408G
18
07/2006
Delete ‘Preliminary’ status from datasheet; Add ‘Ultra Thin’ description to MLP 2x3
package; Delete ‘1.8V not available’ on Figure 1 Note; Add 1.8V range on Table 4 under
Write Cycle Time.
AT93C86A [DATASHEET]
Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015
XXXXXX
Atmel Corporation
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© 2015 Atmel Corporation. / Rev.: Atmel-3408K-SEEPROM-AT93C86A-Datasheet_122015.
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