SAM4S-EK2 .................................................................................................................... User Guide 11176A–ATARM–24-Sep-12 Section 1 Introduction .................................................................................................................1-1 1.1 SAM4S Evaluation Kit ........................................................................................................ 1-1 1.2 User Guide ......................................................................................................................... 1-1 1.3 References and Applicable Documents ............................................................................. 1-1 Section 2 Kit Contents ................................................................................................................2-1 2.1 Deliverables ....................................................................................................................... 2-1 2.2 Electrostatic Warning ......................................................................................................... 2-2 Section 3 Power Up ....................................................................................................................3-1 3.1 Power up the Board ........................................................................................................... 3-1 3.2 DevStart ............................................................................................................................. 3-1 3.3 Recovery Procedure .......................................................................................................... 3-1 3.4 Sample Code and Technical Support ................................................................................ 3-2 Section 4 Evaluation Kit Hardware .............................................................................................4-1 4.1 Board Overview.................................................................................................................. 4-1 4.2 Features List ...................................................................................................................... 4-2 4.3 Function Blocks.................................................................................................................. 4-2 4.3.1 Processor............................................................................................................. 4-2 4.3.2 Memory ................................................................................................................ 4-2 4.3.3 Clock Circuitry...................................................................................................... 4-3 4.3.4 Reset Circuitry ..................................................................................................... 4-4 4.3.5 Power Supply and Management.......................................................................... 4-4 4.3.6 UART ................................................................................................................... 4-5 4.3.7 USART................................................................................................................. 4-5 4.3.8 Display Interface .................................................................................................. 4-6 4.3.9 JTAG/ICE............................................................................................................. 4-8 4.3.10 Audio Interface..................................................................................................... 4-9 4.3.11 USB Device ....................................................................................................... 4-11 4.3.12 Analog Interface ................................................................................................ 4-11 4.3.13 QTouch Elements .............................................................................................. 4-12 4.3.14 User Buttons ...................................................................................................... 4-13 4.3.15 LEDs .................................................................................................................. 4-14 4.3.16 SD/MMC Card ................................................................................................... 4-14 4.3.17 ZigBEE............................................................................................................... 4-14 4.3.18 PIO Expansion ................................................................................................... 4-15 SAM4S-EK2 User Guide 1-1 11176A–ATARM–24-Sep-12 4.4 4.5 Configuration.................................................................................................................... 4-16 4.4.1 PIO Usage ......................................................................................................... 4-16 4.4.2 Jumpers ............................................................................................................. 4-19 4.4.3 Test Points ......................................................................................................... 4-20 4.4.4 Assigned PIO Lines, Disconnection Possibility.................................................. 4-20 Connectors....................................................................................................................... 4-22 4.5.1 Power Supply Connector J9 .............................................................................. 4-22 4.5.2 USART Connector J5 With RTS/CTS Handshake Support ............................... 4-22 4.5.3 UART Connector J7 .......................................................................................... 4-23 4.5.4 USB Device Connector J15 ............................................................................... 4-23 4.5.5 TFT LCD Connector J8...................................................................................... 4-23 4.5.6 JTAG Debugging Connector J6 ......................................................................... 4-25 4.5.7 SD/MMC - MCI Connector J3 ............................................................................ 4-26 4.5.8 Analog Connector CN1 & CN2 .......................................................................... 4-27 4.5.9 RS485 Connector J14 ....................................................................................... 4-27 4.5.10 Headphone Connector J11 ................................................................................ 4-28 4.5.11 ZigBEE Connector J16 ...................................................................................... 4-28 4.5.12 PIO Expansion Port C Connector J12 ............................................................... 4-29 4.5.13 PIO Expansion Port A Connector J13 .............................................................. 4-30 4.5.14 PIO Expansion Port B Connector J14 ............................................................... 4-31 Section 5 Schematics .................................................................................................................5-1 5.1 Schematics......................................................................................................................... 5-1 Section 6 Troubleshooting ..........................................................................................................6-1 6.1 Self-Test............................................................................................................................. 6-1 6.2 Board Recovery ................................................................................................................. 6-1 Section 7 Revision History..........................................................................................................7-1 7.1 Revision History ................................................................................................................. 7-1 SAM4S-EK2 User Guide 1-2 11176A–ATARM–24-Sep-12 Section 1 Introduction 1.1 SAM4S Evaluation Kit The SAM4S Evaluation Kit (SAM4S-EK2) enables evaluation capabilities and code development of applications running on a SAM4SD32 device. 1.2 User Guide This guide focuses on the SAM4S-EK2 board as an evaluation platform. It is made up of 6 sections: 1.3 Section 1 includes references, applicable documents, acronyms and abbreviations. Section 2 describes the kit contents, its main features and specifications. Section 3 provides instructions to power up the SAM4S-EK2 and describes how to use it. Section 4 provides board specifications, describes the development environment and presents the hardware resources, default jumper, switch settings and connectors. Section 5 provides schematics. Section 6 provides troubleshooting instructions. References and Applicable Documents Table 1-1. References and Applicable Documents Title Comment SAM4SD32 Datasheet www.atmel.com SAM4S-EK2 User Guide 1-1 11176A–ATARM–24-Sep-12 Section 2 Kit Contents 2.1 Deliverables The Atmel® SAM4S-EK2 toolkit contains the following items: Board: – a SAM4S-EK2 board – a universal input AC/DC power supply with US, Europe and UK plug adapters Cables: – one USB cable – one serial RS232 cable A Welcome Letter Figure 2-1. Unpacked SAM4S-EK2 Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit. SAM4S-EK2 User Guide 2-1 11176A–ATARM–24-Sep-12 Kit Contents 2.2 Electrostatic Warning The SAM4S-EK2 board is shipped in a protective anti-static bag. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board. SAM4S-EK2 User Guide 2-2 11176A–ATARM–24-Sep-12 Section 3 Power Up 3.1 Power up the Board Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it into the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The board LCD should light up and display a welcome page. Then, click or touch the icons displayed on the screen and enjoy the demo. 3.2 Sample Code and Technical Support After boot up, you can run some sample code or your own application on the development kit. You can download sample code and get technical support from the Atmel web site: http://www.atmel.com SAM4S-EK2 User Guide 3-1 11176A–ATARM–24-Sep-12 Section 4 Evaluation Kit Hardware 4.1 Board Overview This section introduces the Atmel SAM4S-EK2 Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments. The SAM4S-EK2 board is based on the integration of an ARM® Cortex®-M4 processor with on-board NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications. Figure 4-1. SAM4S-EK2 Block Diagram SAM4S-EK2 User Guide 4-1 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.2 Features List Here is the list of the main board components and interfaces: SAM4SD32 chip LQFP100 package with optional socket footprint 12 MHz crystal 32.768 KHz crystal Optional SMB connector for external system clock input NAND Flash 2.8 inch TFT color LCD display with touch panel and backlight UART port with level shifter circuit USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit Microphone input and mono/stereo headphone jack output SD/MMC interface Reset button: NRST User buttons: Left and Right QTouch® buttons: Up, Down, Left, Right, Valid and Slider Full Speed USB device port JTAG/ICE port On-board power regulation Two user LEDs Power LED BNC connector for ADC input BNC connector for DAC output User potentiometer connected to the ADC input ZigBEE connector 2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB) 4.3 Function Blocks 4.3.1 Processor The SAM4S-EK2 is equipped with a SAM4SD32 device in LQFP100 package. 4.3.2 Memory The SAM4SD32 chip embeds: 2048 Kbytes of embedded Flash 160 Kbytes of embedded SRAM 16 Kbytes of ROM with embedded BootLoader routines (UART, USB) and In-Application Programming functions (IAP) routines SAM4S-EK2 User Guide 4-2 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware The SAM4SD32 features an External Bus Interface (EBI) that permits interfacing to a broad range of external memories and virtually to any parallel peripheral. The SAM4S-EK2 board is equipped with a memory device connected to the SAM4 EBI: One NAND Flash MT29F2G08ABAEA. Figure 4-2. NAND Flash +3 V3 +3 V3 R1 5 47 K NANDFLASH R1 6 47 K 16 17 8 18 PC17 PC16 PC9 PC10 JP 9 He ade r2 9 PC14 PC18 R1 9 7 19 0R 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 +3 V3 R2 1 MN3 MT29F2G08ABAEA 47 K R2 2 0R DNP DG ND CL E AL E RE WE I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE R/B WP N.C28 N.C27 N.C26 N.C25 N.C24 N.C23 PRE N.C22 N.C21 N.C20 N.C19 N.C18 N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 VCC VCC VS S VS S 29 30 31 32 41 42 43 44 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 48 47 46 45 40 39 38 35 34 33 28 27 +3 V3 37 12 36 13 C2 7 10 0nF C2 8 10 0nF C2 9 1u F DG ND NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper can disconnect it from the on-board memories, thereby letting NCS0 free for other custom purposes. 4.3.3 Clock Circuitry The clock generator of a SAM4SD32 microcontroller is composed of: A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB) A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default value), 8 or 12 MHz. A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the peripherals. The input frequency of PLLA is from 7.5 to 20 MHz The SAM4S-EK2 board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator 12 MHz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default). Figure 4-3. External Clock Source NOT POPULATED J1 1 3 5 C3 20pF DNP R11 0R XIN32 1 R1 R2 49.9R 1% R3 3 DNP Y3 32.768KHz 1 MN1 C1 DGND 20pF R4 0R XIN 2 2 4 XOUT32 DGND DGND 3 Y1 DNP Y2 2 DGND DGND SAM4S-EK2 User Guide R7 DNP 12MHz R5 C2 PB9 R6 PB8 R8 0R DNP 97 XOUT 20pF DNP 96 PB9 _XIN SAM4SD32 PB8_XOUT PA7_RTS0_PWMH3 PA8_CTS0_AD12BTRG R12 0R C4 20pF 49 48 XIN32 R9 XOUT32 R10 DNP DNP PA7 PA8 4-3 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware The SAM4SD32 chip internally generates the following clocks: 4.3.4 SLCK, the Slow Clock, which is the only permanent clock of the system MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz Fast RC Oscillator PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA) PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB) Reset Circuitry On-board NRST button BP1 provides an external reset control of the SAM4SD32. The NRST pin is bidirectional. It is handled by the on-chip reset controller. It can be driven low to provide a reset signal out to the external components. Conversely, it can be asserted low from the outside to reset the microcontroller Core and the peripherals. The NRST pin integrates a permanent pull-up resistor of 100 kOhm to VDDIO. On the SAM4S-EK2 board, the NRST signal is connected to the LCD module and JTAG port. Note: 4.3.5 At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom application, you need to check for these device’s datasheets about reset duration requirements. Then, you need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM4SD32 datasheet for in-depth information. Power Supply and Management The SAM4S-EK2 board is supplied with an external 5V DC block through input J9. It is protected by a PolyZen diode (MN9) and an LC combinatory filter (MN10). The PolyZen is used in the event of an incorrect power supply connection. The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board. Figure 4-4. Power Block MN10 BNX002-01 J9 MN9 MP179P 2.1mm ZEN056V130A24LS 1 1 3 2 1 2 2 3 C64 100nF + C65 22uF SV CV SG CG1 CG2 CG3 +5V 3 4 5 6 + C66 22uF DGND MN12 MIC29152W U Micrel's 1.5A LDO, TO263-5 +5V +3V3 ADJ GND2 SD GND1 VOUT 3 1 VIN 4 5 R89 169K 1% + C75 100uF 6 2 C76 100nF R92 102K 1% DGND The SAM4SD32 product has different types of power supply pins: VDDIN pin: Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies. The voltage ranges from 1.8V to 3.6V. SAM4S-EK2 User Guide 4-4 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware VDDIO pins: Power for the Peripherals I/O lines. The voltage ranges from 1.62V to 3.6V. VDDOUT pin: Output of the internal voltage regulator. VDDCORE pins: Power for the core, including the processor, embedded memories and peripherals. The voltage ranges from 1.62V to 1.95V. VDDPLL pin: Power for the PLL A, PLL B and 12 MHz oscillator. The voltage ranges from 1.62V to 1.95V. Note: 4.3.6 VDDPLL should be decoupled and filtered from VDDCORE. UART The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART is associated with two PDC channels to reduce the processor time on packet handling. This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to the DB9 male connector J7. Figure 4-5. UART MN6 MAX3232CSE +3V3 16 R45 100K PA10 PA9 TP5 SMD +3V3 C40 100nF C1+ 1 C38 100nF 2 6 V+ C1- V- C2+ 3 4 C41 100nF R46 100K 15 R47 0R R48 0R TP6 SMD J7 1 6 2 7 3 8 4 9 5 C42 100nF 11 12 10 9 GND T1IN R1OUT T2IN R2OUT C2T1OUT R1IN T2OUT R2IN 5 14 13 7 8 DGND DGND 11 +3V3 VCC 10 C39 100nF FGND 4.3.7 USART The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data length, parity, number of stop bits) to support a broad range of serial communication standards. The USART is also associated with PDC channels for TX/RX data access. Note: For design optimization purposes, both transmitters have been implemented on the same PIO lines, that is PA21, 22, 23, 24, 25. To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21. Should you need to implement an RS485 channel in place of the RS232, follow the procedure below: 1. make sure your software will permanently set PA23 to a high level - this will permanently disable the RS232 receiver. 2. change JP31 to make sure that 2-3 pins are connected. SAM4S-EK2 User Guide 4-5 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.3.7.1 RS232 SAM4S-EK2 connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5. Figure 4-6. USART Evaluation Kit Hardware USART C3 1 4.7 uF C3 2 10 0nF C3 3 10 0nF 1 21 DG ND C3 6 10 0nF 23 R3 2 47 K +3 V3 19 5 PA 23 R3 1 0R PA 22 PA 21_ 232 PA 24 PA 25 R3 3 R3 4 R3 5 R3 6 R3 7 0R 0R 0R 0R 47 K 7 10 8 11 9 12 +3 V3 MN5 ADM3 312 EARU VCC C1 + V+ C1 C2 + 6 C3 4 10 0nF 20 2 VC2 C3 + GND C3 5 10 0nF 4 24 J5 EN C3 - T1 IN R1 OUT T2 IN R2 OUT T3 IN R3 OUT T1 OUT R1 IN T2 OUT R2 IN T3 OUT R3 IN 1 6 2 7 3 8 4 9 5 C3 7 10 0nF SD 22 18 15 17 14 16 13 R3 8 0R DG ND 11 3 10 +3 V3 DG ND FG ND 4.3.7.2 RS485 As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bus termination resistors selection (JP10, JP11, JP12). Figure 4-7. RS485 +3 V3 +3 V3 RS485 R2 3 10 K PA 21_ 485 R2 5 0R 1 PA 25 R2 6 0R 2 PA 24 R2 7 0R 3 PA 22 R2 8 0R 4 MN4 ADM3 485 ARZ RO VCC RE GND R2 4 TB D DNP 8 5 DE DI A B 6 7 +3 V3 1 J4 2 DG ND 3 DNP JP 28 He ade r2 n m JP 10 He ade r2 C3 0 10 0nF R2 9 12 0R JP 11 He ade r2 JP 12 He ade r2 FG ND R3 0 TB D DNP DG ND 4.3.8 Display Interface The SAM4S-EK2 carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated driver IC is ILI9325. The LCD display area is 2.8 inches diagonally measured, with a native resolution of 240 x 320 dots. SAM4S-EK2 User Guide 4-6 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.3.8.1 LCD Module The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port and the push-button BP1. The LCD chip select signal is connected to NCS1; the jumper JP13 can disconnect it so that this PIO line is available for other custom usage. The SAM4SD32 communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol data bus has to be implemented in software. Figure 4-8. LCD Block +3 V3 + C4 3 10 uF PC[0..31] C4 4 10 0nF C4 5 10 0nF R4 9 47 K DG ND DG ND DG ND PC13 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 LCD_DB17 LCD_DB16 LCD_DB15 LCD_DB14 LCD_DB13 LCD_DB12 LCD_DB11 LCD_DB10 LCD_DB9 LCD_DB8 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 +3 V3 PC11 PC8 PC19 R5 6 10 K PC15 JP 13 He ade r2 NRST NRST LE D_A R5 9 0R LE D_K 1 LE D_K 2 LE D_K 3 LE D_K 4 Y_ UP Y_ DO WN X_ RIG HT X_ LEFT R5 8 4.7 K DG ND LCD_DB0 R6 1 LCD_DB4 LCD_DB2 LCD_DB3 LCD_DB1 LCD_DB8 LCD_DB6 LCD_DB7 LCD_DB5 1 2 3 4 1 2 3 4 LCD_DB9 R6 3 4.7 K DNP 8 7 RA 2 6 4.7 Kx4 5 DNP 8 7 RA 3 6 4.7 Kx4 5 DNP J8 FH26- 39S -0.3 SHW VDD DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 VDD RD WR RS CS RE SE T IM0 IM1 GND LE D-A LE DK 1 LE DK 2 LE DK 3 LE DK 4 Y+ YX+ XNC GND Z7 DG ND DG ND PIN 39 PINs on BOT FTM28 0C34D PIN 1 DG ND DG ND Six slots on PCBfor LCDshield LCD DG ND X_ RIG HT Y_ UP X_ LEFT Y_ DO WN 4.7 K DNP 1 The part is placed as close as possible to J8 5 4 3 2 DG ND D1 PA CDN04 4Y5 R TV S, S OT23-5 DNP NOT POPULATED DG ND 4.3.8.2 Backlight Control The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by an AAT3155 charge pump, MN8. The AAT3155 is controlled by the SAM4SD32 through a single PIO line PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for other custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently enabled by default. On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation. Figure 4-9. Backlight Control +3 V3 PC13 +3 V3 R6 8 0R R6 4 47 K 10 C5 4 1u F 9 11 5 FB 1 BN03K 31 4S3 00R C5 7 4.7 uF 4 MN8 AA T31 55ITP- T1 C1 + C2 + C1 EN/SE T C2 OUTCP IN GND D1 D2 D3 D4 7 6 C5 5 1u F TP 7 8 LE D_A 3 2 1 12 LE D_K 1 LE D_K 2 LE D_K 3 LE D_K 4 C5 6 1u F DG ND DG ND SAM4S-EK2 User Guide LCDBACKLIGHT 4-7 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.3.8.3 Touch Screen Interface The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device on the SAM4SD32 SPI bus. The controller sends back the information about the X and Y positions, as well as a measurement for the pressure applied to the touch panel. The touch panel can be used with either a stylus or a finger. The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two interrupt signals are connected and provide events information back to the microcontroller: PenIrq and Busy. Note: PenIrq (PA16) is shared with ZigBEE signal IRQ0. Busy (PA17) is shared with ZigBEE signal IRQ1. Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take care not to have both drivers enabled at the same time on either PA16 or PA17. For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect either end driver from the other: On the touch panel controller side, R67 and R69. On ZigBEE side, R117 and R120. For further information, refer to the “Schematics” section. Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test points (TP8, TP9) for optional function extension. Figure 4-10. Touch Panel Control +3V3 2 3 4 5 X_RIGHT Y_UP X_LEFT Y_DOWN TP8 AGND_TP DCLK DIN DOUT CS BUSY PENIRQ 7 8 4.3.9 XP YP XM YM TP9 R72 100K R62 100K MN7 ADS7843E R73 100K IN3 IN4 VREF VCC1 VCC2 GND LCDTOUCHSCREEN 16 14 12 15 PA14 PA13 PA12 +3V3 JP32 Header2 PA11 13 11 R67 0R 9 1 10 R70 0R 6 R65 100K PA17 R69 0R PA16 +3V3 C58 100nF C59 100nF C60 100nF R71 1R L2 10uH-100mA C61 4.7uF AGND_TP R74 0R DGND JTAG/ICE A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK2 for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger. Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port from this system reset signal. 2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M4 is not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to floating input, the internal pull-up resistor corresponding to this PIO line must be enabled. SAM4S-EK2 User Guide 4-8 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Figure 4-11. JTAG Interface +3V3 R39 100K R40 100K R41 100K R42 100K R43 100K PB4 PB6 PB7 PB5 NRST R44 0R J6 1 3 5 7 9 11 13 15 17 19 VTref Vsupply GND1 nTRST GND2 TDI GND3 TMS GND4 TCK GND5 RTCK GND6 TDO GND7 nSRST DBGRQ GND8 DBGACK GND9 2 4 6 8 10 12 14 16 18 20 DGND 4.3.10 Audio Interface The SAM4S-EK2 board supports both audio recording and playback. The audio volume can be adjusted using the potentiometer RV1, and the microphone amplifier gain can be adjusted via jumpers (fixed gain of 24 or 26 dB). 4.3.10.1 Microphone Input The embedded microphone is connected to an audio pre-amplifier using the TS922 operational amplifier (MN11). The gain is set by using JP14 and JP15 jumpers; both must be set or removed at the same time. By modifying the jumper positions, you can select each of the following gain values: 20 dB (default setting, both JP14 and JP15 are off) 26 dB (both JP14 and JP15 are on). Notes: 1. R83 is a default 0 Ohm resistor that enables the disconnection of PB0 from the audio input path for custom usage. 2. The audio pre-amplifier MN11 is powered by a dedicated low dropout regulator MIC5219-3.3 (MN14). SAM4S-EK2 User Guide 4-9 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Figure 4-12. Microphone Input AUDIO IN C6 2 10 0pF AV DD R7 7 47 0R C6 3 22 uF R7 8 1K R7 9 1K R8 0 1K AG ND R8 2 1K R8 4 1K C6 8 1u F R8 5 1K C7 3 22 uF C6 9 1n F R8 8 47 0R R8 7 47 K VCC OUT2 GND 6 R9 3 10 0K AG ND AV DD 8 JP 15 He ade r2 PB 0 VCC3 3 FB 2 C7 4 BN03K 31 4S3 00R 10 0nF R9 1 0R 4 IN2AG ND 5 AG ND R8 3 0R C7 1 22 nF AG ND R9 0 10 0K C7 7 4.7 uF R8 1 10 0R 1 C7 2 1n F AV DD AG ND He ade r2 IN1+ 7 AG ND JP 14 IN1- 3 R8 6 47 K AG ND 47 K OUT1 2 MIC1 SV B6 050 47 K R7 6 MN11 TS 922 2 1 C6 7 1u F R7 5 DG ND IN2+ JP14 and JP15 should be set or removed together AG ND 4.3.10.2 Headphone Output The SAM4S-EK2 evaluation kit supports mono/stereo audio playback driven by a TPA0223 audio amplifier connected to two DAC channels of the microcontroller. The TPA0223 is a 2W mono Bridge-Tied-Load (BTL) amplifier designed to drive speakers with as low as 4 Ohm impedance. The amplifier can be reconfigured on the fly to drive two stereo Single-Ended (SE) signals into head phones. Figure 4-13. Headphone Output 1 2 AUDIO OUT J1 0 JP 29 FB 3 BN03K 31 4S3 00R VDD_ AMP 2 + C8 0 10 uF C7 9 1u F 3 VCC3 3 MN13 TP A02 23DGQ 3 VDD RO /MO + 6 C8 1 C8 2 10 0nF + 1 +5 V R9 5 1K C8 4 JP 17 TP 12 Te st P ad S Q-4 0TH 0.4 7uF 33 K He ade R9 r29 47 K 1 LO /MO - 0.4 7uF R1 00 33 K JP 19 He ade R1 r204 47 K SHUTD0WN 33 K BY PA SS 9 AG ND C8 3 1K 22 0uF-TA N-6 .3V AG ND C8 5 R1 05 10 RIN MO NO -IN LIN ST/MN 11 AUDIO _O UTL C8 8 R9 8 5 P AD PB 13 AG ND + R9 7 DG ND 0.4 7uF J1 1 5 Ph one jack Ste reo 3.5 4 3 2 1 22 0uF-TA N-6 .3V GND 7 2 4 C8 6 R1 01 10 0K R1 03 10 0K 0.4 7uF R1 02 JP 20 He ade r2 8 AG ND AG ND VDD_ AMP 10 0K C8 7 1u F AG ND AG ND SAM4S-EK2 User Guide 4-10 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Using a readily available 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. When closed, a 100-kOhm/1-kOhm divider pulls the ST/MN input low. When a jack plug is inserted, the 1-kOhm resistor is disconnected and the ST/MN input is pulled high. The mono speaker (J10 connector) is also physically disconnected from the RO/MO+ output so that no sound is heard from the speaker while the headphones are inserted. 4.3.11 USB Device The SAM4SD32 UDP port is compliant with the Universal Serial Bus (USB) rev 2.0 Full Speed device specification. J15 is a micro B-type receptacle for USB device. Both 27-Ohm resistors R114 and R116 build up a 90-Ohm differential impedance together with the (embedded) 6-Ohm output impedance of the SAM4SD32 full speed channel drivers. R110 and R112 build up a divider bridge from VBUS +5V to implement plug-in detection (5V level gets lowered to a PIO compatible 3.3V level) through PC21. Figure 4-14. USB US B Micro B ID G 11 7 6 5 D+ 4 D- 3 5V 1 FG ND J1 5 TB D 2 10 8 9 RV 2 V5 .5MLA0 603 RV 1 V5 .5MLA0 603 PC21 R1 10 47 K R1 12 68 K C9 4 10 pF DG ND FG ND DG ND PB 10 R1 14 27 R PB 11 R1 16 27 R USB 4.3.12 Analog Interface 4.3.12.1 Analog Reference The 2.5V voltage reference is based on a LM4040 (Precision Micropower Shunt Voltage Reference). This ADVREF level can be set as 2.5V or 3.3V via the jumper JP2. Figure 4-15. Analog Vref VCC33 ADVREF +5V 1 1 2 ADVREF C5 100nF JP2 R13 2.2K 3 SAM4SD32 MN2 LM4040-2.5 DGND DGND SAM4S-EK2 User Guide 4-11 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.3.12.2 Analog Input The BNC connector CN1 is connected to the ADC port PB1 as an external analog input. An on-board 50Ohm resistor termination can be applied by closing jumper JP16. A low pass filter can be implemented for the BNC connector CN1 by replacing R94 and C78 with custom resistor and capacitor values, depending on your application requirements. A 10-KOhm potentiometer (VR1) is also connected to this channel to implement an easy access to ADC programming and debugging (or implement an analog user control like display brightness, volume, etc.). Either of these two functions can be selected by jumper JP18. Figure 4-16. ADC Input CN1 BNC R9 4 0R JP 16 He ade r2 C7 8 10 nF R9 6 49 .9R 3 DG ND AD5 VCC3 3 VR1 10 K V R 2 C8 9 10 nF 1 2 JP 18 PB 1 1 3 Potentiometer Clockwise 2-->3 ADC DG ND 4.3.12.3 Analog Output The BNC connector CN2 is connected to the DAC port PB13 and provides an external analog output. An on-board 50-Ohm resistor termination can be enabled by closing jumper JP21. A filter can be implemented on this output channel by replacing R106 and C90 with appropriate resistor and capacitor values, depending on the application requirements. Figure 4-17. DAC Output CN2 BNC 3 R106 0R JP21 Header2 C90 DAC1 2.2uF 2 JP30 PB13 1 R109 49.9R AUDIO_OUTL DGND 4.3.13 DAC QTouch Elements QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive effect of human fingers approaching it. 4.3.13.1 Keys The SAM4S-EK2 implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and VALID) using five pairs of PIO. SAM4S-EK2 User Guide 4-12 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Figure 4-18. QST Keys PC25 R51 1K C47 22nF PC24 PC31 R53 K1 DNP 1K C49 22nF PC30 PC29 R55 1K C51 22nF PC28 PC23 R57 1K C52 22nF PC22 PC27 R60 1K C53 22nF PC26 4.3.13.2 Slider A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition method using three pairs of PIOs. Such a sensor is used to detect a linear finger displacement on a sensitive area. A typical implementation is volume control. Figure 4-19. QT_Slider S1 QTouch S lide r SR PA 1 R5 0 1K C4 6 22 nF SL PA 0 PA 3 R5 2 1K SM C4 8 22 nF PA 2 SR PA 5 R5 4 1K C5 0 22 nF PA 4 22nF use X7R 4.3.14 User Buttons There are two mechanical user buttons on the SAM4S-EK2, which are connected to PIO lines and defined to be "left" and "right" buttons by default. In addition, a mechanical button controls the system reset, signal NRST. Figure 4-20. System Buttons BP1 1 2 3 4 BP2 1 2 3 4 BP3 1 2 3 4 NRST JP25 PB3 JP26 PC12 DGND SAM4S-EK2 User Guide 4-13 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.3.15 LEDs There are three LEDs on the SAM4S-EK2 board: A blue LED (D2) and a green LED (D3), which are user defined and controlled by the GPIO. A red LED (D4), which is a power LED indicating that the 3.3V power rail is active. It is also controlled by the GPIO and can be treated as a user LED as well. The only difference with the two others is that it is controlled through a MOS transistor. By default, the PIO line is disabled; a pull-up resistor controls the MOS to light the LED when the power is ON. Figure 4-21. LEDs +3V3 PA19 R111 220R D2 Blue-led PA20 R113 220R D3 Green-led PC20 R115 100K 1 Q1 IRLML2502 2 3 R117 220R D4 Red-led DGND 4.3.16 SD/MMC Card The SAM4S-EK2 has a high-speed 4-bit multimedia MMC interface, which is connected to a 4-bit SD/MMC micro card slot featuring a card detection switch. Figure 4-22. SD Card 4 3 2 1 +3 V3 SDCARD R1 8 10 K RA 1 68 Kx4 J3 TF01A 5 6 7 8 R1 7 10 K PA 26 PA 27 PA 28 R1 26 R1 27 0R 0R PA 29 R2 0 0R PA 30 PA 31 R1 24 R1 25 0R 0R 1 2 3 4 5 6 7 8 10 9 PA 6 + C2 5 10 uF DA T2 DA T3 CMD VCC CL K VS S DA T0 DA T1 GND CD Sh 1 Sh 2 Sh 3 11 12 13 DG ND C2 6 10 0nF DG ND 4.3.17 ZigBEE SAM4S-EK2 has a 10-pin male connector for the RZ600 ZigBEE module. Note: SAM4S-EK2 User Guide 0 Ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the design, thereby enabling their individual disconnection, should a conflict occur in your application. 4-14 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Figure 4-23. ZigBEE Interface PA 18 R1 18 PA 17 R1 19 PB 2 PA 12 ZB_RSTN IRQ1_ZBEE SPIO_NPCS2# MISO J1 6 HE 10 5x2 2 4 6 8 10 1 3 5 7 9 0R 0R R1 20 R1 21 0R 0R C9 5 18 pF C9 6 2.2 nF IRQ0_ZBEE SLP_TR MOSI SPCK JP 27 He ade r2 +3 V3 C9 7 2.2 uF DG ND ZIGBEE 4.3.18 PA 16 PA 15 PA 13 PA 14 PIO Expansion The SAM4S-EK2 product features three PIO controllers, PIOA, PIOB and PIOC, which are multiplexed with the I/O lines of the embedded peripherals. Each PIO Controller controls up to 32 lines (16 for PIOB). Expansion ports J12, J13 and J14 provide PIO lines access for customer defined usage. Figure 4-24. PIO Expansion PB [0..14] PA [0..31] PC[0..31] +5 V JP 23 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 +3 V3 DG ND Note: SAM4S-EK2 User Guide J1 2 PIO C +3 V3 3 +5 V JP 24 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC16 PC17 PC18 PC19 PC20 PC21 PA 6 PA 7 PA 8 PA 9 PA 10 PA 11 PA 12 PA 13 PA 14 PA 15 +3 V3 DG ND +3 V3 DG ND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J1 3 PIO A +3 V3 3 1 2 +3 V3 3 2 JP 22 1 2 +5 V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PA 16 PA 17 PA 18 PA 19 PA 20 PA 21 PA 22 PA 23 PA 24 PA 25 PA 26 PA 27 PA 28 PA 29 PA 30 PA 31 PB 0 PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7 +3 V3 DG ND 1 3 5 7 9 11 13 15 17 19 21 23 J1 4 2 4 6 8 10 12 14 16 18 20 22 24 PIO B PB 8 PB 9 PB 10 PB 11 PB 12 PB 13 PB 14 +3 V3 DG ND +3 V3 DG ND All PIO lines are available on these expansion connectors, except those that are used for the QTouch elements. 4-15 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.4 Configuration This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM4S-EK2 board. 4.4.1 PIO Usage Table 4-1. PIO Port A Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function 1 PA0 PWMH0 TIOA0 A17 WKUP0 QTouch slider (left) SNS 2 PA1 PWMH1 TIOB0 A18 WKUP1 QTouch slider (left) SNSK 3 PA2 PWMH2 SCK0 DATRG WKUP2 QTouch slider (middle) SNS 4 PA3 TWD0 NPCS3 5 PA4 TWCK0 TCLK0 WKUP3 QTouch slider (right) SNS 6 PA5 RXD0 NPCS3 WKUP4 QTouch slider (right) SNSK 7 PA6 TXD0 PCK0 8 PA7 RTS0 PWMH3 9 PA8 CTS0 AD12BTR G 10 PA9 URXD0 NPCS1 11 PA10 UTXD0 NPCS2 12 PA11 NPCS0 PWMH0 13 PA12 MISO PWMH1 MISO_TSC ZigBEE MISO 14 PA13 MOSI PWMH2 MOSI_TSC ZigBEE MOSI 15 PA14 SPCK PWMH3 SPCK_TSC ZigBEE CLK 16 PA15 TF TIOA1 PWML3 WKUP14 / PIO_DCEN1 ZigBEE SLPTR 17 PA16 TK TIOB1 PWML2 WKUP15 / PIO_DCEN2 IRQ_TSC ZigBEE IRQ0 18 PA17 TD PCK1 PWMH3 AD0 BUSY_TSC ZigBEE IRQ1 19 PA18 RD PCK2 A14 AD1 ZigBEE RSTN 20 PA19 RK PWML0 A15 AD2/ WKUP9 Blue LED (UserLED1) 21 PA20 RF PWML1 A16 AD3/ WKUP10 Green LED (UserLED2) 22 PA21 RXD1 PCK1 23 PA22 TXD1 NPCS3 24 PA23 SCK1 25 PA24 26 Comment QTouch slider (middle) SNSK MCI card detection WKUP5 PWMFI0 WKUP6 XIN32 CLK32KHz XOUT32 CLK32KHz UART receive data UART transmit data WKUP7 WKUP8 NPCS0# (TSC) AD8 USART RXD NCS2 AD9 USART TXD PWMH0 A19 POI_DCCLK RTS1 PWMH1 A20 POI_DC0 USART RTS PA25 CTS1 PWMH2 A23 POI_DC1 USART CTS 27 PA26 DCD1 TIOA2 MCDA2 POI_DC2 MCI data bit 2 28 PA27 DTR1 TIOB2 MCDA3 POI_DC3 MCI data bit 3 29 PA28 DSR1 TCLK1 MCCDA POI_DC4 MCI command SAM4S-EK2 User Guide USART transceiver enable 4-16 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-1. PIO Port A Pin Assignments and Signal Descriptions (Continued) No I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function 30 PA29 RI1 TCLK2 MCCK POI_DC5 31 PA30 PWML2 NPCS2 MCDA0 WKUP11 / POI_DC6 MCI data bit 0 32 PA31 NPCS1 PCK2 MCDA1 POI_DC7 MCI data bit 1 Comment MCI clock Table 4-2. PIO Port B Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B Peripheral C 1 PB0 PWMH0 AD4 Microphone input 2 PB1 PWMH1 AD5 Analog input 3 PB2 URXD1 NPCS2 AD6 / WKUP12 ZigBee chip select 4 PB3 UTXD1 PCK2 AD7 User push-button 1 5 PB4 TWD1 PWMH2 6 PB5 TWCK1 PWML0 7 Extra Function System Function TDI Comment JTAG data in TDO/ TRACESWO JTAG data out PB6 TMS/SWDIO JTAG test mode select 8 PB7 TCK/SWCLK JTAG clock 9 PB8 XOUT CLK12MHz 10 PB9 XIN CLK12MHz 11 PB10 DDM USB DM 12 PB11 DDP USB DP 13 PB12 PWML1 14 PB13 PWML2 PCK0 DAC0 Audio Output R 15 PB14 NPCS1 PWMH3 DAC1 Audio Output L WKUP13 ERASE Flash erase selector Table 4-3. PIO Port C Pin Assignments and Signal Descriptions No I/O Line Peripheral A Peripheral B 1 PC0 D0 PWML0 EBI D0 2 PC1 D1 PWML1 EBI D1 3 PC2 D2 PWML2 EBI D2 4 PC3 D3 PWML3 EBI D3 5 PC4 D4 NPCS1 EBI D4 6 PC5 D5 EBI D5 7 PC6 D6 EBI D6 8 PC7 D7 EBI D7 9 PC8 NWR0/NWE 10 PC9 NANDOE NAND Flash output enable 11 PC10 NANDWE NAND Flash write enable 12 PC11 NRD SAM4S-EK2 User Guide Peripheral C Extra Function System Function Comments TFT LCD write enable TFT LCD read enable 4-17 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-3. PIO Port C Pin Assignments and Signal Descriptions (Continued) Peripheral B Peripheral C Extra Function System Function No I/O Line Peripheral A 13 PC12 NCS3 14 PC13 NWAIT 15 PC14 NCS0 16 PC15 NCS1 17 PC16 A21/NANDALE NAND Flash ALE 18 PC17 A22/NANDCLE NAND Flash CLE 19 PC18 A0/NBS0 PWMH0 20 PC19 A1 PWMH1 TFT LCD RegSel 21 PC20 A2 PWMH2 Red LED (Power) 22 PC21 A3 PWMH3 USB Vbus detection 23 PC22 A4 PWML3 QTouch valid button SNS 24 PC23 A5 TIOA3 QTouch valid button SNSK 25 PC24 A6 TIOB3 QTouch up button SNS 26 PC25 A7 TCLK3 QTouch up button SNSK 27 PC26 A8 TIOA4 QTouch down button SNS 28 PC27 A9 TIOB4 QTouch down button SNSK 29 PC28 A10 TCLK4 AD13 QTouch left button SNS 30 PC29 A11 TIOA5 AD14 QTouch left button SNSK 31 PC30 A12 TIOB5 QTouch right button SNS 32 PC31 A13 TCLK5 QTouch right button SNSK SAM4S-EK2 User Guide PWML0 Comments AD12 User push-button 2 AD10 LCD backlight control NAND Flash chip select PWML1 AD11 TFT LCD chip select RDYBSY NAND Flash RDY/BSY 4-18 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.4.2 Jumpers The SAM4S-EK2 board jumpers are essentially used for two main purposes: functional selection or current measurement. Details are given below. Table 4-4. Jumpers Setting Designation Label Default Setting JP1 JTAG OPEN JP2 ADVREF 1-2 Analog reference voltage selection between 3.3V (close 1-2) and 2.5V (close 2-3) JP3 ERASE OPEN Close to reinitialize the Flash contents and some of its NVM bits. JP4 TEST Not populated (OPEN) JP5 VDDPLL CLOSE Access for current measurement on VDDPLL JP6 VDDIO CLOSE Access for current measurement on VDDIO JP7 VDDIN CLOSE Access for current measurement on VDDIN JP8 VDDCORE CLOSE Access for current measurement on VDDCORE JP9 CE FLASH CLOSE NCS0 enable NAND Flash chip select JP10 RS485 OPEN Maintain differential impedance for RS485 interface JP11 RS485 CLOSE Maintain impedance matching for RS485 interface JP12 RS485 OPEN Maintain differential impedance for RS485 interface JP13 CS CLOSE NCS1 chip select LCD JP14 - JP15 MIC GAIN0 CLOSE (both) 20db OPEN (both) 26db JP16 ADC input OPEN JP17 – JP19 MIC Gain stage JP18 SELECT ADC INP 1-2 2-3 JP20 MONO/STEREO CLOSE Close to fix in mono speaker, no matter the stereo plug state JP21 DAC output OPEN Close for impedance matching on DAC BNC port JP22 PIO expansion J12 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP23 PIO expansion J13 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP24 PIO expansion J14 voltage supply 2-3 Set to 3.3V (position 1-2 sets to 5V) JP25 BP2 CLOSE Open to disconnect and free PB3 for custom usage JP26 BP3 CLOSE Open to disconnect and free PC12 for custom usage JP27 ZIGBEE CLOSE Power supply connection/disconnection for the ZigBEE module May also be used as a current measurement point SAM4S-EK2 User Guide Feature Close to select the JTAG boundary scan of the SAM4SD32 Close for manufacturing test or fast programming mode Close both to lower gain stage on microphone input. Close for impedance matching on ADC BNC port Close to mux RIN/LIN into MONO-IN path within audio PA ADC input potentiometer ADC input BNC 4-19 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-5. Audio Input Configuration 4.4.3 JP17 JP19 MONO-STEREO INPUT OFF OFF PIN test point (TP12) OFF ON Left-in only ON OFF Right-in only ON ON Sum of Left-in and Right-in Test Points Some test points have been placed on the SAM4S-EK2 board for the verification of important signals. Table 4-6. Test Points 4.4.4 Reference Function TP1, TP2, TP3, TP4 GND TP5 TP6 UART TXD UART RXD TP7 TP8, TP9 LCD Backlight driver anode Aux ADC input for TSC TP12 Optional Audio PA input Assigned PIO Lines, Disconnection Possibility As pointed out in some previous interface description, 0 Ohm resistors have been inserted on the path of the receiver PIO lines of the SAM4S-EK2. These are the PIO lines connected to an external driver on the board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion connectors for example). This feature gives the user an added level of versatility for prototyping a system of his own. See the table below. Table 4-7. Disconnecting Possibility Designation Default Assignment PIO R19 0R PC18, RDY/BSY on NAND Flash R20 0R PA29 R22 DNP Optional write protection on NAND Flash R25 0R PA21_485 R26 0R PA25 R27 0R PA24 R28 0R PA22 R31 0R PA23 R33 0R PA22 R34 0R PA21_232 R35 0R PA24 R36 0R PA25 R44 0R NRST SAM4S-EK2 User Guide 4-20 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-7. Disconnecting Possibility Designation Default Assignment PIO R47 0R PA9 R48 0R R2OUT/MN5 R59 0R LCD backlight LED anode R67 0R PA17 R68 0R PC13 R69 0R PA16 R70 0R Vref TSC R118 0R PA18 ZB_RSTN R119 0R PA17 IRQ1_ZBEE R120 0R PA16 IRQ0_ZBEE R121 0R PA15 SLP_TR Table 4-8. Default Not Populated Parts Reference Function J1, R1 Y1, R3, R7 R6, R8 R9, R10 JP1, JP4 C13 J2 External clock resource input Backup 12 MHz crystal Isolation between 12 MHZ clock source and GPIO line Isolation between 32 kHz clock source and GPIO line JTAGSEL and TEST selector Coupling capacitor LQFP100 Socket R22 R24, R30 JP28 D1 R61, R63, RA2, RA3 R122, R123 SAM4S-EK2 User Guide Optional write protection on NAND Flash Differential impedance matching for RS485 cable Option for software test Optional ESD protection for LCD touch panel Optional databus termination for LCD controller Optional TWI 4-21 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5 Connectors 4.5.1 Power Supply Connector J9 The SAM4S-EK2 evaluation board can be powered from a 5V DC power supply connected to the external power supply jack J9. The positive pole is the center pin. Figure 4-25. Power Supply Connector J9 Table 4-9. Power Supply Connector J9 Signal Descriptions 4.5.2 Pin Mnemonic Signal Description 1 Center +5 VCC 2 Gnd Ground reference USART Connector J5 With RTS/CTS Handshake Support Figure 4-26. Male RS232/USART Connector J5 Table 4-10. Serial COM1 Connector J5 Signal Descriptions Pin Mnemonic Signal Description 1, 4, 6, 9 NC NO CONNECTION 2 TXD TRANSMITTED DATA RS232 serial data output signal 3 RXD RECEIVED DATA RS232 serial data input signal 5 GND GROUND 7 RTS READY TO SEND Active-positive RS232 input signal 8 CTS CLEAR TO SEND Active-positive RS232 output signal SAM4S-EK2 User Guide 4-22 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.3 UART Connector J7 Figure 4-27. Male RS232/UART connector J7 Table 4-11. Male RS232/UART Connector J7 Signal Descriptions 4.5.4 Pin Mnemonic Signal Description 1, 4, 6, 7, 8, 9 NC NO CONNECTION 2 TXD TRANSMITTED DATA RS232 serial data output signal 3 RXD RECEIVED DATA RS232 serial data input signal 5 GND GROUND USB Device Connector J15 Figure 4-28. Micro-B USB Connector J15 Table 4-12. Micro-B USB Connector J15 Signal Descriptions 4.5.5 Pin Mnemonic Signal Description 1 Vbus 5V power 2 DM Data - 3 DP Data + 4 Gnd Ground 5 Shield Shield TFT LCD Connector J8 One 39-pin connector is available on the board to connect the LCD module, backlight and touch screen. Figure 4-29. LCD Connector J8 SAM4S-EK2 User Guide 4-23 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-13. LCD Connector J8 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic Pin Mnemonic 1 3.3V 2 LCD_DB17 (PC7) 3 LCD_DB16 (PC6) 4 LCD_DB15 (PC5) 5 LCD_DB14 (PC4) 6 LCD_DB13 (PC3) 7 LCD_DB12 (PC2) 8 LCD_DB11 (PC1) 9 LCD_DB10 (PC0) 10 LCD_DB09 (NC) 11 LCD_DB08 (NC) 12 LCD_DB07 13 LCD_DB06 (NC) 14 LCD_DB05 (NC) 15 LCD_DB04 (NC) 16 LCD_DB03 (NC) 17 LCD_DB02 (NC) 18 LCD_DB01 (NC) 19 LCD_DB00 (NC) 20 3.3V 21 RD (PC11) 22 WR (PC8) 23 RS (PC19) 24 CS (PC15) 25 RESET 26 IM0 27 IM1 28 GND 29 LED-A 30 LED-K1 31 LED-K2 32 LED-K3 33 LED-K4 34 Y UP 35 Y DOWN 36 X RIGHT 37 X LEFT 38 NC 39 GND 4-24 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.6 JTAG Debugging Connector J6 This JTAG connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable. Its signal assignment is compatible with the SAM-ICE or any similar third-party interface. Figure 4-30. JTAG/ICE Connector J6 Table 4-14. JTAG/ICE Connector J6 Signal Descriptions Pin Mnemonic Description This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd on the target board and must not have a series resistor. 1 VTref. 3.3V power 2 Vsupply. 3.3V power This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system. 3 nTRST TARGET RESET — Active-low output signal that resets the target JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. 4 GND 5 TDI TEST DATA INPUT — Serial data output line, sampled on the rising edge of the TCK signal 6 GND 7 TMS TEST MODE SELECT 8 GND 9 TCK TEST CLOCK — Output timing signal, for synchronizing test logic and control register access 10 GND 11 RTCK Input Return test clock signal from the target 12 GND 13 TDO JTAG TEST DATA OUTPUT — Serial data output from the target 14 GND SAM4S-EK2 User Guide Common ground. JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. Common ground. JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target’s JTAG state machine, sampled on the rising edge of the TCK signal. Common ground. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. Common ground. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. Common ground. JTAG data output from target CPU. Typically connected to TDO on target CPU. Common ground. 4-25 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware Table 4-14. JTAG/ICE Connector J6 Signal Descriptions (Continued) Pin Mnemonic 15 nSRST RESET — 16 GND Common ground. 17 RFU This pin is not connected in SAM-ICE. 18 GND Common ground. 19 RFU This pin is not connected in SAM-ICE. 20 GND Common ground. 4.5.7 Description Active-low reset signal. Target CPU reset signal. SD/MMC - MCI Connector J3 Figure 4-31. SD/MMC Connector J3 Table 4-15. SD/MMC Connector J3 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic Pin Mnemonic 1 RSV/DAT3 2 CDA 3 GND 4 VCC 5 CLK 6 GND 7 DAT0 8 DAT1 9 DAT2 10 Card Detect 11 GND 12 4-26 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.8 Analog Connector CN1 & CN2 Figure 4-32. Analog Input Connector CN1 and Analog Output CN2, Bottom View Table 4-16. Analog Input, Output Connector CN1, CN2 Signal Descriptions 4.5.9 Pin Mnemonic 1, 2, 3, 4 GND 5 Analog input PB1 for CN1 and analog output PB13 for CN2 respectively RS485 Connector J14 Figure 4-33. RS485 Connector J14 Table 4-17. RS485 J14 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic 1 A - non-inverted RS485 signal A 2 Frame ground 3 B - non-inverted RS485 signal B 4-27 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.10 Headphone Connector J11 Figure 4-34. Headphone J11 Table 4-18. Headphone J11 Signal Descriptions Pin Mnemonic 1 AGND 2 Out left 3 4 5 4.5.11 Out Right ZigBEE Connector J16 Figure 4-35. ZigBee Connector J16 Table 4-19. Connector J16 Signal Descriptions Function Signal Name Port Pin Pin Port Signal Name Function EEPROM for MAC address, CAP array settings and serial number TST: test mode activation CLKM: RF chip clock output Reset /RST 1 2 Misc. Interrupt Request IRQ 3 4 SLP_TR SLP_TR SPI chip select /SEL 5 6 MOSI SPI MOSI SPI MISO MISO 7 8 SCLK SPI CLK Power Supply GND 9 10 VCC VCC SAM4S-EK2 User Guide GND VCC Option on Misc. Port Set by Zero Ohm Resistor or Solder Shunts Voltage range: 1.8V to 5.5V, typically regulated to 3.3V 4-28 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.12 PIO Expansion Port C Connector J12 Figure 4-36. PIO Expansion Connector J12 Table 4-20. Connector J12 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic Pin Mnemonic 1 +5V or +3.3V 2 +5V or +3.3V 3 GND 4 GND 5 PC0 6 PC16 7 PC1 8 PC17 9 PC2 10 PC18 11 PC3 12 PC19 13 PC4 14 PC20 15 PC5 16 PC21 17 PC6 18 NC 19 PC7 20 NC 21 PC8 22 NC 23 PC9 24 NC 25 PC10 26 NC 27 PC11 28 NC 29 PC12 30 NC 31 PC13 32 NC 33 PC14 34 NC 35 PC15 36 NC 37 GND 38 GND 39 3.3V 40 3.3V 4-29 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.13 PIO Expansion Port A Connector J13 Figure 4-37. PIO Expansion Connector J13 Table 4-21. Connector J13 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic Pin Mnemonic 1 +5V or +3.3V 2 +5V or +3.3V 3 GND 4 GND 5 NC 6 PA16 7 NC 8 PA17 9 NC 10 PA18 11 NC 12 PA19 13 NC 14 PA20 15 NC 16 PA21 17 PA6 18 PA22 19 PA7 20 PA23 21 PA8 22 PA24 23 PA9 24 PA25 25 PA10 26 PA26 27 PA11 28 PA27 29 PA12 30 PA28 31 PA13 32 PA29 33 PA14 34 PA30 35 PA15 36 PA31 37 GND 38 GND 39 3.3V 40 3.3V 4-30 11176A–ATARM–24-Sep-12 Evaluation Kit Hardware 4.5.14 PIO Expansion Port B Connector J14 Figure 4-38. PIO Expansion Connector J14 Table 4-22. Connector J14 Signal Descriptions SAM4S-EK2 User Guide Pin Mnemonic Pin Mnemonic 1 +5V or +3.3V 2 +5V or +3.3V 3 GND 4 GND 5 PB0 6 PB8 7 PB1 8 PB9 9 PB2 10 PB10 11 PB3 12 PB11 13 PB4 14 PB12 15 PB5 16 PB13 17 PB6 18 PB14 19 PB7 20 NC 21 GND 22 GND 23 3.3V 24 3.3V 4-31 11176A–ATARM–24-Sep-12 Section 5 Schematics 5.1 Schematics This section contains the following schematics: Block Diagram Board Configuration Microcontroller NAND Flash & Serial IF TFT-LCD & QTouch Audio & Power Supply USB IF & ZigBee SAM4S-EK2 User Guide 5-1 11176A–ATARM–24-Sep-12 5 4 3 2 1 D D 5 V Input PHONE JACK AUDIO Out (DAC) UART0 ATMEL Cortex-M4 ARM Processor SAM4SD32 (LQFP100) USART1 ADC/ DAC USART1 PIO A, B, C Sheet 6 ICE QTOUCH RS232 HSMCI PIO A, B, C Micro SD NAND FLASH AUDIO In (ADC) POT C POWER C HE 10 RS485 MIC POWER SUPPLY (3.3V) Sheet 4 TOUCH SCREEN Sheet 5 ZIGBEE INTERFACE LEDs, Buttons Board Configuration Sheet B PIO A, B, C Extension Sheet 2 Sheet 3 HE 14 B FS DEVICE USB 2.8" 240x320 TFT HE 10 LCD INTERFACE Sheet 7 A A A REV SAM4S-EK2 INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 Block Diagram This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 VER. DATE REV. SHEET A 1 7 5 4 3 2 1 JUMPER and SOLDERDROP REVISION HISTORY D REV DATA A 2012.04 SCHEMATICS CONVENTIONS NOTE ORIGINAL RELEASED PAGE 3 (1) Resistance Unit: "K" is "Kohm", "R" is "Ohm¸" (2) "DNP" means the component is not populated by default TEST POINT 5 PAGE C 1 2 3 4 5 6 7 PAGE DESCRIPTION Block Diagram Reference guide Microcontroller NAND Flash, RS232, RS485, MCI, JTAG LCD, Touch items Audio, AD/DA, Power IO Expansion, USB, ZigBEE, LED, Button 3 REFERENCE FUNCTION TP1, TP2, TP3, TP4 4 5 6 DEFAULT FUNCTION JP1 OPEN Close to select JTAG boundary scan JP2 1-2 Analog reference voltage selection between 3.3V and 3.0V JP3 OPEN Close to reinitialize the Flash contents and some of its NVM bits JP4 OPEN Close for manufacturing test or fast programming mode D 4 TABLE OF CONTENTS REFERENCE 6 GND JP5, JP6, JP7, JP8 CLOSE Access for current measurement on each power rail JP9 CLOSE Nand Flash chip select enable JP11 CLOSE RS485 bus termination enable JP10, JP12 RS485 pull resistor selectors JP28 OPEN OPEN JP31 1-2 JP13 CLOSE LCD chip select enable JP32 CLOSE TOUCH SCREEN chip select enable JP14, JP15 OPEN Sync close to degrade gain stage on microphone input JP17, JP19 OPEN Close to mux RIN/LIN into MONO-IN path within audio PA JP16, JP21 OPEN Close for impedance matching on AD/DA BNC port JP18 1-2 ADC input selection between BNC port and potentiometer Option for software test RS232 USART and RS485 selection TP5 UART TXD TP6 UART RXD TP7 LCD backlight driver anode JP20 OPEN Close to fix in mono speaker mode, no matter stereo plug state TP8, TP9 Aux ADC input for TSC JP29 2-3 AUDIO Amplifier power select between VCC33 and +5V JP30 1-2 DAC output between AUDIO left channel and BNC connector TP12 Optional audio PA input 7 C JP22, JP23, JP24 1-2 DC voltage selection between 3.3V and 5V on PIO expansion ports JP25 CLOSE Button BP2 disable JP26 CLOSE Button BP3 disable JP27 CLOSE Power consumption measure for ZigBEE module PIO MUXING PIOA B PIOA USAGE USAGE PIOB USAGE PIOC USAGE PIOC USAGE DEFAULT NO POPULATE PARTS PA0 TSLIDR_SL_SNS PA16 TSC_IRQ/ZB_IRQ0 PB0 MIC INPUT PC0 D0 PC16 NAND_ALE PA1 TSLIDR_SL_SNSK PA17 TSC_BUSY/ZB_IRQ1 PB1 ANA INPUT PC1 D1 PC17 NAND_CLE PA2 TSLIDR_SM_SNS PA18 ZB_RSTN PB2 ZB_NPCS2 PC2 D2 PC18 NAND_RDYBSY PA3 TSLIDR_SM_SNSK PA19 LED_BLUE PB3 USER_PB1 PC3 D3 PC19 REGSEL_LCD PA4 TSLIDR_SR_SNS PA20 LED_GREEN PB4 JTAG PC4 D4 PC20 LED_RED(POWER) PA5 TSLIDR_SR_SNSK PA21 RXD1 PB5 JTAG PC5 D5 PC21 USB_CNX PA6 MCI_CD PA22 TXD1 PB6 JTAG PC6 D6 PC22 TVALID_SNS PA7 CLK_32K PA23 COM1EN PB7 JTAG PC7 D7 PC23 TVALID_SNSK PA8 CLK_32K PA24 RTS1 PB8 CLK_12M PC8 WR_LCD PC24 TUP_SNS PA9 RX_UART0 PA25 CTS1 PB9 CLK_12M PC9 NAND_OE PC25 TUP_SNSK PA10 TX_UART0 PA26 MCI PB10 USB_DDM PC10 NAND_WE PC26 TDWN_SNS R24, R30 Differential impedance matching for RS485 cable PA11 TSC_CS PA27 MCI PB11 USB_DDP PC11 RD_LCD PC27 TDWN_SNSK JP28 Option for software test PA12 MISO PA28 MCI PB12 ERASE PC12 USER_PB2 PC28 TLEFT_SNS PA13 MOSI PA29 MCI PB13 AUDIO OUT R PC13 EN_LCD PC29 TLEFT_SNSK D1 Optional ESD protection for LCD touch panel PA14 SPCK PA30 MCI PB14 AUDIO OUT L PC14 NAND_NCS0 PC30 TRIGHT_SNS R61, R63, RA2, RA3 Optional databus termination for LCD controller PA15 ZB_SLPTR PA31 MCI PC15 NSC1_LCD PC31 TRIGHT_SNSK R122, R123 Optional TWI PAGE 3 4 5 7 REFERENCE FUNCTION J1, R1 External clock resource input Y1, R3, R7 Backup 12MHz crystal R6, R8 Isolation between 12MHz clock source and GPIO line B R9, R10 Isolation between 32KHz clock source and GPIO line JP1, JP4 JTAGSEL and TEST selector C13 Coupling capacitor J2 LQFP100 Socket R22 Optional write protection on NAND flash A A A REV SAM4S-EK2 INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 Board Configuration This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 VER. DATE REV. SHEET A 2 7 5 4 3 2 1 PC[0..31] PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 J1 SMA nm 1 3 5 DNP R1 0R nm PA[0..31] DNP PB8_XOUT 1 XIN32 PB2 PB3 R12 0R C4 20pF PB10 PB11 7 PB3 9 PB10 88 PB11 89 PB2_URXD1_NPCS2_AD12B6 PB3_UTXD1_PCK2_AD12B7 ATSAM4SD32-LQFP100 PB10_DDM PB11_DDP JP1 Header2 nm C +3V3 DNP PB4 PB6 PB7 PB5 NRST PB0 PB1 JTAGSEL 77 PB4 PB6 PB7 PB5 51 79 83 76 NRST 60 PB0 PB1 3 5 PB12 87 JTAGSEL PB4_TWD1_PWMH2_TDI PB6_TMS_SWDIO PB7_TCK_SWCLK PB5_TWCK1_PWML0_TDO NRST ADVREF PB0_PWMH0_AD12B4 PB1_PWMH1_AD12B5 PB13_PWML2_PCK0_DACO0 VDDIO VDDCORE PA16 PC7 PA15 PA14 PC6 PA13 PA24 PC5 PC4 PA25 PA26 PC3 PA12 PA11 PC2 PA10 PA9 PC1 XOUT32 XIN32 VDDIO 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LQFP100 XIN XOUT PB13 99 PB14 C VCC33 +5V PB13 C5 100nF JP2 R13 2.2K MN2 PB14 VDDIO GND GND 27 95 GND 70 45 GND LM4040AIM3X-3.0 26 VDDPLL VDDCORE VDDCORE 85 VDDCORE 56 VDDCORE 36 93 DNP 2 GNDANA 2 DGND R107 0R DGND DGND C15 100nF C14 100nF DNP C13 4.7uF C12 100nF C11 100nF C9 100nF C10 100nF C8 2.2uF DGND PB[0..14] PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 VDDPLL VDDIO VDDCORE DGND DGND VDDPLL DGND VDDOUT VDDIO PC25 PB13 PC24 PC23 PB11 PB10 PB12 PC22 VDDIO VDDCORE PC21 PB7 PC20 PA31 PC19 PB6 PC18 JTAGSEL PB5 VDDPLL JP5 Header2 L1 10uH-100mA C22 100nF R14 1R JP6 Header2 B +3V3 TP1 VDDIN TP2 TP3 TP4 JP7 Header2 C23 4.7uF DGND + C24 10uF A JP8 VDDCORE Header2 DNP DGND DGND C70 4.7uF PC14 PA1 PC16 PA0 PC17 PA27 PC8 PA28 NRST TEST PC9 PA29 PA30 PC10 PA3 PA2 PC11 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PB4 PA6 PA5 PC28 PA4 C7 100nF C6 100nF PB14 A VDDCORE ADVREF DNP VDDIO J2 Socket-QFP100 SOCKET_THROUGHT_HOLE NOT POPULATED 16 VDDIN B 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 VDDOUT VDDOUT TEST 10 ADVREF 61 PB12_PWML1_ERASE 11 TEST DNP Header2 nm PB14_NPCS1_PWMH3_DACO1 VDDIN JP4 PB3 PC31 PB2 PC30 PB1 PC29 PB0 PA21 PA18 PC26 PA17 VDDOUT VDDIN JP3 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PC0 PA20 PC12 PA23 PC13 PA22 PC15 PA19 PC27 VDDCORE +3V3 1 C21 4.7uF XOUT32 DGND PB2 C20 4.7uF 2 Y3 32.768KHz C19 100nF 3 XIN32 R9 XOUT32 R10 PA0 PA1 PA2 PA3 PA4 PA5 PA6 0R nm PA7 0R nm PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 1 96 74 72 67 66 55 53 52 49 48 46 44 42 41 33 31 30 28 12 14 18 24 15 20 22 34 38 39 57 59 63 64 81 3 PB8 R8 PA0_PWMH0_TIOA0_A17 PA1_PWMH1_TIOB0_A18 PA2_PWMH2_SCK0_DATRG PA3_TWD0_NPCS3 PA4_TWCK0_TCLK0 PA5_RXD0_NPCS3 PA6_TXD0_PCKO PA7_RTS0_PWMH3 PA8_CTS0_AD12BTRG PA9_URXD0_NPCS1 PA10_UTXD0_NPCS2 PA11_NPCS0_PWMH0 PA12_MISO_PWMH1 PA13_MOSI_PWMH2 PA14_SPCK_PWMH3 PA15_TF_TIOA1_PWML3 PA16_TK_TIOB1_PWML2 PA17_TD_PCK1_PWMH3_AD12B0 PA18_RD_PCK2_A14_AD12B1 PA19_RK_PWML0_A15_AD12B2 PA20_RF_PWML1_A16_AD12B3 PA21_RXD1_PCK1_AD12B8 PA22_TXD1_NPCS3_NCS2_AD12B9 PA23_SCK1_PWMH0_A19 PA24_RTS1_PWMH1_A20 PA25_CTS1_PWMH2_A23 PA26_DCD1_TIOA2_MCDA2 PA27_DTR1_TIOB2_MCDA3 PA28_DSR1_TCLK1_MCCDA PA29_RI1_TCLK2_MCCK PA30_PWML2_NPCS2_MCDA0 PA31_NPCS1_PCK2_MCDA1 VDDIO 0R nm R11 0R 0R nm DNP PB9_XIN XOUT 20pF DNP C3 20pF 97 VDDIO 0R 0R nm DNP R6 98 12MHz R5 C2 XIN PB9 VDDIO R7 0R 91 2 R4 Y2 DGND DGND D 20pF C18 100nF C1 Y1 DNP VDDIO 3 69 DGND C17 100nF DGND MN1 AT91SAM4SD32-LQFP100 50 DNP 1 D 0R nm C16 100nF R3 25 47 43 40 37 35 32 29 58 62 65 68 23 21 71 19 73 75 78 80 82 84 86 90 92 94 13 17 54 4 6 8 R2 49.9R 1% PC0_D0_PWML0 PC1_D1_PWML1 PC2_D2_PWML2 PC3_D3_PWML3 PC4_D4_NPCS1 PC5_D5 PC6_D6 PC7_D7 PC8_NWR0_NWE PC9_NANDOE PC10_NANDWE PC11_NRD PC12_NCS3_AD12B12 PC13_NWAIT_PWML0_AD12B10 PC14_NCS0 PC15_NCS1PWML1_AD12B11 PC16_A21_NANDALE PC17_A22_NANDCLE PC18_A0_NBS0_PWMH0 PC19_A1_PWMH1 PC20_A2_PWMH2 PC21_A3_PWMH3 PC22_A4_PWML3 PC23_A5_TIOA3 PC24_A6_TIOB3 PC25_A7_TCLK3 PC26_A8_TIOA4 PC27_A9_TIOB4 PC28_A10_TCLK4 PC29_A11_TIOA5_AD12B13 PC30_A12_TIOB5_AD12B14 PC31_A13_TCLK5_AD12B15 2 4 A DGND REV DGND SAM4S-EK2 VDDIO INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 Microcontroller This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 VER. DATE REV. SHEET A 3 7 5 4 +3V3 PC[0..31] D MN3 MT29F2G08ABAEA 16 17 8 18 CLE ALE RE WE JP9 Header2 9 PC14 PC18 R19 R21 R/B WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 +3V3 47K R22 0R DNP DGND I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CE 7 19 0R +3V3 NAND FLASH R16 47K PC17 PC16 PC9 PC10 PA[0..31] 1 4 3 2 1 R15 47K 2 N.C28 N.C27 N.C26 N.C25 N.C24 N.C23 PRE N.C22 N.C21 N.C20 N.C19 N.C18 N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 N.C15 N.C16 N.C17 VCC VCC VSS VSS 29 30 31 32 41 42 43 44 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 R17 10K 48 47 46 45 40 39 38 35 34 33 28 27 PA26 PA27 PA28 R126 R127 0R 0R PA29 R20 0R PA30 PA31 R124 R125 0R 0R 10 9 + C25 10uF C27 100nF C28 100nF C29 1uF +3V3 +3V3 RS 485 V+ B R31 0R 5 PA22 PA21_232 PA24 PA25 R33 R34 R35 R36 R37 0R 0R 0R 0R 47K 7 10 8 11 9 12 +3V3 C2C3+ T1IN R1OUT T2IN R2OUT T3IN R3OUT 3 1 CTS1 PA25 R26 0R RTS1 PA24 R27 0R 3 TXD1 PA22 R28 T1OUT R1IN T2OUT R2IN T3OUT R3IN 4 0R R38 0R R39 100K UTXD0 URXD0 PA10 PA9 TP5 0R R48 0R TP6 JP11 Header2 2 6 V+ C1- V- C2+ GND C2- PB5 NRST 1 T1IN R1OUT T2IN R2OUT T1OUT R1IN T2OUT R2IN R40 100K R41 100K R42 100K R43 100K R44 0R J6 HE10 20PTS 1 3 5 7 9 11 13 15 17 19 VTref Vsupply nTRST GND1 TDI GND2 TMS GND3 TCK GND4 RTCK GND5 TDO GND6 nSRST GND7 DBGRQ GND8 DBGACK GND9 2 4 6 8 10 12 14 16 18 20 DGND 4 J7 1 6 2 7 3 8 4 9 5 5 14 13 7 8 DGND DGND A A REV SAM4S-EK2 FGND INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 NAND Flash & Serial IF This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 B ICE INTERFACE 3 C42 100nF 11 12 10 9 JP12 Header2 FGND C38 100nF 15 R47 R29 120R 11 A C1+ C41 100nF R46 100K 3 PB4 PB6 PB7 10 R45 100K C40 100nF DGND FGND MN6 MAX3232CSE +3V3 6 7 2 DGND +3V3 +3V3 A B J4 1 DE DI JP10 Header2 C30 100nF +3V3 UART C39 100nF +3V3 8 5 1 6 2 7 3 8 4 9 5 DGND VCC GND C R30 TBD DNP DGND 16 RE VCC J5 22 18 15 17 14 16 13 RO JP28 Header2 nm 4 24 C37 100nF C3- 1 DNP SD EN 0R 2 C35 100nF GND 19 PA23 PA21_232 R25 R24 TBD DNP MN4 ADM3485ARZ 11 TXD1 RXD1 RTS1 CTS1 23 JP31 PA21_485 20 2 V- C36 100nF R32 47K 2 PA21 C1C2+ RXD1 6 C34 100nF 21 DGND +3V3 PA21_485 C33 100nF 1 C26 100nF DGND 10 C32 100nF DGND GND CD 36 13 MN5 ADM3312EARU C31 4.7uF 11 12 13 Sh1 Sh2 Sh3 37 12 USART C1+ DAT2 DAT3 CMD VCC CLK VSS DAT0 DAT1 +3V3 R23 10K VCC D J3 TF01A PA6 C 3 RA1 68Kx4 1 2 3 4 5 6 7 8 DGND +3V3 SD CARD R18 10K 5 6 7 8 +3V3 3 3 2 1 VER. DATE REV. SHEET A 4 7 5 4 3 2 1 +3V3 PA[0..31] + C43 10uF PC[0..31] C44 100nF C45 100nF R49 47K DGND DGND DGND J8 FH26-39S-0.3SHW D PC13 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 LCD_DB17 LCD_DB16 LCD_DB15 LCD_DB14 LCD_DB13 LCD_DB12 LCD_DB11 LCD_DB10 LCD_DB9 LCD_DB8 LCD_DB7 LCD_DB6 LCD_DB5 LCD_DB4 LCD_DB3 LCD_DB2 LCD_DB1 LCD_DB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 +3V3 PC11 PC8 PC19 R56 10K PC15 JP13 Header2 NRST NRST C LED_A R59 0R LED_K1 LED_K2 LED_K3 LED_K4 Y_UP Y_DOWN X_RIGHT X_LEFT R58 4.7K DGND R63 1K C47 22nF PC24 PC31 R53 K1 QTouch Key 1K C49 22nF PC30 DGND DGND PC29 R55 1K C51 22nF PC28 PIN 39 PC23 PINs on BOT R57 1K C52 22nF FTM280C34D C PC22 PIN 1 PC27 DGND R60 1K C53 22nF DGND PC26 QTOUCH Six slots on PCB for LCD shield LCD DGND X_RIGHT Y_UP X_LEFT Y_DOWN 4.7K DNP B D R51 S1 QTouch Slider SR The part is placed as close as possible to J8 PA1 3 LCD_DB9 4.7K DNP 8 7 RA2 6 4.7Kx4 5 DNP 8 7 RA3 6 4.7Kx4 5 DNP 4 1 2 3 4 1 2 3 4 5 R61 LCD_DB4 LCD_DB2 LCD_DB3 LCD_DB1 LCD_DB8 LCD_DB6 LCD_DB7 LCD_DB5 1 LCD_DB0 Z7 PC25 VDD DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD RD WR RS CS RESET IM0 IM1 GND LED-A LEDK1 LEDK2 LEDK3 LEDK4 Y+ YX+ XNC GND 2 1K C46 22nF D1 PACDN044Y5R TVS, SOT23-5 DNP DGND R50 SL PA0 NOT POPULATED B PA3 DGND R52 1K SM C48 22nF +3V3 PA2 SR R62 100K MN7 ADS7843E 2 3 4 5 X_RIGHT Y_UP X_LEFT Y_DOWN TP8 XP YP XM YM BUSY PENIRQ TP9 7 8 R72 100K DCLK DIN DOUT CS R73 100K IN3 IN4 VREF VCC1 VCC2 GND 16 14 12 15 PA14 PA13 PA12 13 11 +3V3 JP32 Header2 0R 10 R65 100K PA17 R69 0R PA16 +3V3 9 1 10 6 R70 MN8 AAT3155ITP-T1 +3V3 PA11 R67 PA5 PC13 R68 0R C58 100nF C59 100nF C60 100nF L2 10uH-100mA +3V3 C2+ C1EN/SET C2- 5 OUTCP IN C57 4.7uF 4 C61 4.7uF PA4 C55 1uF 9 11 FB1 BN03K314S300R 1K C50 22nF 7 C54 1uF R64 47K 0R R71 1R C1+ R54 GND D1 D2 D3 D4 6 TP7 8 LED_A 3 2 1 12 LED_K1 LED_K2 LED_K3 LED_K4 R74 0R 22nF use X7R C56 1uF DGND A A DGND AGND_TP LCD TOUCH SCREEN AGND_TP LCD BACKLIGHT DGND A REV SAM4S-EK2 INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 TFT-LCD & QTouch This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 VER. DATE REV. SHEET A 5 7 5 4 3 AUDIO IN R75 47K R76 1 C62 100pF AVDD R77 470R 2 JP14 J9 Power Jack 2.1mm 1 2 Header2 47K 1 MN9 ZEN056V130A24LS 3 MN10 BNX002-01 1 2 D AGND R84 1K 2 R85 1K C68 1uF C69 1nF 3 R88 470R R83 0R R87 47K AVDD AGND AGND AGND 4 GND MN12 MIC29152WU Micrel's 1.5A LDO, TO263-5 VCC33 +3V3 FB2 BN03K314S300R 1 R91 0R VIN VOUT SD ADJ 3 5 R93 100K C77 4.7uF C 4 5 R89 169K 1% + C75 100uF-TAN-6.3V IN2AGND D + C98 220uF-ELE-16V DGND 2 OUT2 6 + C66 22uF +5V C74 100nF R90 100K SG CG1 CG2 CG3 +5V 3 4 5 6 PB0 8 VCC JP15 Header2 AVDD + C65 22uF CV C71 22nF IN1+ 7 AGND 1 C72 1nF R86 47K AGND C73 22uF R81 100R IN1OUT1 2 MIC1 SVB6050 C64 100nF 2 R82 1K MN11 TS922 GND2 R80 1K GND1 R79 1K 1 C67 1uF 6 R78 1K 3 C63 22uF SV C76 100nF DGND R92 102K 1% IN2+ JP14 and JP15 should be set or removed together C DGND J10 AGND 1 2 AUDIO OUT CN1 BNC R94 0R +5V AGND JP17 TP12 Test Pad SQ-40TH B 0.47uF C81 C82 100nF R98 33K Header2 R99 47K C85 0.47uF R100 33K JP19 Header2 R104 47K R105 33K 5 LO/MO- 10 AGND 220uF-TAN-6.3V R95 1K R97 1K C83 JP16 Header2 C78 10nF R96 49.9R 220uF-TAN-6.3V RIN AGND 1 MONO-IN ST/MN SHUTD0WN 9 BYPASS LIN PAD AUDIO_OUTL C88 6 DGND 3 DGND 0.47uF RO/MO+ R101 100K 2 R103 100K 4 C86 0.47uF R102 JP20 Header2 AD5 VCC33 Potentiometer Clockwise 2-->3 VR1 10K VR C87 1uF 2 JP18 PB1 2 B 8 C89 10nF 1 GND 7 VDD_AMP 100K 3 3 C84 PB13 + C80 10uF C79 1uF VDD + 3 VCC33 J11 5 Phonejack Stereo 3.5 4 3 2 1 VDD_AMP 2 + 1 JP29 MN13 TPA0223DGQ FB3 BN03K314S300R 1 AGND 11 AGND AGND ADC AGND DGND AGND CN3 BNC 3 R106 0R JP21 Header2 +5V VCC33 C90 DAC1 2.2uF 2 JP30 R109 49.9R PB14 1 MN14 MIC5219-3.3YMM 2 3 IN OUT AUDIO_OUTL 1 C91 4.7uF 4 DGND A EN BYP GND GND GND GND + C92 100uF-TAN-6.3V 5 6 7 8 DAC DGND C93 470pF DGND A DGND DGND A REV SAM4S-EK2 INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 DATE REV. SHEET A Audio & Power supply 5 VER. 1 6 7 5 4 3 2 1 PB[0..14] PA[0..31] D D PC[0..31] +3V3 3 JP23 +5V J12 C +3V3 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PC16 PC17 PC18 PC19 PC20 PC21 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 +3V3 +3V3 DGND J14 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 1 3 5 7 9 11 13 15 17 19 21 23 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 +3V3 DGND 2 4 6 8 10 12 14 16 18 20 22 24 PIO B PB8 PB9 PB10 PB11 PB12 PB13 PB14 TWD1 PB4 TWCK1 PB5 R122 4.7K DNP R123 4.7K DNP +3V3 DGND C +3V3 PIO A DGND +3V3 +3V3 3 DGND USB Micro B ID G 11 7 6 +3V3 R111 220R PA19 5 D+ 4 D- 3 RV2 V5.5MLA0603 1 FGND 5V 2 J15 TBD 10 8 9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PIO C DGND JP24 +5V J13 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 +3V3 3 2 1 2 1 2 JP22 +5V D2 3 4 BP2 R113 220R PA20 BP1 1 2 LED Blue D3 1 2 LED Green 3 4 NRST JP25 Header2 PB3 RV1 V5.5MLA0603 B BP3 PC21 R110 R112 47K 68K PC20 R115 1 2 100K 1 C94 10pF DGND Q1 IRLML2502 FGND 2 R117 220R 3 D4 LED Red 3 4 JP26 Header2 B PC12 BUTTONS DGND DGND DGND PB10 R114 27R PB11 R116 27R LEDS +3V3 +5V USB DGND ZB_RSTN IRQ1_ZBEE SPIO_NPCS2# MISO A PA18 R118 PA17 R119 PB2 PA12 0R 0R 1 3 5 7 9 J16 HE10 5x2 2 4 6 8 10 R120 R121 0R 0R C95 18pF Note: Pin1 is not on the indentation side Pin1 ZIGBEE IRQ0_ZBEE SLP_TR MOSI SPCK PA16 PA15 PA13 PA14 C96 2.2nF JP27 Header2 PROTOTYPE AREA Pitch = 2.54MM +3V3 A C97 2.2uF DGND A REV HE10 SAM4S-EK2 INIT EDIT MODIF. SCALE PP DES. 30-APR-12 XXX XX-XXX-XX DATE 1/1 4 3 2 DATE REV. SHEET A User IF & ZigBee This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 VER. 1 7 7 Section 6 Troubleshooting 6.1 Self-Test A software test package is available to implement a functional test for each section of the board. Refer to the SAM4S-EK2 page on www.atmel.com. 6.2 Board Recovery Closing JP3 and powering the board will assert ERASE and clear GPNVM bit 1, and thereby select the boot from the ROM by default. The MCU will boot from the internal ROM to enable a SAM-BA connection through the UART. Connect the SAM4S-EK2 UART port (J3) to a PC COM port through a RS232 crossover cable. You can then run the SAM-BA application from that PC to program the internal Flash of the MCU as well as the GPNVM bit 1. SAM4S-EK2 User Guide 6-1 11176A–ATARM–24-Sep-12 Section 7 Revision History 7.1 Revision History Table 7-1. Document Comments 11176A Initial version. SAM4S-EK2 User Guide Change Request Ref. 7-1 11176A–ATARM–24-Sep-12 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel technical support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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ARM®, ARM®Powered logo, Cortex®, Thumb®-2 and others are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 11176A–ATARM–24-Sep-12