STK501 ............................................................................. User Guide Table of Contents Table of Contents Section 1 Introduction ........................................................................................... 1-1 1.1 Features ....................................................................................................1-2 Section 2 Using the STK501 Top Module............................................................. 2-1 2.1 Connecting the STK501 to the STK500 Starter Kit ...................................2-1 2.1.1 2.2 Placing an ATmega103(L) or ATmega128(L) on the STK500............2-1 PORT Connectors.....................................................................................2-2 2.2.1 PORT E/PORT F ................................................................................2-2 2.2.2 PORT G/AUX .....................................................................................2-3 2.2.2.1 PG0 - PG4 ...................................................................................2-3 2.2.2.2 A16...............................................................................................2-3 2.2.2.3 SRAMEN......................................................................................2-3 2.2.2.4 PEN..............................................................................................2-3 2.3 Programming the ATmega103(L)/ 128(L) .................................................2-3 2.3.1 In-System Programming.....................................................................2-3 2.3.2 High-voltage Programming.................................................................2-4 2.4 2.5 JTAG Connector .......................................................................................2-5 External SRAM .........................................................................................2-6 2.5.1 A16 .....................................................................................................2-7 2.5.2 SRAMEN ............................................................................................2-7 2.6 2.7 2.8 2.9 2.10 Ram High Address Jumpers .....................................................................2-8 A[7:0] Connector .......................................................................................2-8 Using the SRAM Interface with AT90S/LS8515 and ATmega161 ............2-8 TOSC Switch ............................................................................................2-9 RS-232C Port............................................................................................2-9 Section 3 Troubleshooting Guide ......................................................................... 3-1 Section 4 Technical Specifications ....................................................................... 4-1 Section 5 Technical Support................................................................................. 5-1 i Table of Contents Section 6 Complete Schematics........................................................................... 6-1 ii Section 1 Introduction The STK501 board is a top module designed to add ATmega103(L) and ATmega128(L) support to the STK500 development board from Atmel Corporation. With this board the STK500 is extended to support all current AVR devices in a single development environment. The STK501 includes connectors, jumpers and hardware allowing full utilization of the new features of the ATmega128(L) while the Zero Insertion Force (ZIF) socket allows easy use of TQFP packages for prototyping. This user guide acts as a general getting started guide as well as a complete technical reference for advanced users. In addition to adding support for new devices, it also adds new support for peripherals previously not supported by the STK500. An additional RS-232 port and external SRAM interface are09/01 among the new features. Devices with dual UART or XRAM interface can all take advantage of the new resources on the STK501 board. Figure 1-1. STK501 Top Module for STK500 AVR® STK501 User Guide 1-1 Rev. 2491A-09/01 Introduction 1.1 Features STK500 Compatible AVR Studio® Compatible Supports ATmega103(L) and ATmega128(L) Zero Insertion Force Socket for TQFP Packages TQFP Footprint for Emulator Adapters Supports all Added Features in ATmega128(L) JTAG Connector for On-chip Debugging Using JTAG ICE (ATmega128(L)) Additional RS-232C Port with Available RTS/CTS Handshake Lines Adds External SRAM Support to the STK500 Board (Usable for all Devices with XRAM Interface) On-board 32 kHz Crystal for Easy RTC Implementations 1-2 AVR® STK501 User Guide Section 2 Using the STK501 Top Module 2.1 Connecting the STK501 to the STK500 Starter Kit The STK501 should be connected to the STK500 expansion header 0 and 1. It is important that the top module is connected in the correct orientation as shown in Figure 2-1. The EXPAND0 written on the STK501 top module should match the EXPAND0 written beside the expansion header on the STK500 board. Figure 2-1. Connecting STK501 to the STK500 Board Note: 2.1.1 Placing an ATmega103(L) or ATmega128(L) on the STK500 Connecting the STK501 with wrong orientation may damage the board. The STK501 contains both a ZIF socket, and the pinout for a TQFP package; which allows an easy way of soldering an emulator adapter directly into the STK501. Care should be taken so that the device (or adapter) is mounted with the correct orientation. Figure 2-2 shows the location of pin 1 for the ZIF socket and the TQFP footprint. Caution: Do not mount an ATmega103(L) or ATmega128(L) on the STK501 at the same time as an AVR is mounted on the STK500 board. AVR® STK501 User Guide 2-1 Rev. 2491A-09/01 Using the STK501 Top Module Figure 2-2. Pin1 on ZIF Socket and TQFP Footprint 2.2 PORT Connectors Since the ATmega103(L) and ATmega128(L) have additional ports not available on the STK500, these ports are located on the STK501 board. They have the same pinout and functionality as the ports on the STK500 board. Port A to Port D which are already present on the STK500 board are not duplicated on the STK501. 2.2.1 PORT E/PORT F Figure 2-3 shows the pinout for the I/O port headers Port E and Port F. Figure 2-3. General I/O Ports 1 2 1 2 PE0 PE2 PE4 PE6 GND PE1 PE3 PE5 PE7 VTG PORT E Note: 2-2 PF0 PF2 PF4 PF6 GND PF1 PF3 PF5 PF7 VTG PORT F Port E is also present on the STK500, but only PE0 to PE2 (3 least significant bits) are accessible there. To access all Port E bits the connector on the STK501 must be used. AVR® STK501 User Guide Using the STK501 Top Module 2.2.2 PORT G/AUX In addition to the normal Port G pins, this connector has some extra signals. See Figure 2-4. Figure 2-4. PORTG/AUX 1 2 PG0 PG2 PG4 SRAMEN GND PG1 PG3 A16 PEN VTG PORT G/AUX 2.2.2.1 PG0 - PG4 These are general I/O ports for the ATmega128(L) and connect to the ZIF socket and the TQFP footprint. The PG3 and PG4 signals are routed through the TOSC switch since these pins also are inputs for a 32 kHz oscillator. For a description on the TOSC switch see Section 2.9. Note: ATmega103(L) does not have Port G. 2.2.2.2 A16 This line goes to A16 (most significant address bit) on the SRAM. See Section 2.5 for more information about this signal. can be connected to any AVR pin. 2.2.2.3 SRAMEN The SRAMEN signal controls if the SRAM is enabled or not. To enable the SRAM a LOW level should be applied to this pin. See “External SRAM”, Section 2.5, for more information on how to use this signal. This signal is pulled high by default. 2.2.2.4 PEN The PEN pin is connected to the PEN pin on the ATmega103(L)/128(L). This pin is described in the programming section of the ATmega103(L) and ATmega128(L) datasheets. 2.3 Programming the The ATmega103(L) and ATmega128(L) can be programmed using both SPI and Highvoltage Parallel Programming. This sub section will explain how to connect the programATmega103(L)/ ming cables to successfully use one of these two modes. The AVR Studio STK500 128(L) software is used in the same way as for other AVR parts. Note: 2.3.1 In-System Programming The ATmega128(L) also supports Self Programming. See AVR109 application note for more information on this topic. To program the ATmega103(L) or ATmega128(L) using ISP programming mode, connect the 6-wire cable between the ISP6PIN connector on the STK500 board and the ISP connector on the STK501 board as shown in Figure 2-5. The device can be programmed using the serial programming mode in the AVR Studio STK500 software. Note: AVR® STK501 User Guide See the STK500 User Guide for information on how to use the STK500 frontend software for ISP programming. 2-3 Using the STK501 Top Module Figure 2-5. In-System Programming 2.3.2 High-voltage Programming To program the ATmega103(L) or ATmega128(L) using High-voltage (Parallel) Programming, connect the PROGCTRL to PORTD and PROGDATA to PORTB on the STK500 as shown in Figure 2-6. As described in the STK500 User Guide, the BSFL2 jumper must be mounted when High-voltage Programming ATmega devices. This also applies to the High-voltage Programming of ATmega103(L) and ATmega128(L). The device can now be programmed using the High-voltage Programming mode in AVR Studio STK500 software. Note: See the STK500 User Guide for information on how to use the STK500 frontend software in High-voltage Programming mode. Note: For the High-voltage Programming mode to function correctly, the target voltage must be higher than 4.5V. Caution: Make sure the SRAM (if mounted) can handle this voltage. 2-4 AVR® STK501 User Guide Using the STK501 Top Module Figure 2-6. High-voltage (Parallel) Programming 2.4 JTAG Connector The JTAG connector is intended for the ATmega128(L) that has a built-in JTAG interface. The pinout of the JTAG connector is shown in Figure 2-7 and is compliant with the pinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connector allows On-chip Debugging of the ATmega128(L). More information about the JTAG ICE and On-chip Debugging can be found in the AVR JTAG ICE User Guide, which is available at the Atmel web site, www.atmel.com. Figure 2-7. JTAG Connector 1 2 TCK TDO TMS VTG TDI GND VTG RST NC GND JTAG Figure 2-8 shows how to connect the JTAG ICE probe on the STK501 board. AVR® STK501 User Guide 2-5 Using the STK501 Top Module Figure 2-8. Connecting JTAG ICE to the STK501 2.5 External SRAM The STK501 contains a footprint where an external SRAM device can be mounted. Make sure the SRAM device has the same voltage range as the rest of the design. Caution: Special care should be taken if a low voltage SRAM is used, since High-voltage Programming requires a programming voltage higher than 4.5V. Low-voltage SRAM may be damaged if High-voltage Programming of the target AVR is done. Table 2-1 shows a list of recommended SRAM devices, and typical range of operation. It is important that the SRAM device is soldered with the correct orientation as shown in Figure 2-9. Note: The SRAM is disabled by default. To enable SRAM support, put a jumper between the SRAMEN and GND pin on the PORTG/AUX connector. Figure 2-9. Pin1 on SRAM Footprint and Pinout 2-6 A0 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CS 5 28 OE D0 6 27 D7 D1 7 26 D6 VCC 8 25 GND GND 9 24 VCC 128Kx8 D2 10 23 D5 D3 11 22 D4 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 AVR® STK501 User Guide Using the STK501 Top Module Table 2-1. Recommended SRAM Devices 2.5.1 A16 Manufacturer Part Number Supply Voltage (V) Package ISSI IS63LV1024-T 3.3 TSOP-II ISSI IS63LV1024-J 3.3 SOJ 300-mil ISSI IS63LV1024-K 3.3 SOJ 400-mil IDT IDT71124-Y 5.0 SOJ 400-mil IDT IDT71V124SA-TY 3.3 SOJ 300-mil IDT IDT71V124SA-Y 3.3 SOJ 400-mil IDT IDT71V124SA-PH 3.3 TSOP-II The A16 pin on the PORTG/AUX connector is connected to A16 (address pin 16) on the SRAM. ATmega103(L) and ATmega128(L) support up to 60 KB of external SRAM. The STK501 SRAM footprint is for a 128 KB SRAM. Implementing software control of the A16 line will increase the memory range from 64 KB to 128 KB. This line is pulled low by default, addressing the lower 64 KB of the SRAM. Figure 2-10. SRAM Block Schematic AVR SRAM A16 A15 A14 A13 A12 A11 A10 A9 A8 PC7 PC6 PC5 A16 From PORTG/AUX connector SRAMEN PC4 PC3 PC2 PC1 PC0 RAM HIGH ADDRESS PORTC VTG 10K x 12 CE OE WE RD (PG1) WR (PG0) ALE (PG2) PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 LE OE D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A7 A6 A5 A4 A3 A2 A1 A0 A2 A4 A1 A3 A5 A7 A6 A5 A4 A3 A2 A1 A0 A6 A7 A0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VTG LATCH A[7:0] PORTA 2.5.2 SRAMEN The SRAMEN pin on the PORTG/AUX connector is connected to the Chip-enable (CE) pin of the SRAM. This signal controls if the SRAM should be enabled or not. To enable the SRAM, a low level should be applied to this pin. This pin is pulled high by default, through a 10 kΩ resistor. Figure 2-10 shows a simplified block schematic on how the SRAM interface is implemented. Figure 2-11 shows how to enable the SRAM by shorting SRAMEN and GND on the PORTG/AUX connector using one of the supplied jumpers. This signal can also be controlled by software or by some external control logic. AVR® STK501 User Guide 2-7 Using the STK501 Top Module Figure 2-11. SRAMEN Connected to GND 2.6 Ram High Address Jumpers When External Memory is enabled in an AVR, all Port C pins are by default used for the high address byte. If the full 60 KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal port pin function as described in the ATmega128(L) datasheet. AT90S/LS8515, ATmega103(L) and ATmega161 do not have this feature, and all jumpers should be connected if using the XRAM interface with these devices. If some or all of the Port C pins are released for normal port pin functions, the corresponding “RAM High Address” jumper should be removed to avoid any Port C activity to reach the SRAM address pins thus corrupting the address. If a jumper is removed, the corresponding address line will be pulled low giving a logic zero on that address bit on the SRAM. See the block schematic on Figure 2-10. 2.7 A[7:0] Connector The connector marked A[7:0] contains the 8 least-significant bits of the external SRAM address bus. The purpose of the connector is to provide easy access to the address bus. The 8 most significant bits can be found on the “Ram High Addresses” jumpers or the Port C connector. The connector is placed after the latch as shown in Figure 2-10. This connector is handy when using the SRAM interface to interface external devices. 2.8 Using the SRAM Interface with AT90S/LS8515 and ATmega161 When using the SRAM interface with devices placed in the STK500 board, some additional straps are required. The reason is that the RD, WR, and ALE signals are not on the same port pins for the AT90S8515/ATmega161(L) and ATmega103(L)/ ATmega128(L), so these signals must be routed manually using two of the 2-wire cables. Table 2-2. Signal Routing Required for AT90S8515A and ATmega161(L) Connections 2-8 STK500 STK501 Description Write Signal WR PD6 PG0 Connect PD6:STK500 to PG0:STK501 Read Signal RD PD7 PG1 Connect PD7:STK500 to PG1:STK501 Address Latch Enable ALE PE1 PG2 Connect PE1:STK500 to PG2:STK501 AVR® STK501 User Guide Using the STK501 Top Module Figure 2-12. Enabling SRAM Interface for Devices in STK500 2.9 TOSC Switch On the ATmega128(L) the TOSC1 and TOSC2 lines are shared with Port G (PG4 and PG3). The TOSC switch select if the 32 kHz crystal, or the Port G connector pins should be connected to the pins on the device. Figure 2-13 shows a simplified block schematic on how this is implemented. Note: Port G is not available on the ATmega103(L), the switch will thus only select if the 32 kHz crystal should be connected or not. Figure 2-13. TOSC Block Schematic AVR 32 kHz PG3/TOSC2 PG3 PG4/TOSC1 PG4 To PORT G/AUX Connector TOSC Switch 2.10 RS-232C Port The ATmega128(L) has an additional UART compared to the ATmega103(L). The RS232 port on the STK501 board has in addition to the RXD and TXD lines support for RTS and CTS flow control. Figure 2-14 shows a simplified block schematic on how this is implemented. Note: AVR® STK501 User Guide The UART in ATmega128(L) does not support hardware RTS or CTS control. If such functionality is needed, it must be implemented in software. 2-9 Using the STK501 Top Module RS232 SPARE2 Figure 2-14. UART Block Schematic 4 6 2 3 7 8 5 RS-232/Logic Level Converter RxD CTS TxD RTS This UART can also be used from devices placed in the STK500 board. Simply connect the appropriate port pins to RXD and TXD on the STK501 board. Note: 2-10 If no software RTS/CTS flow control is implemented, a jumper shorting RTS and CTS will ensure correct communication with an external application that uses such flow control. AVR® STK501 User Guide Section 3 Troubleshooting Guide Table 3-1. Troubleshooting Guide Problem Reason Solution The SRAM is not connected. Verify all solderings, and make sure the Pin1 on the SRAM matches the one on the footprint. Make sure the SRAM pinout is correct. SRAMEN is not mounted. Make sure that the SRAMEN is connected to GND on the AUX connector. XRAM interface is not enabled in the AVR device. Verify that the code actually enables the XRAM interface. Some of the ADDRESS HIGH BYTE jumpers may be set incorrectly. Connect some or all of ADDRESS HIGH BYTE jumpers. SRAM does not work when used by devices on the STK500 board. WR, RD and ALE signals must be strapped using two 2-wire cables. Use two 2-wire cables, and connect these signals to the appropriate pins. After doing a High-voltage Programming of the AVR, the SRAM does not work properly. The SRAM might be damaged due to the Highvoltage needed to program the AVR. Make sure the SRAM handles 5V, if High-voltage Programming mode should be used. SRAM does not work properly. AVR® STK501 User Guide 3-1 Troubleshooting Guide 3-2 AVR® STK501 User Guide Section 4 Technical Specifications System Unit Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 x 119 x 27 mm Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 g Operating Conditions Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V - 5.5V Connections Serial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-pin D-SUB female Serial Communications Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 kbps AVR® STK501 User Guide 4-1 Technical Specifications 4-2 AVR® STK501 User Guide Section 5 Technical Support For Technical support, please contact [email protected]. When requesting technical support, please include the following information: Which target AVR device is used (complete part number) AVR® STK501 User Guide Target voltage and speed Clock source and fuse setting of the AVR Programming method (ISP or High-voltage) Hardware revisions of the AVR tools, found on the PCB Version number of AVR Studio. This can be found in the AVR Studio help menu. PC operating system and version/build PC processor type and speed A detailed description of the problem 5-1 Technical Support 5-2 AVR® STK501 User Guide Section 6 Complete Schematics On the following pages the complete schematics and assembly drawing of the STK501 revision B are shown. AVR® STK501 User Guide 6-1 A B C TOSC1 RESET TOSC1 RESET 1 PGT[4..0] TOSC2 TOSC2 PGT[4..0] PBT[7..0] PET[7..0] PBT[7..0] PET[7..0] PEN AREFT AREFT PEN PFT[7..0] PFT[7..0] VTG PBT7 PET0 PET1 PET2 PET3 PET4 PET5 PET6 PET7 PBT0 PBT1 PBT2 PBT3 PBT4 PBT5 PBT6 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PEN PE0/PDI/RXD PE1/PDO/TXD PE2/AC+ PE3/ACPE4/INT4 PE5/INT5 PE6/INT6 PE7/INT7 PB0/SS PB1/SCK PB2/MOSI PB3/MISO PB4/OC0 PB5/OC1A PB6/OC1B U101 C101 100N_16V_X7R GND C107 100N_16V_X7R GND AVTG 1 2 TQFP Footprint GND VTG ATMEGA128 2 C102 100N_16V_X7R VTG C103 100N_16V_X7R GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C104 100N_16V_X7R 3 2 BLM-21A102S 1 L101 AD3/PA3 AD4/PA4 AD5/PA5 AD6/PA6 AD7/PA7 ALE/PG2 A15/PC7 A14/PC6 A13/PC5 A12/PC4 A11/PC3 A10/PC2 A9/PC1 A8/PC0 RD/PG1 WR/PG0 3 PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 PAT3 PAT4 PAT5 PAT6 PAT7 C105 100N_16V_X7R PDT[7..0] PCT[7..0] PAT[7..0] 4 C106 100N_16V_X7R AVTG XT2 XT1 PDT[7..0] PGT1 PGT0 PCT[7..0] PGT2 PAT[7..0] 4 5 PGT[4..0] RESET TOSC1 TOSC2 PBT[7..0] PET[7..0] PGT[4..0] RESET TOSC1 TOSC2 PBT[7..0] PET[7..0] PEN AREFT AREFT PEN PFT[7..0] PFT[7..0] ZIF Socket 5 PBT7 PET0 PET1 PET2 PET3 PET4 PET5 PET6 PET7 PBT0 PBT1 PBT2 PBT3 PBT4 PBT5 PBT6 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ST101 C108 100N_16V_X7R GND AVTG 1 2 2 1 6 GND PFT0 PFT1 PFT2 PFT3 PFT4 PFT5 PFT6 PFT7 D 1 2 PFT0 PFT1 PFT2 PFT3 PFT4 PFT5 PFT6 PFT7 2 1 2 PAT0 PAT1 PAT2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC AGND AREF ADC0/PF0 ADC1/PF1 ADC2/PF2 ADC3/PF3 ADC4/PF4 ADC6/PF6 ADC6/PF6 ADC7/PF7 GND VCC AD0/PA0 AD1/PA1 AD2/PA2 PB7/OC2 PG3/TOSC2 PG4/TOSC1 RESET VCC GND XTAL2 XTAL1 PD0/INT0 PD1/INT1 PD2/INT2 PD3/INT3 PD4/IC1 PD5 PD6/T1 PD7/T2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PDT0 PDT1 PDT2 PDT3 PDT4 PDT5 PDT6 PDT7 1 2 1 2 1 2 VTG PAT0 PAT1 PAT2 TQFP64 ZIF SOCKET 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 6 VTG 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6-2 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 7 Rev. B PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 PAT3 PAT4 PAT5 PAT6 PAT7 7 Copyright Atmel Corporation 2001 A9903.3.1010.B STK501 PDT0 PDT1 PDT2 PDT3 PDT4 PDT5 PDT6 PDT7 1 19-Jun-2001 Page 1 of 3 PDT[7..0] PCT[7..0] PAT[7..0] XT2 XT1 PDT[7..0] 8 PGT1 PGT0 PCT[7..0] PGT2 PAT[7..0] 8 A B C D Complete Schematics Figure 6-1. Schematics, 1 of 3 AVR® STK501 User Guide A B C 1 2 PFT[7..0] PCT[7..0] PFT[7..0] PAT[7..0] PCT[7..0] PET[7..0] PAT[7..0] RESET PET[7..0] GND PFT0 PFT2 PFT4 PFT6 1 3 5 7 9 PFT7 PFT4 PFT6 PFT5 GND 2 4 6 8 10 PORTF J203 C201 100N_16V_X7R VTG 1 2 PFT1 PFT3 PFT5 PFT7 VTG VTG 2 1 3 5 7 9 3 JTAG J204 2 4 6 8 10 J201 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PET0 PET2 PET4 PET6 GND GND 1 3 5 7 9 VTG GND PCT6 PCT4 PCT2 PCT0 PAT6 PAT4 PAT2 PAT0 AREFT PET2 PET0 GND 2 4 6 8 10 PORTE J205 VTG EXPAND0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 RESET GND GND PCT7 PCT5 PCT3 PCT1 PAT7 PAT5 PAT3 PAT1 PET1 RESET R202 0R GND 1 3 1 2 2 PET1 PET3 PET5 PET7 VTG 4 C203 100N_16V_X7R GND 4 J206 2 VCC 4 MOSI 6 GND MISO 31 SCK RESET 5 PET0 SRAMEN PGT[4..0] GND JS201 JS202 SRAMEN PGT[4..0] 5 GND PGT0 PGT2 PGT4 ISP_CONNECTOR J208 2 4 6 8 10 NOT MOUNTED VTG PBT7 PBT5 PBT3 PBT1 PDT7 PDT5 PDT3 PDT1 XT1 GND VTG PGT1 PGT3 PBT1 Port G special features PG0: nWR PG1: nRD PG2: ALE PG3: TOSC2 PG4: TOSC1 PORTG/AUX 1 3 5 7 9 RESET GND VTG PET1 VTG GND VTG AREFT 5 1 2 2 R203 0R PEN R201 10K VTG A16 J202 6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 6 PEN A16 EXPAND1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C204 100N_16V_X7R GND GND 1 2 1 GND GND PBT6 PBT4 PBT2 PBT0 PDT6 PDT4 PDT2 PDT0 XT2 GND J207 2 4 6 8 10 GND Rev. B VTG 7 Copyright Atmel Corporation 2001 A9903.3.1010.B A1 A3 A5 A7 19-Jun-2001 Page 2 of 3 A[7..0] PBT[7..0] A[7..0] PDT[7..0] PBT[7..0] XT2 XT1 PDT[7..0] C202 100N_16V_X7R LATCHED ADDRESS 1 3 5 7 9 STK501 A0 A2 A4 A6 7 VTG 1 AVR® STK501 User Guide 2 D 1 8 8 A B C D Complete Schematics Figure 6-2. Schematics, 2 of 3 6-3 A B C 1 11 1 6 2 7 3 8 4 9 5 10 GND GND 2 PGT[4..0] PAT[7..0] PAT[7..0] KF22-E-9-S-N J301 SRAMEN SRAMEN A16 PGT[4..0] A16 PCT[7..0] C301 100N_16V_X7R PCT[7..0] GND 2 1 VTG C308 10P_50V_NP0 33R 1 R311 2 1 GND 2 U301 3 C304 100N_16V_X7R GND VTG 1 11 OE LE 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 C303 100N_16V_X7R PAT0 PAT1 PAT2 PAT3 PAT4 PAT5 PAT6 PAT7 GND VTG 20 VCC GND 2 6 8 7 13 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 V- V+ 74AHC573PW VTG A0 A1 A2 A3 A4 A5 A6 A7 R2 GND VTG 1 GND 100N_16V_X7R 2 GND C307 C2+ 4 C2- 5 9 10 12 11 MAX3232ECAE T2 R1 T1 C1+ 1 C1- 3 U303 PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 JS301 4 JP301 JS303 2 4 6 8 10 12 14 16 JS304 C306 100N_16V_X7R C305 100N_16V_X7R RAM HIGH ADDRESS 1 3 5 7 9 11 13 15 JS302 JS305 2 JS306 R301 10K GND 1 4 JS307 R302 10K RXD CTS JS308 5 J302 R304 10K 2 4 5 JS309 RS232 SPARE2 1 3 R303 10K TXD RTS R305 10K R306 10K R307 10K R308 10K R309 10K A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 TOSC1 6 PGT[4..0] TOSC1 PGT[4..0] TOSC2 TOSC2 R310 10K VTG 6 1 2 3 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 10 1 2 1 2 PGT1 PGT0 2 16 VCC GND 15 1 2 2 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 U302 VCC VCC GND GND I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 32kHz XC301 1 2 C302 100N_16V_X7R PGT4 PGT3 GND 7 Copyright Atmel Corporation 2001 Page 3 of 3 Rev. B 4 3 VTG A[7..0] 19-Jun-2001 GND 4 6 3 1 GND VTG PAT0 PAT1 PAT2 PAT3 PAT4 PAT5 PAT6 PAT7 A[7..0] STK501 5 2 TOSC SW301 VTG 8 24 9 25 6 7 10 11 22 23 26 27 7 A9903.3.1010.B 10K 2 R313 1 10K 2 R312 1 VTG 128Kx8 SRAM 5 28 CE 12 OE WE 1 2 3 4 13 14 15 16 17 18 19 20 21 29 30 31 32 7 2 6-4 1 D 1 8 8 A B C D Complete Schematics Figure 6-3. Schematics, 3 of 3 AVR® STK501 User Guide PGT2 Complete Schematics Figure 6-4. Assembly Drawing, 1 of 1 AVR® STK501 User Guide 6-5 Complete Schematics 6-6 AVR® STK501 User Guide Atmel Headquarters Atmel Product Operations Corporate Headquarters Atmel Colorado Springs Europe Atmel Grenoble 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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