View detail for SAM3X-EK

SAM3X-EK
....................................................................................................................
User Guide
11156A–ATARM–25-May-12
Section 1
Introduction .................................................................................................................1-1
1.1
SAM3X Evaluation Kit ........................................................................................................ 1-1
1.2
User Guide ......................................................................................................................... 1-1
1.3
References and Applicable Documents ............................................................................. 1-1
Section 2
Kit Contents ................................................................................................................2-1
2.1
Deliverables ....................................................................................................................... 2-1
2.2
Electrostatic Warning ......................................................................................................... 2-2
Section 3
Power Up ....................................................................................................................3-1
3.1
Power up the Board ........................................................................................................... 3-1
3.2
Battery................................................................................................................................ 3-1
3.3
DevStart ............................................................................................................................. 3-1
3.4
Recovery Procedure .......................................................................................................... 3-1
3.5
Sample Code and Technical Support ................................................................................ 3-2
Section 4
Evaluation Kit Hardware .............................................................................................4-1
4.1
Board Overview.................................................................................................................. 4-1
4.2
Features List ...................................................................................................................... 4-2
4.3
Function Blocks.................................................................................................................. 4-2
4.3.1
Processor............................................................................................................. 4-2
4.3.2
Memory ................................................................................................................ 4-2
4.3.3
Clock Circuitry...................................................................................................... 4-4
4.3.4
Reset and Wake-Up Circuitry .............................................................................. 4-4
4.3.5
Power Supply and Management.......................................................................... 4-5
4.3.6
UART ................................................................................................................... 4-6
4.3.7
USART................................................................................................................. 4-6
4.3.8
LEDs .................................................................................................................... 4-7
4.3.9
LCD, Backlight Control and Touch Panel ............................................................ 4-8
4.3.10 JTAG/ICE........................................................................................................... 4-10
4.3.11 Audio Codec ...................................................................................................... 4-10
4.3.12 USB ................................................................................................................... 4-11
4.3.13 Analog Interface................................................................................................. 4-12
4.3.14 User Buttons ...................................................................................................... 4-13
4.3.15 QTouch Elements .............................................................................................. 4-13
4.3.16 EEPROM ........................................................................................................... 4-14
4.3.17 SD Card ............................................................................................................. 4-15
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11156A–ATARM–25-May-12
4.3.18 ZigBee ............................................................................................................... 4-15
4.3.19 PIO Expansion ................................................................................................... 4-17
4.3.20 Ethernet MAC 10/100 (EMAC) .......................................................................... 4-18
4.3.21 CAN ................................................................................................................... 4-18
4.4
Configuration.................................................................................................................... 4-19
4.4.1
PIO Usage ......................................................................................................... 4-20
4.4.2
Jumpers ............................................................................................................. 4-25
4.4.3
Test Points ......................................................................................................... 4-26
4.4.4
Assigned PIO Lines, Disconnection Possibility.................................................. 4-26
Section 5
Schematics .................................................................................................................5-1
5.1
Schematics......................................................................................................................... 5-1
Section 6
Troubleshooting ..........................................................................................................6-1
6.1
Self-Test............................................................................................................................. 6-1
6.2
Board Recovery ................................................................................................................. 6-1
Section 7
Revision History..........................................................................................................7-1
7.1
Revision History ................................................................................................................. 7-1
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11156A–ATARM–25-May-12
SAM3X-EK User Guide
Section 1
Introduction
1.1
SAM3X Evaluation Kit
The SAM3X Evaluation Kit (SAM3X-EK) allows to evaluate the SAM3X series devices. It has enough
features to demonstrate most of the product’s capabilities to its users. The SAM3X-EK also features
extension connectors to allow users to add new interfaces in case they are not on-board.
1.2
User Guide
This guide gives details on how the SAM3X-EK has been designed. It is made up of 6 sections:
1.3
„
Section 1 includes references, applicable documents
„
Section 2 describes the kit contents and main features
„
Section 3 provides instructions on how to power up the SAM3X-EK and describes how to use it
„
Section 4 describes the hardware resources, including default jumper and switch settings, and the
schematics
„
Section 5 provides all the board schematics
„
Section 6 gives troubleshooting recommendations
References and Applicable Documents
Table 1-1. References and Applicable Documents
Title
Comment
SAM3X Datasheet
http://www.atmel.com/dyn/products/devices.asp?category_id=163&family_id=605&subfamily_id=2363
SAM3X-EK User Guide
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11156A–ATARM–25-May-12
Section 2
Kit Contents
2.1
Deliverables
The Atmel® SAM3X-EK toolkit contains the following items:
„
a SAM3X-EK board
„
one power supply
„
one universal input AC/DC power supply with US, Europe and UK plug adapters
„
one 3V Lithium Battery type CR1225
„
one USB cable
„
one Micro A to Type A receptacle changer
„
one serial RS232 cable
„
one Ethernet cross cable
„
A Welcome Letter
Figure 2-1.
Unpacked SAM3X-EK
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues
concerning the contents of the kit.
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11156A–ATARM–25-May-12
2.2
Electrostatic Warning
The SAM3X-EK board is shipped in a protective anti-static bag. The board must not be subjected to high
electrostatic potentials. A grounding strap or similar protective device should be worn when handling the
board. Avoid touching the components or any other metallic element of the board.
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11156A–ATARM–25-May-12
SAM3X-EK User Guide
Section 3
Power Up
3.1
Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2
Battery
The SAM3X-EK ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and
time backup function of the SAM3X series devices when the board is switched off.
3.3
DevStart
The on-board NAND Flash contains “SAM3X-EK DevStart”.
It is stored in the “SAM3X-EK DevStart” folder on the USB Flash disk available when the SAM3X-EK is
connected to a host computer and you click on the Flash Disk icon of the on-board demo.
Click the file “welcome.html” in this folder to launch SAM3X-EK DevStart.
SAM3X-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU
toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and how
to program it into the SAM3X-EK. Optionally, if you have a SAM-ICE™, instructions are also given about
how to debug the code.
We recommend that you backup the “SAM3X-EK DevStart” folder on your computer before
launching it.
3.4
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM3X-EK to the state as it
was when shipped by Atmel.
Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want
to recover from this situation.
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11156A–ATARM–25-May-12
3.5
Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical support from Atmel website: www.atmel.com
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11156A–ATARM–25-May-12
SAM3X-EK User Guide
Section 4
Evaluation Kit Hardware
4.1
Board Overview
This section introduces the Atmel SAM3X Evaluation Kit design. It introduces system-level concepts,
such as power distribution, memory, and interface assignments.
The SAM3X-EK board is based on the integration of an ARM® Cortex®-M3 processor with on-board
SDRAM, NAND-Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications.
Figure 4-1.
SAM3X-EK Block Diagram
SAM3X-EK User Guide
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11156A–ATARM–25-May-12
4.2
Features List
Here is the list of the main board components and interfaces:
„
SAM3X8H LFBGA chip with optional socket footprint
„
12 MHz crystal
„
32.768 KHz crystal
„
SDRAM
„
NAND-Flash
„
Backup Battery
„
2.8 inch TFT color LCD display with touch-panel and backlight
„
UART port with level shifter IC
„
USART port with level shifter IC
„
Audio codec with input and output jacks: stereo headphone out and mono microphone in
„
SD/MMC interface
„
QTouch elements: Up, Down, Left, Right, Valid and Slider
„
Reset and Wake-Up buttons: NRST, NRSTB, FWUP
„
User buttons: Left and Right
„
High Speed USB Host/Device port
„
JTAG/ICE port
„
On-board power regulation with shutdown control (by the SAM3 chip)
„
Three user LEDs
„
Power LED
„
User potentiometer connected to the ADC input
„
IEEE 802.15.4 / ZigBee® connector
„
Two serial CAN 2.0B communication port via two RJ12 connectors
„
One Ethernet Physical Transceiver Layer with RJ45 connector
„
Five peripheral Input/Output Extension Connectors HE10 (PIOA, B, C, D, E)
4.3
Function Blocks
4.3.1
Processor
The SAM3X-EK is equipped with a SAM3X8H in a LFBGA217 package.
4.3.2
Memory
The SAM3X8H chip embeds:
„
512 Kbytes of embedded Flash
„
100Kbytes of embedded SRAM with dual bank
„
16 Kbytes of ROM with embedded bootloader routines (UART, USB) and IAP (In-Application
Programming functions) routines.
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11156A–ATARM–25-May-12
SAM3X-EK User Guide
The SAM3X8H features an External Bus Interface (EBI) that permits interfacing to a broad range of
external memories and virtually any parallel peripheral. The SAM3X-EK board is equipped with two kinds
of memory devices connected to the SAM3X8H EBI:
Figure 4-2.
„
One 4Mega x16 x4 banks SDRAM device(1)
„
One NAND-Flash MT29F2G08AAD.
SDRAM
[3,5,8] PC[0..30]
MN7
17
18
PD14
(SDWE)
16
19
28
41
54
6
12
46
52
100nF
CAS
RAS
100nF
15
39
PD16
PD15
PD10
C58
(NBS0)
(NBS1)
[3,8] PC21
100nF
38
SDCK
C57
[3]
100nF
(SDCKE) 37
PD13
+3V3
1
14
27
3
9
43
49
C56
36
40
100nF
(A14)
C55
PD4
100nF
20
21
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
C54
(BA0)
(BA1)
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
100nF
PD6
PD7
[3,6,7,8] PD[0..30]
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
C53
23
24
25
26
29
30
31
32
33
34
22
35
C52
PD22
PD23
PD11
PD25
(A2)
(A3)
(A4)
(A5)
(A6)
(A7)
(A8)
(A9)
(A10)
(A11)
(SDA10)
(A13)
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
JP9
(SDCS)
[3,8] PD12
Note:
Figure 4-3.
256 Mbits SDRAM
1. Brand and reference may vary. Check the bill of materiel (BOM) corresponding to your
kit version to get precise information regarding that matter.
NAND-Flash
[3,5,8] PC[0..30]
+3V3
R30
R31
1K
470K
MN8
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
PD9
PD8
PC19
PC20
PA6
[3,8] PA2
(NANDCLE)
(NANDALE)
(NANDOE)
(NANDWE)
(NCS0)
JP8
(NANDRDY)R32
+3V3
16
17
8
18
9
7
0R
R33
19
470K
R34
DNP
1
2
3
4
5
6
10
11
14
15
20
23
24
35
21
22
38
CLE
ALE
RE
WE
CE
R/B
WP
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
VCC
VCC
VCC_N.C
VCC_N.C
VSS
VSS
VSS_N.C
VSS_N.C
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
+3V3
Optional 16bits DATA BUS
With MT29F2G16AAD Micron
12
37
34
39
C50
100nF
C51
100nF
13
36
25
48
MT29F2G08AAD
8-bits NAND Flash is mounted by default
SAM3X-EK User Guide
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11156A–ATARM–25-May-12
The chip select signals SDCS and NCS0 are used for SDRAM and NAND-Flash chips selection, respectively. Furthermore, a dedicated jumper can disconnect these from the memories, to let SDCS and
NCS0 be used for other custom purpose.
4.3.3
Clock Circuitry
The clock generator of a SAM3X8H microcontroller is made up of:
„
A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
„
A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB)
„
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast
device startup
„
A 480 MHz UTMI PLL providing a clock for the USB High Speed Controller
„
A 96 to 192 MHz programmable PLL (input from 8 to 16 MHz), capable of providing the clock MCK to
the processor and to the peripherals.
The SAM3X-EK board is equipped with one 12 MHz crystal, one 32,768 Hz crystal.
External Clock Source
P2
U5
XOUT
XIN32
20pF
20pF
U6
4
C40
C42
3
Y2
32.768KHz
XIN
10pF
10pF
4
2
3
C33
C36
1
Y1
12MHz
4.3.4
P1
1
2
Figure 4-4.
XOUT32
Reset and Wake-Up Circuitry
The on-board NRST button BP1 and NRSTB button BP2 provide the SAM3X8H with external reset control. The on-board WAKE-UP button BP3 can be used to wake up the chip from low power modes.
Figure 4-5.
System Buttons
BP1
NRST
1
2
3
4
NRSTB
1
2
10nF
3
4
1
2
3
4
VDDBU [3]
NRSTB [3]
R23
BP3
WAKE UP
NRST [3,5,7]
C22
BP2
100K
VDDBU [3]
FWUP [3]
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It
will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller).
There is no constraint on the length of the reset pulse, in any case the reset controller guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 k?.
On the SAM3X-EK board, the NRST signal is connected to the LCD module, JTAG port and Ethernet
Physical Transceiver.
The NRSTB pin is input only and enables asynchronous reset of the SAM3X/A series when asserted
low. The NRSTB pin integrates a permanent pull-up resistor of about 15 kOhms. This allows connection
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11156A–ATARM–25-May-12
SAM3X-EK User Guide
of a simple push button on the NRSTB pin as a system-user reset. In all modes, this pin will reset the
chip including the Backup region (RTC, RTT and Supply Controller). It reacts as the Power-on reset. It
can be used as an external system reset source. In harsh environments, it is recommended to add an
external capacitor (10 nF) between NRSTB and VDDBU. (For filtering values, refer to “I/O characteristics” in the “Electrical Characteristics” section of the product datasheet) The NRSTB input has an
embedded anti-glitch filtering system.
The FWUP pin is enabled as a wake up source by writing the FWUPEN bit to 1 in the Supply Controller
Wake Up Mode Register (SUPC_WUMR). Then, the FWUPDBC field in the same register selects the
debouncing period, which can be selected between 3, 32, 512, 4,096 or 32,768 slow clock cycles. This
corresponds respectively to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1 second
(for a typical slow clock frequency of 32 kHz). Programming FWUPDBC to 0x0 selects an immediate
wake up, i.e., the FWUP must be low during a minimum of one slow clock period to wake up the core
power supply. If the FWUP pin is asserted for a time longer than the debouncing period, a wake up of the
core power supply is started and the FWUP bit in the Supply Controller Status Register (SUPC_SR) is
set and remains high until the register is read.
4.3.5
Power Supply and Management
The SAM3X-EK board is supplied with an external 5V DC block through input J1. A protection circuitry is
obtained by a PolyZen diode MN1 and an LC combinatory filter MN2.
The adjustable LDO regulator MN3 is employed for the main supply of the 3.3V rail. It powers all the
3.3V board components. The shut down control of this LDO is made by MOSFETs Q1, Q2 piloted by the
SAM3X8H SHDN pin. When SAM3X8H is in backup mode, SHDN pin outputs a low level signal, which
shuts down the LDO. When the device is running (not in backup mode), SHDN pin outputs a high level
signal, which enables the LDO.
By closing the “FORCE POWER ON” jumper JP3, the P-channel MOSFET Q1 will be forced on, no matter the level present on the SHDN pin, and the LDO 3.3V output will thereby be forced active.
Power Block
MN2
BNX002-01
1
2
2
3
C1
100nF
SV
2
3
PWR_CN
Q1
IRLML6401
1
R5
100K
+ C2
22uF
MN3
MIC29152WU
Micrel's 1.5A LDO, TO263-5
+5V
2
4
5
6
SG CG1
CG2
CG3
+5V
R4
100K
+5V
3
CV
1
VIN
VOUT
SD
ADJ
GND2
MN1
ZEN056V130A24LS
3
GND1
1
5
3
R7
10K
[3]
SHDN
Q2
IRLML2502
1
C13
15pF
+3V3
4
R3
169K 1%
+ C10
100uF
6
J1
MP179P 2.1mm
1
2
3
Figure 4-6.
C11
100nF
R6
102K 1%
JP3
2
Vout=(Rup/Rdown+1)*1.24
The SAM3X-EK board uses the 3.3V LDO output as its main supply source. VDDUTMI, VDDANA,
VDDIO, VDDIN are powered directly from that source.
The internal 1.8V regulator output feeds VDDCORE and VDDPLL.
SAM3X-EK User Guide
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11156A–ATARM–25-May-12
VDDCORE and VDDPLL can also be powered by an external supply. (Refer to the SAM3X datasheet for
more details).
VDDBU pin is powered from the 3.3V rail and a backup battery BT1 via a dual Schottky diode D1.
Figure 4-7.
Backup Battery
D1
BAT54C
JP2
[3]
BT1
CR12_16_20_25
+3V3
1
3
VDDBU
2
C6
100nF
4.3.6
UART
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for on-site programming solutions. Moreover,
the association with two peripheral DMA controller (PDC) channels permits packet handling for these
tasks with processor time reduced to a minimum.
This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN14 and brought to
the DB9 male connector J11.
Figure 4-8.
UART
MN14
MAX3232CSE
+3V3
16
R111
100K
[3]
[3]
PA9
PA8
(UTXD)
(URXD)
+3V3
R112
100K
C121
100nF
C1+
V+
C1-
V-
C2+
C120
100nF
2
6
3
4
C124
100nF
J11
C123
100nF
15
11
12
10
9
GND
T1IN
R1OUT
T2IN
R2OUT
C2T1OUT
R1IN
T2OUT
R2IN
UART
4.3.7
1
5
14
13
7
8
1
6
2
7
3
8
4
9
5
11
+3V3
VCC
10
C119
100nF
USART
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length,
parity, number of stop bits) to support a maximum of standards. The receiver implements parity error,
framing error and overrun error detection. The receiver time-out enables handling variable-length frames
and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485, LIN and SPI buses, with
ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature
enables an out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to
the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
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SAM3X-EK User Guide
There are 4 USARTs on the SAM3X8H device.
4.3.7.1
RS232
SAM3X-EK connects the USART0 bus (including TXD, RXD, RTS, CTS handshake signals control) to
the DB9 male connector J13 through the RS232 Transceiver MN16.
RS232
MN16
ADM3312EARU
+3V3
3
C125
4.7uF
C126
100nF
21
4
3
2
1
+3V3
PA11
PA10
PB25
PB26
23
19
(COM0_EN) R119
0R
5
(TXD0)
(RXD0)
(RTS0)
(CTS0)
0R
0R
0R
0R
7
10
8
11
9
12
R120
R121
R122
R123
C1C2+
6
20
2
V-
C129
100nF
4
24
C2C3+
GND
J13
1
6
2
7
3
8
4
9
5
C131
100nF
SD
EN
22
C3-
T1IN
R1OUT
T2IN
R2OUT
T3IN
R3OUT
18
15
17
14
16
13
T1OUT
R1IN
T2OUT
R2IN
T3OUT
R3IN
R124
0R
10
PE14
[3]
[3]
[3]
[3]
V+
C130
100nF
5
6
7
8
[3]
C1+
C128
100nF
1
RR7
47KX4
VCC
C127
100nF
11
Figure 4-9.
RS232 COM
4.3.7.2
RS485
As noticed above, the USART0 is shared with the RS485 port, connected to the transceiver MN15, connected to the 3-point connector J12. The design includes selectable jumpers for RS485 bus termination
resistors selection (JP14, JP15 and JP16).
Figure 4-10. RS485
+3V3
R106
47K
+3V3
R107
47K
R108
DNP
MN15
ADM3485ARZ
[3]
PA10
[3]
PB26
[3]
PB25
[3]
PA11
(RXD0)
R109
0R
1
(CTS0)
R110
0R
2
(RTS0)
R113
0R
3
(TXD0)
R114
0R
4
RO
RE
VCC
GND
JP14
C122
100nF
J12
1
DE
DI
2
A
B
R115
47K
RS 485
4.3.8
+3V3
8
5
6
7
3
R117
120R
JP15
JP16
R118
DNP
LEDs
There are four LEDs on the SAM3X-EK board:
„
D2 blue, D3 amber and D4 green LEDs are user defined and controlled by the GPIO.
„
D5 red LED is a power LED indicating that the 3.3V rail is enabled. It can also be controlled by the
GPIO (by default, the GPIO is disabled and an on-board pull-up to 3.3V lights the LED).
SAM3X-EK User Guide
4-7
11156A–ATARM–25-May-12
Figure 4-11. LEDs
+3V3
D2
D3
Blue
Amber
R10
470R
R11
470R
D4
D5
green
red
R12
R13
1K
1K
R14
100K
3
Q3
IRLML2502
POWER_LED#
1
PA13 [3,8]
2
USR_LED1#
4.3.9
PB13 [3,8]
USR_LED2#
PB12 [3,8]
USR_LED3#
PA12 [3,8]
LCD, Backlight Control and Touch Panel
SAM3X-EK carries one TFT/Transmissive LCD module with touch screen, FTM280C12D, with integrated driver IC HX8347. The LCD display size is 2.8 inches, with a native resolution of 240 x 320 pixels.
4.3.9.1
LCD Module
Table 4-1. LCD Module Pin Out
4-8
11156A–ATARM–25-May-12
Pin
Symbol
Function
1
GND
Ground
2
CS
Chip Select
3
RS
Register select signal
4
WR
Write operation signal
5
RD
Read operation signal
6~21
DB0~DB15
Data bus
22~23
NC
No connection
24
RESET
Reset signal
25
GND
Ground
26
X+
Touch panel X_RIGHT
27
Y+
Touch panel Y_UP
28
X-
Touch panel X_LEFT
29
Y-
Touch panel Y_DOWN
30
GND
Ground
31
VDD1
Power supply for digital IO Pad
32
VDD2
Power supply for analog circuit
33~36
A1~A4
Power supply for backlight
37~38
NC
No connection
39
K
Backlight ground
SAM3X-EK User Guide
The LCD module gets its reset from NRST. As explained previously, this NRST is shared with the JTAG
port and the push button BP1. The LCD chip select signal is connected to NCS2 (a dedicated jumper can
disable it, making NCS2 available for other custom usage).
The SAM3X8H communicates with the LCD through PIOC where a 16-bit parallel “8080-like” protocol
data bus has to be implemented by software.
Figure 4-12. LCD Block
+3V3
R36
100K
J4
FH26-39S-0.3SHW
[3,4,8] PC[0..30]
JP10
PC22
PC18
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
[3,8]
PB24
[3,8]
PA29
A1
NWE
NRD
[2,3,7] NRST
4.3.9.2
LED_A1
LED_A2
LED_A3
LED_A4
C67
100nF
R44
R45
R46
R47
0R
0R
0R
0R
PIN 39
+ C66
10uF
2.8" 320x240
TFT LCD DISPLAY
PINs
on
BOT
+3V3
GND1
CS
RS
WR
RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
NC1
NC2
RESET
GND2
X+
Y+
XYGND3
VDD1
VDD2
A1
A2
A3
A4
NC3
NC4
K
PIN 1
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
1
(NCS2) 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
FTM280C12D
Backlight Control
LCD backlight is made of 4 white chip LEDs in parallel, driven by an AAT3194 charge pump, MN10. The
AAT3194 is controlled by the SAM3X8H through a single line Simple Serial Control (S2Cwire) interface,
which permits to enable, disable, and set the LED drive current (LED brightness control) from a 32-level
logarithmic scale. Four 0-Ohm resistors R44/R45/R46/R47 are implemented for optional current limitation (replace 0 Ohm with the required resistor value).
Figure 4-13. Backlight Control
+3V3
MN10
AAT3194ITP
4
R56
47K
R60
0R
[3,8]
C2+
C1EN/SET
C2-
10
B2
BN03K314S300R
OUT
IN
C75
4.7uF
11
4.3.9.3
1
C73
1uF
3
9
PB27
+3V3
C1+
C72
1uF
GND
D1
D2
D3
D4
12
2
8
7
6
5
LED_A1
LED_A2
LED_A3
LED_A4
C76
1uF
Touch Screen Interface
The LCD module integrates a 4-wire touch screen panel controlled by MN9, ADS7843, which is a slave
device on the SAM3X8H SPI bus.
The ADS7843 touch ADC auxiliary inputs IN3/IN4 are connected to test points for optional function
extension.
SAM3X-EK User Guide
4-9
11156A–ATARM–25-May-12
Figure 4-14. Touch Screen Controller
+3V3
R49
100K
MN9
ADS7843E
2
3
4
5
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
TP5
SMD
TP6
SMD
R57
100K
AGND_TP
DCLK
DIN
DOUT
CS
BUSY
PENIRQ
7
8
4.3.10
XP
YP
XM
YM
R58
100K
IN3
IN4
+3V3
VREF
VCC1
VCC2
GND
16
14
12
15
R50
100K
R51
0R
13
11
R52
0R
9
1
10
R54
(SPI0_SPCK)
(SPI0_MOSI)
(SPI0_MISO)
(SPI0_NPCS0)
BUSY_TSC
0R IRQ_TSC
+3V3
R53
C69
100nF
6
PA27
PA26
PA25
PA28
[3,8]
[3,8]
[3,8]
[3,8]
PA30 [3,8]
PA31 [3,8]
0R
C70
100nF
C71
100nF
R55
1R
L4
10uH/150mA
C74
4.7uF
R59
0R
AGND_TP
LCD TOUCH SCREEN
JTAG/ICE
A standard 20-pin JTAG connector is implemented on the SAM3X-EK for any ARM JTAG emulator connection, such as SAM-ICE from Segger.
Note that the NRST net is connected to the system button BP1, and is also used to reset the LCD module. 0-Ohm resistor R24 may be removed in order to isolate the JTAG port from the system reset signal.
Figure 4-15. JTAG Connector
+3V3
R18
100K
[3,8]
[3,8]
[3,8]
R19
100K
R21
100K
R20
100K
R22
100K
PB29
PB31
PB28
[3,8]
PB30
[3,5,7] NRST
R24
0R
J2
1
3
5
7
9
11
13
15
17
19
VTref
Vsupply
nTRST
GND1
TDI
GND2
TMS
GND3
TCK
GND4
RTCK
GND5
TDO
GND6
nSRST
GND7
DBGRQ GND8
DBGACK GND9
2
4
6
8
10
12
14
16
18
20
ICE INTERFACE
4.3.11
Audio Codec
The SAM3X-EK includes a WOLFSON codec WM8731 for digital sound input and output. This interface
includes audio jacks for:
„
microphone input
„
headphone output
The SAM3X8H programmable clock output is used to generate the WM8731 master clock (MCLK). The
SAM3X8H ODT (On-Die Termination) feature guarantees a signal integrity on this clock line without the
need for external discrete components.
WM8731 pin 21 MODE is pulled down by default; this configures the device as a TWI device for internal
register access.
Pin15 CSB is pulled up, which sets its TWI address as 33 [0x0011011].
The WM8731 digital interface works in slave mode on the SAM3X8H Synchronous Serial Controller
(SSC) interface, which means that Codec digital audio bit clock and ADC/DAC left/right control clock are
to be generated by the SAM3X8H.
The WM8731 ADC and DAC have separated left/right control clocks to run at different rates.
4-10
11156A–ATARM–25-May-12
SAM3X-EK User Guide
The bit clock is shared; it can be the SSC transmitter clock (TK) or the receiver clock (RK). The default
setting on SAM3X-EK is TK and RK shorted together through R71/R72. Please note that trying different
ADC/DAC rates would mean different RK/TK rates; this default setting can be modified.
The 0-Ohm resistors R71/R72/R73/R74 have been implemented to offer a disconnection possibility
(freeing these dedicated PIO lines for other custom usage).
Figure 4-16. Codec Block
MN11
XWM8731EDS
+3V3
1
27
DGND
AGND
HPGND
AVDD
14
8
C79
100nF
C80
100nF
28
26
2
16
+ C84
10uF
C85
100nF
12
13
C81
100nF
+ C82
10uF
15
11
XTO
CLKOUT
AGND_AUDIO
VMID
LHPOUT
LOUT
ROUT
RHPOUT
9
C83
10
C86
+
C78
100nF
AVDD
HPVDD
220uF
+
+ C77
10uF
DBVDD
DCVDD
220uF
J5
PHONEJACK
B3
BN03K314S600R
R61
47K
1
2
3
4
5
B4
BN03K314S600R
R62
47K
C87
470pF
HEADPHONE
LINE-OUT
C88
470pF
AGND_AUDIO
+3V3
+3V3
+3V3
AGND_AUDIO
R63
100K
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
(TWD0)
(TWCK0)
(PCK0)
(TK)
R71
(RF)
R72
(TD)
(TF)
(RD)
R73
(RF)
R74
PA17
PA18
PB22
PA14
PB19
PA16
PA15
PB18
PB17
R76
R64
4.7K
R66
4.7K
LLINEIN
22
23
24
0R
0R
25
3
4
5
6
7
10K
21
0R
0R
CSB
SDIN
SCLK
XTI/MCLK
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
MODE
RLINEIN
20
R67
100K
19
R68
100K
AGND_AUDIO
AGND_AUDIO
MICBIAS
MICIN
17
R75
680R
18
R77
330R
C98
J7
PHONEJACK
B7
BN03K314S600R
1uF
R78
C99
220pF
R79
47K
0R
5
4
3
2
1
MONO MICRO INPUT
AGND_AUDIO
AGND_AUDIO
4.3.12
USB
The SAM3X8H USB port is compliant with the Universal Serial Bus (USB) rev 2.0 specification at all
speeds. J3 is a micro AB-type receptacle for USB Host/Device.
Both R25 and R26 39-Ohm resistors build up a 90-Ohm differential impedance together with the 5-Ohm
output impedance of the Hi-speed channel drivers.
MN4 build up a power controler to guarantee the mode of USB can be switched between Device and
Host mode.
Table 4-2. I/O Lines Description
PIn Name
Pin Description
UOTGVBOF
USB VBus On/Off: Bus Power Control Port
VBUS
VBus: Bus Power Measurement Port
D-
Data -: Differential Data Line - Port
Input/Output
D+
Data +: Differential Data Line + Port
Input/Output
DFSDM
FS Data -: Full-Speed Differential Data Line - Port
Input/Output
DFSDP
FS Data +: Full-Speed Differential Data Line + Port
Input/Output
SAM3X-EK User Guide
Type
Active Level
Output
VBUSPO
Input
4-11
11156A–ATARM–25-May-12
PIn Name
Pin Description
Type
DHSDM
HS Data -: Hi-Speed Differential Data Line - Port
Input/Output
DHSDP
HS Data +: Hi-Speed Differential Data Line + Port
Input/Output
UOTGID
USB Identification: Mini Connector Identification Port
Input
Active Level
Low: Mini-A plug
High Z: Mini-B plug
Figure 4-17. USB Block
+3V3
R8
R17
10K
100K
MN4
8
+5V
7
6
C21
100nF
5
EN
OUT2
IN
FLG
OUT1
GND
NC1
NC2
1
(UOTGVBOF)
2
USB_FAULT
PB10 [3,8]
PE5 [3,8]
3
4
SP2525-2
B1
BN03K314S300R
RV1
VBUS [3]
+ C23
33uF
V5.5MLA0603
J3
C24
100nF
SHD
7
VBUS
DM
DP
ID
GND
1
2
3
4
5
(UOTGID)
DHSDM [3]
DHSDP [3]
PB11 [3,8]
6
USB Micro AB
USB
PIn Name
Pin Description
UOTGVBOF
USB VBus On/Off: Bus Power Control Port
VBUS
VBus: Bus Power Measurement Port
D-
Data -: Differential Data Line - Port
Input/Output
D+
Data +: Differential Data Line + Port
Input/Output
DFSDM
FS Data -: Full-Speed Differential Data Line - Port
Input/Output
DFSDP
FS Data +: Full-Speed Differential Data Line + Port
Input/Output
DHSDM
HS Data -: Hi-Speed Differential Data Line - Port
Input/Output
DHSDP
HS Data +: Hi-Speed Differential Data Line + Port
Input/Output
UOTGID
USB Identification: Mini Connector Identification Port
4.3.13
Type
Active Level
Output
VBUSPO
Input
Input
Low: Mini-A plug
High Z: Mini-B plug
Analog Interface
The 3.0V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).
This ADVREF level can be set as 3.0V or 3.3V via the jumper JP7.
4-12
11156A–ATARM–25-May-12
SAM3X-EK User Guide
Figure 4-18. Analog VREF
+3V3
U15
1
+3V3
ADVREF
+5V
R27
4.7K
JP7
2
+3V
D6
3
C47
100nF
C16
2.2uF
LM4040-3.0
A 10 KOhm potentiometer (VR1) is connected to ADC1 port PA3 to implement an easy access to ADC
programming and debugging(or implement an analog user control such as display brightness, volume,
etc.).
Figure 4-19. ADC Input
Potentiometer
1
+3V3
JP4
4
VR1
10K
R35
3
JP
4.3.14
AD1
2
0R
PA3
5
R15
DNP
[3,8]
C20
10nF
User Buttons
There are two mechanical user buttons on the SAM3X-EK, which are connected to PIO lines and defined
to be "left" and "right" buttons by default.
Figure 4-20. User Buttons
BP4
RIGHT CLICK
1
2
3
4
PB23 [3,8]
3
4
PE7
BP5
LEFT CLICK
4.3.15
1
2
[3,8]
QTouch Elements
QTouch keys consist in a series of sensors formed by the association of a copper area and the capacitive
effect of human fingers approaching it.
4.3.15.1 Keys
The SAM3X-EK implements five individual capacitive touch keys (UP, DOWN, RIGHT, LEFT and VALID)
using five pairs of PIO.
SAM3X-EK User Guide
4-13
11156A–ATARM–25-May-12
Figure 4-21. QST Keys
[3]
R38
PE21
1K
C60
22nF
[3]
PE20
[3]
PE27
[3]
PE26
[3]
PE25
R40
K1
DNP
1K
C62
22nF
R42
1K
C64
22nF
[3]
PE24
[3]
PE19
R43
1K
C65
22nF
[3]
PE18
[3]
PE23
R48
1K
C68
22nF
[3]
4.3.15.2
QST Keys
PE22
Slider
A group of channels forms a Slider. A Slider is composed of three channels for a QTouch acquisition
method using three pairs of PIO. Such a sensor is used to detect a linear finger displacement on a
sensitive area. A typical implementation is volume control.
Figure 4-22. QT_Slider
S1
DNP
SR
[3]
PF1
[3]
PF0
[3]
PF3
R37
1K
C59
22nF
R39
SL
1K
SM
C61
22nF
[3]
PF2
[3]
PF5
[3]
PF4
SR
R41
1K
C63
22nF
QT Slider
4.3.16
EEPROM
There is one serial EEPROM on the SAM3X-EK, which is connected to TWI interface. Pin1 A0 is pulled
up, which sets its TWI address as 51 [0x1010001] by JP11 default open.
4-14
11156A–ATARM–25-May-12
SAM3X-EK User Guide
Figure 4-23. EEPROM Block
+3V3
R83
10K
MN12
6
5
(TWCK0)
(TWD0)
[3,8] PA18
[3,8] PA17
+3V3
C100
100nF
8
4
SCL
SDA
A0
A1
A3
1
2
3
JP11
VCC
GND
WP
7
AT24C512BN
SERIAL EEPROM
4.3.17
SD Card
The SAM3X-EK has an MMC/MMCPlus high-speed 8-bit multimedia interface. This interface is used as
a 4/8-bit interface, connected to an 8-bit SD/MMC card slot with card detection.
Figure 4-24. SD Card Socket
R82
10K
[3,8]
PA23
[3,8]
[3,8]
PA24
PD0
[3,8]
[3,8]
PA20
PD1
RR2
47KX4
RR1
47KX4
J8
7SDMM-B0-2211-A
5
6
7
8
R81
10K
5
6
7
8
R80
10K
4
3
2
1
4
3
2
1
+3V3
(MCDA2)
1
(MCDA3)
(MCDA4)
2
3
(MCCDA)
(MCDA5)
4
5
6
7
[3,8]
[3,8]
PA19
PD2
[3,8]
[3,8]
PE6
PD3
[3,8]
[3,8]
PA21
PA22
(MCCK)
(MCDA6)
8
9
(MCI_CD)
(MCDA7)
10
11
(MCDA0)
(MCDA1)
12
13
14
DAT2
RSV/DAT3
DAT4
CMD
DAT5
GND
VCC
CLK
DAT6
GROUND1
SHELLED1
SHELLED2
GROUND
15
17
18
16
CD
DAT7
DAT0
DAT1
SD_WP
+3V3
+ C101
10uF
C102
100nF
Table 4-3. Pin Card Detection Scheme
Status
4.3.18
Detection
WITHOUT CARD
SD_WP: OPEN
CD: OPEN
SD Card inserted with write protection lock
SD_WP: OPEN
CD: GND
SD Card inserted with write protection unlock, or other card inserted
SD_WP: GND
CD: GND
IEEE 802.15.4 / ZigBee
SAM3X-EK has a 10-pin male connector for the RZ600 IEEE 802.15.4 / ZigBee module.
SAM3X-EK User Guide
4-15
11156A–ATARM–25-May-12
Figure 4-25. IEEE 802.15.4 / ZigBee
J10
[3,8] PE9
[3,8] PE12
[3,8] PE31
[3,8] PE28
ZB_RSTN
R102
ZB_IRQ1
R104
(SPI1_NPCS0)
(SPI1_MISO)
0R
0R
1
3
5
7
9
2
4
6
8
10
R103
R105
0R
0R
C116
18pF
ZB_IRQ0
ZB_SLPTR
(SPI1_MOSI)
(SPI1_SPCK)
C117
2.2nF
PE11 [3,8]
PE10 [3,8]
PE29 [3,8]
PE30 [3,8]
JP13
+3V3
C118
2.2uF
IEEE 802.15.4 / ZigBee for Atmel RZ600
4-16
11156A–ATARM–25-May-12
SAM3X-EK User Guide
4.3.19
PIO Expansion
The SAM3X8H product features six PIO controllers, PIOA-F, which are multiplexed with the I/O lines of
the embedded peripherals. Each PIO Controller controls up to 32 lines (31 for PIOC and PIOD, 6 for
PIOF).
Expansion ports J14, J15, J16, J18 and J19 provide PIO lines access for customer defined usage.
Figure 4-26. PIO Expansion Ports
[3,4,5] PC[0..30]
[2,3,5,6,7]
PB[0..31]
[2,3,4,5,6,7] PA[0..31]
JP18
+5V
1
J15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+3V3
3
JP19
+5V
1
J16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
+3V3
+3V3
[2,3,5,6,7]
+3V3
3
2
+3V3
3
2
1
2
JP17
+5V
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
+3V3
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
+3V3
PE[0..31]
[3,4,6,7] PD[0..30]
+3V3
3
JP21
+5V
1
2
1
J19
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+3V3
3
2
JP20
+5V
J18
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
+3V3
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PE16
PE17
PE28
PE29
PE30
PE31
+3V3
PIO EXPANSION
Note: All PIO lines are available on these expansion connectors, except those that are used for
the QTouch elements.
SAM3X-EK User Guide
4-17
11156A–ATARM–25-May-12
4.3.20
Ethernet MAC 10/100 (EMAC)
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using
an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface.
The SAM3X-EK is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical Layer
TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as defined
by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment (PMA),
Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface provides RMII (Reduced MII), for 100Base-TX or 10Base-TX. The RMII interfaces
are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard.
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status
LEDs. For guarantee DM9161AEP is reset properly, a reset IC MN19 is integrated too.
Figure 4-27. Ethernet Block
+3V3
R84
10K
Y3
1 OE
[3,8] PD17
C103
100nF
VDD 4
50MHz
2 VSS
OUT 3 R85
0R
C92
DNP
C104
[3,8] PB6
[3,8] PB5
[3,8] PB4
[3,8] PB7
(ETX1)
(ETX0)
(ETXEN)
TP7
SMD
(ERX1)
(ERX0)
26
27
28
29
(ECRSDV)
34
37
(ERXER)
16
38
+3V3
(EMDC)
(EMDIO)
(MDINTR)
R93
+3V3
3
VCC
MR
RESET
GND
100nF
41
100nF
30
C114
100nF
23
1
2
3
4
8
7
6
5
1
2
3
4
R98
0R
2
8
3
RX-
4
AVDDR
AVDDR
DM9161AEP
AVDDT
AGND
AGND
AGND
DISMDIX
BGRESG
DVDD
1
C106
100nF
2
C107
100nF
DVDD
40
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
RESET
N.C
+ C108
10uF
R91
R92
10
9
TX-
2
3 RD+
RX+
3
RX-
6
C105
100nF
75
7 NC
49.9R 1%
+ C109
10uF
100nF
75
75
4
5
1nF
GND_ETH
8
C111
100nF
5
6
46
75
7
8
+3V3
GND_ETH
47
R94
R95
6.8K
PWRDWN
2 TD-
AVDDT
49.9R 1%
AVDDT
9
C110
DVDD
10
1
6 RDB8
BLM21BD222TN1
COL/RMII
CRS/PHYAD4
DGND
DGND
DGND
TX+
5 CT
TX_ER/TXD4
RX_ER/RXD4/RPTR
15
33
44
RR5
10KX4
1 TD+
48
31
11
12
13
14
0R
GND_ETH
R70
RR6
10K
10KX4
RJ45 ETHERNET CONNECTOR
+3V3
D8
Amber R96
470R
FULL DUPLEX
D9
green R97
1K
SPEED 100
D10
green R99
1K
LINK&ACT
45
1
R90
100K
CAT811
R87
RR4
10KX4
+3V3
MN19
4
[2,3,5] NRST
8
7
6
5
8
7
6
5
1
2
3
4
RR3
10KX4
RX+
+3V3
C113
49.9R 1%
AVDDT
RX_CLK/10BTSER
RX_DV/TESTMODE
MDC
MDIO
MDINTR
R89
7
4 CT
TX-
24
25
32
C112
R88
J9
TX+
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
1.5K
JP12
43
49.9R 1%
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
39
Install as need to alter PHY
address, must override internal
pullup on SAM3
XT1
REF_CLK/XT2
17
18
19
20
21
22
36
35
[3,8] PB8
[3,8] PB9
[3,8] PA5
GND_ETH
MN13
42
8
7
6
5
[3,8] PB3
[3,8] PB2
[3,8] PB1
R86
0R
(EREFCK)
1
2
3
4
[3,8] PB0
100nF
DNP
+3V3
+ C115
10uF
R100
0R
R101
0R
R116
GND_EARTH
DNP
GND_ETH
ETHERNET
4.3.21
CAN
The CAN controller provides all the features required to implement the serial communication protocol
CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A
and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle
all types of frames (Data, Remote, Error and Overload) and achieves a bit rate of 1 Mbit/sec.
The SAM3X8H has two CAN Controllers with eight Mailboxes.
4-18
11156A–ATARM–25-May-12
SAM3X-EK User Guide
SAM3X-EK connects the CAN0 and CAN1 bus (including CANRX0/1, CANTX0/1, CANRX0/1EN,
CANTX0/1RS handshake signals control) to the RJ12 female connector J17 and J20 through the CAN
Transceiver MN17 and MN18.
Figure 4-28. CAN
+3V3
R125
10K
[3]
PB20
(CANTX0RS) R126
J17
1
MN17
8 Rs
0R
JP22
2
CANH 7
[3]
PA0
[3]
PB21
[3]
PA1
(CANTX0)
R127
1 D
0R
3
CANL 6
(CANRX0EN) R129
0R
5 EN
(CANRX0)
0R
4 R
R128
120R
4
5
R130
6
+3V3
R131
2 GND
1
2
3
CAN RJ12
4
5
6
VCC 3
10K
SN65HVD234
+ C132
10uF
C133
100nF
CAN0
+3V3
R132
10K
[3]
PE15
(CANTX1RS) R134
J20
1
MN18
8 Rs
0R
JP23
2
CANH 7
[3]
PB14
[3]
PE16
[3]
PB15
(CANTX1)
R133
3
1 D
0R
CANL 6
(CANRX1EN) R136
0R
5 EN
R137
0R
4 R
R135
120R
4
5
(CANRX1)
6
+3V3
R138
2 GND
1
2
3
CAN RJ12
4
5
6
VCC 3
10K
SN65HVD234
+ C134
10uF
4.4
C135
100nF
CAN1
Configuration
This section describes the PIO usage, the jumpers, the test points and the solder drops of a SAM3U-EK
board.
SAM3X-EK User Guide
4-19
11156A–ATARM–25-May-12
4.4.1
PIO Usage
Table 4-4. PIO Port A Assignment
I/O Line
Peripheral A
Peripheral B
PA0
CANTX0
PWML3
PA1
CANRX0
PCK0
PA2
TIOA1
PA3
EK Usage
Device
CANTX0
CAN
WKUP0
CANRX0
CAN
NANDRDY
AD0
NANDRDY
NAND-Flash
TIOB1
PWMFI1
AD1/WKUP1
AD1
ADC INPUT
PA4
TCLK1
NWAIT
AD2
PA5
TIOA2
PWMFI0
WKUP2
MD_INTR
Ethernet
PA6
TIOB2
NCS0
AD3
NCS0
NAND-Flash
PA7
TCLK2
NCS1
WKUP3
NCS1
SDRAM
PA8
URXD
PWMH0
WKUP4
URXD
UART
PA9
UTXD
PWMH3
UTXD
UART
PA10
RXD0
DATRG
WKUP5
RXD0
USART
PA11
TXD0
ADTRG
WKUP6
TXD0
USART
PA12
RXD1
PWML1
WKUP7
USER_LED3
USER_LED
PA13
TXD1
PWMH2
POWER_LED
POWER_LED
PA14
RTS1
TK
TK
Audio codec
PA15
CTS1
TF
WKUP8
TF
Audio codec
PA16
SPCK1
TD
AD7
TD
Audio codec
PA17
TWD0
SPCK0
TWD0
Audio codec
PA18
TWCK0
A20
TWCK0
Audio codec
PA19
MCCK
PWMH1
MCCK
SD/MMC
PA20
MCCDA
PWML2
MCCDA
SD/MMC
PA21
MCDA0
PWML0
MCDA0
SD/MMC
PA22
MCDA1
TCLK3
AD4
MCDA1
SD/MMC
PA23
MCDA2
TCLK4
AD5
MCDA2
SD/MMC
PA24
MCDA3
PCK1
AD6
MCDA3
SD/MMC
PA25
SPI0_MISO
A18
SPI0_MISO
Touch Controller
PA26
SPI0_MOSI
A19
SPI0_MOSI
Touch Controller
PA27
SPI0_SPCK
A20
WKUP10
SPI0_SPCK
Touch Controller
PA28
SPI0_NPCS0
PCK2
WKUP11
SPI0_NPCS0
Touch Controller
PA29
SPI0_NPCS1
NRD
NRD
LCD
PA30
SPI0_NPCS2
PCK1
BUSY_TSC
Touch Controller
PA31
SPI0_NPCS3
PCK2
IRQ_TSC
Touch Controller
4-20
11156A–ATARM–25-May-12
Extra Function
WKUP9
SAM3X-EK User Guide
Table 4-5. PIO Port B Assignment
I/O Line
Peripheral A
Peripheral B
PB0
ETXCK/EREFCK
PB1
EK Usage
Device
TIOA3
ETXCK/EREFCK
Ethernet
ETXEN
TIOB3
ETXEN
Ethernet
PB2
ETX0
TIOA4
ETX0
Ethernet
PB3
ETX1
TIOB4
ETX1
Ethernet
PB4
ECRSDV/ERXDV
TIOA5
ECRSDV/ERXDV
Ethernet
PB5
ERX0
TIOB5
ERX0
Ethernet
PB6
ERX1
PWML4
ERX1
Ethernet
PB7
ERXER
PWML5
ERXER
Ethernet
PB8
EMDC
PWML6
EMDC
Ethernet
PB9
EMDIO
PWML7
EMDIO
Ethernet
PB10
UOTGVBOF
A18
UOTGVBOF
USB
PB11
UOTGID
A19
UOTGID
USB
PB12
TWD1
PWMH0
AD8
USER_LED2
USER_LED
PB13
TWCK1
PWMH1
AD9
USER_LED1
USER_LED
PB14
CANTX1
PWMH2
CANTX1
CAN
PB15
CANRX1
PWMH3
DAC0/WKUP12
CANRX1
CAN
PB16
TCLK5
PWML0
DAC1
PB17
RF
PWML1
AD10
RF
Audio codec
PB18
RD
PWML2
AD11
RD
Audio codec
PB19
RK
PWML3
AD12
RK
Audio codec
PB20
TXD2
SPI0_NPCS1
AD13
CANTX0RS
CAN
PB21
RXD2
SPI0_NPCS2
AD14/WKUP13
CANRX0EN
CAN
PB22
RTS2
PCK0
PCK0
Audio codec
PB23
CTS2
SPI0_NPCS3
BP4_RIGHT
USER KEY
PB24
SCK2
NCS2
NCS2
LCD
PB25
RTS0
TIOA0
RTS0
USART
PB26
CTS0
TCLK0
CTS0
USART
PB27
NCS3
TIOB0
BL_EN
LCD
PB28
TCK/SWCLK
TCK
JTAG/ICE
PB29
TDI
TDI
JTAG/ICE
PB30
TDO/TRACESWO
TDO
JTAG/ICE
PB31
TMS/SWDIO
TMS
JTAG/ICE
SAM3X-EK User Guide
Extra Function
WKUP14
WKUP15
4-21
11156A–ATARM–25-May-12
Table 4-6. PIO Port C Assignment
I/O Line
Peripheral A
Peripheral B
PC0
Extra Function
EK Usage
Device
ERASE
ERASE
SAM3X8H
PC1
PC2
D0
PWML0
D0
SDRAM, NAND-Flash, LCD
PC3
D1
PWMH0
D1
SDRAM, NAND-Flash, LCD
PC4
D2
PWML1
D2
SDRAM, NAND-Flash, LCD
PC5
D3
PWMH1
D3
SDRAM, NAND-Flash, LCD
PC6
D4
PWML2
D4
SDRAM, NAND-Flash, LCD
PC7
D5
PWMH2
D5
SDRAM, NAND-Flash, LCD
PC8
D6
PWML3
D6
SDRAM, NAND-Flash, LCD
PC9
D7
PWMH3
D7
SDRAM, NAND-Flash, LCD
PC10
D8
ECRS
D8
SDRAM, NAND-Flash, LCD
PC11
D9
ERX2
D9
SDRAM, NAND-Flash, LCD
PC12
D10
ERX3
D10
SDRAM, NAND-Flash, LCD
PC13
D11
ECOL
D11
SDRAM, NAND-Flash, LCD
PC14
D12
ERXCK
D12
SDRAM, NAND-Flash, LCD
PC15
D13
ETX2
D13
SDRAM, NAND-Flash, LCD
PC16
D14
ETX3
D14
SDRAM, NAND-Flash, LCD
PC17
D15
ETXER
D15
SDRAM, NAND-Flash, LCD
PC18
NWR0/NWE
PWMH6
NWE
LCD
PC19
NANDOE
PWMH5
NANDOE
NAND-Flash
PC20
NANDWE
PWMH4
NANDWE
NAND-Flash
PC21
A0/NBS0
PWML4
NBS0
SDRAM
PC22
A1
PWML5
A1
LCD
PC23
A2
PWML6
A2
SDRAM
PC24
A3
PWML7
A3
SDRAM
PC25
A4
TIOA6
A4
SDRAM
PC26
A5
TIOB6
A5
SDRAM
PC27
A6
TCLK6
A6
SDRAM
PC28
A7
TIOA7
A7
SDRAM
PC29
A8
TIOB7
A8
SDRAM
PC30
A9
TCLK7
A9
SDRAM
4-22
11156A–ATARM–25-May-12
SAM3X-EK User Guide
Table 4-7. PIO Port D Assignment
I/O Line
Peripheral A
Peripheral B
PD0
A10
PD1
EK Usage
Device
MCDA4
MCDA4
SD/MMC
A11
MCDA5
MCDA5
SD/MMC
PD2
A12
MCDA6
MCDA6
SD/MMC
PD3
A13
MCDA7
MCDA7
SD/MMC
PD4
A14
TXD3
A14
SDRAM
PD5
A15
RXD3
PD6
A16/BA0
PWMFI2
BA0
SDRAM
PD7
A17/BA1
TIOA8
BA1
SDRAM
PD8
A21/NANDALE
TIOB8
NANDALE
NAND-Flash
PD9
A22/NANDCLE
TCLK8
NANDCLE
NAND-Flash
PD10
NWR1/NBS1
NBS1
SDRAM
PD11
SDA10
SDA10
SDRAM
PD12
SDCS
SDCS
SDRAM
PD13
SDCKE
SDCKE
SDRAM
PD14
SDWE
SDWE
SDRAM
PD15
RAS
RAS
SDRAM
PD16
CAS
CAS
SDRAM
PD17
A5
OSC_OE
Ethernet
PD18
A6
PD19
A7
PD20
A8
PD21
A9
PD22
A10
A10
SDRAM
PD23
A11
A11
SDRAM
PD24
A12
PD25
A13
A13
SDRAM
PD26
A14
PD27
A15
PD28
A16/BA0
PD29
A17/BA1
PD30
A18
SAM3X-EK User Guide
Extra Function
4-23
11156A–ATARM–25-May-12
Table 4-8. PIO Port E Assignment
I/O Line
Peripheral A
PE0
A19
PE1
A20
PE2
A21/NANDALE
PE3
A22/NANDCLE
PE4
A23
PE5
PE6
Peripheral B
EK Usage
Device
NCS4
USB_FAULT
USB
NCS5
MCI_CD
SD/MMC
BP5_LEFT
USER KEY
PE7
Extra Function
PE8
PE9
TIOA3
ZB_RSTN
ZigBee
PE10
TIOB3
ZB_SLPTR
ZigBee
PE11
TIOA4
ZB_IRQ0
ZigBee
PE12
TIOB4
ZB_IRQ1
ZigBee
PE13
TIOA5
PE14
TIOB5
COM0_EN
RS232
PE15
PWMH0
CANTX1RS
CAN
PE16
PWMH1
SCK3
CANRX1EN
CAN
PE17
PWML2
PE18
PWML0
NCS6
QTVALID_SNS
QTouch Keys
PE19
PWML4
QTVALID_SNSK
QTouch Keys
PE20
PWMH4
QTUP_SNS
QTouch Keys
PE21
PWML5
QTUP_SNSK
QTouch Keys
PE22
PWMH5
QTDWN_SNS
QTouch Keys
PE23
PWML6
QTDWN_SNSK
QTouch Keys
PE24
PWMH6
QTLEFT_SNS
QTouch Keys
PE25
PWML7
QTLEFT_SNSK
QTouch Keys
PE26
PWMH7
MCDB2
QTRIGHT_SNS
QTouch Keys
PE27
NCS7
MCDB3
QTRIGHT_SNSK
QTouch Keys
PE28
SPI1_MISO
SPI1_MISO
ZigBee
PE29
SPI1_MOSI
SPI1_MOSI
ZigBee
PE30
SPI1_SPCK
SPI1_SPCK
ZigBee
PE31
SPI1_NPCS0
SPI1_NPCS0
ZigBee
4-24
11156A–ATARM–25-May-12
MCCDB
MCDB0
MCDB1
SAM3X-EK User Guide
Table 4-9. PIO Port F Assignment
I/O Line
Peripheral A
PF0
EK Usage
Device
SPI1_NPCS1
QTSLIDER_SL_S
NS
QTouch Slider
PF1
SPI1_NPCS2
QTSLIDER_SL_S
NSK
QTouch Slider
PF2
SPI1_NPCS3
QTSLIDER_SM_
SNS
QTouch Slider
PF3
PWMH3
QTSLIDER_SM_
SNSK
QTouch Slider
PF4
CTS3
QTSLIDER_SR_S
NS
QTouch Slider
PF5
RTS3
QTSLIDER_SR_S
NSK
QTouch Slider
4.4.2
Peripheral B
Extra Function
Jumpers
The SAM3X-EK board jumpers are essentially used for two main purposes: functional selection or
current measurement. Details are given below.
Table 4-10. Jumpers Setting
Designation
Default
Setting
Label
Feature
JP1(1-2)
VDDIO
CLOSE
Access for current measurement on VDDIO
JP1(3-4)
VDDCORE
CLOSE
Access for current measurement on VDDCORE
JP1(5-6)
VDDPLL
CLOSE
Access for current measurement on VDDPLL
JP1(7-8)
VDDUTMI
CLOSE
Access for current measurement on VDDUTMI
JP1(9-10)
VDDIN
CLOSE
Access for current measurement on VDDIN
JP1(11-12)
VDDANA
CLOSE
Access for current measurement on VDDANA
JP2
VDDBU
CLOSE
Access for current measurement on VDDBU
JP3
FORCE
POWER ON
CLOSE
Close Force +3V3 LDO output valid
JP4
ADC INPUT
CLOSE
ADC input potentiometer
JP6
ERASE
OPEN
Close to reinitialize the Flash contents and some of its NVM bits
JP7
ADVREF
1-2
Analog reference voltage selection between 3.3V (close 1-2) and
3.0V (close 2-3)
JP8
NCS0
CLOSE
NCS0 enable NAND Flash chip select
JP9
SDCS
CLOSE
SDCS enable SDRAM Flash chip select
JP10
NCS2
CLOSE
NCS2 chip select LCD
JP11
ADDRESS
SELECT
OPEN
EEPROM TWI address select (OPEN:51 CLOSE:50)
JP12
DISMDIX
CLOSE
Enable HP Auto-MDIX mode
JP13
ZIGBEE
CLOSE
Power supply connection/disconnection for the ZigBEE module
May also be used as a current measurement point
SAM3X-EK User Guide
4-25
11156A–ATARM–25-May-12
Table 4-10. Jumpers Setting
Designation
Default
Setting
Label
Feature
JP14-JP16
RS485
CLOSE
RS485 bus termination resistors selection
JP17-JP21
PIO expansion
connector
voltage supply
2-3
Set to 3.3V (position 1-2 sets to 5V)
JP22-JP23
CAN
CLOSE
CAN bus termination resistors selection
4.4.3
Test Points
Some test points have been placed on the SAM3X-EK board for the verification of important signals.
Table 4-11. Test Points
4.4.4
Designation
Part
Description
TP1
Ring Hook
GND
TP2
Ring Hook
GND
TP3
Ring Hook
GND
TP4
Ring Hook
GND
TP5
Pad
Aux ADC input IN3 for touch screen control
TP6
Pad
Aux ADC input IN4 for touch screen control
TP7
Pad
Ethernet TX CLK
Assigned PIO Lines, Disconnection Possibility
As pointed out previously in the interface description, 0 Ohm resistors have been inserted on the path of
the receiver PIO lines of the SAM3X-EK. These are the PIO lines connected to an external driver on the
board. The 0 Ohm resistors allow disconnecting each of these for custom usage (through PIO expansion
connectors for example). This feature gives the user an added level of versatility for prototyping a system
of his own. See the table below.
Table 4-12. Disconnecting Possibility
4-26
11156A–ATARM–25-May-12
Designation
Default Assignment
PIO
R24
0R
NRST
R32
0R
PA2, RDY/BSY on NAND Flash
R35
0R
PA3
R51
0R
PA28
R52
0R
PA30
R53
0R
PA31
R44-47
0R
LCD parallel backlight LED anode
R60
0R
PB27
R71
0R
PA14
R72
0R
PB19
R73
0R
PB18
R74
0R
PB17
SAM3X-EK User Guide
Table 4-12. Disconnecting Possibility
Designation
Default Assignment
PIO
R86
0R
PB0
R102
0R
PE9
R103
0R
PE11
R104
0R
PE12
R105
0R
PE10
R109
0R
PA10, RS485
R110
0R
PB26, RS485
R113
0R
PB25, RS485
R114
0R
PA11, RS485
R119
0R
PE14
R120
0R
PA11, RS232
R121
0R
PA10, RS232
R122
0R
PB25, RS232
R123
0R
PB26, RS232
R126
0R
PB20
R127
0R
PA0
R129
0R
PB21
R130
0R
PA1
R133
0R
PB14
R134
0R
PE15
R136
0R
PE16
R137
0R
PB15
Table 4-13. Default Not Populated Parts
Designation
Default Assignment
R15
Optional termination for ADC input
R87
Optional RC filter for DM9161AEP reset
C92
Optional filter for 50MHz Oscillator output
D7
Optional ESD protection for LCD touch panel
K1
Virtual component for QTouch keys set - implemented as copper areas
S1
Virtual component for QTouch slider set - implemented as copper areas
R34
Optional write protection NAND Flash
R139,R140
Optional JTAGSEL and TST enable
R108,R118
Optional termination for RS485
SAM3X-EK User Guide
4-27
11156A–ATARM–25-May-12
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
„
TOP LEVEL
„
POWER SUPPLY & USB & JTAG
„
ATSAM3X_LFBGA217
„
EBI_MEMORY
„
DISPLAY & QTouch
„
Audio & HSMCI & TWI
„
ETHERNET & ZIGBEE
„
SERIAL & USER INTERFACES
SAM3X-EK User Guide
5-1
11156A–ATARM–25-May-12
5V
POWER SUPPLY
2
3
EBI SDRAM INTERFACE
3V3
USER'S
INTERFACE
EBI
POWER
NAND
FLASH
D
CARD
READER
ADC1
C
AUDIO
OUT
Sheet 2
MIC
ATMEL
Cortex-M3 ARM Processor
SAM3X (LFBGA217)
C
PIO A,...F
SERIAL
EEPROM
QTOUCH
PIO
UART
PIO A,...F
COM
TOUCH SCREEN
Sheet 5
CAN0
RJ 45
B
10/100 FAST
ETHERNET
HE 10
CAN1
ZIGBEE
INTERFACE
USART0
PIO
PIO
EXPANSION
CONNECTOR
Sheet 7
A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
USAGE
CANTX0
CANRX0
NANDRDY
AD1
MDINTR
NCS0
NCS1
URXD
UTXD
RXD0
TXD0
USER_LED3
POWER_LED
TK
TF
TD
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB0
PB1
USAGE
TWD0
TWCK0
MCCK
MCCDA
MCDA0
MCDA1
MCDA2
MCDA3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
NRD
BUSY_TSC
IRQ_TSC
EREFCK
ETXEN
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
RF
RD
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PC0
PC1
PC2
PC3
USAGE
RK
CANTX0RS
CANRX0EN
PCK0
BP4_RIGHT
NCS2
RTS0
CTS0
BL_EN
TCK
TDI
TDO
TMS
ERASE
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
D0
D1
USAGE
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
NWE
NANDOE
NANDWE
PIO MUXING
USAGE
NBS0
A1
A2
A3
A4
A5
A6
A7
A8
A9
MCDA4
MCDA5
MCDA6
MCDA7
A14
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PD0
PD1
PD2
PD3
PD4
PD5
PD6
BA0
B
Sheet 8
Sheet 3
USAGE
ETX0
ETX1
ECRSDV
ERX0
ERX1
ERXER
EMDC
EMDIO
UOTGVBOF
UOTGID
USER_LED2
USER_LED1
CANTX1
CANRX1
RS232
Sheet 6
2.8"
240x320
TFT
RJ12
LCD INTERFACE
MMC SD
SDIO
PIO
RS485
ICE
INTERFACE
Sheet 4
HE 10
USB
HOST
DEVICE
HE 10
EBI NANDFLASH INTERFACE
POT
D
1
SDRAM
256Mbit
4
5
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
USAGE
BA1
NANDALE
NANDCLE
NBS1
SDA10
SDCS
SDCKE
SDWE
RAS
CAS
OSC_OE
A10
A11
USAGE
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
A13
USB_FAULT
MCI_CD
BP5_LEFT
ZB_RSTN
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
USAGE
ZB_SLPTR
ZB_IRQ0
ZB_IRQ1
COM0_EN
CANTX1RS
CANRX1EN
QTVALID_SNS
QTVALID_SNSK
QTUP_SNS
QTUP_SNSK
QTDOWN_SNS
QTDOWN_SNSK
QTLEFT_SNS
QTLEFT_SNSK
QTRIGHT_SNS
USAGE
QTRIGHT_SNSK
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
QTSLIDR_SL_SNS
QTSLIDR_SL_SNSK
QTSLIDR_SM_SNS
QTSLIDR_SM_SNSK
QTSLIDR_SR_SNS
QTSLIDR_SR_SNSK
PE27
PE28
PE29
PE30
PE31
PF0
PF1
PF2
PF3
PF4
PF5
NOTE
"DNP" means the component is not populated by default
A
SAM3X-EK
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
TOP LEVEL
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
1
8
4
5
J1
MP179P 2.1mm
1
2
1
MN1
ZEN056V130A24LS
3
+3V3
MN2
BNX002-01
1
2
2
3
C1
100nF
SV
2
3
L1
10uH/150mA
+5V
JP1-4
7
3
CV
4
5
6
SG CG1
CG2
CG3
1
8
VDDUTMI [3]
R1
+ C2
22uF
C4
1R
C3
100nF
D1
BAT54C
100nF
C5
4.7uF
1
JP2
[3]
3
VDDBU
2
D
L2
10uH/150mA
2
1
SD
1
R5
100K
GND1
PWR_CN
C8
100nF
5
ADJ
+ C10
100uF
3
SHDN
C7
1R
100nF
C11
100nF
C6
100nF
VDDANA [3]
JP1-1
1
2
VDDIO [3]
C12
4.7uF
R6
102K 1%
Q2
IRLML2502
1
R7
10K
[3]
12
R2
C9
4.7uF
R3
169K 1%
6
3
Q1
IRLML6401
3
2
R4
100K
+3V3
4
VOUT
GND2
VIN
+5V
D
JP1-6
11
MN3
MIC29152WU
Micrel's 1.5A LDO, TO263-5
+5V
BT1
CR12_16_20_25
+3V3
JP3
JP1-5
9
C13
15pF
2
10
VDDIN [3]
C14
4.7uF
Vout=(Rup/Rdown+1)*1.24
C
C
+3V3
D2
D3
D4
D5
Blue
Amber
green
red
R12
R13
1K
1K
JP1-2
R11
470R
3
VDDOUT
R14
100K
Potentiometer
4
VDDCORE [3]
+3V3
C15
4.7uF
L3
10uH/150mA
JP1-3
5
3
1
R10
470R
[3]
6
VDDPLL [3]
POWER_LED#
1
PA13 [3,8]
B
AD1
2
R35
0R
PA3
5
R15
DNP
JP
C19
4.7uF
2
USR_LED1#
C17
100nF
1R
C18
100nF
VR1
10K
3
Q3
IRLML2502
JP4
4
R16
[3,8]
C20
10nF
PB13 [3,8]
USR_LED2#
PB12 [3,8]
USR_LED3#
PA12 [3,8]
+3V3
R8
R17
10K
100K
B
MN4
8
+5V
BP1
1
2
NRST
3
4
NRSTB
NRST [3,5,7]
C22
BP2
1
2
7
10nF
3
4
6
C21
100nF
5
VDDBU [3]
OUT2
EN
IN
FLG
OUT1
GND
NC1
NC2
1
(UOTGVBOF)
2
USB_FAULT
PE5 [3,8]
3
R18
100K
4
WAKE UP
R23
3
4
100K
VDDBU [3]
[3,8]
[3,8]
[3,8]
BN03K314S300R
RV1
FWUP [3]
1
2
3
4
J3
3
4
PE7
R22
100K
J2
1
3
5
7
9
11
13
15
17
19
R24
[3,8]
0R
C24
100nF
VTref
Vsupply
nTRST
GND1
TDI
GND2
TMS
GND3
TCK
GND4
RTCK
GND5
TDO
GND6
nSRST
GND7
DBGRQ GND8
DBGACK GND9
VBUS
DM
DP
ID
GND
1
2
3
4
5
(UOTGID)
DHSDM [3]
DHSDP [3]
PB11 [3,8]
6
A
ADHESIVE FEET
Z1
Z2
Z3
11.1
11.1
11.1
TP1
GND
TP2
GND
TP3
GND
TP4
GND
B
A
INIT EDIT
REV
MODIF.
USB Micro AB
USB
BUTTONS
Z4
Z5
Z6
11.1
11.1
11.1
SAM3X-EK
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
POWER SUPPLY & USB & JTAG
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
2
4
6
8
10
12
14
16
18
20
ICE INTERFACE
SHD
1
2
LEFT CLICK
R20
100K
PB29
PB31
PB28
7
PB23 [3,8]
BP5
A
R21
100K
[3,8]
PB30
[3,5,7] NRST
VBUS [3]
+ C23
33uF
V5.5MLA0603
BP4
RIGHT CLICK
R19
100K
SP2525-2
NRSTB [3]
B1
BP3
1
2
+3V3
PB10 [3,8]
3
2
1
VER.
DATE
REV.
SHEET
A
2
9
4
5
[2,5,6,7,8]
PA[0..31] [2,4,5,6,7,8]
MN5A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
D
C
J1
J3
N16
P17
P16
K3
R17
K2
K1
B2
B1
C2
C1
D3
D2
D1
U16
E4
R14
M14
R15
C16
R16
T17
U17
B17
A17
B16
A16
C15
T10
T8
PB[0..31]
ATSAM3X_LFBGA217
MN5C
B15
A15
D14
A14
C13
D13
B13
A13
C12
B9
A9
C9
N17
M16
B4
T15
T16
M17
L16
L17
K17
K16
C4
A3
B3
C3
A1
N15
K4
L1
L3
N4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
[4,6,7,8] PD[0..30]
PC[0..30] [4,5,8]
MN5B
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
2
3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
C8
R7
T7
R8
C14
N14
P14
R13
T13
U13
B14
M15
L14
L15
K15
K14
J14
J17
J16
J15
C7
A6
D7
B6
C6
A5
B5
C5
A4
H17
H16
ATSAM3X_LFBGA217
PE[0..31] [2,5,6,7,8]
E3
E2
E1
F4
F3
F2
F1
G4
H2
J2
P4
P9
R9
T9
U9
U10
R10
R11
T11
U11
P12
P13
R12
T12
U12
H15
G17
G16
G15
F17
F16
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
ATSAM3X_LFBGA217
[5]
MN5E
MN5D
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
1
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
E17
F14
E16
E15
D17
D16
E14
D15
C17
A12
C11
B11
A11
C10
B10
A10
B8
A8
A7
B7
D8
D4
D5
D6
A2
B12
G3
G2
G1
H3
H1
F15
PF[0..5]
MN5F
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
PF0
PF1
PF2
PF3
PF4
PF5
D12
L2
M1
M2
M3
M4
PF0
PF1
PF2
PF3
PF4
PF5
D
ATSAM3X_LFBGA217
C
ATSAM3X_LFBGA217
ATSAM3X_LFBGA217
MN5G
ATSAM3X_LFBGA217
DHSDP
DHSDM
[2]
VBUS
T1
T2
U3
1
U4
VBG
P1
2
B
3
4
1
C33
C36
2
Y1
12MHz
U5
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
XIN
4
XIN32
VDDPLL
XOUT32
VDDBU
[2] SHDN
T5
JTAGSEL
FWUP
SHDN
P3
R3
P5
P6
N3
R4
C48
10pF
SDCK
GNDBU
T6
D10
G14
J4
L4
P10
R1
C25
D9
H4
H9
H14
P11
C34
C27
C29
100nF
C26
100nF
C28
100nF
C30
C39
100nF
C35
100nF
C38
100nF
C43
100nF
C45
100nF
C37
VDDOUT [2]
VDDCORE [2]
100nF
100nF
100nF
VDDIO [2]
B
100nF
100nF
N1
C41
VDDPLL [2]
100nF
T3
VDDUTMI [2]
P8
+3V3
VDDBU [2]
T14
VDDANA [2]
+3V3
+5V
R27
4.7K
JP7
2
U15
T4
JTAGSEL
+3V
C47
100nF
TST
GNDANA
[2] FWUP
VDDIN [2]
D11
SDCK [4]
D6
C16
2.2uF
LM4040-3.0
C49
100nF
P7
VBG
[8]
NC1
NC2
NC3
NC4
NC5
NC6
PC0
NRSTB
GNDUTMI
R6
U14
R5
[2] NRSTB
ADVREF
GNDPLL
TST
NRST
R2
P15
U8
U7
XOUT
VDDTUMI
U6
TST
(ERASE)
R28
6.8K 1%
VBG
JTAGSEL
DNP
VDDIO
VBUS
VDDANA
JP6
[2]
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
20pF
20pF
[2,5,7] NRST
R140
DHSDP
DHSDM
N2
DNP
VDDOUT
GND
GND
GND
GND
GND
GND
GND
GND
R139
VDDIN
H8
H10
J8
J9
J10
K8
K9
K10
VDDBU
DFSDP
DFSDM
10pF
10pF
P2
C40
C42
3
Y2
32.768KHz
[2]
U1
U2
1
[2]
[2]
39R
39R
3
R25
R26
A
0R
A
R29
SUP1
SAM3X-EK
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
ATSAM3X_LFBGA217
SG-BGA-6004
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
3
8
4
5
2
3
[3,5,8] PC[0..30]
1
[3,5,8] PC[0..30]
+3V3
MN7
C
PD14
(SDWE)
16
19
28
41
54
6
12
46
52
16
17
8
18
9
JP8
(NANDRDY)R32
7
0R
R33
19
470K
100nF
17
18
D
DNP
100nF
CAS
RAS
470K
C58
15
39
R31
1K
R34
100nF
PD16
PD15
(NBS0)
(NBS1)
+3V3
1
14
27
3
9
43
49
C57
38
SDCK
[3,8] PC21
(NANDCLE)
(NANDALE)
(NANDOE)
(NANDWE)
(NCS0)
+3V3
100nF
[3]
PD9
PD8
PC19
PC20
PA6
[3,8] PA2
C56
(SDCKE) 37
PD13
PD10
36
40
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
100nF
(A14)
R30
MN8
C55
PD4
20
21
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
100nF
(BA0)
(BA1)
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
C54
PD6
PD7
A0 MT48LC16M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
DQ10
A10
A11
DQ11
DQ12
BA0
DQ13
DQ14
BA1
DQ15
A12
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
100nF
PD22
PD23
PD11
PD25
23
24
25
26
29
30
31
32
33
34
22
35
C53
[3,6,7,8] PD[0..30]
(A2)
(A3)
(A4)
(A5)
(A6)
(A7)
(A8)
(A9)
(A10)
(A11)
(SDA10)
(A13)
C52
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
D
JP9
[3,8] PD12
1
2
3
4
5
6
10
11
14
15
20
23
24
35
21
22
38
CLE
ALE
RE
WE
CE
R/B
WP
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
VCC
VCC
VCC_N.C
VCC_N.C
VSS
VSS
VSS_N.C
VSS_N.C
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
+3V3
Optional 16bits DATA BUS
With MT29F2G16AAD Micron
12
37
34
39
C50
100nF
C51
100nF
13
36
25
48
C
MT29F2G08AAD
(SDCS)
256 Mbits SDRAM
8-bits NAND Flash is mounted by default
B
B
A
A
SAM3X-EK
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
EBI_MEMORY
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
4
8
4
5
2
3
1
+3V3
R36
100K
J4
FH26-39S-0.3SHW
[3,4,8] PC[0..30]
JP10
D
[3,8]
PC22
PC18
PB24
[3,8]
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
A1
NWE
NRD
PA29
[2,3,7] NRST
LED_A1
LED_A2
LED_A3
LED_A4
C67
100nF
R44
R45
R46
R47
0R
0R
0R
0R
[3]
PE21
[3]
PE20
[3]
PE27
[3]
PE26
[3]
PE25
R38
1K
C60
22nF
R40
K1
DNP
1K
C62
22nF
2.8" 320x240
TFT LCD DISPLAY
R42
1K
C64
22nF
PIN 39
+ C66
10uF
D
PINs
on
BOT
+3V3
C
GND1
CS
RS
WR
RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
NC1
NC2
RESET
GND2
X+
Y+
XYGND3
VDD1
VDD2
A1
A2
A3
A4
NC3
NC4
K
PIN 1
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
1
(NCS2) 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
[3]
PE24
[3]
PE19
R43
1K
C65
22nF
[3]
PE18
[3]
PE23
C
FTM280C12D
R48
1K
C68
22nF
[3]
QST Keys
PE22
+3V3
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
MN10
AAT3194ITP
4
R56
47K
3
4
5
1
The part is placed as
close as possible to J4
2
B
[3,8]
+3V3
C1EN/SET
C2-
10
B2
BN03K314S300R
S1
DNP
1
C73
1uF
3
9
PB27
NOT POPULATED
C2+
C72
1uF
R60
0R
D7
DNP
TVS, SOT23-5
C1+
OUT
IN
C75
4.7uF
11
GND
D1
D2
D3
D4
SR
12
[3]
2
8
7
6
5
LED_A1
LED_A2
LED_A3
LED_A4
PF1
R37
1K
B
C59
22nF
C76
1uF
[3]
PF0
[3]
PF3
R39
SL
1K
SM
C61
22nF
+3V3
R49
100K
MN9
ADS7843E
2
3
4
5
X_RIGHT
Y_UP
X_LEFT
Y_DOWN
TP5
SMD
XP
YP
XM
YM
TP6
SMD
DCLK
DIN
DOUT
CS
BUSY
PENIRQ
7
8
IN3
IN4
VREF
VCC1
VCC2
16
14
12
15
R51
0R
R52
0R
9
1
10
R54
R57
100K
AGND_TP
R58
100K
GND
6
LCD TOUCH SCREEN
(SPI0_SPCK)
(SPI0_MOSI)
(SPI0_MISO)
(SPI0_NPCS0)
BUSY_TSC
0R IRQ_TSC
+3V3
R53
C69
100nF
PF2
SR
R50
100K
13
11
A
[3]
+3V3
PA27
PA26
PA25
PA28
[3]
PF5
[3]
PF4
R41
1K
C63
22nF
[3,8]
[3,8]
[3,8]
[3,8]
PA30 [3,8]
PA31 [3,8]
QT Slider
0R
C70
100nF
C71
100nF
R55
1R
L4
10uH/150mA
C74
4.7uF
A
R59
0R
AGND_TP
SAM3X-EK
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
DISPLAY & QTouch
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
5
8
4
5
MN11
XWM8731EDS
+3V3
1
27
AVDD
HPVDD
DGND
AGND
HPGND
C79
100nF
26
2
D
16
+ C84
10uF
C85
100nF
C81
100nF
C80
100nF
28
12
13
+ C82
10uF
15
11
XTO
CLKOUT
AGND_AUDIO
VMID
LHPOUT
LOUT
ROUT
RHPOUT
9
C83
10
C86
+
C78
100nF
220uF
220uF
J5
PHONEJACK
B3
BN03K314S600R
R61
47K
B4
BN03K314S600R
R62
47K
D
1
2
3
4
5
C87
470pF
+3V3
+ C89
10uF
+3V3
AGND_AUDIO
R63
100K
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
[3,8]
PA17
PA18
PB22
PA14
PB19
PA16
PA15
PB18
PB17
(TWD0)
(TWCK0)
(PCK0)
(TK)
R71
(RF)
R72
(TD)
(TF)
(RD)
R73
(RF)
R74
R64
4.7K
R66
4.7K
LLINEIN
22
23
24
0R
0R
25
3
4
5
6
7
10K
21
0R
0R
R76
C
RLINEIN
CSB
SDIN
SCLK
20
R67
100K
19
R68
100K
L5
10uH/150mA
+3V3
AVDD
HEADPHONE
LINE-OUT
C88
470pF
AGND_AUDIO
+3V3
1
AVDD
14
8
+
+ C77
10uF
DBVDD
DCVDD
2
3
C90
100nF
AGND_AUDIO
+ C91
47uF
R65
0R
AGND_AUDIO
AGND_AUDIO
XTI/MCLK
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
MICBIAS
MODE
MICIN
17
R75
680R
18
R77
330R
C98
J7
PHONEJACK
B7
BN03K314S600R
1uF
R78
C99
220pF
0R
R79
47K
5
4
3
2
1
C
MONO MICRO INPUT
AGND_AUDIO
AGND_AUDIO
+3V3
R82
10K
RR1
47KX4
B
[3,8]
PA23
[3,8]
[3,8]
PA24
PD0
[3,8]
[3,8]
PA20
PD1
R83
RR2
47KX4
10K
J8
7SDMM-B0-2211-A
5
6
7
8
R81
10K
5
6
7
8
R80
10K
4
3
2
1
4
3
2
1
+3V3
(MCDA2)
1
(MCDA3)
(MCDA4)
2
3
(MCCDA)
(MCDA5)
4
5
6
7
[3,8]
[3,8]
PA19
PD2
[3,8]
[3,8]
PE6
PD3
[3,8]
[3,8]
PA21
PA22
(MCCK)
(MCDA6)
8
9
(MCI_CD)
(MCDA7)
10
11
(MCDA0)
(MCDA1)
12
13
14
MN12
+3V3
DAT2
C100
100nF
RSV/DAT3
DAT4
CMD
DAT5
GND
VCC
CLK
DAT6
6
5
(TWCK0)
(TWD0)
[3,8] PA18
[3,8] PA17
GROUND1
SHELLED1
SHELLED2
GROUND
15
8
4
SCL
SDA
A0
A1
A3
1
2
3
B
JP11
VCC
GND
WP
7
AT24C512BN
SERIAL EEPROM
17
18
16
CD
DAT7
DAT0
DAT1
SD_WP
+3V3
A
+ C101
10uF
A
C102
100nF
SAM3X-EK
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
Audio & HSMCI & TWI
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
6
8
4
5
Y3
1 OE
1
+3V3
R84
10K
[3,8] PD17
2
3
C103
100nF
VDD 4
50MHz
2 VSS
OUT 3 R85
0R
C92
DNP
D
D
C104
R86
0R
[3,8] PB4
[3,8] PB7
(ERX1)
(ERX0)
26
27
28
29
(ECRSDV)
34
37
(ERXER)
16
38
+3V3
(EMDC)
(EMDIO)
(MDINTR)
[3,8] PB8
[3,8] PB9
[3,8] PA5
R93
4
3
[2,3,5] NRST
VCC
MR
RESET
GND
R87
41
C113
100nF
30
8
7
6
5
C114
100nF
RX-
0R
2
8
3
AVDDR
AVDDR
B8
1
C106
100nF
2
C107
100nF
AVDDT
AGND
AGND
AGND
DVDD
BGRESG
9
PWRDWN
40
R91
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
RESET
N.C
R92
10
9
TX-
2
3 RD+
RX+
3
RX-
6
C105
100nF
75
75
7 NC
49.9R 1%
+ C109
10uF
100nF
75
4
C
5
1nF
GND_ETH
8
C111
100nF
75
7
8
+3V3
GND_ETH
47
R94
R95
6.8K
DVDD
10
AVDDT
C110
+ C108
10uF
5
6
46
DVDD
DGND
DGND
DGND
2 TD-
AVDDT
49.9R 1%
DM9161AEP
DISMDIX
23
1
6 RD-
4
BLM21BD222TN1
COL/RMII
CRS/PHYAD4
15
33
44
RR5
10KX4
R98
0R
R70
GND_ETH
RJ45 ETHERNET CONNECTOR
RR6
+3V3
10K
48
31
11
12
13
14
10KX4
D8
Amber R96
470R
FULL DUPLEX
D9
green R97
1K
SPEED 100
D10
green R99
1K
LINK&ACT
45
1
R90
100K
CAT811
B
1
2
3
4
8
7
6
5
RR4
10KX4
+3V3
MN19
+3V3
1
2
3
4
8
7
6
5
1
2
3
4
RR3
10KX4
100nF
TX+
5 CT
+3V3
C112
1 TD+
TX_ER/TXD4
RX_ER/RXD4/RPTR
MDC
MDIO
MDINTR
49.9R 1%
7
AVDDT
RX+
RX_CLK/10BTSER
RX_DV/TESTMODE
24
25
32
R89
4 CT
TX-
39
Install as need to alter PHY
address, must override internal
pullup on SAM3
R88
J9
TX+
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
1.5K
JP12
43
49.9R 1%
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
36
35
C
XT1
8
7
6
5
TP7
SMD
[3,8] PB6
[3,8] PB5
REF_CLK/XT2
17
18
19
20
21
22
(ETX1)
(ETX0)
(ETXEN)
[3,8] PB3
[3,8] PB2
[3,8] PB1
GND_ETH
MN13
42
1
2
3
4
(EREFCK)
[3,8] PB0
100nF
B
DNP
+3V3
+ C115
10uF
R100
0R
R101
0R
R116
DNP
GND_EARTH
GND_ETH
ETHERNET
J10
[3,8] PE9
[3,8] PE12
[3,8] PE31
[3,8] PE28
A
ZB_RSTN
R102
ZB_IRQ1
R104
(SPI1_NPCS0)
(SPI1_MISO)
0R
0R
1
3
5
7
9
2
4
6
8
10
R103
R105
0R
0R
C116
18pF
ZB_IRQ0
ZB_SLPTR
(SPI1_MOSI)
(SPI1_SPCK)
C117
2.2nF
PE11 [3,8]
PE10 [3,8]
PE29 [3,8]
PE30 [3,8]
JP13
A
+3V3
C118
2.2uF
SAM3X-EK
ZIGBEE
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
ETHERNET & ZIGBEE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
VER.
DATE
REV.
SHEET
A
7
8
4
5
2
3
MN14
MAX3232CSE
1
+3V3
+3V3
+3V3
16
C119
100nF
+3V3
D
R111
100K
[3]
[3]
+3V3
C121
100nF
V+
C1-
V-
C2+
11
12
10
9
GND
4
J11
1
6
2
7
3
8
4
9
5
T1IN
R1OUT
T2IN
R2OUT
5
C2-
14
13
7
8
T1OUT
R1IN
T2OUT
R2IN
R108
DNP
MN15
ADM3485ARZ
C123
100nF
15
R107
47K
3
C124
100nF
R112
100K
R106
47K
C120
100nF
2
6
(UTXD)
(URXD)
PA9
PA8
1
C1+
VCC
[3]
PA10
[3]
PB26
[3]
PB25
[3]
PA11
(RXD0)
R109
0R
1
(CTS0)
R110
0R
2
(RTS0)
R113
0R
3
(TXD0)
R114
0R
4
RO
VCC
RE
GND
+3V3
8
JP14
C122
100nF
5
DI
A
B
3
R115
47K
23
19
(COM0_EN) R119
0R
5
(TXD0)
(RXD0)
(RTS0)
(CTS0)
0R
0R
0R
0R
7
10
8
11
9
12
R120
R121
R122
R123
11
10
C129
100nF
4
24
C2C3+
T1IN
R1OUT
T2IN
R2OUT
T3IN
R3OUT
22
C3-
18
15
17
14
16
13
R124
0R
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
RS232 COM
+3V3
+3V3
PB20
[3]
PA0
[3]
PB21
(CANTX0RS) R126
JP22
B
2
CANH 7
[3]
(CANTX0)
R127
3
1 D
0R
CANL 6
(CANRX0EN) R129
0R
5 EN
(CANRX0)
0R
4 R
R128
120R
4
5
PA1
R130
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
6
+3V3
R131
2 GND
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
C133
100nF
[2,3,5,6,7]
3
(CANTX1RS) R134
0R
(CANTX1)
0R
1 D
1
JP23
2
[3]
[3]
3
CANL 6
(CANRX1EN) R136
PE16
R135
120R
5 EN
0R
4
5
(CANRX1)
PB15
R137
4 R
0R
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
+3V3
+3V3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
6
+3V3
R138
2 GND
PE[0..31]
1
+3V3
3
JP21
+5V
1
5
J19
6
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
1
2
3
CAN RJ12
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J18
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
+3V3
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE16
PE17
PE28
PE29
PE30
PE31
+3V3
A
5
PIO EXPANSION
6
SN65HVD234
C135
100nF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
4
VCC 3
+ C134
10uF
+3V3
3
4
10K
SAM3X-EK
CAN1
B
A
INIT EDIT
REV
MODIF.
SCALE
WL
WL
DES.
2010-08-16
2010-03-12 XXX XX-XXX-XX
DATE
1/1
SERIAL & USER INTERFACES
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
+3V3
B
JP20
+5V
CAN RJ12
J20
MN18
8 Rs
CANH 7
A
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
CAN0
R132
10K
R133
+3V3
+3V3
3
[3,4,6,7] PD[0..30]
+3V3
PB14
1
1
VCC 3
+ C132
10uF
[3]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
+3V3
SN65HVD234
PE15
JP19
+5V
J16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10K
[3]
+3V3
3
J17
1
MN17
8 Rs
0R
1
2
R125
10K
[3]
JP18
+5V
J15
J13
1
6
2
7
3
8
4
9
5
C131
100nF
T1OUT
R1IN
T2OUT
R2IN
T3OUT
R3IN
+3V3
3
2
1
SD
EN
JP17
+5V
10
PA11
PA10
PB25
PB26
C1C2+
V-
GND
PA[0..31]
20
2
2
4
3
2
1
PE14
V+
C130
100nF
5
6
7
8
[3]
[3]
[3]
[3]
[3]
[2,3,4,5,6,7]
C128
100nF
21
+3V3
RR7
47KX4
C1+
C127
100nF
1
C
VCC
R118
DNP
PB[0..31]
2
C126
100nF
[2,3,5,6,7]
6
11
C125
4.7uF
JP16
2
3
JP15
R117
120R
[3,4,5] PC[0..30]
MN16
ADM3312EARU
+3V3
D
2
6
7
RS 485
UART
J12
1
DE
4
3
2
1
VER.
DATE
REV.
SHEET
A
8
8
Section 6
Troubleshooting
6.1
Self-Test
A test package software is available to implement a functional test for each section of the board. Refer to
the SAM3X-EK page on www.atmel.com.
6.2
Board Recovery
The SAM3X-EK is delivered with an on-board recovery procedure allowing to reprogram the board as it
was when shipped. This procedure is accessible from the Flash disk mounted on a PC when the board is
connected to this PC through the USB as described in Section 3.
SAM3X-EK User Guide
6-1
11156A–ATARM–25-May-12
Section 7
Revision History
7.1
Revision History
Table 7-1.
Document
Comments
11156A
First issue.
SAM3X-EK User Guide
Change Request
Ref.
7-1
11156A–ATARM–25-May-12
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11156A–ATARM–25-May-12
/xM