View detail for ATF697FF Evaluation Board User Guide

ATMEL ATF697FF
ATF697FF Configurable Processor evaluation board B
USER GUIDE [DRAFT]
Overview
This document describes the evaluation board B dedicated to ATMEL ATF697FF
configurable processor.
The ATF697FF is a multi-chip module made of an ATMEL AT697F die together with an
ATMEL ATF280F die. This allows extension of the 32-bit SPARC® V8 processor
functionalities by adding a user dedicated area made of a 280 Kgate FPGA.
The board is designed to allow an easy evaluation of the product using demonstration
software. It also provides all the features for extensive testing and application
development over the complete device by providing access to all the processor and the
reconfigurable unit signals.
Features
•
On-board power supply circuitry
• External power supply sources connection
• Board powering by the PCI interface
• Compact-PCI connection for self powering in a standard C-PCI rack
•
•
On-board reset circuitry
ATF697FF module sample
• AT697F processor die + ATF280F FPGA die in a single chip
• Socket for mounting/dismounting the ATF697FF without damage risk
•
On board memories
• AT697F application memories : SDRAM, SRAM and parallel EEPROM
• Reconfiguarble unit configuration memory : Serial EEPROM
•
•
Configurable clocks
User interface
•
•
•
•
•
2 green LEDs controlled by the ATF697FF processor
2 switch buttons controlled by the ATF697FF processor
8 red LEDs controlled by the ATF697FF reconfigurable unit
8 switch buttons controlled by the ATF697FF reconfigurable unit
Communication Interface
• 1 RS-232 serial interface
• 2 Space wire ports
•
Test Facilities
• 1 Debug port (DSU) for ATF697FF LEON2 SPARC processor debugging
• 1 HE10 connector for serial EEPROM configuration
• 2x50 pin expansion connectors on the reconfigurable unit I/Os for future
prototype boards
• 10 pin JTAG connector
TWDS101711−TEMPLATE−10/11
Figure 1: ATF697FF evaluation board B
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Table of Contents
1. Hardware Description ...................................................................................... 4
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
Block Diagram .................................................................................................... 4
Processor Module ............................................................................................... 4
1.2.1 Processor Module Package ..................................................................... 4
1.2.2 ATF697FF Module Pin-out....................................................................... 5
Memories .......................................................................................................... 11
1.3.1 PROM Memories.................................................................................... 11
1.3.2 RAM Memories ...................................................................................... 15
Power Supply.................................................................................................... 17
1.4.1 Power Inputs .......................................................................................... 18
1.4.2 Voltage test points.................................................................................. 20
1.4.3 Current probe ......................................................................................... 20
1.4.4 Decoupling Capacitance ........................................................................ 22
Clock ............................................................................................................. 23
1.5.2 Clock configuration................................................................................. 25
Reset ............................................................................................................. 27
Serial Link ......................................................................................................... 29
1.7.2 Disabling Serial Link Flow Control.......................................................... 29
SpaceWire Interface ......................................................................................... 31
PCI interface ..................................................................................................... 32
LEDs ............................................................................................................. 33
1.10.1 Status LEDs ........................................................................................... 33
1.10.2 General Purpose LEDs .......................................................................... 34
Pushbuttons/Switches....................................................................................... 35
1.11.1 Configuration Switches .......................................................................... 35
1.11.2 General Purpose switches/pushbuttons................................................. 36
Debug Support Unit .......................................................................................... 38
Space Programmer Interface............................................................................ 39
JTAG Interface.................................................................................................. 40
Probes / Test Points.......................................................................................... 41
1.15.1 Probes / test points description .............................................................. 41
1.15.2 Probes / test points localization.............................................................. 42
Expansion Connectors...................................................................................... 47
Board default strap configuration ...................................................................... 51
2. Ordering Information...................................................................................... 53
Appendix A. Expansion ....................................................................................... 54
A.1
A.2
Connector Specification .................................................................................... 54
Mechanical Constraints..................................................................................... 54
Appendix B. CDCE configuration........................................................................ 56
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1.
Hardware Description
1.1
Block Diagram
The following figure gives an overview of the ATF697FF evaluation board B.
Figure 2: ATF697FF evaluation board B
1.2
1.2.1
Processor Module
Processor Module Package
The ATF697FF package is the MQFPT-352 space qualified package.
Figure 3: ATF697FF component
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The evaluation board B is provided with the ATF697FF module mounted on its socket . This makes it easy to mount/un-mount
the device without risking damaging it.
1.2.2
ATF697FF Module Pin-out
Table 1-1.
ATF280FF pin mapping
Pin Number
Pin Name
Pin Number
Pin Name
1
IO482_FPGA_GCK5
186
CB[7]
2
IO487
187
D[0]
3
IO493
188
D[1]
4
IO497
189
D[2]
5
IO503
190
D[3]
6
IO505
191
D[4]
7
IO507
192
D[5]
8
IO511
193
VDD18
9
IO513
194
VSS
10
IO517
195
D[6]
11
IO519
196
D[7]
12
IO523
197
D[8]
13
IO525
198
D[9]
14
IO527
199
D[10]
15
IO531
200
D[11]
16
IO533
201
D[12]
17
FPGA_VCC18
202
D[13]
18
VSS
203
D[14]
19
IO537
204
D[15]
20
IO539
205
D[16]
21
IO543_FPGA_FCK3
206
D[17]
22
IO545
207
D[18]
23
IO547_FPGA_CS0*
208
D[19]
24
IO551
209
VDD18
25
IO553
210
VSS
26
IO557
211
D[20]
27
IO559
212
D[21]
28
IO563
213
D[22]
29
IO565
214
D[23]
30
IO567
215
D[24]
31
IO571
216
D[25]
32
IO573
217
D[26]
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Pin Number
Pin Name
Pin Number
Pin Name
33
FPGA_VCC33
218
D[27]
34
VSS
219
D[28]
35
IO577
220
D[29]
36
FPGA_VCC18
221
D[30]
37
IO579
222
D[31]
38
IO583
223
SDCAS
39
IO585
224
SDCLK
40
IO591
225
VCC33
41
IO593_FPGA_ILVDSB1
226
VSS
42
IO594_FPGA_ILVDSNB1
227
SDCS[0]
43
IO597_FPGA_ILVDSB2
228
SDCS[1]
44
IO598_FPGA_ILVDSNB2
229
SDDQM[0]
45
FPGA_LVDS_REF_B
230
SDDQM[1]
46
IO599_FPGA_OLVDSB1
231
SDDQM[2]
47
IO600_FPGA_OLVDSNB1
232
SDDQM[3]
48
IO599_FPGA_OLVDSB2
233
SDRAS
49
IO600_FPGA_OLVDSNB2
234
SDWE
50
VSS
235
A[0]
51
IO605
236
A[1]
52
IO607
237
A[2]
53
IO611
238
A[3]
54
IO613
239
A[4]
55
IO617
240
A[5]
56
IO619
241
PROC_VDD18
57
IO623
242
VSS
58
IO625
243
A[6]
59
IO627
244
A[7]
60
IO633
245
A[8]
61
IO637
246
A[9]
62
IO639
247
A[10]
63
IO643
248
A[11]
64
IO645
249
A[12]
65
FPGA_VCC33
250
A[13]
66
VSS
251
A[14]
67
IO647
252
A[15]
68
IO651
253
A[16]
69
IO653
254
A[17]
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Pin Number
Pin Name
Pin Number
Pin Name
70
IO655_FPGA_CHECK*
255
A[18]
71
IO658_FPGA_FCK4
256
A[19]
72
IO661
257
VDD18
73
IO665
258
VSS
74
IO667
259
A[20]
75
IO673
260
A[21]
76
IO679
261
A[22]
77
IO685
262
A[23]
78
IO671
263
A[24]
79
IO677
264
A[25]
80
IO683
265
A[26]
81
FPGA_VCC18
266
A[27]
82
VSS
267
GPIO[0]
83
IO687
268
GPIO[1]
84
IO693
269
GPIO[2]
85
IO691
270
GPIO[3]
86
IO697
271
GPIO[4]
87
IO699
272
GPIO[5]
88
IO703
273
FPGA_VCC18
89
IO705
274
VSS
90
IO707
275
GPIO[6]
91
IO711
276
GPIO[7]
92
IO713_FPGA_D0
277
GPIO[8]
93
IO717
278
GPIO[9]
94
TCK
279
GPIO[10]
95
IO720_FPGA_GCK6_FPGA_CSOUT
280
GPIO[11]
96
IO722_FPGA_GCK7
281
GPIO[12]
97
FPGA_VCC18
282
GPIO[13]
98
VSS
283
GPIO[14]
99
IO725
284
GPIO [15]
100
FPGA_CCLK
285
VDD_PLL
101
IO727
286
VSS_PLL
102
IO731
287
IO225_FPGA_OTS
103
IO733
288
IO240_FPGA_GCK2
104
IO737
289
VCC33
105
IO739
290
VSS
106
IO743
291
IO241_FPGA_GCK3
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Pin Number
Pin Name
Pin Number
Pin Name
107
IO745
292
IO259_FPGA_LDC
108
IO747
293
IO265_FPGA_HDC
109
IO751
294
IO303_FPGA_INIT
110
IO753
295
IO353_FPGA_ILVDSA1
111
IO757
296
IO354_FPGA_ILVDSNA1
112
IO759
297
IO357_FPGA_ILVDSA2
113
FPGA_VCC33
298
IO358_FPGA_ILVDSNA2
114
VSS
299
FPGA_LVDS_REF_A
115
IO763
300
IO359_FPGA_OLVDSA1
116
IO765
301
IO360_FPGA_OLVDSNA1
117
IO767
302
IO363_FPGA_OLVDSA2
118
IO771
303
IO364_FPGA_OLVDSNA2
119
IO773
304
IO365
120
IO777
305
FPGA_VCC18
121
IO779
306
VSS
122
IO783
307
IO367
123
IO785
308
IO371
124
IO787
309
IO373
125
IO791
310
IO377
126
IO793
311
IO379
127
IO1_FPGA_GCK1
312
IO383
128
IO960_FPGA_GCK8
313
IO385
129
FPGA_VCC18
314
IO387
130
VSS
315
IO397
131
TDI
316
IO393
132
TDO
317
IO399
133
TMS
318
IO403
134
TRST
319
IO405
135
BEXC
320
IO407
136
SKEW [0]
321
FPGA_VCC33
137
SKEW [1]
322
VSS
138
DSURX
323
IO411
139
DSUTX
324
IO413
140
DSUEN
325
IO417
141
DSUBRE
326
IO419
142
DSUACT
327
IO423
143
BYPASS
328
IO425
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Pin Number
Pin Name
Pin Number
Pin Name
144
CLK
329
IO427
145
VCC33
330
IO431
146
VSS
331
IO433
147
LOCK
332
IO437
148
PROC_RESET
333
IO439
149
ERROR
334
IO443
150
WDOG
335
IO445
151
FPGA_M1
336
IO447
152
FPGA_M0
337
FPGA_VCC18
153
FPGA_M2
338
VSS
154
WRITE
339
IO453
155
READ
340
IO457
156
ROMS[0]
341
IO459
157
ROMS[1]
342
IO463
158
BRDY
343
IO465
159
OE
344
IO467
160
IOS
345
IO471
161
FPGA_VCC18
346
IO473
162
VSS
347
IO477
163
RWE[0]
348
FPGA_CON
164
RWE[1]
349
IO480_FPGA_GCK4
165
RWE[2]
350
IO485
166
RWE[3]
351
IO491
167
RAMOE[0]
352
FPGA_RESET
168
RAMOE[1]
169
RAMOE[2]
170
RAMOE[3]
171
RAMOE[4]
172
RAMS[0]
173
RAMS[1]
174
RAMS[2]
175
RAMS[3]
176
RAMS[4]
177
FPGA_VCC18
178
VSS
179
CB[0]
180
CB[1]
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Pin Number
Pin Name
181
CB[2]
182
CB[3]
183
CB[4]
184
CB[5]
185
CB [6]
Pin Number
Pin Name
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1.3
Memories
The ATF697FF evaluation board B implements a full set of memories including serial and parallel PROM, SRAM and SDRAM.
Except for the SDRAM, all the other memories embedded on the board are fully representative of space qualified components.
In order to allow flexible ATF697FF peripheral management, all the memory interface control signals are shared between the
internal processor and the reconfigurable unit. One exception is the SDRAM interface for which the SDCLK signal is the only
control signal shared.
The designer who implements the reconfigurable unit structure shall take special care of the usage done of the memory
interface control signals in order to prevent its design from any conflict with ATF697FF-processor memory interface.
!
1.3.1
PROM Memories
Two PROM facilities are provided on the evaluation board B:
•
•
512 Kbytes of parallel EEPROM,
4 Mbits of serial EEPROM.
1.3.1.1 Parallel EEPROM
The 512 Kbytes of EEPROM memory are made of four AT28LV010 devices.
The parallel EEPROM is primarily intended for use as a boot memory for the system when booting first from the processor.
Figure 4: Parallel EEPROM interface
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Parallel EEPROM activation
The evaluation board B provides a switch that allows user to enable/disable use of the parallel EEPROM.
Table 1-2.
EEPROM Selection
Parallel EEPROM
J701
Parallel EEPROM enabled
3-2
Parallel EEPROM disabled
1-2
•
When J701 is configured in the “enable” position, the ATF697FF processor can boot directly from the parallel
EEPROM.
•
When J701 is configured in the “disable” position, the ATF697FF processor has no possibility to boot directly from
an on-board memory. Such configuration is used to perform a processor boot from serial memory, thus through the
reconfigurable unit. In such configuration, the processor is seen as a slave during the boot-up sequence.
Whatever is the default hardware setting on the board, connection 2 of J701 is connected to the ATF697FF reconfigurable
unit IO605 (pin 49) making it possible to enable/disable the parallel eeprom by reconfigurable unit ‘s software.
1.3.1.2 Serial EEPROM
The reconfigurable unit embedded in the ATF697FF requires up to 4Mbits for its configuration.
EEPROM memory are built around two space qualified devices:
•
•
The 4 Mbits of serial
Four cascaded AT17LV010 devices (1Mbit / device)
One AT69170 device (4 Mbit device)
EEPROM Selection
Two kinds of serial EEPROMs can be used for booting the reconfigurable unit when configured in mode 0. The user can
choose to download its bit stream either from AT17 cascade or from the AT69170 device. The selection is performed thanks to
J1602 and J1603 switches.
Table 1-3.
FPGA Configuration - EEPROM Selection
Reconfigurable unit configuration
J1602
J1603
ATF697FF configuration from AT69170
1-2
1-2
ATF697FF configuration from AT17 cascade
3-4
3-4
ATF697FF configuration as a slave
5-6
5-6
It is also possible to configure the ATF697FF reconfigurable unit in slave serial mode (mode 1)
AT17 cascade
The 4 AT17LV010 cascade is built following the standard cascading scheme.
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1
2
3
4
Figure 5: AT17 cascade
Note:
In order to ensure that the reconfigurable unit configuration will succeed with the correct data download:
During the EEPROM programmation:
•
•
•
•
the AT17 (1) connected to CS1_AT17 and with the A2 line driven to ‘GND’ shall be addressed first,
then the AT17 (2) connected to CS1_AT17 and with the A2 line driven to ‘VDD’ shall be addressed,
then the AT17 (3) connected to CS2_AT17 and with the A2 line driven to ‘GND’ shall be addressed,
to finish the AT17 (4) connected to CS2_AT17 and with the A2 line driven to ‘VDD’ shall be addressed.
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Serial EEPROM interface to ATF697FF
The serial EEPROMs can be programmed either by the ATF697FF processor emulating the serial interface or through the
Space Programmer using the external programming connector (refer to “Space Programmer Interface” section for details on
the external programming interface).
Table 1-4.
AT69170 programming source selection
AT69170 programming source
J1604
Processor unit
OFF
Space programmer
ON
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1.3.2
RAM Memories
The ATF697FF memory controller manages two types of RAM, including SRAM and SDRAM. The two memory types are
implemented on-board, providing up to 66Mbytes of data/code.
1.3.2.1 SRAM
The evaluation board B embeds one 40-bit SRAM bank made of two space qualified SRAM memories:
•
•
1 AT68166 SRAM memory connected to the data bus
1 AT60142 SRAM memory connected to the EDAC checkbit bus (When EDAC protection functionality is used)
Figure 6: SRAM memory implementation
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1.3.2.2 SDRAM
The evaluation board B embeds one 40-bit SDRAM bank made of three Micron MT48LC16M16 SDRAM memories:
•
•
2 SDRAM memories are connected to the data bus
SDRAM memory is connected to the EDAC checkbit bus (When EDAC protection functionality is used)
Figure 7: SRAM implementation
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1.4
Power Supply
The ATF697FF evaluation board B is designed to generate all the supply voltages required by the on-board components, thus
including:
•
•
•
1.25V (VDD_P1V25) as reference voltage for LVDS I/Os,
1.8V (VDD_P1V8) for ATF697FF core supply,
3.3V (VDD_P3V3) for I/Os.
The power can be supplied by different sources:
•
An external +6V to +12V power supply connected on the jack connector that is then regulated on-board to fit the
device characteristics,
•
•
A +5V power supply from Compact PCI connector that is then regulated on-board to fit the device characteristics,
A direct external powering sources to apply the +5V, +3.3V and +1.8V directly.
1.25
VREF
5V from CPCI
Ext.
connector
3V3 from ext.
connector
TPS54325
EXT_CPCI_VDD
VIN
EN
1000µF
PH
VREF_P1V25
VDD_P3V3
VDD_P3V3
PWRGD
1V8 from ext.
connector
TPS54325
VIN
EN
VDD_P1V8
PH
VDD_P3V3
PWRGD
MAX16052
4.5V voltage
detection
Figure 8: Power supply generation – overview
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1.4.1
Power Inputs
1.4.1.1 Jack powering
Power can be applied via the 2.1mm jack connector (J404) in either polarity thanks to the input diode rectifier protection. An
external power supply source from +6V up to +12V can be connected to the jack connector for on board 1.8V, 3.3V and 5V
generation.
•
An embedded voltage regulator provides the 3.3V source for the board. When the 3.3V power supply operates, an
orange power-on led lights on the front panel,
•
An embedded voltage regulator provides the 1.8V source for the board. When the 1.8V power supply operates, a
green power-on led lights on the front panel,
•
Directly derived from the 3.3V line, another on-board regulator provides the 1.25V required by the LVDS.
When used as a PCI board, it is possible to power the evaluation board B directly through the compact PCI interface. No
external power supply is necessary on J404.
1.4.1.2 Compact PCI powering
Power can also be applied through the compact PCI connector.
In this case the switch J403/J413 should be placed on ‘1-2’ position .
1.4.1.3 Direct powering
It is also possible to directly power the 3.3V line by connecting a 3.3V source to connector J408. In this case, J407 ‘PWR33’
switch must be configured in ‘3-2’.
It is also possible to directly power the 1.8V line by connecting a 1.8V source to connector J406 In this case, J405 ‘PWR18’
switch must be configured in ‘3-2’.
In this configuration, the 5V line should be also bring either by the jack connector or the compact PCI connector to power up
others components such as the reset controller MAX16052. Otherwises, the evaluation board is maintened under reset by the
reset controller.
1.4.1.4 PCI powering
N/A
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1.4.1.5 Power configuration summary
differents straps configuration: power supply
On
board
(J404)
1
External
connector
On
board
(J406)
X
X
X
X
X
X
X
(optional)
X
12V
Compact
connector
-12V
On
board
Compact
power
(mandatory)
External
connector
1.8V
(mandatory)
3.3V
PCI
1.25V
Compact
connector
(mandatory)
Jack
connector
(mandatory)
5V
Configuration
number
PCI
Table 1-5.
PCI
(J408)
X
X
X
J403
J405
J407
2-3
1-2
1-2
X
X
X
J403
J405
J407
1-2
1-2
1-2
J413
2-3
2
J413
1-2
3
X
X
X
J403
J405
J407
2-3
2-3
2-3
X
X
X
J403
J405
J407
1-2
2-3
2-3
J413
2-3
4
J413
1-2
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1.4.2
Voltage test points
The evaluation board B provides a set of test points for voltage measurement. All the voltage references of the board can be
accessed though these test points:
Table 1-6.
Voltage probe definition
Voltage
Definition
Test point reference
VDD_3V3
3V3 voltage test point
TP403
VDD_1V8
1V8 voltage test point
TP406
EXT_CPCI_VDD
External or compact PCI voltage test point
TP401
GND
Ground test point
TP407, TP408, TP409, TP410, TP411
1.4.3
Current probe
The evaluation board B is built to enable measurement of the processor current consumptions over the main components.
Table 1-7.
Current probe definition
Current
Definition
Jumper reference
I_P3V3_FPGA
3V3 FPGA current measurement
J409
I_P3V3_PROC
3V3 processor current measurement
J410
I_P1V8_FPGA
1V8 FPGA current measurement
J411
I_P1V8_PROC
1V8 processor current measurement
J412
I_GLOBAL
Global current measurement
J403
Each current probe consists in a simple “jumper” that can be easily removed for current probe insertion. Then two ports are
available and the measurement tool can be inserted in the power loop.
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Figure 9: current probe localization
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1.4.4
Decoupling Capacitance
The evaluation board is designed to enable the use of the ATF697FF processor core at frequencies from 0Hz up to 100MHz,
the ATF697FF reconfigurable unit at frequencies up to 50 MHz.
The PCI interface by itself can run at frequencies up to 33MHz.
The following assumptions are taken for capacitance calculation:
•
•
•
Power lines are grouped by four VDD/VSS (or VCC/VSS) pairs
Characteristic frequencies are 33MHz and 100MHz
Capacitance used have an intrinsic inductance value close 1.5nH
The decoupling capacitance chosen for the evaluation board B are
•
•
•
•
3nF
33nF
100 nF
10 µF
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1.5
Clock
The ATF697FF evaluation board B provides a flexible set of clocks that allows designer to configure its design in an optimized
way. Clock signals can take the following sources :
•
The CDCE925PW programmable clock generator is used for generation of most of the clocks. Default configuration
generates 25 MHz clock outputs on CLK_GEN[5:1] signals.
•
A 33 MHz clock is provided directly to the ATF697FF reconfigurable unit from an external 33 MHz oscillator allowing
internal routing of the clock signal in the reconfigurable unit up to the PCI_CLK line.
•
One SMB connector (J1301) is provided on board to make possible injection of a clock on the reconfigurable unit
directly from a laboratory clock generator. The other (J501) is populated for internal use.
Here is an overview of the clock tree implemented on the board.
Figure 10: Steropes evaluation board B clock tree
The following table lists the clock signals that are made available on the evaluation board B.
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Table 1-8.
Clock signals
Clock name
Direction
ATF697FF
pin
Part of ATF697FF affected
Comments
CLK_PROC
IN
144
ATF697FF processor
Main clock of the ATF697FF processor
SDCLK
OUT
224
ATF697FF processor
Clock for SDRAM memory interface
UART_CLK
OUT
270
ATF697FF processor
Clock for the UART peripheral
JTAG_CLK
IN
94
ATF697FF
processor
reconfigurable unit
CLK_EXT_FPGA
IN
96
and
Clock for JTAG
from J1103 connector
ATF697FF reconfigurable unit
Clock for ATF697FF reconfigurable unit
From J1301 connector
CLK_EXP_FPGA
IN
349
ATF697FF reconfigurable unit
J2201 connector
Expansion connector 1
CLK_FPGA_OUT
OUT
21
ATF697FF reconfigurable unit
CCLK
OUT
100
ATF697FF reconfigurable unit
Clock configuration for the ATF697FF
EEPROM memories
33MHz
IN
25MHz
1
ATF697FF
communication
internal
PCI
Clock for the internal PCI communication
From Y1301 quartz
IN
From Y1201 quartz
Input of the MN1201 clock generator
CLK_GEN1
IN
95
ATF697FF
processor
CLK_GEN2
IN
288
ATF697FF reconfigurable unit
Generated from the 25MHz through the
MN1202 component
CLK_GEN3
IN
291
ATF697FF reconfigurable unit
Generated from the 25MHz through the
MN1202 component
CLK_GEN4
IN
127
ATF697FF reconfigurable unit
Generated from the 25MHz through the
MN1202 component
CLK_GEN5
IN
128
ATF697FF reconfigurable unit
Generated from the 25MHz through the
MN1202 component
Note:
reconfigurable
unit
and
Generated from the 25MHz through the
MN1202 component
The direction is from the component point of view
The following table lists the different straps that can be done with the evaluation board B for the clock configuration:
Table 1-9.
straps configurations for the ATF697FF processor clock
Signal name
Source
Connection (configuration)
CLK_PROC
CLK_GEN5
J502 (1-2)
CLK_FPGA_OUT
J502 (3-4)
CLK_GEN1
J502 (5-6)
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1.5.2
Clock configuration
The clock configuration is based on the CDCE925 that can be configured through its I2C interface. The following figure gives
an overview of the CDCE925PW internal structure.
Figure 11: Clock generator
From a 25 MHZ input, the CDCE925 can generate up to 5 different frequencies.
On the evaluation board B, S0 pin of the CDCE925PW is pulled-up to enable the five clock channels at power up.
Figure 12: Clock generator configuration interface
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Default I2C slave address for the CDCE925PW is 0x64 (bits A[6:0]).
The CDCE925 component could be driven by two means:
•
The space programmer could program the CDCE925 component by using the DATA pin, the CCLK or the CS_PLL
pins from the space programmer.
•
The ATF697FF processor could program as well the CDCE925 component by using the GPIO4, 5 and 6.
Refer to the CDCE925 configuration appendix for details on the configuration procedure.
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1.6
Reset
The ATF697FF evaluation board B provides various reset sources. User accessible reset sources are the following:
•
A global reset push button (SW1803), placed on front panel generates a reset on both the ATF697FF processor and
reconfigurable unit when power supplies are under the nominal conditions.
A reset input from the expansion connector allowing an expansion board to reset the evaluation board B.
This input allows a global reset on the evaluation board B.
•
•
•
•
•
A local reset push button (SW1801) generating a reset on the ATF697FF processor.
•
A reset, on GPIO[3] from the ATF697FF processor to the ATF697FF reconfigurable unit allowing the processor to
reset the reconfigurable unit.
•
A reset output from the global reset output to the expansion connector allowing an expansion board to be resetted by
the evaluation board B.
A local reset push button (SW1802) generating a reset on the ATF697FF reconfigurable unit.
A local reset push button (SW1804) generating a reset on the ATF697FF reconfigurable unit logic.
A reset on IO259_LDC, from the ATF697FF reconfigurable unit to the ATF697FF processor allowing the
reconfigurable unit to reset the processor.
In addition to the user accessible reset sources, the board embeds some automated resets that prevent the board components
from being either damaged or behaving in wrong states.
A 5V reset controller from the MAX16052. The output is named SUPPLY_GOOD.
This controller generates a reset when the main EXT_CPCI_VDD voltage is under 4.5 V.
•
A 3V3 reset controller from the TPS54325. The output is named 3V3_GOOD
This controller allows generation of a reset when P3V3 voltage is under 3.0 V.
•
A 1V8 reset controller from the TPS54325. The output is named 1V8_GOOD
This controller allows generation of a reset when P1V8 voltage is under 1.7 V.
•
•
During the power-up sequence, ATF697FF reconfigurable unit is maintained under reset as long as the configuration
EEPROMs (AT17LV010 and AT69170) are not ready.
The following table summarizes the list of available reset.
Table 1-10. : reset list
Reset signal name
Active
level
Comment
1V8_GOOD*
Low
Reset from TPS54325 active low when 1V8 power supply is under nominal conditions (1.7V)
3V3_GOOD*
Low
Reset from TPS54325 active low when 3V3 power supply is under nominal conditions (3.0V)
SUPPLY_GOOD*
Low
Reset from MAX16052 active low when power supply is under nominal conditions (4.5V)
JTAG_NSRST*
Low
JTAG software active low reset
SPACE_NRST*
Low
Space programmer active low reset
EXT_RST_IN*
Low
Expansion connector active low reset
GLOBAL_RESET*
Low
Global reset active low. This signal is a logical “AND” of 1V8_GOOD, 3V3_GOOD,
SUPPLY_GOOD, JTAG_NSRST, SPACE_NRST, EXT_RST_IN
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Reset signal name
Active
level
PROC_RESET*
Low
Reset for ATF697FF processor. This signal is a logical “AND” of GLOBAL_RESET and reset from
push button
FPGA_RESET*
Low
Reset for ATF697FF reconfigurable unit. This signal is a logical “AND” of GLOBAL_RESET, reset
from push button and reset from serial EEPROMs (READY output). This signal resets the
reconfigurable unit. On a low to high transition, the reconfigurable unit is reconfigured.
FPGA_RESET*_APP
Low
Application reset. This signal allows a reset of reconfigurable unit internal logic. This signal is
“AND” gated with ATF697FF processor RAMS3* and WRITE* signals allowing the ATF697FF
processor to reset the ATF697FF reconfigurable unit logic when writing at RAMS3 base address.
Comment
The following figure shows the reset implementation on board.
Figure 13: Reset tree
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1.7
Serial Link
The ATF697FF evaluation board B includes all the required hardware to manage one RS232 serial communication link. A 9way D-type connector is provided for serial connection. The connector is a female DB9 connector. Flow control facilities are
also made available.
Table 1-11. RS-232 interface connector
DB9
Signal name
I/O Type
Description
1
-
-
Not connected
2
RS232_TXD1
O
Transmit Data
3
RS232_RXD1
I
Receive Data
4
-
-
Not connected
5
GND
-
Signal Ground
6
-
-
Not connected
7
RS232_CTS1
I
Clear To Send
8
RS232_RTS1
O
Request To Send
9
-
-
Not connected
Uart 1 of the ATF697FF processor is connected to this interface.
The second serial link provided by the ATF697FF processor can be accessed through the expansion connector. No
transceiver is implemented on board to adapt the signal levels of this second uart.
Figure 14: Serial Link Location
1.7.2
Disabling Serial Link Flow Control
The flow control lines of the RS232 interface are mapped with an alternate function of the board.
•
•
GPIO13 (RTS) can be used as a control signal for the D1102 LED
GPIO12 (CTS) can be used as an input connected to SW1102 switch
It is possible to physically disconnect the flow control line for use of the alternate function thanks to J1002 and J1003 jumpers.
Here is the summary of the configuration:
Table 1-12. GPIO13 line configuration
GPIO13 configuration
J1002
RTS (flow control)
1-2
LED1102 control signal
2-3
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Table 1-13. GPIO12 line configuration
GPIO12 configuration
J1002
CTS (flow control)
1-2
SW1102 input
2-3
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1.8
SpaceWire Interface
The ATF697FF evaluation board B includes two SpaceWire communication link. Each SpaceWire channel is build around a 9way Micro D-type female connector with the standard pin assignement:
Table 1-14. Space wire interface connector
DSU DB9
Signal name
I/O Type
1
DIN+
I
2
SIN+
I
3
GND
-
4
SOUT-
O
5
DOUT-
O
6
DIN-
I
7
SIN-
I
8
SOUT+
O
DOUT+
O
9
Description
The spacewire interfaces are connected to the ATF697FF reconfigurable unit LVDS interface as defined in the following tables
Table 1-15. SPW1 assignment
ATF697FF reconfigurable unit signal
Signal Name
FPGA_ILVDSA1
DIN1+
FPGA_ILVDSNA1
DIN1-
FPGA_ILVDSA2
SIN1+
FPGA_ILVDSNA2
SIN1-
FPGA_OLVDSA1
SOUT1+
FPGA_OLVDSNA1
SOUT1-
FPGA_OLVDSA2
DOUT1+
FPGA_OLVDSNA2
DOUT1-
Table 1-16. SPW2 assignment
ATF697FF reconfigurable unit signal
Signal Name
FPGA_ILVDSB1
DIN2+
FPGA_ILVDSNB1
DIN2-
FPGA_ILVDSB2
SIN2+
FPGA_ILVDSNB2
SIN2-
FPGA_OLVDSB1
SOUT2+
FPGA_OLVDSNB1
SOUT2-
FPGA_OLVDSB2
DOUT2+
FPGA_OLVDSNB2
DOUT2-
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Figure 15: space wire interface
1.9
PCI interface
N/A
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1.10
LEDs
1.10.1 Status LEDs
On the front panel, six LEDs gives information on reconfigurable unit power supply status as follows:
•
•
Power supply LEDs D401 (left side)
•
Top red LED indicate the good level of input power
•
Middle yellow LED indicate the good level of 3V3 regulated power
•
Bottom green LED indicate the good level of 1V8 regulated power
reconfigurable unit configuration LEDs, D1801 (right side)
•
Top red LED indicate the reconfigurable unit is in error
•
Middle yellow LED indicate the reconfigurable unit is booting
•
Bottom green LED indicate the reconfigurable unit is successfully programmed
Figure 16: board status leds
On the top side of the PCB, a red LED D1001 indicate that DSU break is active.
Figure 17: DSU Break Status LEDs
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1.10.2 General Purpose LEDs
The evaluation board B includes 10 general purpose leds connected to the GPIO interface.
•
•
Two green LEDs are directly connected to the ATF697FF-processor GPIOs
Eight red LEDs are connected to ATF697FF reconfigurable unit IOs
Here is the pin assignment of the LEDs :
Table 1-17.
LEDs assignement
LED name
IO name
ATF697FF pin number
D1101
PROC_GPIO11
280
D1102
PROC_GPIO13
281
D1701
FPGA_LED0
28
D1702
FPGA_LED1
29
D1703
FPGA_LED2
30
D1704
FPGA_LED3
31
D1705
FPGA_LED4
32
D1706
FPGA_LED5
35
D1707
FPGA_LED6
37
D1708
FPGA_LED7
38
Figure 18: User LEDs location
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1.11
Pushbuttons/Switches
1.11.1 Configuration Switches
The board is equipped with an 8 channel configuration switch (SW1601) that allows configuration of
•
•
•
•
•
•
ATF697FF -processor reset
ATF697FF - reconfigurable unit reset
ATF697FF - reconfigurable unit programming configuration
DSU activation
EEPROM low power mode
EEPROM protection mode
The following assignment applies:
Table 1-18. Configuration DIP switch assignment
Position
1
2
3
4
5
6
7
8
Function
When set ON, reset
the processor while
the
reconfigurable
unit is not configured
When set ON,
force
the
reconfigurable
unit to reset
When
set
ON disable
the
DSU,
else DSU is
enabled
When set ON,
AT69170
power is in
normal mode
else in low
power mode
When set ON,
AT17LV010 write
protect is disabled
else write protect
is enabled
When sets to ON
reconfigurable
unit
boot mode is 0, used
for serial EEPROM
configuration source.
When sets to OFF
reconfigurable
unit
boot mode is 7, used
for Space Programmer
configuration source
Figure 19: configuration switch location
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1.11.2 General Purpose switches/pushbuttons
The evaluation board B includes 10 general purpose switches connected to the GPIO interface.
•
•
Two are directly connected to the ATF697FF -processor GPIOs
Eight are connected to ATF697FF - reconfigurable unit IOs
Here is the pin assignment of the switches/pushbuttons:
Table 1-19. switches/pushbuttons assignement
Switch name
IO name
ATF697FF pin number
SW1101
PROC_GPIO10
279
SW1102
PROC_GPIO12
281
SW1701
FPGA_SW0
14
SW1702
FPGA_SW1
15
SW1703
FPGA_SW2
19
SW1704
FPGA_SW3
20
SW1705
FPGA_SW4
24
SW1706
FPGA_SW5
25
SW1707
FPGA_SW6
26
SW1708
FPGA_SW7
27
Figure 20: User switches/pushbuttons location
Here is the description of the default state of each IO when the pushbuttons are released:
Table 1-20. : default state of IO
LED name
IO name
ATF697FF pin number
Default Level
SW1101
PROC_PIO10
279
High
SW1102
PROC_PIO12
281
High
SW1701
FPGA_SW0
14
High
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LED name
IO name
ATF697FF pin number
Default Level
SW1702
FPGA_SW1
15
High
SW1703
FPGA_SW2
19
High
SW1704
FPGA_SW3
20
High
SW1705
FPGA_SW4
24
High
SW1706
FPGA_SW5
25
High
SW1707
FPGA_SW6
26
High
SW1708
FPGA_SW7
27
High
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1.12
Debug Support Unit
The ATF697FF processor Debug Support Unit is based on a RS232 serial link connected to a host platform. The ATF697FF
evaluation board B includes all the required hardware to manage the RS232 communication and the debug facilities. A female
9-way D-type connector is provided for serial connection.
Table 1-21. DSU interface connector
DB9
Signal name
I/O Type
Description
1
-
-
Not connected
2
RS232_DSUTX1
O
Transmit Data
3
RS232_DSURX1
I
Receive Data
4
-
-
Not connected
5
GND
-
Signal Ground
6
-
-
Not connected
7
-
-
Not connected
8
-
-
Not connected
9
-
-
Not connected
Figure 21: DSU Link Location
It is possible to send a break signal to the DSU interface thanks to the SW1001 pushbutton. See Push buttons/ leds section to
visualize the DSU break switch location.
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1.13
Space Programmer Interface
A 10-pin HE10 connector is provided on the front panel of the board to allow connection of the SpaceProgrammer interface.
This interface is used for download of a bitstream in the serial memories and configuration of the clock manager.
The following table presents the assignment of the signals on the connector
Table 1-22. Space programmer connector pinout
Pin
Signal name
I/O Type
Description
1
DATA
I/O
Serial data input
2
CS_SLAVE_CON_FPGA
I/O
Reconfigurable unit configuration status
3
CCLK
I/O
Serial clock input
4
CS_PLL
-
CDCE925 clock enable
5
CS2_AT17
I/O
AT17LV010 group 2 serial enable
6
CS1_AT17
I/O
AT17LV010 group 1 serial enable
7
GND
-
Ground
8
VDD_P3V3
-
3V3 power supply for external probe buffers
9
SPACE_NRST
I/O
Global reset to/from connector
10
CS_AT69170_FPGA_INIT
I/O
AT69170 serial enable or FPGA init pin
Figure 22: Space programmer Interface location
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1.14
JTAG Interface
A 10-pin HE10 connector is provided on board to enable connection of the JTAG interface. The following table presents the
assignment of the signals on the JTAG connector.
Table 1-23. JTAG connector pinout
Pin
Signal name
I/O Type
Description
1
-
-
Not connected
2
-
-
Not connected
3
JTAG_NSRST
I
Global reset from connector
4
JTAG_TMS
I
Test mode select
5
JTAG_TDI
I
Test data input
6
JTAG_TCK
I
Test clock
7
JTAG_TDO
O
Test data output
8
JTAG_NTRST
I
JTAG test reset (must be a push/pull input)
9
VDD_P3V3
-
3V3 power supply for external probe
10
GND
-
Ground
Figure 23: JTAG connector location
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1.15
Probes / Test Points
1.15.1 Probes / test points description
Here is the list of the probes and test points provided on the evaluation board B:
Test point Name
Comments
TP401
Input power supply (from CPCI connector or external power supply)
TP402
1V8_GOOD signal measurement
TP403
3V3 voltage measurement
TP404
3V3_GOOD signal measurement
TP405
SUPPLY_GOOD signal measurement
TP406
1V8 voltage measurement
TP501
ATF697FF signal error
TP502
ATF697FF Watchdog
TP503
ATF697FF processor clock
TP701
CE* parallel EEPROMS
TP1201
25 MHz clock input
TP1301
ATF697FF FPGA clock
TP1302
PCI_CLK
TP1601
ATF697FF FPGA INIT
TP1602
ATF697FF FPGA CON
TP1603
ATF697FF FPGA_LDC
TP1604
ATF697FF FPGA-HDC
TP1801
ATF697FF FPGA_RESET_APP*
TP1802
ATF697FF FPGA_RESET*
TP1803
ATF697FF PROC_RESET*
TP1804
ATF697FF GLOBAL_RESET
TP1901
Serial EEPROMs WP1 & WP2
TP407, TP408, TP409, TP410, TP411
GND test point
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1.15.2 Probes / test points localization
6
5
4
1
2
3
Figure 24: test point location : global view
Figure 25: zoom 1
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Figure 26: zoom 2
Figure 27: zoom 3
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Figure 28: zoom 4
Figure 29: zoom 5
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Figure 30: zoom 6
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1.16
Expansion Connectors
For users who want to extend the evaluation board B capabilities, Two 2 x 50 expansion connectors are provided on the
evaluation board B. They are made two 2x50 high density BERGSTACK 61083-104400LF connectors.
Table 1-25. Expansion connector 1
Pin
Signal name
Type
Description
Pin
Signal name
Type
Description
1
GND
-
Ground
2
VDD_P3V3
-
3V3 power supply
3
EXT_IO45
I/O
General I/O (FPGA)
4
-
-
Not connected
5
EXT_IO44
I/O
General I/O (FPGA)
6
-
-
Not connected
7
EXT_IO43
I/O
General I/O (FPGA)
8
-
-
Not connected
9
EXT_IO42
I/O
General I/O (FPGA)
10
-
-
Not connected
11
EXT_IO41
I/O
General I/O (FPGA)
12
EXT_RST_IN
I
Expansion connector reset
13
EXT_IO40
I/O
General I/O (FPGA)
14
GLOBAL_RESET
O
Board global reset output
15
EXT_IO39
I/O
General I/O (FPGA)
16
CLK_EXT_FPGA
I
External clock input for FPGA
17
EXT_IO38
I/O
General I/O (FPGA)
18
CLK_GEN4
O
Clock output 4 from CDCE925
19
EXT_IO37
I/O
General I/O (FPGA)
20
EXT_IO85
I/O
General I/O (FPGA)
21
EXT_IO36
I/O
General I/O (FPGA)
22
EXT_IO84
I/O
General I/O (FPGA)
23
EXT_IO35
I/O
General I/O (FPGA)
24
EXT_IO83
I/O
General I/O (FPGA)
25
EXT_IO34
I/O
General I/O (FPGA)
26
EXT_IO82
I/O
General I/O (FPGA)
27
EXT_IO33
I/O
General I/O (FPGA)
28
EXT_IO81
I/O
General I/O (FPGA)
29
EXT_IO32
I/O
General I/O (FPGA)
30
EXT_IO80
I/O
General I/O (FPGA)
31
EXT_IO31
I/O
General I/O (FPGA)
32
EXT_IO79
I/O
General I/O (FPGA)
33
EXT_IO30
I/O
General I/O (FPGA)
34
EXT_IO78
I/O
General I/O (FPGA)
35
EXT_IO29
I/O
General I/O (FPGA)
36
EXT_IO77
I/O
General I/O (FPGA)
37
EXT_IO28
I/O
General I/O (FPGA)
38
EXT_IO76
I/O
General I/O (FPGA)
39
EXT_IO27
I/O
General I/O (FPGA)
40
EXT_IO75
I/O
General I/O (FPGA)
41
EXT_IO26
I/O
General I/O (FPGA)
42
EXT_IO74
I/O
General I/O (FPGA)
43
EXT_IO25
I/O
General I/O (FPGA)
44
EXT_IO73
I/O
General I/O (FPGA)
45
EXT_IO24
I/O
General I/O (FPGA)
46
EXT_IO72
I/O
General I/O (FPGA)
47
EXT_IO23
I/O
General I/O (FPGA)
48
EXT_IO71
I/O
General I/O (FPGA)
49
EXT_IO22
I/O
General I/O (FPGA)
50
EXT_IO70
I/O
General I/O (FPGA)
51
EXT_IO21
I/O
General I/O (FPGA)
52
EXT_IO69
I/O
General I/O (FPGA)
53
EXT_IO20
I/O
General I/O (FPGA)
54
EXT_IO68
I/O
General I/O (FPGA)
55
EXT_IO19
I/O
General I/O (FPGA)
56
EXT_IO67
I/O
General I/O (FPGA)
57
EXT_IO18
I/O
General I/O (FPGA)
58
EXT_IO66
I/O
General I/O (FPGA)
59
EXT_IO17
I/O
General I/O (FPGA)
60
EXT_IO65
I/O
General I/O (FPGA)
ATMEL ATF697FF[USER GUIDE][DRAFT]
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47
Pin
Signal name
Type
Description
Pin
Signal name
Type
Description
61
EXT_IO16
I/O
General I/O (FPGA)
62
EXT_IO64
I/O
General I/O (FPGA)
63
EXT_IO15
I/O
General I/O (FPGA)
64
EXT_IO63
I/O
General I/O (FPGA)
65
EXT_IO14
I/O
General I/O (FPGA)
66
EXT_IO62
I/O
General I/O (FPGA)
67
EXT_IO101
I/O
General I/O (FPGA)
68
EXT_IO61
I/O
General I/O (FPGA)
69
EXT_IO100
I/O
General I/O (FPGA)
70
EXT_IO60
I/O
General I/O (FPGA)
71
EXT_IO13
I/O
General I/O (FPGA)
72
EXT_IO59
I/O
General I/O (FPGA)
73
EXT_IO12
I/O
General I/O (FPGA)
74
EXT_IO58
I/O
General I/O (FPGA)
75
EXT_IO11
I/O
General I/O (FPGA)
76
EXT_IO57
I/O
General I/O (FPGA)
77
EXT_IO10
I/O
General I/O (FPGA)
78
EXT_IO56
I/O
General I/O (FPGA)
79
EXT_IO9
I/O
General I/O (FPGA)
80
EXT_IO55
I/O
General I/O (FPGA)
81
EXT_IO8
I/O
General I/O (FPGA)
82
EXT_IO54
I/O
General I/O (FPGA)
83
EXT_IO7
I/O
General I/O (FPGA)
84
EXT_IO53
I/O
General I/O (FPGA)
85
EXT_IO6
I/O
General I/O (FPGA)
86
EXT_IO52
I/O
General I/O (FPGA)
87
EXT_IO5
I/O
General I/O (FPGA)
88
EXT_IO51
I/O
General I/O (FPGA)
89
EXT_IO4
I/O
General I/O (FPGA)
90
EXT_IO50
I/O
General I/O (FPGA)
91
EXT_IO3
I/O
General I/O (FPGA)
92
EXT_IO49
I/O
General I/O (FPGA)
93
EXT_IO2
I/O
General I/O (FPGA)
94
EXT_IO48
I/O
General I/O (FPGA)
95
EXT_IO1
I/O
General I/O (FPGA)
96
EXT_IO47
I/O
General I/O (FPGA)
97
EXT_IO0
I/O
General I/O (FPGA)
98
EXT_IO46
I/O
General I/O (FPGA)
99
VDD_P3V3
-
3V3 power supply
100
GND
-
ground
Table 1-26. Expansion connector 2
Signal
name
I/O
Type
Description
Pin
1
GND
-
Ground
3
-
-
5
-
7
Signal
name
I/O
Type
Description
2
VDD_P3V3
-
3V3 power supply
Not connected
4
-
-
Not connected
-
Not connected
6
-
-
Not connected
-
-
Not connected
8
-
-
Not connected
9
-
-
Not connected
10
-
-
Not connected
11
-
-
Not connected
12
-
-
Not connected
13
-
-
Not connected
14
-
-
Not connected
15
-
-
Not connected
16
EXT_IO112
I/O
General I/O (FPGA)
17
-
-
Not connected
18
CLK_GEN5
O
Clock output 5 from CDCE925
19
-
-
Not connected
20
EXT_IO110
I/O
General I/O (FPGA)
21
-
-
Not connected
22
EXT_IO109
I/O
General I/O (FPGA)
Pin
ATMEL ATF697FF[USER GUIDE][DRAFT]
41002Ad1 – AERO 04/12
48
Signal
name
I/O
Type
Description
Pin
23
-
-
Not connected
25
-
-
27
-
29
Signal
name
I/O
Type
Description
24
EXT_IO108
I/O
General I/O (FPGA)
Not connected
26
EXT_IO107
I/O
General I/O (FPGA)
-
Not connected
28
EXT_IO106
I/O
General I/O (FPGA)
-
-
Not connected
30
EXPA_IO1
I/O
To J2203 only
31
-
-
Not connected
32
EXPA_IO2
I/O
To J2203 only
33
-
-
Not connected
34
EXPA_IO3
I/O
To J2203 only
35
-
-
Not connected
36
EXPA_IO4
I/O
To J2203 only
37
-
-
Not connected
38
EXPA_IO5
I/O
To J2203 only
39
-
-
Not connected
40
-
-
Not connected
41
-
-
Not connected
42
-
-
Not connected
43
-
-
Not connected
44
-
-
Not connected
45
-
-
Not connected
46
EXT_IO105
I/O
General I/O (FPGA)
47
-
-
Not connected
48
-
-
Not connected
49
-
-
Not connected
50
-
-
Not connected
51
-
-
Not connected
52
-
-
Not connected
53
-
-
Not connected
54
-
-
Not connected
55
-
-
Not connected
56
-
-
Not connected
57
-
-
Not connected
58
-
-
Not connected
59
-
-
Not connected
60
-
-
Not connected
61
-
-
Not connected
62
-
-
Not connected
63
-
-
Not connected
64
-
-
Not connected
65
-
-
Not connected
66
-
-
Not connected
67
EXT_IO103
I/O
General
I/O
(RECONFIGURABLE UNIT)
68
-
-
Not connected
69
EXT_IO102
I/O
General
I/O
(RECONFIGURABLE UNIT)
70
-
-
Not connected
71
EXT_IO99
I/O
General
I/O
(RECONFIGURABLE UNIT)
72
EXT_IO111
I/O
General
I/O
(RECONFIGURABLE
UNIT), this pin is pulled up to 3V3
73
EXT_IO98
I/O
General
I/O
(RECONFIGURABLE UNIT)
74
EXT_IO104
I/O
General I/O (RECONFIGURABLE UNIT)
75
EXT_IO97
I/O
General
I/O
(RECONFIGURABLE UNIT)
76
-
-
Not connected
77
EXT_IO96
I/O
General
I/O
(RECONFIGURABLE UNIT)
78
-
-
Not connected
79
EXT_IO95
I/O
General
I/O
(RECONFIGURABLE UNIT)
80
-
-
Not connected
81
EXT_IO94
I/O
General
I/O
(RECONFIGURABLE UNIT)
82
-
-
Not connected
Pin
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41002Ad1 – AERO 04/12
49
Signal
name
I/O
Type
83
EXT_IO93
85
Signal
name
I/O
Type
Description
84
-
-
Not connected
General
I/O
(RECONFIGURABLE UNIT)
86
-
-
Not connected
I/O
General
I/O
(RECONFIGURABLE UNIT)
88
-
-
Not connected
EXT_IO90
I/O
General
I/O
(RECONFIGURABLE UNIT)
90
-
-
Not connected
91
EXT_IO89
I/O
General
I/O
(RECONFIGURABLE UNIT)
92
-
-
Not connected
93
EXT_IO88
I/O
General
I/O
(RECONFIGURABLE UNIT)
94
-
-
Not connected
95
EXT_IO87
I/O
General
I/O
(RECONFIGURABLE UNIT)
96
-
-
Not connected
97
EXT_IO86
I/O
General
I/O
(RECONFIGURABLE UNIT)
98
-
-
Not connected
99
VDD_P3V3
-
3V3 power supply
100
GND
-
ground
Pin
Description
Pin
I/O
General
I/O
(RECONFIGURABLE UNIT)
EXT_IO92
I/O
87
EXT_IO91
89
See appendix B “Expansion connector” for details on the hardware placement specification of the expansion connectors
ATMEL ATF697FF[USER GUIDE][DRAFT]
41002Ad1 – AERO 04/12
50
1.17
Board default strap configuration
The next table presents the default strap configuration for the ATF697FF evatuation board.
Table 1-27. default configuration strap
Reference
Default position
Strap functionality
J403
2-3
global power supply source selection
J405
1-2
3V3 power supply source selection
J407
1-2
1V8 power supply source selection
J409
Closed
current measurement for 3V3 on the reconfigurable unit
J410
Closed
current measurement for 3V3 on the processor
J411
Closed
current measurement for 1V8 on the reconfigurable unit
J412
Closed
current measurement for 1V8 on the processor
J413
2-3
global power supply source selection
J502
1-2
clock processor selection
J504
Open
pll bybass activation for the processor
J505
Closed
skew0 selection
J506
Closed
skew1 selection
J507
Open
processor ROM bus width selection
J701
1-2
serial or parallel boot activation
J1002
2-3
GPIO13 functionality selection
J1003
2-3
GPIO12 functionality selection
J1602
3-4
reconfigurable unit CON selection
J1603
3-4
reconfigurable unit INIT selection
J1604
Open
AT69170 programming source
SW1601.1
OFF
reconfigurable unit resets processor connection
SW1601.2
OFF
force reconfigurable unit reset
ATMEL ATF697FF[USER GUIDE][DRAFT]
41002Ad1 – AERO 04/12
51
Reference
Default position
Strap functionality
SW1601.3
OFF
DSU enable
SW1601.4
ON
AT69170 power mown mode
SW1601.5
ON
AT17 write protection
SW1601.6
ON
reconfigurable unit mode selection
SW1601.7
ON
reconfigurable unit mode selection
SW1601.8
ON
reconfigurable unit mode selection
ATMEL ATF697FF[USER GUIDE][DRAFT]
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52
2.
Ordering Information
Atmel ATF697FF Evaluation board Ordering Code
Atmel Ordering Code
Product Embedded
Temperature Range
Quality Flow
ATF697FF-EVAB
ATF697FF-KW-E
Industrial
Engineering
ATMEL ATF697FF[USER GUIDE][DRAFT]
41002Ad1 – AERO 04/12
53
Appendix A.
Expansion
In order to interface the ATF697FF evaluation board B with an expansion board, two specific connectors are used. These are
two 2x50 headers soldered at the top side of the Board. They are male 2x50 CMS high density connectors.
The two expansion connectors provide a full access to all the signals of the ATF697FF reconfigurable unit. The pin assignment
of these two connectors is available in Section “Expansion Connectors”, of this document.
A.1
Connector Specification
The expansion interface is based on two high density connectors. The implementation chosen for the ATF697FF evaluation
board B relies on two 2x50 male Bergstak® connectors. Here is the reference of the connector embedded on the evaluation
board B:
Male 2x50 Bergstak CMS provided by Farnell under 973-324 reference
The connection of a mezzanine board to the evaluation board B can be performed using the following reference:
Female 2x50 Bergstak CMS provided by Farnell under 973-336 reference
A.2
Mechanical Constraints
The following figure presents the mechanical constraints for development of an expansion board that can be plugged on the
ATF697FF evaluation board B. All dimensions are given at more or less 0.20mm.
Note:
If more information is required, an ATT697FF.brd file is available under request. This document can be sent to any
customer requiring a global view of the board and requiring additional measurement constraints over the board.
Such file can be read and analyzed with “Allegro Free Physical Viewer”, a free tool from Cadence®.
55
ATMEL ATF697FF[USER GUIDE][DRAFT]
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Appendix B. CDCE configuration
The clock generator has a dedicate software “TIclockpro” to configure the different clocks outputs as needed.
This software could be downloaded at http://www.ti.com/product/cdce925#toolssoftware
Figure 31: global view of the TI CDCE925 software
Here is the procedure to follow to configure and program the CDCE component:
Configure as needed the differents outputs of the CDCE925.
Save the file in .hex format
Launch the space programmer tools and select the space programmer configuration
Active low reset : the button should be green and the low checkbox should be selected.
Click on the CDCE component and click on load bitstream.
Select the file previously created
Active the write checkbox
Click on run flow! Button.
When the text box appears, the component is correctly programmed.
56
Figure 32: space programmer view
ATMEL ATF697FF[USER GUIDE][DRAFT]
41002Ad1 – AERO 04/12
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57
ATMEL ATF697FF[USER GUIDE][DRAFT]
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