TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com 4.5-V to 18-V, 3-A OUTPUT SYNCHRONOUS STEP DOWN SWITCHER WITH INTEGRATED FET ( SWIFT™) Check for Samples: TPS54325-Q1 FEATURES 1 • • 23 • • • • • • • • Qualified for Automotive Applications D-CAP2™ Mode Enables Fast Transient Response Low Output Ripple and Allows Ceramic Output Capacitor Wide VCC Input Voltage Range: 4.5 V to 18 V Wide VIN Input Voltage Range: 2.0 V to 18 V Output Voltage Range: 0.76 V to 5.5 V Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications –120 mΩ (High Side) and 70 mΩ (Low Side) High Efficiency, less than 10 μA at shutdown High Initial Bandgap Reference Accuracy Adjustable Soft Start • • • • Pre-Biased Soft Start 700-kHz Switching Frequency (fSW) Cycle By Cycle Over Current Limit Power Good Output APPLICATIONS • Wide Range of Applications for Low Voltage System – Digital TV Power Supply – High Definition Blue-ray Disc™ Players – Networking Home Terminal – Digital Set Top Box (STB) DESCRIPTION The TPS54325-Q1 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325-Q1 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The main control loop for the TPS54325-Q1 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325-Q1 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325-Q1 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 105°C. VOUT (50 mV / div) IOUT (2 A / div) 100 µs / div 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, D-CAP2, PowerPAD are trademarks of Texas Instruments. Blue-ray Disc is a trademark of Blu-ray Disc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 105°C (1) (2) PowerPAD™ (HTSSOP) – PWP ORDERABLE PART NUMBER TOP-SIDE MARKING TPS54325TPWPRQ1 54325Q1 Reel of 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VI Input voltage range VO Output voltage range Vdiff Voltage from GND to POWERPAD (1) VALUE UNIT VIN, VCC, EN –0.3 to 20 V VBST –0.3 to 26 V VBST (vs SW1, SW2) –0.3 to 6.5 V VFB, VO, SS, PG –0.3 to 6.5 V SW1, SW2 –2 to 20 V SW1, SW2 (10 ns transient) –3 to 20 V VREG5 –0.3 to 6.5 V PGND1, PGND2 –0.3 to 0.3 V Human Body Model (HBM) ESD rating Electrostatic discharge V 2 kV 1000 V TJ Operating junction temperature –40 to 150 °C Tstg Storage temperature –55 to 150 °C (1) Charged Device Model (CDM) –0.2 to 0.2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS54325-Q1 THERMAL METRIC (1) PWP UNITS 14 PINS θJA Junction-to-ambient thermal resistance 46.3 θJCtop Junction-to-case (top) thermal resistance 1.7 θJB Junction-to-board thermal resistance 31.1 ψJT Junction-to-top characterization parameter 36.6 ψJB Junction-to-board characterization parameter 7.2 θJCbot Junction-to-case (bottom) thermal resistance 31.4 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range, VCC, VIN = 12V (unless otherwise noted) MIN MAX UNIT VCC Supply input voltage range 4.5 18 V VIN Power input voltage range 2 18 V VBST –0.1 24 VBST (vs SW1, SW2) –0.1 6 SS, PG –0.1 6 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 VI Input voltage range –3 18 PGND1, PGND2 –0.1 0.1 SW1, SW2 (10 ns transient) V VO Output voltage range VREG5 –0.1 6 V IO Output Current range IVREG5 0 10 mA TA Operating free-air temperature –40 105 °C TJ Operating junction temperature –40 125 °C TYP MAX UNIT 850 1300 μA 10 μA ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN SUPPLY CURRENT IVCC Operating - non-switching supply current VCC current, TA = 25°C, EN = 5 V, VFB = 0.8 V IVCCSDN Shutdown supply current VCC current, TA = 25°C, EN = 0 V LOGIC THRESHOLD VENH EN high-level input voltage EN VENL EN low-level input voltage EN 2 V 0.4 V VFB VOLTAGE AND DISCHARGE RESISTANCE VFBTH VFB threshold voltage TA = 25°C, VO = 1.05 V 757 TA = 0°C to 105°C, VO = 1.05 V (1) 753 777 TA = -40°C to 105°C, VO = 1.05 V (1) 750 780 IVFB VFB input current VFB = 0.8 V, TA = 25°C RDischg VO discharge resistance EN = 0 V, VO = 0.5 V, TA = 25°C 765 775 mV 0 ±0.1 μA 50 100 Ω 5.5 5.7 V 20 mV 100 mV VREG5 OUTPUT VVREG5 VREG5 output voltage TA = 25°C, 6.0 V < VCC < 18 V, 0 < IVREG5 < 5 mA VLN5 Line regulation 6.0 V < VCC < 18 V, IVREG5 = 5 mA VLD5 Load regulation 0 mA < IVREG5 < 5 mA IVREG5 Output current VCC = 6 V, VREG5 = 4.0 V, TA = 25°C Rdsonh High side switch resistance 25°C, VBST - SW1, SW2 = 5.5 V Rdsonl Low side switch resistance 25°C 5.3 70 mA 120 mΩ 70 mΩ MOSFET CURRENT LIMIT Iocl Current limit TA = 25°C to 105°C TA = -40°C 3.5 4.1 3.25 3.5 A THERMAL SHUTDOWN TSDN (1) Thermal shutdown threshold Shutdown temperature Hysteresis (1) (1) 150 25 °C Not production tested. Copyright © 2011, Texas Instruments Incorporated 3 TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL TON On time VIN = 12 V, VO = 1.05 V 145 ns TOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 ns SOFT START ISSC SS charge current VSS = 0 V 1.4 2.0 ISSD SS discharge current VSS = 0.5 V 0.1 0.2 VFB rising (good) 85 90 2.6 μA mA POWER GOOD VTHPG PG threshold IPG PG sink current VFB falling (fault) 95 85 PG = 0.5 V 2.5 5 115 120 % mA OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold TOVPDEL Output OVP prop delay VUVP Output UVP trip threshold TUVPDEL Output UVP delay TUVPEN Output UVP enable delay OVP detect 125 UVP detect 65 Hysteresis 70 75 10 0.25 Relative to soft-start time % μs 5 % ms x 1.7 UVLO VUVLO UVLO threshold Wake up VREG5 voltage 3.45 3.70 3.95 Hysteresis VREG5 voltage 0.15 0.25 0.35 V DEVICE INFORMATION PWP PACKAGE (TOP VIEW) VO 1 14 VCC VFB 2 13 VIN VREG5 3 12 VBST 11 SW2 SW1 POWERPAD TPS54325 SS 4 GND 5 10 PG 6 9 PGND2 EN 7 8 PGND1 PWP HTSSOP14 TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION VO 1 Connect to output of converter. This terminal is used for On-Time Adjustment. VFB 2 Converter feedback input. Connect with feedback resistor divider. VREG5 3 5.5 V power supply output. A capacitor (typical 1μF) should be connected to GND. SS 4 Soft-start control. A external capacitor should be connected to GND. GND 5 Signal ground pin 4 Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME DESCRIPTION NO. PG 6 Open drain power good output EN 7 Enable control input PGND1, PGND2 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and GND strongly together near the IC. 8, 9 SW1, SW2 Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current comparators. 10, 11 VBST 12 Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin. VIN 13 Power input and connected to high side NFET drain VCC 14 Supply input for 5 V internal linear regulator for the control circuitry PowerPAD™ Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to PGND. Back side FUNCTIONAL BLOCK DIAGRAM -30% UV VCC 14 OV 1 VO VIN 13 +20% 12 SS VREG5 SGND 1 µF 11 10 2 Ceramic Capacitor 9 8 4 Softstart PGND PGND GND SGND Ref 6 VCC -10% UV VREG5 7 PGND SW SS EN VO 1.5 µH 3 5 10 µH SW SS PG VBST 0.1 µF Ref VFB VIN EN Logic Copyright © 2011, Texas Instruments Incorporated OV UVLO UVLO Protection Logic TSD REF Ref 5 TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com OVERVIEW The TPS54325-Q1 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types. DETAILED DESCRIPTION PWM Operation The main control loop of the TPS54325-Q1 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control. PWM Frequency and Adaptive On-Time Control TPS54325-Q1 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54325-Q1 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant. Soft Start and Pre-Biased Soft Start The TPS54325-Q1 has an adjustable soft start . When the EN pin becomes high, 2.0-μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 2 μA. C6(nF) • Vref C6(nF) • 0.765 Tss(ms) = − = − Iss(µA) 2 (1) The TPS54325-Q1 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage (VFB), the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. Power Good The TPS54325-Q1 has power-good output. The power-good function is activated after soft start has finished. If the output voltage becomes within -10% of the target value, internal comparators detect power good state and the power good signal becomes high. During start up, power good start after 1.7 times soft-start time to avoid a glitch of power-good signal. If the feedback voltage goes under 15% of the target value, the power good signal becomes low after 10 μs internal delay. Output Discharge Control The TPS54325-Q1 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO and thermal shutdown). The device discharges outputs using an internal 50-Ω MOSFET which is connected to VO and PGND. The internal low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. 6 Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com Current Protection The TPS54325-Q1 has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current trip level. In order to provide both good accuracy and cost effective solution, the device supports temperature compensated internal MOSFET RDS(on) sensing. The inductor current is monitored by the voltage between PGND pin and SW1/SW2 pin. In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and shutdown. Over/Under Voltage Protection The TPS54325-Q1 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver turns off and the low-side MOSFET turns on. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 μs, the device latches off both internal top and bottom MOSFET. This function is enabled approximately 1.7 x soft-start time. UVLO Protection The TPS54325-Q1 has under voltage lock out protection (UVLO) that monitors the voltage of VREG5 pin. When the VREG5 voltage is lower than UVLO threshold voltage, the TPS54325-Q1 is shut off. This is non-latch protection. Thermal Shutdown The TPS54325-Q1 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 150°C), the device is shut off. This is non-latch protection. TYPICAL CHARACTERISTICS 1200 8 IVCCSDN - Shutdown Current - µA IVCC - Supply Current - µA 1000 800 600 400 200 0 -50 0 50 100 TJ - Junction Temperature - °C Figure 1. VCC TEMPERATURE vs. JUNCTION TEMPERATURE Copyright © 2011, Texas Instruments Incorporated 150 6 4 2 0 -50 0 50 100 150 TJ - Junction Temperature - °C Figure 2. VCC SHUTDOWN CURRENT vs. JUNCTION TEMPERATURE 7 TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.100 1.075 VI = 18 V 1.050 VI = 12 V 1.025 VI = 5.5 V Vout - Output Voltage - V VOUT - Output Voltage - V 1.100 1.075 Io = 0 A 1.050 Io = 1 A 1.025 1.000 1.000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 IOUT - Output Current - A 10 15 20 VIN - Input Voltage - V Figure 3. 1.05-V OUTPUT VOLTAGE vs. OUTPUT CURRENT VOUT (50 mV / div) Figure 4. 1.05-V OUTPUT VOLTAGE vs. INPUT VOLTAGE EN (10 V / div) VOUT (0.5 V / div) IOUT (2 A / div) PG (5 V / div) 100 µs / div Figure 5. 1.05-V, 0-A TO 3-A LOAD TRANSIERESPONSE 8 400 µs / div Figure 6. START-UP WAVE FORM Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 100 80 70 60 50 40 0.0 fSW - Switching Frequency - kHz Efficiency - % 90 900 VO = 3.3 V ॰ ! ! ! ! ⑰ " " # " $ VO = 2.5 V VO = 1.8 V 800 VO = 1.8 V 700 600 VO = 3.3 V 500 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 VIN - Input Voltage - V Iout - Output Current - A Figure 7. EFFICIENCY vs. OUTPUT CURRENT (VIN = 12 V) Figure 8. SWITCHING FREQUENCY vs. INPUT VOLTAGE (IO=1 A) 900 fSW - Switching Frequency - kHz VO = 1.05 V VO (10 mV / div) 800 VO = 1.8 V 700 VO = 2.5 V SW (5 V / div) 600 500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 IO - Output Current - A Figure 9. SWICHING FREQUENCY vs. OUTPUT CURRENT Copyright © 2011, Texas Instruments Incorporated Figure 10. VOLTAGE RIPPLE AT OUTPUT 9 TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VO = 1.05 V VIN (50 mV / div) SW (5 V / div) Figure 11. VOLTAGE RIPPLE AT INPUT 10 Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • • • begin the design process, you must define these parameters for your application as follows: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple Output Inductor Selection The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improves S/N ratio and contributes to stable operation. Smaller ripple currents result in lower output voltage ripple. When using low ESR output capacitors output ripple voltage is usually low, so larger ripple currents are acceptable. The coefficient Kind represents the percentage of ripple current. The value of Kind must not be greater than 0.4. Use 0.3 when using low ESR output capacitors. Equation 2 can be used to calculate L1. Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS current of Equation 5. VOUT VIN (max) - VOUT •− LO = − VIN (max) IOUT • fSW • Kind (2) VOUT VIN (max) - VOUT • Ilp - p = V L •f (3) IN (max) O SW Ilp - p Ilpeak = IO + 2 − 1 Ilp - p2 ILo(RMS) = IO2 + − 12 √ (4) (5) Output Capacitor Selection The capacitor value and ESR determines the amount of output voltage ripple. Recommended to use ceramic output capacitor. Using Equation 6 to Equation 8, an initial estimate for the capacitor value, ESR, and RMS current can be calculated. If the load transients are significant consider using the load step, instead of ripple current to calculate the maximum ESR. Minimum CO should be over 20 μF. 1 •− 1 CO > − 8 • fSW VO(ripple) - RESR − I(ripple) (6) VO(ripple) RESR < − Il(ripple) (7) VOUT • (VIN - VOUT) ICO(RMS) =− − √12 • VIN • LO • fSW (8) ( ) Input Capacitor Selection The TPS54325-Q1 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage. In case of separate VCC and VIN, then a ceramic capacitor over 10 μF is recommended for the VIN and also placing ceramic capacitor over 0.1 μF for the VCC is recommended. Copyright © 2011, Texas Instruments Incorporated 11 TPS54325-Q1 SLVSAT1 – JUNE 2011 www.ti.com Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommended to use a ceramic capacitor. VREG5 Capacitor Selection A 1-μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommended to use a ceramic capacitor. Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1% tolerance or better divider resistors. Start by using Equation 9 and Equation 10 to calculate VOUT. To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable. For output voltage from 0.76 V to 2.5 V: R1 VOUT = 0.765 • 1 + − R2 ( ) (9) For output voltage over 2.5 V: R1 VOUT = (0.763 + 0.0017 • VOUT) • 1 + − R2 ( ) (10) THERMAL INFORMATION This PowerPAD™ package incorporates an exposed thermal pad that is designed to be connected to an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating abilities, refer to Technical Breif, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004. The exposed thermal pad dimensions for this package are shown in the following illustration. 8 14 Thermal Pad 2.46 ° 7 1 2.31 Figure 12. Thermal Pad Dimensions 12 Copyright © 2011, Texas Instruments Incorporated TPS54325-Q1 www.ti.com SLVSAT1 – JUNE 2011 LAYOUT CONSIDERATIONS 1. Keep the input switching current loop as small as possible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 3. Keep analog and non-switching components away from switching components. 4. Make a single point connection from the signal ground to power ground. 5. Do not allow switching current to flow under the device. 6. Keep the pattern lines for VIN and PGND broad. 7. Exposed pad of device must be connected to PGND with solder. 8. VREG5 capacitor should be placed near the device, and connected PGND. 9. Output capacitor should be connected to a broad pattern of the PGND. 10. Voltage feedback loop should be as short as possible, and preferably with ground shield. 11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND. 12. Providing sufficient via is preferable for VIN, SW and PGND connection. 13. PCB pattern for VIN, SW, and PGND should be as broad as possible. 14. If VIN and VCC is shorted, VIN and VCC patterns need to be connected with broad pattern lines. 15. VIN Capacitor should be placed as near as possible to the device. Copyright © 2011, Texas Instruments Incorporated 13 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device TPS54325TPWPRQ1 Status (1) ACTIVE Package Type Package Drawing HTSSOP PWP Pins Package Qty 14 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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