SC1218 High Speed Synchronous MOSFET Driver POWER MANAGEMENT Description Features Advanced Digital Timing to Filter Out Very Narrow PWM The SC1218 is a high speed, robust, dual output driver to drive high-side and low-side N-MOSFETs in synchronous buck converters. Combined with Semtech’s multi-phase PWM controller SC2649, one can build high performance, versatile voltage regulators for next generation microprocessors. SC1218 is built upon a CMOS technology which provides enough voltage capacity to handle computer applications. In addition, the advanced timing circuitry is adopted to filter out very narrow PWM pulses at the input of the driver. The latched UVLO and enhanced adaptive shoot-through protection further enhance the robustness of the SC1218. With integrated bootstrap diode, the SC1218 is offered in both SOIC-8 package and MLPQ-8 3x3mm package. These features further reduce the thermal stress and BOM cost. Pulses +12V Gate Drive Voltage Integrated Bootstrap Diode High Peak Drive Current Adaptive Non-overlapping Gate Drives Provide Shootthrough Protection Support Dynamic VID operation Ultra-low Propagation Delay Floating Top Gate Drive Crowbar Function for Over Voltage Protection High Frequency (up to 2 MHz) Operation Allows Use of Small Inductors and Low Cost Ceramic Capacitors Under Voltage Lockout Low Quiescent Current Enable Function for Both Gate OFF Shut Down Lead-free Part and Fully WEEE and RoHS Compliant Applications Intel Next Generation Processor Power Supplies AMD AthlonTM and AMD-K8TM Processor Power Supplies High Current Low Voltage DC-DC Converters Typical Application Circuit VIN Cbst Mtop Cin 1uF BST TG PWM CO DRN EN EN PGND Rv in VIN 2R2 Revision: October 14, 2005 Cv in 1uF BG SC1218 1 Lout Rdrn VOUT (optional) Mbot Cout www.semtech.com SC1218 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units VI N -0.3 to 16 V BST to DRN VBST-DRN -0.3 to 16 V BST to VIN VBST-VIN -0.3 to 16 V TG to DRN VTG-DRN -0.3 to 16 V -2 V -0.3 to VIN+16 V VIN Supply Voltage TG to DRN Pulse Conditions VPEAK w ith tPULSE < 20ns(1) VTG-DRN-PULSE BST to PGND VBST-PGND BST to PGND Pulse DRN to PGND DRN to PGND Pulse VBST-PGND-PULSE tPULSE <20ns 38 V VDRN-PGND VBST-VDRN = 10V -2 to VIN+16 V VPEAK w ith tPULSE < 200ns(1) -5 to 35 V VPEAK w ith tPULSE < 20ns(1) -8 to 35 V -0.3 to VIN+0.3 V -3.5 V VDRN-PGND-PULSE BG to PGND VBG-PGND BG to PGND Pulse VPEAK w ith tPULSE < 20ns(1) VBG-PGND-PULSE PWM Input CO -0.3 to VIN+0.3 V Enable Input EN -0.3 to VIN+0.3 V Continuous Pow er Dissipation TA=25oC, TJ=125oC PD Thermal Resistance Junction to Case θJC Junction Temperature Range TJ 0 to 150 o Storage Temperature Range TSTG -65 to 150 o TLEAD SOIC-8 300 o Lead Temperature (Soldering) 10 Sec. MLPQ-8 260 o SOIC-8 0.5 MLPQ-8 2.56 SOIC-8 40 MLPQ-8 8 W C/W o C C C C Notes: (1) Pulse width measured at 10% of the triangular spike waveform. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required. Electrical Characteristics Unless specified: TA = 25°C; VIN = 12V. Parameter Symbol Conditions M in Typ M ax Units 5 12 14 V EN=5V; CO=0V 3.35 4.4 mA EN=5V; CO=5V 2.9 4 mA EN=0V 1.35 2.5 mA Power Supply Supply Voltage VI N Quiescent Current 2005 Semtech Corp. VI N IQ 2 www.semtech.com SC1218 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C; VIN = 12V. Parameter Symbol Conditions M in Typ M ax Units 4.3 V Under Voltage Lockout Start Threshold of VIN Voltage VIN_START 4 Hysteresis VhysUVLO 250 mV EN Logic High Input Voltage VEN_H Logic Low Input Voltage VEN_L 2.65 V 0.8 V CO Logic High Input Voltage VCO_H Logic Low Input Voltage VCO_L 2.9 V 0.8 Internal Pull-down Resistor 40 V Kohm High Side Driver (TG) Output Impedence RSRC_TG RSINK_TG VBST-VDRN= 12V 1.68 2.1 Oh m 0.52 0.78 Oh m ISRC_TG_PK VIN=12V, CTG=10nF 2.8 A ISINK_TG_PK VIN=12V, CTG=10nF 6.5 A Propagation Delay, TG Going High tPDH_TG VBST-VDRN= 12V 37 ns Propagation Delay, TG Going Low tPDL_TG VBST-VDRN= 12V 50 ns tON_MIN_TG For CO pulse width < 40ns 40 ns Output Peak Current TG Minimum On-time(1) Low Side Driver (BG) Output Impedence RSRC_BG RSINK_BG VIN = 12V 1.36 2.0 Oh m 0.52 0.78 Oh m ISRC_BG_PK VIN=12V, CBG=10nF 3.5 A ISINK_BG_PK VIN=12V, CBG=10nF 7.5 A Propagation Delay, BG Going High tPDH_BG VIN = 12V 20 ns Propagation Delay, BG Going Low tPDL_BG VIN = 12V 27 ns BG Minimum OFF-time(1) tOFF_MIN_BG For CO pulse width < 40ns 140 ns BG Maximum Turn ON Delay(1) tDH_MAX_BG From CO=Low, VDRN>1V 175 ns Output Peak Current NOTE: (1). Guaranteed by design. 2005 Semtech Corp. 3 www.semtech.com SC1218 POWER MANAGEMENT Timing Diagrams VCO_HI CO VCO_LO TG tPDL_TG tPDH_TG BG 1.4V tPDL_BG tPDH_BG DRN 1.0V VIN & EN VIN>UVLO & EN=“HI” 2005 Semtech Corp. Rising Edge Transition Falling Edge Transition 4 www.semtech.com SC1218 POWER MANAGEMENT Pin Configuration MLPQ-8 3x3mm Top View SOIC-8 Top View BST TG BST 1 8 TG CO 2 7 DRN CO 1 6 DRN EN 3 6 PGND EN 2 5 PGND VIN 4 5 BG 8 3 7 4 VIN BG EXPOSED PAD MUST BE SOLDERED TO POWER GROUND PLANE Pin Descriptions SOIC-8 M LPQ-8 Pin Name 1 8 BST Bootstrap supply pin for the top gate drive. Connect a 1uF ceramic capacitor between BST and DRN pin to develop a floating bootstrap voltage for the high side driver. 2 1 CO PWM input signal from external controller. An internal 40Kohm resistor is connected from this pin to the PGND. 3 2 EN When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced low. 4 3 VIN Supply power for the bottom gate driver and the internal control circuitry. Connect to input power rail of the converter and dcouple with a 1µF ceramic with lead length no more than 0.2" (5mm). 5 4 BG Output gate drive for the bottom (synchronous) MOSFET. An internal 20Kohm resistor is connected from this pin to PGND. 6 5 PGND Supply power ground return. Keep this pin close to the bottom MOSFET source during layout. Connect this pin to the power phase node of the synchronous buck converter (source of top MOSFET and drain of bottom MOSFET). The DRN pin provides a return path for top gate drive. Its voltage is deteced for adaptive shoot-through protection. This pin is subjected to a negative spike of -8V relative to PGND without affecting the operation. An internal 20Kohm resistor is connected from this pin to PGND. 7 6 DRN 8 7 TG Pin Function Output gate drive for the top (switching) MOSFET. Ordering Information Device Package Temp Range (TJ) SC1218STRT (1)(3) SOIC-8 0° to 150°C SC1218MLTRT (2)(3) MLPQ-8 0° to 150°C Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Only available in tape and reel packaging. A reel contains 3000 devices. (3) Devices are lead-free and fully WEEE and RoHS compliant. 2005 Semtech Corp. 5 www.semtech.com SC1218 POWER MANAGEMENT Block Diagram VIN BST UVLO TG EN CONTROL & OVERLAP PROTECTION CIRCUIT CO DRN R R BG PGND R Typical Performance Characteristics CO CO TG TG BG BG Fig. 1. TG Rise and BG Fall Times 2005 Semtech Corp. Fig. 2. TG Fall and BG Rise Times 6 www.semtech.com SC1218 POWER MANAGEMENT Typical Performance Characteristics (Cont.) 25 20 VIN=12V VIN=12V CLoad=3.3nF TA=25°C TG 20 19 FALL TIME (ns) RISE TIME (ns) BG 18 17 TG BG 15 10 5 16 0 15 0 25 50 75 100 0 125 2 4 TEMPERATURE (°C) 160 VIN=12V 10 CLoad=3.3nF VIN=12V 140 TG SUPPLY CURRENT (mA) 10 FALL TIME (ns) 8 Fig. 6. TG and BG Fall Times vs. Load Capacitance. Fig. 3. TG and BG Rise Times vs. Temperature. 11 6 LOAD CAPACITANCE (nF) 9 BG 8 7 CLoad_TG=3.3nF CLoad_BG=3.3nF 120 TA=25°C 100 80 60 40 20 6 0 0 25 50 75 100 125 0 200 400 TEMPERATURE (°C) Fig. 4. TG and BG Fall Times vs. Temperature. 27 VIN=12V 1000 1200 1400 1600 VIN=12V TG TA=25°C CLoad_TG=3.3nF 40 RISE TIME (ns) 800 Fig. 7. Supply Current vs. Frequency. SUPPLY CURRENT (mA) 50 600 FREQUENCY (KHz) BG 30 20 10 26 CLoad_BG=3.3nF Freq.=200KHz 25 24 23 22 0 0 2 4 6 8 0 10 50 75 100 125 Fig. 8. Supply Current vs. Temperature. Fig. 5. TG and BG Rise Times vs. Load Capacitance. 2005 Semtech Corp. 25 TEMPERATURE (°C) LOAD CAPACITANCE (nF) 7 www.semtech.com SC1218 POWER MANAGEMENT Typical Performance Characteristics (Cont.) 4.5 9.0 CLOAD_TG=10nF 4.0 CLOAD_BG=10nF 3.5 TA=25°C BG 2.5 C LOAD_BG=10nF 7.0 TA=25°C BG TG 6.0 TG ISINK_PK (A) ISRC_PK (A) 3.0 C LOAD_TG=10nF 8.0 2.0 5.0 4.0 1.5 3.0 1.0 2.0 0.5 1.0 0.0 0.0 5 6 7 8 9 10 11 12 13 14 5 VIN (V) 7 8 9 10 11 12 13 14 VIN (V) Fig. 10. Peak Sinking Current vs. Supply Voltage. Fig. 9. Peak Sourcing Current vs. Supply Voltage. 2005 Semtech Corp. 6 8 www.semtech.com SC1218 POWER MANAGEMENT Applications Information narrow pulse for the driver. The pulse is so narrow that it reaches the rising edge threshold of the SC1218 at one point then immediately falls below the falling edge threshold. To prevent the SC1218 from reacting to such narrow PWM pulses, which may cause driver output ringing or shoot through, advanced PWM timing circuitry is added to ease the gate transitions. A minimum off-time (typically 140ns) for the bottom gate and a minimum on-time (typically 40ns) for the top gate are enforced to make the operation safe under such conditions. THEOR Y OF OPERA TION THEORY OPERATION The SC1218 is a high speed, robust, dual output driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features internal bootstrap diode, adaptive delay for shoot-through protection, 12V gate drive voltage, and disable shutdown. It also supports dynamic VID operation and CROWBAR function. This driver combined with PWM controller SC2649 forms a multi-phase voltage regulator for advanced microprocessors. Star tup and UVL O Startup UVLO To startup the driver, a supply voltage is applied to the VIN pin of the SC1218. The top and bottom gates are held low until VIN exceeds the UVLO threshold of the driver, typically 4.0V. The UVLO threshold has hysteresis, typically -250mV, to improve the nosie immunity from the VIN pin. Dynamic VID Operation Some processors changes VID dynamically during operation (Dynamic VID operation). A dynamic VID can occur under light load or heavy load conditions. At light load, it can force the converter to sink current. After turn-off of the top FET, the reversed inductor current flows through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high and voids the adaptive circuit. SC1218 features a maximum BG turn on delay (tDH_MAX_BG) to override the adaptive delay to turn the bottom FET on. The preset maximum BG turn on delay time (tDH_MAX_BG) from the PWM falling egde to the bottom gate turn-on is set to be 175ns. Gat e TTransition ransition and Shoo t-thr ough Pr o t ection Gate Shoot-thr t-through Pro Refer to the Timing Diagrams section, the rising edge of the PWM input initiates the turn-off of bottom FET and the turn-on of top FET. After a short propagation delay (tPDL_BG) from PWM rising edge, the bottom gate falls (tF_BG). The adaptive circuit in the SC1218 detects the bottom gate voltage. It holds the top gate off until the bottom gate voltage drops below 1.4V for a preset delay time (tPDH_TG). This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, depended on the direction of the inductor current. The phase node could be low (ground) or high (VIN). Switching FFreq req uency or and MOSFET requency uency,, Induct Inductor MOSFETss The SC1218 is capable of providing more than 3.5A peak drive current, and operating up to 2MHz PWM frequency without causing thermal stress on the driver. The selection of switching frequency, together with inductor and FETs is a trade-off between the cost, size, and thermal management of a multi-phase voltage regulator. Typically, these parameters could be in the range of: The falling edge of the PWM input controls the turn-off of top FET and the turn-on of bottom FET. After a short propagation delay (tPDL_TG) from PWM falling edge, the top gate falls (tF_TG). As the inductor current commutates from the top FET to the body diode of the bottom FET, the phase node falls. The adaptive circuit in the SC1218 detects the phase node voltage. It holds the bottom FET off until the phase node voltage drops below 1.0V. This prevents the top and bottom FETs from conducting simultaneously (shoot-through). If the phase node voltage remains high during the transition for a preset maximum BG turn on delay (tDH_MAX_BG) , then the bottom gate will be turned on. This supports the CROWBAR function and the sinking current capacity required from dynamic VID operation. a) Switching Frequency: 100kHz to 500kHz per phase b) Inductor Value: 0.2uH to 2uH c) MOSFETs: 4mOhm to 20mOhm RDS(ON) and 20nC to 100nC total gate charge Bootstrap and Chip Decoupling Capacitors The top gate driver of the SC1218 is a DRN refered gate drive whose supply voltage is derived from a bootstrap circuit comprising a capacitor,CBST, and a built-in diode. The capacitor value can be calculated based on the total gate charge of the top FET, QTOP, and an allowed voltage ripple on the capacitor, ∆VBST, in one PWM cycle: Narrow PWM Pulse Filtering During a load transient, soft start, or soft shutdown of the voltage regulator, the PWM controller may generate a very 2005 Semtech Corp. C BST > 9 QTOP ∆VBST www.semtech.com SC1218 POWER MANAGEMENT Applications Information (Cont.) The typical layout examples of SC1218 based on above guidelines are shown in Fig.12 and Fig.13. Typically, a 1uF/16V ceramic capacitor is used. In addition, a small resistor (one ohm) is recommended in between DRN pin of the SC1218 and the phase node. The resistor is used to alleviate the stress of the SC1218, resulting from the negative spike at the phase node, and also to control the switching speed. A negative spike could occur at the phase node during the top FET turn-off due to parasitic inductance in the switching loop. The spike could be minimized with a careful PCB layout. In the applications with TO-220 package FETs, it is suggested to use a clamping diode on the DRN pin to mitigate the impact of the excessive phase node negative spikes. 1000 Fsw=600kHz POWER DISSIPATION (mW) 800 For VIN pin of the SC1218, it is recommended to use a 1uF/16V ceramic capacitor for decoupling. 600 Fsw=400kHz 400 Fsw=200kHz 200 0 40 60 80 100 120 TOTAL GATE CHARGE (nC) Driv er Dissipation and Junction TTem em perature Driver emperature The driver power dissipation is a function of chip quiescent current IQ, switching frequency FSW, and supply voltage VIN. It is approximated as: Fig. 11. Power dissipation. C BST PD = ( I Q + QTOTAL ⋅ FSW ) ⋅VIN To top FET RDRN where QTOTAL is the total gate charge of the top-side and bottom-side FETs. The power dissipation vs total gate charge at the given switching frequency is plotted in Fig.11. The driver junction temperature can be calculated based on the juntion to case thermal resistance and Printed Circuit Board (PCB) temperature. PWM To phase node To bottom FET R VIN C VIN LA YOUT GUIDELINES LAY The switching regulator is a high di/dt and dv/dt power circuit. PCB layout is critical. A good layout can achieve optimum circuit performance with minimized component stress, resulting in better system reliability. For a multiphase voltage regulator, the SC1218 driver, FETs, inductor, and supply decoupling capacitors in each phase have to be considered as a unit. For the SC1218 driver, the following guidelines are typically recommended during PCB layout: Fig. 12. Component placement for SOIC-8 VIN PWM To Top FET RVIN a) Place the SC1218 close to the FETs for shortest gate drive traces and ground return paths; b) Connect decoupling capacitor as close as possible to the VIN pin and the PGND pin. The trace length of the capacitor on the VIN pin should be no more than 0.2” (5mm); and c) Locate the bootstrap capacitor close to the SC1218. 2005 Semtech Corp. CBST To Phase Node RDRN CVIN To Bottom FET EN Fig. 13. Component placement for MLPQ-8. 10 www.semtech.com SC1218 POWER MANAGEMENT Outline Drawing - SOIC-8 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A D e N 2X E/2 E1 E 1 2 ccc C 2X N/2 TIPS .069 .053 .010 .004 .065 .049 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc e/2 B D aaa C SEATING PLANE h A2 A C A1 bxN bbb 1.35 1.75 0.25 0.10 1.65 1.25 0.31 0.51 0.25 0.17 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 8 0° 8° 0.10 0.25 0.20 h H C A-B D c GAGE PLANE 0.25 SEE DETAIL L (L1) A DETAIL SIDE VIEW 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AA. Land Pattern - SOIC-8 X DIMENSIONS INCHES MILLIMETERS DIM (C) G Z Y P 2005 Semtech Corp. (.205) .118 .050 .024 .087 .291 C G P X Y Z (5.20) 3.00 1.27 0.60 2.20 7.40 NOTES: 11 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. www.semtech.com SC1218 POWER MANAGEMENT Outline Drawing - MLPQ-8, 3 x 3mm A D B Top View PIN 1 INDICATOR (LASER MARK) DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX E 0 A2 A aaa C A .032 .040 A1 .000 .002 .008 BSC A2 .012 b .007 .118 BSC D .071 D2 .059 .071 E2 .059 .118 BSC E e .026 BSC L .012 .016 .020 K .008 8 N 0 0° 12° aaa .003 .008 bbb A1 SEATING PLANE C D2 e/2 Bottom View 0.08 1.00 0.00 0.05 0.20 REF 0.19 0.30 3.00 BSC 1.50 1.80 1.50 1.80 3.00 BSC 0.65 BSC 0.30 0.40 0.50 0.20 8 0° 12° 0.08 0.20 L E/2 E2 2 1 N K e b bbb D/2 C A B Land Pattern - MLPQ-8, 3 x 3mm H DIM (C) K G Z Y X P/2 P C G H K P X Y Z DIMENSIONS INCHES MILLIMETERS (.122) .089 .073 .073 .026 .014 .033 .156 (3.10) 2.25 1.85 1.85 0.65 0.35 0.85 3.95 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. THE VIAS ON THE CENTER PAD SHOULD MAINTAIN THE GOOD THERMAL CONTACT OF THE DEVICE TO THE PCB GROUND PLANE. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 12 www.semtech.com