SC1211 High Speed, Combi-SenseTM Synchronous MOSFET Driver POWER MANAGEMENT Description Features u High efficiency u +12V supply voltage with internal LDO for optimum The SC1211 is a high speed, Combi-SenseTM, dual output driver designed to drive high-side and low-side MOSFETs in a synchronous Buck converter. These drivers combined with Combi-Sense PWM controllers, such as Semtech SC2643VX or SC2643, provide a cost effective multi-phase voltage regulator for advanced microprocessors. gate drive u High peak drive current u Adaptive non-overlapping gate drives provide u u The Combi-SenseTM is a technique to sense the inductor current for peak current mode control of voltage regulator without using sensing resistor. It provides the following advantages: - No costly precision sensing resistor - Lossless current sensing - High level noise free signal - Fast response - Suitable for wide range of duty cycle - Only two small signal components (third optional) The detailed explanation of the technique can be found in the Applications Information section. u u u u u u shoot-through protection Support Combi-SenseTM and VID-on-fly operations Fast rise and fall times (15ns typical with 3000pf load) Ultra-low (<30ns) propagation delay (BG going low) Floating top gate drive Crowbar function for over voltage protection High frequency (to 1.5 MHz) operation allows use of small inductors and low cost ceramic capacitors Under-voltage-lockout Low quiescent current Applications A 30ns max propagation delay from input transition to the gate of the power FET’s guarantees operation at high switching frequencies. Internal overlap protection circuit prevents shoot-through from Vin to PGND in the main and synchronous MOSFETs. The adaptive overlap protection circuit ensures the bottom FET does not turn on until the top FET source has reached 1V, to prevent crossconduction. u Intel Pentium® processor power supplies u AMD AthlonTM and AMD-K8TM processor power supplies u High current low voltage DC-DC converters 8.5V gate drive provides optimum enhancement of MOSFETs at minimum driver and MOSFET switching loss. High current drive capability allows fast switching, thus reducing switching losses at high (up to 1.5MHz) frequencies without causing thermal stress on the driver. Under-voltage-lockout and over-temperature shutdown features are included for proper and safe operation. Timed latches and improved robustness are built into the housekeeping functions such as the Under Voltage Lockout and adaptive Shoot-through protection circuitry to prevent false triggering and to assure safe operation. The SC1211 is offered in a Power SOIC-8L package. October 12, 2003 1 www.semtech.com C13 2 VID0 VID1 VID2 1uF C30 1 2 6 3 5 4 VPN1 U4 D1N4148 D3 4.7uF C26 DRN TG BG VREG BST VIN CO VPN 8 4.7uF 7 C35 VPN2 C38 1nF 9 VPN1 C39 1nF 1R0 R22 SC1211 9 100 R28 Q5 VIN 100 R27 Q3 VIN 100 R26 C3 C1 C31 Q6 4.7uF Q4 1500uF 4.7uF 2.2nF C34 1R0 R23 L4 + 900nH 1500uF C28 2.2nF C25 1R0 R19 L3 + 900nH C15 2.2nF C8 1R0 R3 L2 + 900nH 1500uF C17 Q2 4.7uF 1 PGND 1R0 R15 SC1211 VPN3 C37 1nF SC1211 9 1R0 R2 Q1 2 P4GND VCORE 3.7k VPN2 PGND 7 VID3 0.1uF R21 8 SC2643VX 13 14 C23 VPN VID1 VID0 15 U3 VIN VID2 VID3 VID5 PGOOD 10k R17 VREG 12 11 1uF VID4 VCC 250k R18 CO 10 16 17 18 BST C22 OSCREF AGND 1uF C16 4.7uF C11 BG VID4 C36 DACSTEP FB D1N4148 D2 TG 0.1uF 9 8 7 19 20 21 22 23 24 PGND DRN 470pF R25 optional OUT1 OUT2 OUT3 OUT4 OUTSEN OS4 4 1uF C20 R16 GNDSEN ERROUT BGOUT OS1 U2 5 100k 6 5 4 OS2 OS3 3 C21 21.5k R13 500 3 2 1 VPN3 6 optional R20 R12 4.7nF VCORE R8 301 1uF 2 VID5 R10 33.2k R7 931 U1 D1N4148 C2 1 PGOOD VID_PWRGD 4.7nF C10 4.7nF 22.1k C7 3.3nF 4.7uF VPN 33.2k R11 22.1k 22.1k 2 C6 0.1uF C4 D1 CO R6 VPN3 VCC 2R2 R1 VIN R9 33.2k R5 R4 C12 VPN2 VPN1 10 R14 640nH VIN 0R0 R24 C5 C9 + L1 BST C14 + 4 VREG 7 C18 + 2003 Semtech Corp. TG 8 C19 + 3 BG C24 + 1 DRN C27 + 2 C29 + 1 1 C32 + 1 C33 + 2 + +12V P4GND 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V 1800uF/6.3V VCORE SC1211 POWER MANAGEMENT Typical Application Circuit 2 6 5 www.semtech.com SC1211 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units VI N 16 V BST to DRN VBST-DRN 11 V TG to DRN VTG-DRN -0.3 to 11 V -2 V 40 V 45 V -2 to 30 V VPEAK, tPULSE < 200ns (2) -5 to 35 V VPEAK, tPULSE < 20ns (2) -VREG to 35 V -0.3 to 11 V -3.5 V VREG-PGND 11 V VPN 16 V 20 V -0.3 to 8.5 V 2.56 W VI N Supply Voltage TG to DRN Pulse Conditions VPEAK, tPULSE < 20ns VTG-DRN-PULSE BST to PGND (2) VBST-PGND BST to PGND Pulse tPULSE < 100ns VBST-GND-PULSE DRN to PGND VDRN-PGND DRN to PGND Pulse VDRN-PGND-PULSE BG to PGND VBG-PGND BG to PGND Pulse VPEAK, tPULSE < 20ns VBG-PGND-PULSE VREG to PGND VPN to PGND VPN to PGND Pulse (2) tPULSE < 100ns VPN-PULSE PWM Input CO Continuous Pow er Dissipation PD Thermal Resistance Junction to Case θJC 8 °C/W Junction Temperature Range TJ 0 to +150 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C TA = 25°C, TJ =125°C NOTE: (1). This device is ESD sensitive. Use of standard ESD handling precautions is required. (2). Pulse width measured from 50% to 50% of peak voltage VPEAK. Electrical Characteristics Unless specified: TA = 25°C; VIN = 12V; VREG = 8.5V Parameter Symbol C onditions Min Typ Max U nits 9 12 15 V Pow er Supply Supply Voltage Qui escent C urrent, Operati ng VI N Iq_op 3.0 mA Start Threshold of VREG Voltage VREG_START 4 Hysteresi s VhysUVLO 160 mV U nder Voltage Lockout 4.3 V Internal LD O LD O Output VREG VI N = 9V to 15V 8.5 V D rop Out Voltage VDROP VI N = 5V to 8.8V 0.3 V 2003 Semtech Corp. 3 www.semtech.com SC1211 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C; VIN = 12V; VREG = 8.5V Parameter Symbol Conditions Min Typ Max Units CO Logic High Input Voltage VCO_H Logic Low Input Voltage VCO_L 2.0 V 0.8 V T hermal Shutdown Over Temperature Trip Point TOTP 155 °C Hysteresis THYST 10 °C High Side Driver (T G) Output Impedance RSRC_TG RSINK_TG VBST - VDRN = 8.5V 1.5 3.0 1.0 2.0 Ω Rise Time tR_TG CL = 3.3nF, VBST - VDRN = 8.5V 15 ns Fall Time tF_TG CL = 3.3nF, VBST - VDRN = 8.5V 10 ns Propagation Delay, TG Going High tPDH_TG VBST - VDRN = 8.5V 37 ns Propagation Delay, TG Going Low tPDL_TG VBST - VDRN = 8.5V 30 ns Low-Side Driver (BG) Output Impedance RSRC_BG RSINK_BG VREG = 8.5V 1.5 3.0 1.5 3.0 Ω Rise Time tR_BG CL = 3.3nF, VREG = 8.5V 10 ns Fall Time tF_BG CL = 3.3nF, VREG = 8.5V 10 ns Propagation Delay, BG Going High tPDH_BG VREG = 8.5V 20 ns Propagation Delay, BG Going Low tPDL_BG VREG = 8.5V 27 ns BG Minimum Off-time (1) tOFF_BG 75 ns VREG ramping up tPDH_UVLO 2 µs VREG ramping down tPDL_UVLO 2 µs Under-Voltage-Lockout T ime Delay NOTE: (1) Guaranteed by design. 2003 Semtech Corp. 4 www.semtech.com SC1211 POWER MANAGEMENT Timing Diagrams CO DRN 1.0V TG t PDH_TG BG t PDL_TG t F_TG tR_TG 1.4V t PDL_BG tF_BG tPDH_BG Rising Edge Transition 2003 Semtech Corp. tR_BG Falling Edge Transition 5 www.semtech.com SC1211 POWER MANAGEMENT Pin Configuration Ordering Information Top View Device (1) SC1211STR 1 8 BG TG 2 7 VREG BST 3 6 VIN CO 4 5 VPN PGND DRN P ackag e Temp Range (TJ) EDP SO-8 0° to 125°C Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. EXPOSED PAD MUST BE SOLDERED TO POWER GROUND PLANE (Power SOIC-8) Pin Descriptions Pin # Pin N ame 1 D RN 2 TG 3 BST Bootstrap pi n. A capaci tor i s connected between BST and D RN pi ns to develop the floati ng bootstrap voltage for the hi gh-si de MOSFET. The capaci tor value i s typi cally 1µF (cerami c). 4 CO Logi c level PWM i nput si gnal to the SC 1211 suppli ed by external controller. An i nternal 50kohm resi stor i s connected from thi s pi n to PGND . 5 VPN Vi rtual Phase Node. C onnect an RC between thi s pi n and the output sense poi nt to Enable C ombi -Sense TM operati on. See the Typi cal Appli cati on C i rcui t. 6 VIN Supply power for LD O and the i nternal C ombi -Sense converter. 7 VREG 8 BG PAD PGND 2003 Semtech Corp. Pin Function The power phase node (or swi tchi ng node) of the synchronous buck converter. Thi s pi n can be subjected to a negati ve spi ke up to -VREG relati ve to PGND wi thout affecti ng operati on. Output gate dri ve for the swi tchi ng (top) MOSFET. TM ci rcui try. C onnect to i nput power rai l of the LD O output. D ecouple wi th 1µF to 4.7µF (cerami c) wi th lead length no more than 0.2" (5mm). Output gate dri ve for the synchronous (bottom) MOSFET. Ground. Keep thi s pi n close to the synchronous MOSFETs source. 6 www.semtech.com SC1211 POWER MANAGEMENT Block Diagram VIN LDO UVLO LOGIC VREG VPN BST CO CONTROL & OVERLAP PROT ECTION CIRCUIT TG DRN BG PGND 2003 Semtech Corp. 7 www.semtech.com SC1211 POWER MANAGEMENT Applications Information THEOR Y OF OPERA TION THEORY OPERATION simultaneously or shoot-through. The SC1211 is a high speed, Combi-SenseTM, dual output driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features adaptive delay for shoot-through protection and VID-on-Fly operation; internal LDO for optimum gate drive voltage; and Virtual Phase Node for Combi-SenseTM solution. These drivers combined with PWM controller SC2643VX form a multi-phase voltage regulator for advanced microprocessors. A three-phase voltage regulator with 12V input 60A output is shown in the Typical Application Circuit section. Minimum Off-Time for Bottom Gate During a load transient of the voltage regulator, the PWM controller could generate a very narrow pulse for the driver SC1211. The pulse is so narrow that it reaches the rising edge threshold of the SC1211 at one point then immediately falls below the falling edge threshold. To response such a PWM input, the bottom gate of the SC1211 has to pull down and pull up almost simultaneously, resulting in a voltage spike at the BG pin. The spike could exceed the gate voltage rating and damage the gate. To prevent such fast gate transition, a minimum off-time (typically 75ns) for the bottom gate is designed in the SC1211. When the PWM input reaches the rising edge threshold of the SC1211, the bottom gate pulls low and will stay low for the minimum off-time no matter what the PWM input at the CO pin is. Startup and UVLO To startup the driver, a supply voltage is applied to VIN pin of the SC1211. The top and bottom gates are held low until VIN exceeds UVLO threshold of the driver, typically 4.0V. Then the top gate remains low and the bottom gate is pulled high to turn on the bottom FET. Once VIN exceeds UVLO threshold of the PWM controller, typically 7.5V, the soft-start begins and the PWM signal takes fully control of the gate transitions. VID-on-Fly Operation Certain new processors have required to changing the VID dynamically during the operation, or refered as VIDon-Fly operation. A VID-on-Fly can occur under light load or heavy load conditions. At light load, it could force the converter to sink current. Upon turn-off of the top FET, the reversed inductor current has to be freewheeling through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high. The SC1211 incorporates the ability by pulling the bottom gate to high internally, which over rides the adaptive circuit and turns the bottom FET on. The delay time from the PWM falling egde to the bottom gate turn-on is set at 200ns typically. Gat e TTransition ransition and Shoo ough Pr o t ection Gate Shoott thr through Pro Refer to the Timing Diagrams section, the rising edge of the PWM input initiates the bottom FET turn-off and the top FET turn-on. After a short propagation delay (tPDL_BG), the bottom gate begins to fall (tF_BG). An adaptive circuit in the SC1211 monitors the bottom gate voltage to drop below 1.4V. Then after a preset delay time (tPDH_TG) is expired, the top gate turns on. The delay time is set to be 20ns typically. This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, upon the direction of the inductor current. The phase node could be low (ground) or high (VIN). Virtual Phase Node for Combi-Sense TM Peak-Current-Mode control is widely employed in multiphase voltage regulators. It features phase current balance, fast transient response, and over current protection, etc. These are essential to low-voltage high-current regulators designed for advanced microprocessors. Usually, a costly current sensing resistor is required to obtain the output inductor current information for the peak current control. The Combi-SenseTM technique featured by the SC1211 is an approach to sense inductor current without using sensing resistor. The falling edge of the PWM input controls the top FET turn-off and the bottom FET turn-on. After a short propagation delay (tPDL_TG), the top gate begins to fall (tF_TG). As the inductor current is commutated from the top FET to the body diode of the bottom FET, the phase node begins to fall. The adaptive circuit in the SC1211 detects the phase node voltage. It holds the bottom FET off until the phase node voltage has dropped below 1.0V. This prevents the top and bottom FETs from conducting 2003 Semtech Corp. 8 www.semtech.com SC1211 POWER MANAGEMENT Applications Information (Cont.) Refer to Semtech SC2643VX Combi-Sense TM Current Mode Controller about the details of the Combi-Sense technique. VIN VIN Optimized Gat e Driv e V oltage Gate Drive Voltage Q1 Qcst C VPN Lo DRN With the supply voltage in between 9V to 16V, an internal LDO is designed with the SC1211 to bring the voltage to a lower level for gate drive. An external Ceramic capacitor(1uF to 4.7uF) connected in between Vreg to ground is needed to support the LDO. The LDO output is connected to low gate drive internally, and has to be connected to high gate drive through an external bootstrap circuit. The LDO output voltage is set at 8.5V. The manufacture data and bench tested results show that, for low Rdson FETs run at applied load current, the optimum gate drive voltage is around 8.5V, where the total power losses of power FETs, including conduction loss and switching loss, are minimized. Vout Q2 + Qcsb Co PGND Rcs Ccs SC1211 Inductor C urrent Signal The above circuit shows the concept of Combi-SenseTM technique. An internal totem pole (Qcst, Qcsb) generates a VPN (Virtual Phase Node) signal. This VPN follows the DRN (or the Power Phase Node) with the same timing. A RC network (Rcs and Ccs) is connected between VPN and Vout. During Q1 turn-on, Qcst turns on as well. The voltage drop across Q1 and Lo charges Ccs. During Q2 turn-on, Qcsb turns on as well. The voltage drop across Q2 and Lo discharges Ccs. Both voltage drops are proportional to the inductor current and a resistance equal to FET’s Rdson plus ESR of the inductor. If the time constant Rcs x Ccs is close to the Lo/Ro of the inductor, where Ro is given by Thermal Shut Down The SC1211 will shut down by pulling both driver outputs low if its junction temperature, Tj, exceeds 155°C. COMPONENT SELECTION Switching FFreq req uency or and MOSFET uency,, Induct Inductor MOSFETss requency The SC1211 is capable of providing up to 3.5A peak drive current, and operating up to 1.5MHz PWM frequency without causing thermal stress on the driver. The selection of switching frequency, together with inductor and FETs is a trade-off between the cost, size, and thermal management of a multi-phase voltage regulator. In modern microprocessor applications, these parameters could be in the range of: Ro = Rinductor + Rdson _ hs * D + Rdson _ ls * (1 - D) the signal developed across Ccs will be proportional to the inductor current, where Ro is the equivalent current sensing resistance. In the above equation, Rinductor is ESR of the inductor, Rdson_hs and Rdson_ls are the top and bottom FET’s Rdson, and D is the duty cycle of the converter. Since a perfect timing match down to the nanosecond is impossible, the VPN totem pole is held in tri-state during the communtations of DRN in the SC1211. This avoids errors and offset on the current detection which can be significant since the timing mismatch is multiplied by the input voltage. An optional capacitor between VPN and DRN allows these two nodes to be AC coupled during the tri-state window, hence yields a perfect timing match. 2003 Semtech Corp. Switching Frequency 100kHz to 500kHz per phase Inductor Value 0.2uH to 2uH FETs 4m-ohm to 20m-ohm Rdson 20nC to 100nC total gate charge Bootstrap Circuit The SC1211 uses an external bootstrap circuit to provide a voltage for the top FET drive. This voltage, referring to the Phase Node, is held up by a bootstrap capaci9 www.semtech.com SC1211 POWER MANAGEMENT Applications Information (Cont.) tor. The capacitor value can be calculated based on the total gate charge of the top FET, QTOP, and an allowed voltage ripple on the capacitor, ∆VBST, in one PWM cycle: CBST > QTOP/∆VBST Typically, it is recommended to use a 1uF ceramic capacitor with 25V rating and a commonly available diode IN4148 for the bootstrap circuit. In addition, a small resistor (one ohm) has to be added in between DRN of the SC1211 and the Phase Node. The resistor is used to allievate the stress of the SC1211 from exposing to the negative spike at the Phase node. A negative spike could occur at the Phase Node during the top FET turn-off due to parasitic inductance in the switching loop. The spike could be minimized with a careful PCB layout. In those applications with TO-220 package FETs, it is recommended to use a clamping diode on the DRN pin to mitigate the impact of the excessive phase node negative spike. 3. Locate the components of the bootstrap circuit close to the SC1211. SOLDERING CONSIDERA TION CONSIDERATION The exposed die pad of the SC1211 is used for ground Solder Pad Solder Mask Copper Filters for Supply Power For VREG pin of the SC1211, it is recommended to use a 1uF to 4.7uF, 25V rating ceramic capacitor for decoupling. LA Y OUT GUIDELINES LAY The switching regulator is a high di/dt power circuit. Its Printed Circuit Board (PCB) layout is critical. A good layout can achieve an optimum circuit performance while minimized the component stress, resulting in better system reliability. For a multi-phase voltage regulator, the SC1211 driver, FETs, inductor, and supply decoupling capacitors in each phase have to be considered as a whole during PCB layout. Refer to Semtech SC2643VX/ SC1211 EVB Layout Guideline. Vias return and thermal release of the driver. The pad must be soldered to the ground plane that is further connected to the system ground in the inner layer through multiple vias. For better electrical and thermal performance, it is recommended to use all copper available under the driver as the ground plane, and place the vias as close as possible to the solder pad. Meanwhile, the vias have to be masked out to prevent solder leakage during reflow. The layout arrangement is detailed in the above figure, which also can be found in the “Land Pattern – Power SOIC-8” section. For the SC1211 driver, the following guidelines are typically recommended during PCB layout: 1. Place the SC1211 close to the FETs for shortest gate drive traces and ground return paths. 2. Connect bypass capacitors as close as possible to decoupling pins (VREG and VIN) and PGND. The trace length of the decoupling capacitor on VREG pin should be no more than 0.2” (5mm). 2003 Semtech Corp. 10 www.semtech.com SC1211 POWER MANAGEMENT OutlineDrawing Drawing- Power - PowerSOIC-8L SOIC-8 Outline Land Pattern - Power SOIC-8 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2003 Semtech Corp. 11 www.semtech.com