NB3RL02 Low Phase-Noise Two-Channel Clock Fanout Buffer The NB3RL02 is a low−skew, low jitter 1:2 clock fan−out buffer, ideal for use in portable end−equipment, such as mobile phones. With integrated LDO and output control circuitry. The MCLK_IN pin has an AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peak−to−peak. The two clock outputs are enabled by control inputs CLK_REQ1 and CLK_REQ2. The NB3RL02 has an integrated Low−Drop−Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to provide regulated power to peripheral devices, such as a TCXO. The adaptive clock output buffers offer controlled slew−rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The NB3RL02 is offered in a 0.4 mm pitch wafer−level−chip−scale (WLCS) package and is optimized for very low standby current consumption. www.onsemi.com MARKING DIAGRAMS WLCSP8 CASE 499BQ RL YY WW G RLYYWW G = Specific Device Code = Year = Work Week = Pb−Free Package LOGIC DIAGRAM Features • Low Additive Noise: ♦ • • • • • −149 dBc/Hz at 10 kHz Offset Phase Noise 0.37 ps (rms) Output Jitter Limited Output Slew Rate for EMI Reduction (1 ns to 5 ns/Rise/Fall Time for 10−50 pF Loads) Regulated 1.8 V Output Supply Available for External Clock Source, ie. TCX0 Ultra−Small Package: ♦ 8−ball: 0.4 mm Pitch WLCS ESD Performance Exceeds JESD 22 ♦ 2000 V Human−Body Model (A114−A) ♦ 200 V Machine Model (A115−A) ♦ 1000 V Charged−Device Model (JESD22−C101−A Level III) These are Pb−Free Devices ♦ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Applications • Cellular Phones • Global Positioning Systems (GPS) © Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 3 1 Publication Order Number: NB3RL02/D NB3RL02 1 2 A A1 A2 B B1 B2 C C1 C2 D D1 D2 (Package − Flip Chip) Die Pads Face Down on PCB Figure 1. Pinout (Top View) Table 1. PIN DESCRIPTION Ball No. Name I/O Description A1 VBATT I Input to internal LDO A2 CLK_OUT1 O Clock output 1 B1 VLDO O 1.8 V supply for NB3RL02 and external TCXO B2 CLK_REQ1 I Clock request from peripheral 1 C1 MCLK_IN I Master clock input C2 CLK_REQ2 I Clock request from peripheral 2 D1 GND − Ground D2 CLK_OUT2 O Clock output 2 Table 2. FUNCTION TABLE Inputs Outputs CLK_REQ1 CLK_REQ2 MCLK_IN CLK_OUT1 CLK_OUT2 VLDO L L X L L 0V L H CLK L CLK 1.8 V H L CLK CLK L 1.8 V H H CLK CLK CLK 1.8 V www.onsemi.com 2 NB3RL02 Table 3. ABSOLUTE MAXIMUM RATINGS Symbol VBATT Parameter Condition Min Max Unit −0.3 7 V CLK_REQ_1/2, MCLK_IN −0.3 VBATT + 0.3 V VLDO, CLK_OUT_1/2 (Note 1) −0.3 VBATT + 0.3 VBATT Voltage Range (Note 1) Voltage range (Note 2) IIK Input clamp current at VBATT, CLK_REQ_1/2, and MCLK_IN IO Continuous output current Continuous current through GND, VBATT, VLDO VI < 0 −50 mA CLK_OUT1/2 $20 mA Continuous current through GND, VBATT, VLDO $50 mA Human−Body Model 2000 V Charged−Device Model 1000 Machine Model 200 ESD Rating TJ Operating virtual junction temperature −40 150 °C TA Operating ambient temperature range −40 85 °C Tstg Storage temperature range −55 150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The input negative−voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. All voltage values are with respect to network ground terminal. Table 4. RECOMMENDED OPERATING CONDITIONS (Note 3) Symbol VBATT Parameter Min Max Unit 2.3 5.5 V Input voltage VBATT VI Input voltage Amplitude MCLK_IN, CLK_REQ1/2 0 1.89 V VO Output voltage CLK_OUT1/2 0 1.8 V VIH High−level input voltage CLK_REQ1/2 1.3 1.89 V CLK_REQ1/2 0 0.5 VIL Low−level input voltage IOH High−level output current, DC current IOL Low−level output current, DC current −8 8 3. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. www.onsemi.com 3 V mA mA NB3RL02 Table 5. ELECTRICAL CHARACTERISTICS (TA = −40°C to +85°C) Symbol Parameter Test Conditions Min Typ Max Unit IOUT = 50 mA 1.71 1.8 1.89 V 10 mF LDO VOUT LDO output voltage CLDO External load capacitance IOUT(SC) Short circuit output current IOUT(PK) PSR tsu 1 RL = 0 W 100 Peak output current VBATT = 2.3 V, VLDO = VOUT − 5% 55 Power supply rejection VBATT = 2.3V, IOUT = 2 mA LDO start−up time fIN = 217 Hz and 1 kHz 60 fIN = 3.25 MHz 40 VBATT = 2.3 V , CLDO = 1 mF, CLK_REQ_n to VLDO = 1.71 V mA 100 mA dB 0.2 VBATT = 5.5 V , CLDO = 10 mF, CLK_REQ_n to VLDO = 1.71 V ms 1 ms POWER CONSUMPTION ISB Standby current ICCS Static current consumption IOB Output buffer average current CPD Output power dissipation capacitance Device in standby (all VCLK_REQ_n = 0 V) 0.2 1 mA Device active but not switching, VCLK_REQn = H 0.4 1 mA fIN = 26 MHz, CLOAD = 50 pF 4.2 mA fIN = 26 MHz 44 pF VI = VLDO or GND 1 mA MCLK_IN INPUT II MCLK_IN, CLK_REQ_1/2 leakage current CI MCLK_IN capacitance fIN = 26 MHz 3.75 pF RI MCLK_IN impedance fIN = 26 MHz 5 kW fIN MCLK_IN frequency range 10 26 52 MHz MCLK_IN LVCMOS SOURCE Phase noise Additive jitter tDL MCLK_IN to CLK_OUT_n propagation delay DCL Output duty cycle fIN = 26 MHz, tr/tf v 1 ns 1 kHz offset −140 10 kHz offset −149 100 kHz offset −153 1 MHz offset −151 fIN = 26 MHz, VPP = 0.8 V, BW = 10 kHz − 5 MHz fIN = 26 MHz, DCIN = 50% 45 dBc/Hz 0.37 ps (rms) 10 ns 50 55 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 4 % NB3RL02 Table 5. ELECTRICAL CHARACTERISTICS (TA = −40°C to +85°C) Symbol Parameter Test Conditions Min Typ Max Unit 1.8 V MCLK_IN SINUSOIDAL SOURCE VMA Input amplitude Phase noise 0.3 fIN = 26 MHz, VMA = 1.8 VPP fIN = 26 MHz, VMA = 0.8 VPP Additive jitter tDS MCLK_IN to CLK_OUT_1/2 propagation delay DC Output duty cycle 1 kHz offset −138 10 kHz offset −146 100 kHz offset −151 1 MHz offset −149 1 kHz offset −138 10 kHz offset −146 100 kHz offset −150 1 MHz offset −148 fIN = 26 MHz, VMA = 1.8 VPP, BW = 10 kHz − 5 MHz fIN = 26 MHz, VMA > 1.8 VPP 45 dBc/Hz 0.37 ps (rms) 12 ns 50 55 % CLK_OUT_N OUTPUTS tr 20% to 80% rise time CL = 10 pF to 50 pF 1 5 ns tf 20% to 80% fall time CL = 10 pF to 50 pF 1 5 ns tsk Channel−to−channel skew CL = 10 pF to 50 pF, (CL1 = CL2) −0.5 0.5 ns VOH High−level output voltage IOH = −100 mA, reference to VLDO −0.1 IOH = −8 mA 1.2 VOL Low−level output voltage V IOL = 20 mA 0.2 IOL = 8 mA 0.55 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 5 V NB3RL02 APPLICATION INFORMATION Typical Application buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral can independently request an active clock by asserting a clock request line (CLK_REQ1 or CLK_REQ2). A typical mobile application for the NB3RL02 is shown in Figure 2. An external low noise TCXO clock source is powered by the NB3RL02’s 1.8 V regulated LDO and is Figure 2. Mobile Application When both clock request lines are logic LOW, the NB3RL02 enters a current-saving shutdown mode. In this mode, the LDO output goes to 0 V and turns off the TCXO. Also, the unpowered CLK_OUT1 and CLK_OUT2 outputs are pulled to GND. When the NB3RL02 receives a HIGH from either peripheral CLK_REQn, the 1.8 V LDO output is enabled and will power the TCXO. The output of the TCXO can be a square wave, sine wave, or clipped sine wave and is converted to a buffered square wave. acceptable, but with reduced phase noise and jitter performance. CLK_OUT1 and CLK_OUT2 Outputs The CLK_OUT1 and CLK_OUT2 outputs drive 1.8 V LVCMOS levels with rise/fall times within 1 ns to 5 ns with load capacitors between 10 pF and 50 pF. These relatively slow edge rates will minimize EMI radiation into the system. When not requested, each output is set to Low to avoid false clocking of the load device. LDO Input Clock to Output Square Wave Generator The integrated low noise 1.8 V LDO provides power internal to the NB3RL02 as well as a power source for an external clock such as a TCX0. The input range of the LDO allows the device to be powered directly from a single cell Li battery. The LDO is enabled when either of the CLK_REQn signals is High. When disabled, the device turns off the LDO and enters a low power shutdown mode consuming less than 1 mA from the battery. The LDO requires an output decoupling capacitor in the range of 1 mF to 10 mF for compensation and high frequency PSR. An input bypass capacitor of 1 mF or larger is recommended. Figure 3 shows the MCLK_IN input having an internal AC coupling capacitor. This allows either a square or sine wave signal to be directly connected from a TCXO. Therefore, an external series capacitor is not required. MCLK _IN C MCLK Figure 3. Input Stage The clock frequency band of the NB3RL02 is 10 MHz to 52 MHz with all performance metrics specified at 26 MHz. Typical input sinusoidal signal amplitude is 0.8 VPP for specified performance, but amplitudes as low as 0.3 VPP are www.onsemi.com 6 NB3RL02 ORDERING INFORMATION Device NB3RL02FCT2G Temperature Range Package Shipping† −40°C to 85°C WLCSP8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 7 NB3RL02 PACKAGE DIMENSIONS WLCSP8, 1.57x0.77 CASE 499BQ ISSUE A È È D PIN A1 REFERENCE A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. E A3 DIE COAT 0.10 C 2X 0.10 C 2X DIM A A1 A2 A3 b D E e A2 TOP VIEW DETAIL A A MILLIMETERS MIN MAX 0.50 −−− 0.13 0.17 0.30 REF 0.025 BSC 0.21 0.25 0.77 BSC 1.57 BSC 0.40 BSC 0.10 C A1 8X RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 SIDE VIEW C SEATING PLANE PACKAGE OUTLINE 0.40 PITCH e/2 8X b 0.05 C A B e D e 0.03 C 8X C 0.40 PITCH B A 1 0.23 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2 BOTTOM VIEW ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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