iCE40LM Sony IR Tx Solution October 2013 Reference Design RD1190 General Description The iCE40LM Sony IR Tx Solution is a low power IR Tx solution for mobile devices. It is designed to easily send IR Tx data from the application processor to the IR LED. This reference design acts as data control and buffer between the IR LED and the application processor. The iCE40LM Sony IR Tx Solution is a configurable solution, available as either standalone off the shelf or fully customizable solution, making it an IR Tx standard agnostic solution. Figure 1. System Block Diagram SPI Master Application Processor iCE40LM Sony IR Tx Solution SPI SPI Slave IR TX Data Control and Buffer IR LED Driver Control IR LED Power-On Reset Module As a standalone solution, the iCE40LM Sony IR Tx Solution connects to the application processor’s Serial Peripheral Interface Bus (SPI) with clock frequency set to 10.8MHz. This enables a fast communication speed to/from the processor. The iCE40LM Sony IR Tx standalone solution prepares and sends the data from the application processor to an IR LED. The data is sent to the IR LED with the correct frequency, duration, and interval as required by Sony IR Tx standard. The iCE40LM Sony IR Tx standalone solution has a system operating frequency of 27MHz, and a SPI bus frequency to application processor of 10.8MHz. The SPI bus is configured to have a voltage of 1.8V, and the IR LED is driven by a 3.3V I/O. The fully customizable solution capability of this solution is due to its FPGA based architecture. This capability is ideal, but not limited to users who would like to include additional IR Tx standards, change the data acquisition FIFO depth, create an I/O bridge between IR LEDs and processor, or create additional custom logic. The IR Tx reference design consumes only 335 LUTs. This allows it to fit in a device as small as a iCE40LM1K. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1190_01.1 iCE40LM Sony IR Tx Solution Regardless of the solution type, the iCE40LM implementation of the IR Tx Solution has a core voltage of 1.2V. It is available in a very small form-factor 25-pin WLCSP package. The package has 0.35mm ball pitch, making the overall package size to be 1.71mm x 1.71mm that easily fit into a number of mobile devices such as smart phones. Other packages include .4mm ball pitch with 36 balls (2.5x2.5mm) or 49 balls (3x3mm). The solution operates at industrial temperature range of -40C to 100C. As a standalone solution, user simply obtains the solution which includes the device, Diamond Programmer software, and ready-for-download bitstream. As a fully customizable solution, user will obtain the device, the iCEcube2 design software, the programming software, and the source code of the Sony IR Tx solution. Figure 2. Package Diagram (Balls Up) A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 D2 D1 E5 E4 E3 E2 E1 Features • Configurable IR Tx Solution – Configured to Sony IR Tx Interface – Default System frequency of 27MHz – Power-On Reset capability • Serial Peripheral Interface (SPI) Bus connection to Application Processor with the following Default settings: – Interface frequency of 10.8MHz – Interface voltage of 1.8V – Solution is a “slave” of the Application Processor – SPI slave mode CPOL = 1 and CPHA = 1 (mode “3”) – SPI slave features LSB first • General – Core voltage of 1.2V – I/O voltages of 1.8V and 3.3V – 25-pin WLCS at 1.69mm x 1.69mm with 0.35mm pitch – Industrial (-40C to 100C) Grade Applications • IR Transmitter Capable Devices • Smart Phones • Tablets • Universal Remote Controls 2 iCE40LM Sony IR Tx Solution Functional Block Diagram Figure 3. Functional Block Diagram FIFO Controller IR LED Driver (3.3V I/O) A3 IR LED Control and State Machine Logic i_ssn A4 IR LED Driver Control Data FIFO i_spi_sck A5 Read and Write Data Format Logic i_mosi SPI Slave Module SPI Interface Module E3 i_sys_clk IR TX Data Control and Buffer iCE40LM Sony IR Tx Solution E4 o_ir_tx Power-On Reset Module Specifications Recommended Operating Conditions Table 1. Recommended Operating Conditions Symbol VCC Parameter Core Supply Voltage Min. Typ. Max. Units See DS1045, iCE40LM Family Data Sheet. 1.2 See DS1045, iCE40LM Family Data Sheet. V 1.71 1.8 1.89 V 3.3 3.46 V - See DS1045, iCE40LM Family Data Sheet. VCCIOVB11 Bank 1 I/O Driver Supply Voltage 1 Bank 2 I/O Driver Supply Voltage 3.14 Junction Temperature Operation See DS1045, iCE40LM Family Data Sheet. VCCIOVB2 tJUND o C 1. Assumes operating under “off-the-shelf standalone1 solution”. Power Supply Ramp Rates See DS1045, iCE40LM Family Data Sheet. Power-On-Reset Voltage Levels See DS1045, iCE40LM Family Data Sheet. ESD Performance See DS1045, iCE40LM Family Data Sheet. DC Electrical Characteristics See DS1045, iCE40LM Family Data Sheet. Set the VCCIO values to the values stated in the Recommended Operating Conditions table. 3 iCE40LM Sony IR Tx Solution Power Supply Current See DS1045, iCE40LM Family Data Sheet. Absolute Maximum Ratings See DS1045, iCE40LM Family Data Sheet. Performance Characteristics Table 2. Performance Characteristics1, 3 Symbol Parameter Min. Typ. Max. Units 27 MHz Fcoremax System Frequency Tcoremaxdcd Maximum duty cycle distortion for System Clock % Tcoirtx o_ir_tx clock to out time ns Fspimax SPI Bus Frequency Tsuspi SPI setup time ns Thdspi SPI hold time ns Tsssn i_ssn setup time ns 10.8 Thdssn i_ssn hold time Tpor Power-On Reset duration2 MHz ns 192 Cycles 1. Assumes operating under “off-the-shelf standalone1 solution” 2. Relative to System Frequency 3. All values are based on iCEcube2’s Timing Analyzer’s results. The design is not validated by test engineering. FPGA Characteristics See DS1045, iCE40LM Family Data Sheet. Note that once customization is performed, the values in “Performance Characteristics” may not be the same. Pin Configuration and Function Descriptions Figure 4. Bottom View of iCE40LM4K-SWG25TR (Balls Up) A5 A4 A3 A2 A1 B5 B4 B3 B2 B1 C5 C4 C3 C2 C1 D5 D4 D3 D2 D1 E5 E4 E3 E2 E1 4 iCE40LM Sony IR Tx Solution Table 3. Pin Function Description1 Pad Name Port Name Port Direction Input/Output Description A1 General Purpose I/O A2 VCCIOVB1 Input I/O Power Supply A3 i_ssn Input SPI bus slave select (Active Low) A4 i_spi_sck Input SPI bus serial clock A5 i_mosi Input SPI bus serial data in to slave B1 General Purpose I/O B2 GND Input/Output Input 1.8V I/O for user interface 1.8V I/O for user interface Ground B3 CRESET Input Configuration Reset (Active Low). See Datasheet B4 VCC Input Core Power Supply B5 General Purpose I/O C1 ice_SI Input/Output C2 General Purpose I/O C3 CDONE C4 General Purpose I/O Input/Output 3.3V I/O for user interface C5 General Purpose I/O Input/Output 3.3V I/O for user interface D1 flsh_sclk Input Configuration Clock D2 ice_SO Input Configuration Input from external SPI Memory D3 General Purpose I/O D4 GND Output Input/Output Output Input/Output Input Input/Output 1.8V I/O for user interface Configuration Output to external SPI Memory 1.8V I/O for user interface Configuration Done. See Datasheet 3.3V I/O for user interface Ground D5 General Purpose I/O E1 flsh_cs E2 VCCIOVB2 Input I/O Power Supply E3 i_sys_clk Input System Clock E4 o_ir_tx E5 General Purpose I/O Input Output Input/Output 3.3V I/O for user interface Configuration Chip Select (Active Low) IR LED Output Driver (3.3V) 3.3V I/O for user interface 1. Assumes operating under “off-the-shelf standalone1 solution”. Theory of Operations The iCE40LM Sony IR Tx Solution interfaces between an application processor and an IR LED. It receives Sony based IR Tx data from the processor through the SPI bus. The received data is then formatted for IR driver logic and stored/buffered into a data FIFO. Once the data FIFO is no longer empty, the IR driver logic reads the FIFO content and converts the data into Sony compatible 3.3V 40kHz serial signals that drives the IR LED. It continues to drive the LED until the FIFO is empty, and the whole process begins again when the next set of received data is present. Functional Descriptions This sub-section describes the function of each sub-block in inside the iCE40LM Sony IR Tx Solution. Many of these blocks have HDL module associated with them. Sony IR Tx Top Level The Sony IR Tx Top Level is found in Top_level. This module contains the SPI Slave to Application Processor, the IR Tx Data Control and Buffer, and IR LED Driver Control. It also contains a Power-On Reset (POR) module. The POR module initiates a system reset upon power up for Tpor number of cycles. The iCE40LM Sony IR Tx Solution operates after system reset has been completed. SPI Slave to Application Processor 5 iCE40LM Sony IR Tx Solution This module is used to interface between the iCE40LM Sony IR Tx Solution and the application processor. It is found in SPI_Slave_Wrapper module. This module can only receive data from application processor. Logic to send data to the application processor is not implemented. When data is sent from the application processor, this module simply converts the data from SPI serial data to 8-bit data and indicates whether that data is valid. Note that a set of Sony IR Tx data is expected to come into this solution as a set of three consecutive 8-bit data. IR Tx Data Control and Buffer This module takes the three 8-bit data from the SPI Slave and formats the three bytes into a 21-bit word. After the formatting is completed, the 21-bit word is written into a FIFO. When the FIFO is not empty, this module issues a signal to the IR LED Driver Control module that data is present in the FIFO. The FIFO content is then read and prepared for the IR LED Driver Control module. The information sent to the IR LED Driver Control module is: 20-bit data, 1-bit to indicate whether the data is 20 or 12 bits, and 1-bit to indicate whether the data is valid. IR LED Driver Control This module issues a FIFO read to the IR Tx Data Control and Buffer module when the FIFO from that module is not empty. The signals received from the IR Tx Data Control and Buffer module are then used to calculate the duration of each bit that needs to be transmitted. This module then generates a 40kHz with duty cycle of approximately 25% to drive the IR LED. Controlled by a state machine, each bit is then sent serially via 3.3V output using the 40kHz as the carrier signal with the appropriate durations. The bits are sent from LSB to MSB. Block Descriptions The purpose of this section is to provide detailed descriptions of each block of the iCE40LM Sony IR Tx Solution so as to assist users who want to use this solution as a building block for other IR Tx. Top Level Module (Top_level) This module contains the SPI Slave to Application Processor, the IR Tx Data Control and Buffer, and IR LED Driver Control. The HDL code begins with the POR logic, which is set to Tpor cycles, and the three sub-modules above are instantiated and connected together. The code SPI_Slave_wrapper instantiation is the SPI Slave to Application Processor module. This module can only receive data from the application processor. The received data is then sent to the IR Tx Data Control and Buffer module (SPI_Slave_Registers) where it is formatted for the IR LED Driver Control and stored in FIFO. When that FIFO is no longer empty, the IR LED Driver Control module reads the content of the FIFO. The IR LED Driver Control module then sends out the data serially with the appropriate duration. SPI Slave to Application Processor Module (SPI_Slave_wrapper) This module is found in the SPI_Slave_wrapper file. It is used to provide connection from the application processor to this solution via SPI interface. Note that in this solution, user can only send data from the application processor to the solution, not the other way around. Table 4 summarizes the ports to/from this module. 6 iCE40LM Sony IR Tx Solution Table 4. Ports To/From Application Processor Module Port Name Direction Description o_data[7:0] Output Data received from Application Processor o_tx_ready Output Unused o_rx_ready Output Determines if received data is valid (Active HIGH) o_tx_error Output Unused o_rx_error Output Unused o_miso Output Unused o_tx_ack Output Unused o_tx_no_ack Output Unused i_sys_clk Input System Clock i_sys_rest Input System Reset - Connected to POR i_csn Input Unused i_data[15:0] Input Unused i_wr Input Unused i_rd Input Unused i_cpol Input Unused i_cpha Input Unused i_lsb_first Input Unused i_mosi Input SPI serial data into slave - connected to I/O i_ssn Input SPI slave select (Active Low) - connected to I/O i_sclk Input SPI clock input - connected to I/O The SPI Slave to Application Processor Interface Module code simply instantiates the spi_slave module. Table 5 summarizes the ports to/from the spi_slave module: Table 5. Ports To/From spi_slave Module Port Name Direction Description o_miso_byte_req Output Unused o_mosi_byte[7:0] Output Data received from Application Processor o_mosi_byte_valid Output Determines if received data is valid (Active HIGH) o_cmd_byte Output Unused o_miso Output Unused i_sys_clk Input System Clock i_sys_rst Input System Reset - Connected to POR i_miso_byte[7:0] Input Unused i_miso_byte_valid Input Unused - Tied to Logic 1 i_mosi Input SPI serial data into slave - connected to I/O i_csn Input SPI slave select (Active Low) - connected to I/O i_sclk Input SPI clock input - connected to I/O The following is a walkthrough of the spi_slave code. Codes in this section are taken directly from the HDL file. Note that in most cases, the topics in each paragraph below are presented in the order in which they appear in the HDL code. 7 iCE40LM Sony IR Tx Solution The spi_slave module contains the hard SPI module called “SB_SPI”. It contains logic that determines whether the command is write or read, and the state machine to process the SPI master commands so as to prepare data for the backend interface. IR Tx Data Control Module (SPI_Slave_Registers) This module is found in the SPI_Slave_Registers file. It receives data from the SPI Slave and formats them from three 8-bit data to one 21-bit data. The formatted data are then written into a FIFO. When the FIFO is not empty, this module issues a signal to the IR LED Driver Control module that data is present in the FIFO. The FIFO content is then read, and prepared for the IR LED Driver Control module. The following table summarizes the ports to/from the IR Tx Data Control Module: Table 6. Ports To/From IR Tx Data Control Module Port Name Direction Description o_sys_intr Output Indicates if o_sirc_word is valid data (Assert HIGH) o_sirc_word[19:0] Output Data to send to the IR TX Controller o_sirc_len Output Indicates length of o_sirc_word (1 = 20-bit, 0 = 12-bit) Output Indicate if FIFO is empty (Assert HIGH) - Used to tell the IR TX controller to begin reading the FIFO so to issue command to remote device o_fifo_empty i_sirc_fifo_wr_data[7:0] Input Data received from Application Processor i_sirc_fifo_wr_en Input Determines if received data is valid (Active HIGH) Input Indicate to read data received from Application Processor Controlled by o_tx_read_req of Ir_Tx_Ctrl, which is controlled by FIFO Empty i_sys_clk Input System Clock i_sys_rst Input System Reset - Connected to POR i_sirc_fifo_rd_en The following is a walkthrough of the SPI_Slave_Registers code. Codes in this section are taken directly from the HDL file. Note that in most cases, the topics in each paragraph below are presented in the order in which they appear in the HDL code. The first set of logic in this module converts a set of three successive bytes of data from the application processor into 21-bit data. It assumes that the first two bytes, and bit 0 to 3 and 7 of the third byte contains data. There’s a counter that keeps track of the number of bytes received in a set of data. The counter is also used to determine when the data is ready so that they can be written into the FIFO. The codes for this logic are locates under the following comments: • // Three bytes of data from slave stored as 21 bits word • // FIFO Write enable • // Counter to keep track of three bytes from slave Once the data has been formatted, they are written to a 4 deep by 21-bit FIFO. The following table summarizes the ports to/from the FIFO: 8 iCE40LM Sony IR Tx Solution Table 7. Ports To/From the FIFO Port Name Direction Description o_RdData[20:0] Output Data to send to the IR TX Controller o_Full Output Indicate if FIFO is full (Assert HIGH) - Not used in solution Output Indicate if FIFO is empty (Assert HIGH) - Used to tell the IR TX controller to begin reading the FIFO so to issue command to remote device o_Empty i_clk Input System Clock i_rst Input System Reset - Connected to POR i_RdEn Input Read Enable for o_RdData i_WrEn Input Write Enable for WrData i_WrData[20:0] Input Data received from Application Processor (formatted to 21-bit) After data has been written, the o_Empty will be deasserted, which will indicate the IR LED Driver Control (through o_fifo_empty) to issue a read command to the FIFO. When data has been read, they are now further refined for the IR LED Driver Control. They’re formatted into one 20-bit data bus, a 1-bit signal to indicate whether the data is 20 or 12 bits, and 1-bit to indicate whether the data is valid. The logic for this operation is located under the following comments: • // To generate delayed versions of fifo_rd_en pulses • // To generate o_sirc_word and o_sirc_len after reading from fifo The signals sent to the IR LED Driver Control Module are: o_sys_intr (data valid), o_sirc_word (20-bit data), and o_sirc_len (indicates whether o_sirc_word is 20 or 12-bit). IR LED Driver Control Module (Ir_Tx_Ctrl) This module is found in Ir_Tx_Ctrl file. It issues a FIFO read to the IR Tx Data Control and Buffer module when the FIFO from that module is not empty. The signals received from the IR Tx Data Control and Buffer module are then used to calculate the duration of each bit that needs to be transmitted. This module then generates a 40kHz with duty cycle of approximately 25% to drive the IR LED. Controlled by a state machine, each bit is then sent serially via 3.3V output using the 40kHz as the carrier signal with the appropriate durations. The bits are sent from LSB to MSB. This module has been designed specifically for Sony IR Tx interface. The following table summarizes the ports to/from the IR LED Driver Control Module: Table 8. Ports To/From IR LED Driver Control Module Port Name Direction o_tx_read_req Description Output Indicate to read data received from Application Processor Controlled by FIFO Empty, and connect to SPI_Slave_Registers (i_sirc_fifo_rd_en) Output IR driver port i_sys_clk Input System Clock i_sys_rst Input System Reset - Connected to POR o_ir_tx i_fifo_empty Input Indicate if FIFO for data from processor is empty i_sirc_word Input Data from SPI_Slave_Registers i_sirc_len Input Indicate length i_sirc_word (1 = 20-bit, 0 = 12-bit) i_read_data_vld Input Indicates if i_sirc_word is valid data (Assert HIGH) The following is a walkthrough of the Ir_Tx_Ctrl code. Codes in this section are taken directly from the HDL file. Note that in most cases, the topics in each paragraph below are presented in the order in which they appear in the HDL code. 9 iCE40LM Sony IR Tx Solution When the FIFO at the IR Tx Data Control Module is not empty, this module generates a FIFO read signal if the IR LED Driver is available. The code is shown under the comment: //Generates read request to FIFO of I2C Slave registers Once data is received, they are prepared for transmit to the IR LED. The preparation includes: counting the number of 1s in the data, delaying the data until number of 1s is available, and time offset. These are located under: • // Count number of 1s, used to compute how much of time left within 45ms • //ones_count_i available afterone cycle and hence use this registered • //wait_45ms_offset_i available after 1 cycles and hence use this registered There’s also code to generate the 40kHz signal with 25% duty cycle, per Sony IR Tx requirements. The 40kHz signal is only active whenever there’s data to be sent. The codes are located under: • //IR output active only in START_STATE and Data state, not 40KHz carrier wave in • //IR Tx output, with 25% duty cycle A state machine is used to control the logic above. The same state machine is used to control the serial data output to the IR LED. In addition, a number of counters are implemented to keep track of the time durations required by Sony IR Tx standard. 10 iCE40LM Sony IR Tx Solution Design Considerations SPI Interface This section describes the SPI Interface between iCE40LM Sony IR Tx Solution and the Application Processor. The Application Processor sends data to the iCE40LM Sony IR Tx Solution over SPI lines through the SPI_Slave_wrapper module. This module expects SPI in mode “3” format, i.e. CPHA = 1 and CPOL = 1, and LSB first while transmitting a byte of data over the bus. Note that user can only perform a three-byte writes into this solution. The following timing diagrams show the write access patterns. Figure 5. Timing Diagram of SPI Interface - Multi Byte Write for 20-bit IR Tx Data SCLK MOSI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 X X X 20 MISO CS In Figure 5, bit 0 goes first and the last bit is the bit that indicates whether it is 20-bit or 12-bit data. “x” are “don’t cares”. Figure 6. Timing Diagram of SPI Interface - Multi Byte Write for 12-bit IR Tx Data SCLK MOSI 0 1 2 3 4 5 6 7 8 9 10 11 X X X X X X X X X X X 20 MISO CS In Figure 6, bit 0 goes first and the last bit is the bit that indicates whether it is 20-bit or 12-bit data. “x” are “don’t cares”. Note: CS must not be asserted until all the bytes are read in case of multiple bytes read 11 iCE40LM Sony IR Tx Solution Pseudo Code Example for Application Processor The following code illustrates how an Application Processor could process the interrupt received from the IR Tx to obtain the sensor data. Write three bytes of data to the iCE40LM Sony IR Tx Solution. Third data byte has valid data at bit 0 to 3 and 7, where 7 has the data length indicator (1 = 20-bit, 0 = 12-bit). Design Customization Considerations Since this is an FPGA based solution, user can customize this solution by changing the source code of the IR Tx solution or add additional functions to this solution. Note that when customization is performed, the “Performance Characteristics” values might change. Programming Solutions Due to the FPGA nature of this solution, the solution requires FPGA programming. The programming solutions include, but not limited to programming via FTDI chip, programming via SPI Flash, or programming via application processor. For more information on programming solutions, please refer to “iCE40 Configuration Solutions Guide”. Power Supplies Please refer to FPGA board design guide. Layout Guidelines Please refer to FPGA board design guide. Heatsink Selection Please refer to FPGA board design guide. Software Requirement For standalone solution, Diamond Programmer and “Top_level_bitmap.hex” file. The following steps are required to program the device: 1. Create a new project 2. Set to SPI Programming For fully customizable solution, iCEcube2, Diamond Programmer, and IR Tx HDL source files are required. For more information on iCEcube2, please refer to the iCEcube2 web page. Resource Utilization LUTs Registers PLBs BRAMs I/Os I2Cs SPIs 335 231 81 2 5 0 1 12 iCE40LM Sony IR Tx Solution Typical Application Circuits Figure 7. IR Tx with Pre-programmed SPI Flash VCCIOBV 2 VCCIOBV 1 R3 68 C2 C3 C1 10nF 0.1uF 1uF iCE40LM Sony IR Solution IR LED C8 C9 C7 10nF 0.1uF 1uF E2 VCCIOVB2 R4 2K2 VCCIOVB1 A2 E4 o_ir_tx CRESET B3 System Clock Source Switch E3 i_sys_clk D2 C1 D1 E1 SPI Flash R1 2K2 i_mosi i_spi_sck i_ssn ice_SO Ice_SI flsh_sclk flsh_cs A5 A4 A3 Application Processor’s SPI Ports VCC 3.3V VCC B4 GND B2 GND D4 R2 2K2 LED C3 CDONE 13 C5 C4 10nF 0.1uF C6 1uF iCE40LM Sony IR Tx Solution Figure 8. IR Tx with Direct Programming through FTDI VCCIOBV VCCIOBV 1 2 R3 68 C2 C3 C1 10nF 0.1uF 1uF iCE40LM Sony IR Solution IR LED C8 C9 C7 10nF 0.1uF 1uF E2 VCCIOVB2 R4 2K2 System Clock Source FTDI FT2232H VCCIOVB1 A2 i_mosi i_spi_sck i_ssn A5 A4 A3 E4 o_ir_tx E3 i_sys_clk D2 C1 D1 E1 B3 C3 ice_SO Ice_SI flsh_sclk flsh_cs CRESET CDONE Application Processor’s SPI Ports VCC VCC B4 GND B2 GND D4 14 C5 C4 10nF 0.1uF C6 1uF iCE40LM Sony IR Tx Solution Figure 9. IR Tx with Programming through Application Processor VCCIOBV VCCIOBV 1 2 R3 68 C2 C3 C1 10nF 0.1uF 1uF iCE40LM Sony IR Solution IR LED C8 C9 C7 10nF 0.1uF 1uF E2 VCCIOVB2 R4 2K2 VCCIOVB1 A2 R1 2K2 E4 o_ir_tx CRESET B3 System Clock Source E3 i_sys_clk Application Processor D2 C1 D1 E1 i_mosi i_spi_sck i_ssn ice_SO Ice_SI flsh_sclk flsh_cs A5 A4 A3 Switch Application Processor’s SPI Ports VCC 3.3V VCC B4 GND B2 GND D4 R2 2K2 C3 CDONE LED SPI Flash (Data) 15 C5 C6 C4 10nF 0.1uF 1uF iCE40LM Sony IR Tx Solution Package Diagram 16 iCE40LM Sony IR Tx Solution Disclosures The iCE40LM Sony IR Tx Solution is an FPGA based solution which requires IP to be downloaded to the device for this solution. This solution includes the Diamond Programmer for IP download and iCEcube2 design software for customization. The design files and ready-for-download .hex file are also included. Finally, SPI Flash might be needed depending on whether one time or multi programmable scheme is used. Ordering Information Solution Name Description Package BOM iCE40LM Sony IR Tx Solution (Commercial Grade) Commercial Grade Solution 25-pin WLCS at 1.71mm x 1.71mm iCE40LM4K-SWG25TR Device, iCEcube2 Design Software, Diamond Programmer, IR Tx Design Files, Top_level_bitmap.hex iCE40LM Sony IR Tx Solution (Industrial Grade) Industrial Grade Solution 25-pin WLCS at 1.71mm x 1.71mm iCE40LM4K-SWG25TR Device, iCEcube2 Design Software, Diamond Programmer, Sony IR Tx Design Files, Top_level_bitmap.hex Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version October 2013 01.0 01.1 Change Summary Initial release. Changed system operating frequency of 25MHz to 27MHz. Updated SPI Interface section Updated Pseudo Code Example for Application Processor section. 17