Model 654P/L Advanced PLL LVPECL or LVDS Clock Features Ceramic Surface Mount Package Low Phase Jitter Performance, 600fs Typical Advanced PLL Design w/ Low Fundamental Crystal Frequency Range 10MHz – 1.0GHz * +2.5V or +3.3V Operation Output Enable Standard Tape and Reel Packaging, EIA‐418 Part Dimensions: 5.0 × 3.2 × 1.2mm • 62.00mg Standard Frequencies ‐ 25.00MHz ‐ 27.00MHz ‐ 125.00MHz ‐ 155.52MHz Applications Broadcast Video Storage Area Networking Broadband Access PCI Express Networking Equipment Ethernet/GbE/SyncE Fiber Channel Test and Measurement ‐ 161.1328MHz ‐ 622.08MHz ‐ 644.53125MHz ‐ 693.4830MHz * Check with factory for availability. Description CTS Model 654P/L is a low cost, high performance PLL clock oscillator supporting differential LVPECL or LVDS outputs. Employing the latest IC technology, M654P/L has excellent stability and low phase jitter performance. Ordering Information Output Type P Model 654 Frequency Stability 3 Frequency Code [MHz] X XX or XXX X Code Frequency 1 Output LVPECL LVDS Supply Voltage 3 Code Temp. Range ‐20°C to +70°C C ‐40°C to +85°C I Product Frequency Code Code P L Temperature Range I Code 6 5 3 Stability 2 ±20ppm ±25ppm ±50ppm Packaging T Packing Code 1k pcs./reel T Code 2 3 Voltage +2.5Vdc +3.3Vdc Notes: 1] Refer to document 016‐1454‐0, Frequency Code Tables. 3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater. 2] Consult factory for availability of 6I Stability/Temperature combination. Not all performance combinations and frequencies may be available. Contact your local CTS Representative or CTS Customer Service for availability. DOC# 008‐0549‐0 Rev. B Page 1 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Electrical Specifications Operating Conditions P ARAMETER SYMBO L CO NDITIO NS MIN TYP MAX UNIT Maximum Supp ly Voltage VCC ‐ ‐0.5 ‐ 5.0 V Sup ply Voltage VCC ±5% 2.375 2.5 2.625 3.135 3.3 3.465 ICC Maximum Load ‐ 54 ‐ ‐ 23 ‐ V Sup ply Current LVP ECL LVDS O peratin g Temperature Sto rage Temperature ‐20 +70 TA ‐ TSTG ‐ ‐55 ‐ +125 °C SYMBO L CO NDITIO NS MIN TYP MAX UNIT fO ‐ 10 ‐ 1000 MHz Δf/fO ‐ 20, 25 or 50 ±ppm Δf/f25 First Year @ +25°C, nominal VCC ‐40 +25 mA +85 °C Frequency Stability P ARAMETER Frequenc y Ran ge Frequenc y Stability [Note 1] Aging ‐3 ‐ 3 ppm TYP MAX UNIT Ohms 1.] Inc lusive of initial tolerance at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging. Output Parameters P ARAMETER SYMBO L CO NDITIO NS LVPECL O utput Ty pe ‐ ‐ O utput Load RL Terminated to VCC ‐ 2.0V O utput Voltage Levels VOH VOL MIN PECL Load ‐ ‐ 50 ‐ VCC ‐ 1.03 ‐ VCC ‐ 0.60 VCC ‐ 1.85 ‐ VCC ‐ 1.60 V O utput Duty Cy c le SYM @ VCC ‐ 1.3V 45 ‐ 55 % Rise and Fall Time TR, TF @ 20%/80% Levels, RL = 50 Ohms ‐ 0.25 0.60 ns O utput Ty pe ‐ ‐ O utput Load RL Between Outputs O utput Voltage Levels VOH VOL LVDS LVDS Load ‐ ‐ 100 ‐ Ohms ‐ 1.43 1.60 0.90 1.10 ‐ 45 ‐ 55 % V O utput Duty Cy c le SYM @ 1.25V Differential O utput Voltage VOD RL = 100 Ohms 175 350 454 mV O ffset Voltage VOS LVDS Load 1.20 1.25 1.30 V TR, TF @ 20%/80% Levels, RL = 100 Ohms ‐ ‐ 0.4 ns Rise and Fall Time DOC# 008‐0549‐0 Rev. B Page 2 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Electrical Specifications Output Parameters P ARAMETER SYMBO L CO NDITIO NS MIN TYP MAX UNIT TS Application of VCC ‐ 3 5 ms Start Up Time Enable Func tion [Standby ] Enable Input Voltage VIH Pin 1 Logic '1', Output Enabled 0.7VCC ‐ ‐ V Disable Input Voltage VIL Pin 1 Logic '0', Output Disabled ‐ ‐ 0.3VCC V Disable Current IIL Pin 1 Logic '0', Output Disabled ‐ ‐ 20 uA Enable Time TPLZ Pin 1 Logic '1', Output Enabled ‐ ‐ 5 ns P hase Jitter, RMS tjrms Bandwidth 12 kHz ‐ 20 MHz ‐ 600 <1000 fs pjpk‐pk ‐ ‐ 2.5 ‐ ps pjrms ‐ ‐ 25 ‐ ps P eriod Jitter, pk‐pk P eriod Jitter, RMS Enable Truth Table Pin 1 Pin 4 & Pin 5 Logic ‘1’ Open Logic ‘0’ Output Output High Imp. Test Circuit LVDS LVPECL Output Waveform LVPECL or LVDS DOC# 008‐0549‐0 Rev. B Page 3 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Electrical Specifications Performance Data Phase Noise [typical] 100.00MHz, LVPECL, VCC = 3.3V, TA = +25°C 156.25MHz, LVPECL, VCC = 3.3V, TA = +25°C 312.50MHz, LVPECL, VCC = 3.3V, TA = +25°C 800.00MHz, LVPECL, VCC = 3.3V, TA = +25°C DOC# 008‐0549‐0 Rev. B Page 4 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Performance Data Phase Noise Tabulated Typical, HCMOS, VCC = 3.3V, TA = +25°C P ARAMETER SYMBO L CO NDITIO NS TYP UNIT P ARAMETER LVP ECL @ 1 0 0 .0 0 MHz P h ase No ise Single Side Band ‐ P h ase Jitter, RMS P ARAMETER CO NDITIO NS TYP tjrms P hase Noise UNIT Single Side Band @ 10Hz ‐69.70 @ 10Hz ‐88.60 @ 100Hz ‐92.90 @ 100Hz ‐97.80 @ 1kHz ‐115.90 @ 10kHz ‐126.80 dBc/Hz ‐ @ 1kHz ‐111.40 @ 10kHz ‐121.00 dBc/Hz ‐127.00 @ 100kHz ‐129.50 @ 100kHz @ 1MHz ‐143.50 @ 1MHz ‐141.80 @ 10MHz ‐154.90 @ 10MHz ‐151.50 @ 40MHz ‐155.30 @ 40MHz ‐153.30 Integration Bandwidth 12kHz ‐ 20MHz 714.35 SYMBO L CO NDITIO NS TYP fs P hase Jitter, RMS UNIT P ARAMETER LVP ECL @ 3 1 2 .5 0 MHz tjrms Integration Bandwidth 12kHz ‐ 20MHz 869.93 SYMBO L CO NDITIO NS TYP fs UNIT LVP ECL @ 8 0 0 .0 0 MHz P h ase No ise Single Side Band ‐ P h ase Jitter, RMS SYMBO L LVP ECL @ 1 5 6 .2 5 MHz tjrms P hase Noise Single Side Band @ 10Hz ‐81.30 @ 10Hz ‐85.00 @ 100Hz ‐91.80 @ 100Hz ‐90.90 @ 1kHz ‐105.30 @ 10kHz ‐115.50 dBc/Hz @ 1kHz ‐ @ 10kHz ‐96.90 ‐106.70 dBc/Hz @ 100kHz ‐120.80 @ 100kHz ‐107.50 @ 1MHz ‐136.40 @ 1MHz ‐125.90 @ 10MHz ‐153.20 @ 10MHz ‐145.40 @ 40MHz ‐153.20 @ 40MHz ‐150.40 Integration Bandwidth 12kHz ‐ 20MHz 496.03 fs P hase Jitter, RMS tjrms Integration Bandwidth 12kHz ‐ 20MHz 781.63 fs DOC# 008‐0549‐0 Rev. B Page 5 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Mechanical Specifications Package Drawing Marking Information 1. ** ‐ Manufacturing Site Code. 2. D – Date Code. See Table I for codes. 3. O – Output Type; P = LVPECL, L = LVDS. 3. ST – Frequency Stability/Temperature Code. [Refer to Ordering Information] 4. V – Voltage Code; 3 = 3.3V, 2 = 2.5V. 5. xxxx – Frequency Code. 3‐digits, frequencies below 100MHz 4‐digits, frequencies 100MHz or greater [See document 016‐1454‐0, Frequency Code Tables.] CTS**D 654OSTV ● xxxx Recommended Pad Layout Notes 1. JEDEC termination code (e4). Barrier‐plating is nickel [Ni] with gold [Au] flash plate. 2. Reflow conditions per JEDEC J‐STD‐020; +260°C maximum, 20 seconds. 3. MSL = 1. Pin Assignments Pin Symbol Function 1 2 3 4 5 6 EOH N.C. GND Output Output VCC Enable No Connect Circuit & Package Ground RF Output Complimentary RF Output Supply Voltage Table I ‐ Date Code MO NTH 2001 2002 2003 2004 YEAR 2005 2009 2006 2010 2007 2011 2008 2012 2013 2014 2015 2016 2017 2018 2019 2020 JAN FEB MAR AP R MAY JUN JUL AUG SEP O CT NO V DEC A N a n B P b p C Q c q D R d r E S e s F T f t G U g u H V h v J W j w K X k x L Y l y M Z m z DOC# 008‐0549‐0 Rev. B Page 6 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 654P/L Advanced PLL LVPECL or LVDS Clock Packaging ‐ Tape and Reel Tape Drawing Reel Drawing Notes 1. Device quantity is 1k pieces per 180mm reel. 2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. DOC# 008‐0549‐0 Rev. B Page 7 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.