VDIP1 datasheet

Future Technology Devices International Ltd.
VDIP1
Vinculum VNC1L Module
Datasheet
Document Reference No.: FT_000016
Version 1.02
Issue Date: 2010-05-31
Future Technology Devices International Ltd (FTDI)
Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom
Tel.: +44 (0) 141 429 2777
Fax: + 44 (0) 141 429 2758
E-Mail (Support): [email protected]
Web: http://www.vinculum.com
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow, G41 1HH, United Kingdom. Scotland Registered Number: SC136640
Copyright © 2010 Future Technology Devices International Limited
Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.02
Clearance No.: FTDI# 131
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1
Introduction
The VDIP1 module is an MCU to embedded USB host controller development module for the VNC1L IC
device. The VDIP1 is supplied on a PCB designed to fit into a 24 pin DIP socket, and provides access to
the UART, parallel FIFO, and SPI interface pins on the VNC1L device, via its AD and AC bus pins. Not only
is it ideal for developing and rapid prototyping of VNC1L designs, but also an attractive quantity discount
structure makes this module suitable for incorporation into low and medium volume finished product
designs.
Figure 1.1- VDIP1
The Vinculum VNC1L is the first of FTDI’s Vinculum family of Embedded USB host controller integrated
circuit devices. Not only is it able to handle the USB Host Interface, and data transfer functions but owing
to the inbuilt MCU and embedded Flash memory, Vinculum can encapsulate the USB device classes as
well. When interfacing to mass storage devices such as USB Flash drives, Vinculum also transparently
handles the FAT File structure communicating via UART, SPI or parallel FIFO interfaces via a simple to
implement command set. Vinculum provides a new cost effective solution for providing USB Host
capability into products that previously did not have the hardware resources available. The VNC1L is
available in Pb-free (RoHS compliant) compact 48-Lead LQFP package.
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VDIP1 Vinculum VNC1L Module Datasheet Version 1.02
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Table of Contents
1
Introduction .................................................................... 1
2
Features .......................................................................... 3
3
Pin Out and Signal Description ........................................ 4
3.1
Module Pin Out.......................................................................... 4
3.2
Pin Signal Description ............................................................... 5
3.3
I/O Configuration Using The Jumper Pin Header ...................... 6
3.4
Default Interface I/O Pin Configuration .................................... 7
3.5
Signal Descriptions - UART Interface ........................................ 8
3.6
Signal Descriptions – Serial Peripheral Interface (SPI) ........... 9
3.6.1
SPI Slave Data Read Cycle ......................................................................... 9
3.6.2
SPI Slave Data Write Cycle ....................................................................... 10
3.6.3
SPI Slave Data Timing Diagrams ............................................................... 11
3.7
4
Signal Descriptions - Parallel FIFO Interface .......................... 12
3.7.1
Timing Diagram – Parallel FIFO Read Transaction ........................................ 13
3.7.2
Timing Diagram - Parallel FIFO Write Transaction ........................................ 14
Firmware....................................................................... 15
4.1.1
Firmware Support .................................................................................... 15
4.1.2
Firmware Upgrades .................................................................................. 15
5
Mechanical Dimensions ................................................. 16
6
External circuit Configuration ....................................... 17
6.1
Adding a second USB Port ....................................................... 17
7
Schematic Diagram ....................................................... 18
8
Contact Information ...................................................... 20
Appendix A – References ................................................................. 21
Appendix B – List of Figures and Tables .......................................... 22
List of Figures ................................................................................. 22
List of Tables ................................................................................... 22
Appendix C – Revision History ......................................................... 23
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2
Features
The VDIP1 has the following features:
Uses FTDI’s VNC1L embedded dual USB host
controller IC device
Program or update firmware via USB Flash
disk or via UART/Parallel FIFO/SPI interface
USB single ‘A’ type USB socket to interface
with USB peripheral devices
Power and traffic indicator LED’s
Second USB interface port available via
module pins if required
VNC1L firmware programming control pins
PROG# and RESET# brought out onto jumper
interface
Jumper selectable UART, parallel FIFO or SPI
MCU interfaces
VDIP1 is a Pb-free, RoHS complaint
development module.
Single 5V supply input from USB connection
(no external supply necessary)
Schematics, and firmware files available for
download from the Vinculum website
Auxiliary 3.3 V / 200 mA power output to
external logic.
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3
Pin Out and Signal Description
3.1 Module Pin Out
Figure 3.1 - VDIP1 Module Pin Out (Top View)
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3.2 Pin Signal Description
Pin No.
Name
Pin Name on Type
PCB
Description
1
5V0
5V0
PWR
Input
5.0 V module supply pin. This pin provides the 5.0V output on the
USB ‘A’ type socket, and also the 3.3V supply to VNCL2, via an onboard 3.3 V L.D.O.
2
LED1
LD1
Output
USB port 1 traffic activity indicator LED. This pin is hard wired to a
green LED on board the PCB. It is also brought out onto this pin
which allows for the possibility of bring- ing out an additional LED
traffic indicator out of the VDIP1 board. For example, if the VDIP1
USB connector is brought out onto an instrument front panel, an
activity LED could be mounted along side it.
3
LED2
LD2
Output
USB port 2 traffic activity indicator LED. This pin is hard wired to a
green LED on board the PCB. It is also brought out onto this pin
which allows for the possibility of bring- ing out an additional LED
traffic indicator out of the VDIP1 board. For example, if the VDIP1
USB connector is brought out onto an instrument front panel, an
activity LED could be mounted along side it.
4
USBD1P
U1P
I/O
USB host / slave port 1 - USB Data Signal Plus with integrated pull
up / pull down resistor. Module has on board 27 Ω USB series
resistor. This pin can be brought out along with pin 5 to provide a
second USB port, if required
5
USBD1M
U1M
I/O
USB host / slave port 1 - USB Data Signal Minus with integrated pull
up / pull down resistor. Module has on board 27 Ω USB series
resistor. This pin can be brought out along with pin 4 to provide a
second USB port, if required
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
ADBUS0
GND
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
GND
ACBUS3
ACBUS4
ACBUS5
RESET#
AD0
GND
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AC0
AC1
AC2
GND
AC3
AC4
AC5
RS#
I/O
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWR
I/O
I/O
I/O
Input
5V safe bidirectional data / control bus, AD bit 0
Module ground supply pin
5V safe bidirectional data / control bus, AD bit 1
5V safe bidirectional data / control bus, AD bit 2
5V safe bidirectional data / control bus, AD bit 3
5V safe bidirectional data / control bus, AD bit 4
5V safe bidirectional data / control bus, AD bit 5
5V safe bidirectional data / control bus, AD bit 6
5V safe bidirectional data / control bus, AD bit 7
5V safe bidirectional data / control bus, AC bit 0
5V safe bidirectional data / control bus, AC bit 1
5V safe bidirectional data / control bus, AC bit 2
Module Ground Supply Pin
5V safe bidirectional data / control bus, AC bit 3
5V safe bidirectional data / control bus, AC bit 4
5V safe bidirectional data / control bus, AC bit 5
Can be used by an external device to reset the VNC1L. This pin can be used
in combination with PROG# and the UART / parallel FIFO / SPI interface to
program firmware into the Vinculum
23
PROG#
PG#
Input
24
3V3
This pin is used in combination with the RESET# pin and the UART / parallel
FIFO / SPI interface to pro gra m fir mware into t he VNC1L.
3.3V output from VDIP1’s on board 3.3V L.D.O.
3V3
PWR
Table 3.1 - Pin Signal Descriptions
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3.3 I/O Configuration Using The Jumper Pin Header
Two three way jumper pin headers are provided to allow for simple configuration of the I/O on data and
control bus pins of the VDIP1. This is done by a combination of pulling up or pulling down the VNC1L
ACBUS5 (pin 46) and ACBUS6 (pin 47). The relevant portion of the VDIP1 module schematic is shown in
Figure 3.2
Figure 3.2 – VDIP1 On-Board Jumper Pin Configuration.
ACBUS6
(VNC1L pin 47)
I/O Mode
ACBUS5
(VNC1L pin 46)
Pull-Up
Pull-Up
Serial UART
Pull-Up
Pull-Down
SPI
Pull-Down
Pull-Up
Parallel FIFO
Pull-Down
Pull-Down
Serial UART
Table 3.2 - VDIP1 Port Selection Jumper Pins
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3.4 Default Interface I/O Pin Configuration
The VNC1L device is pre-programmed with default settings for the I/O pins however they can be easily
changed to suit a designers needs. The default interface I/O pin configuration of the VNC1L device are
shown in Table 3.3
Data and Control Bus Configuration
Options
Pin
No.
Name
6
ADBUS0
AD0
I/O
8
ADBUS1
AD1
I/O
Pin
Name
on
PCB
Type
Description
UART
Interface
9
ADBUS2
AD2
I/O
10
ADBUS3
AD3
I/O
11
ADBUS4
AD4
I/O
12
ADBUS5
AD5
I/O
13
ADBUS6
AD6
I/O
14
ADBUS7
AD7
I/O
15
ACBUS0
AC0
I/O
16
ACBUS1
AC1
I/O
17
ACBUS2
AC2
I/O
19
ACBUS3
AC3
I/O
20
ACBUS4
AC4
I/O
Parallel FIFO
Interface
SPI Slave
Interface
I/O Port
5V safe
bidirectional
data / control
bus, AD bit 0
TXD
D0
SCLK
PortAD0
5V safe
bidirectional
data / control
bus, AD bit 1
RXD
D1
SDI
PortAD1
5V safe
bidirectional
data / control
bus, AD bit 2
RTS#
D2
SDO
PortAD2
5V safe
bidirectional
data / control
bus, AD bit 3
CTS#
D3
CS
PortAD3
5V safe
bidirectional
data / control
bus, AD bit 4
DTR#
D4
PortAD4
5V safe
bidirectional
data / control
bus, AD bit 5
DSR#
D5
PortAD5
5V safe
bidirectional
data / control
bus, AD bit 6
DCD#
D6
PortAD6
5V safe
bidirectional
data / control
bus, AD bit 7
RI#
D7
PortAD7
5V safe
bidirectional
data / control
bus, AC bit 0
TXDEN#
RXF#
PortAC0
5V safe
bidirectional
data / control
bus, AC bit 1
TXE#
PortAC1
5V safe
bidirectional
data / control
bus, AC bit 2
RD#
PortAC2
5V safe
bidirectional
data / control
bus, AC bit 3
WR
PortAC3
5V safe
bidirectional
data / control
bus, AC bit 4
Table 3.3 - Default Interface I/O Pin Configuration
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PortAC4
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3.5 Signal Descriptions - UART Interface
The UART interface I/O pin description of the VNC1L device are shown in Table 3.4
Pin No.
Name
Type
Description
6
TXD
Output
Transmit asynchronous data output
8
RXD
Input
Receive asynchronous data input
9
RTS#
Output
Request To Send Control Output / Handshake signal
10
CTS#
Input
Clear To Send Control Input / Handshake signal
11
DTR#
Output
Data Terminal Ready Control Output / Handshake signal
12
DSR#
Input
Data Set Ready Control Input / Handshake signal
13
DCD#
Input
Data Carrier Detect Control Input
Input
Ring Indicator Contro l Input. When the RemoteakeW up option is enabled in the
EEPROM, taking RI# low can be used to resume the PC USB Host controller
from suspend
14
RI#
15
TXDEN#
Input
Enable Transmit Data for RS485 designs
Table 3.4 - Default I/O Pin Configuration – UART Interface
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3.6 Signal Descriptions – Serial Peripheral Interface (SPI)
The SPI I/O pin description of the VNC1L device are shown in Table 3.5
Pins No
Name
Type
Description
6
SCLK
Input
SPI Clock input, 12MHz maximum.
8
SDI
Input
SPI Serial Data Input
9
SDO
Output
SPI Serial Data Output
10
CS
Input
SPI Chip Select Input
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave Interface
3.6.1 SPI Slave Data Read Cycle
When in SPI mode, the timing of a read operation is shown in Figure 3.3
Figure 3.3 – SPI Slave Data Read Cycle.
From Start - SPI CS must be held high for the entire read cycle, and must be taken low for at least one
clock period after t he read is co mpleted. The first bit on SPI Data In is the R/W bit - inputting a ‘1’ here
a llows data to be read fro m the chip. The next bit is the address bit, ADD, which is used to indicate
whether the data register (‘0’) or the status register (‘1’) is read from. During the SPI read cycle a byte of
data will start being output on SPI Data Out on the next clock cycle after t he address bit, MSBAfterfirst.t
he data has been clocked out of the chip, t he status of SPI Data. Out should be checked to see if the
data read is new data. A ‘0’ level here on SPI Data Out means that the data read is new data. A ‘1’
indicates that the data read is old data, and the read cycle should be repeated to get new data.
Remember that CS must be held low for at least one clock period before being taken high again to
continue with the next read or write cycle.
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3.6.2 SPI Slave Data Write Cycle
When in SPI mode, the timing of a write operation is shown in
Figure 3.4 – SPI Slave Data Write Cycle.
From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least
one clock period after t he write is co mpletedThe. first bit on SPI Data In is the R/W bit - inputting
a ‘0’ here a llows data to be written to the chip. The next bit is the address bit, ADD, which is used
to indicate whether the data register (‘0’) or the status register (‘1’) is written to. During the SPI
write cycle a byte of data can be input to SPI Data In on the next clock cycle after t he address bit,
MSBAfterfirst.t he data has been clocked in to the chip, t he status of SPI Data Out should be
checked to see if the data read was accepted. A ‘0’ level on SPI Data Out means that the data
write was accepted. A ‘1’ indicates that the internal buffer is full, and the write should be repeated.
Remember that CS must be held low for at least one clock period before being taken high again to
continue with the next read or write cycle.
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3.6.3 SPI Slave Data Timing Diagrams
Figure 3.5 – SPI Slave Data Timing Diagrams.
Time
Description
Min
T1
SPICLK Period
83
T2
SPICLK High
20
T3
SPICLK Low
20
T4
Input Setup Time
10
T5
Input Hold Time
10
T6
Output Hold Time
2
T7
Output Valid Time
Table 3.6 - SPI Slave Data Timing
Time
-
Typical
Max
Unit
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
20
ns
Description
T1
RXF#
T2
TXE#
T3
-
T4
-
T5
RXF IRQEn
T6
TXE IRQEn
T7
Table 3.7 - SPI Slave Status Register (ADD=’1’)
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3.7 Signal Descriptions - Parallel FIFO Interface
The Parallel FIFO interface I/O pin description of the VNC1L device is shown in Table 3.8
Pin No.
Name
Type
Description
6
D0
I/O
FIFO Data Bus Bit 0
8
D1
I/O
FIFO Data Bus Bit 1
9
D2
I/O
FIFO Data Bus Bit 2
10
D3
I/O
FIFO Data Bus Bit 3
11
D4
I/O
FIFO Data Bus Bit 4
12
D5
I/O
FIFO Data Bus Bit 5
13
D6
I/O
FIFO Data Bus Bit 6
14
D7
I/O
FIFO Data Bus Bit 7
When high, do not read data from the FIFO. When low, there is data
available in the FIFO which can be read by stro bing RD# low, t hen
high again.
15
RXF#
OUTPUT
16
TXE#
OUTPUT
When high, do not write data into the FIFO. When low, data can be
written into the FIFO by strobing WR high, then low.
INPUT
Enables the current
FIFO data byte on D0...D7 when low. Fetched the
next FIFO data byte (if avail- able) fro m the recei ve FIFO buffer w hen
RD# goes fro m high to low
17
RD#
Writes the data byte on the D0...D7 pins into the transmit FIFO buffer
19
WR
INPUT
when WR goes from high to low.
Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface
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3.7.1 Timing Diagram – Parallel FIFO Read Transaction
When in parallel FIFO interface mode, the timing of a read is shown in Figure 3.6 and Table 3.9
Figure 3.6 - FIFO Read Cycle.
Time
Description
Min
Max
Unit
T1
RD# Active Pulse Width
50
-
ns
T2
RD# to RD# Pre-Charge Time
50 + T6
-
ns
T3
RD# Active to Valid Data*
20
50
ns
T4
0
-
ns
T5
Valid Data Hold Time from RD#
Inactive*
RD# Inactive to RXF#
0
25
ns
T6
RXF# Inactive After RD# Cycle
80
-
ns
Table 3.9 FIFO Read Cycle Timing
* Load = 30pF
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3.7.2 Timing Diagram - Parallel FIFO Write Transaction
When in parallel FIFO interface mode, the timing of a write operation is shown in Figure 3.7 and Table
3.10
Figure 3.7 - FIFO Write Cycle.
Time
Description
Min
Max
Unit
T7
WR Active Pulse Width
50
-
ns
T8
WR to WR Pre-Charge Time
50
-
ns
T9
WR Active to Valid Data
20
-
ns
T10
Data Hold Time from WR
Inactive*
WR Inactive to TXE#
0
-
ns
T11
5
25
ns
T12
TXE# Inactive After WR Cycle
80
-
ns
Table 3.10 - FIFO Write Cycle Timing
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4
Firmware
4.1.1 Firmware Support
There are currently 6 standard firmware versions available for VDIP1 module which can be downloaded
from the FTDI website.
VDAP Firmware: USB Host for single Flash Disk and General Purpose USB peripherals. Selectable
UART, FIFO or SPI interface command monitor.
VDPS Firmware: USB Host for single Flash Disk and General Purpose USB peripherals. USB Slave
port connection for connecting to host PC. Selectable UART, FIFO or SPI interface command
monitor.
VDFC Firmware: USB Host for two Flash Disks, Selectable UART, FIFO or SPI interface command
monitor.
VCDC Firmware: USB Host for automatic connection to USB Communications Class Devices. UART
interface command monitor.
VDIF Firmware: USB Host for single Flash Disk and General Purpose USB peripherals. Selectable
UART, FIFO, SPI or USB interface command monitor.
4.1.2 Firmware Upgrades
The VDIP1 module is supplied pre-loaded with the VDAP firmware.
There are two methods of upgrading the firmware on the VDIP1. These methods are described in a
Vinculum Firmware manual please refer to:http://www.vinculum.com/documents/fwspecs/UM_VinculumFirmware_V205.pdf
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5
Mechanical Dimensions
Figure 5.1 VDIP1 Dimensions (Top View)
Figure 5.2 VDIP1 Dimensions (Side View)
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6
External circuit Configuration
6.1 Adding a second USB Port
The external circuit configuration for adding second USB host port, with the USB activity LED,
is shown below in Figure 6.1
Figure 6.1 Additional USB Port Configuration
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7
Schematic Diagram
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Figure 7.1 - Schematic Diagram
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8
Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place,
Centurion Business Park
Glasgow, G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
[email protected]
E-mail (Support) [email protected]
E-mail (General Enquiries) [email protected]
Web Site URL
http://www.ftdichip.com
Web Shop URL
http://www.ftdichip.com
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)
2F, No 516, Sec. 1 NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8791 3570
Fax: +886 (0) 2 8791 3576
E-mail (Sales)
[email protected]
E-mail (Support) [email protected]
E-mail (General Enquiries) [email protected]
Web Site URL
http://www.ftdichip.com
Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)
7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
[email protected]
E-Mail (Support) [email protected]
E-Mail (General Enquiries) [email protected]
Web Site URL
http://www.ftdichip.com
Branch Office – Shanghai, China
Future Technology Devices International Limited (China)
Room 408, 317 Xianxia Road,
ChangNing District,
ShangHai, China
Tel: +86 (21) 62351596
Fax: +86(21) 62351595
E-Mail (Sales): [email protected]
E-Mail (Support): [email protected]
E-Mail (General Enquiries): [email protected]
Web Site URL
http://www.ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
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Appendix A – References
http://www.vinculum.com/documents/fwspecs/UM_VinculumFirmware_V205.pdf
Copyright © 2010 Future Technology Devices International Limited
21
Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.02
Clearance No.: FTDI# 131
`
Appendix B – List of Figures and Tables
List of Figures
Figure 1.1- VDIP1 ......................................................................................................................... 1
Figure 3.1 - VDIP1 Module Pin Out (Top View) .................................................................................. 4
Figure 3.2 – VDIP1 On-Board Jumper Pin Configuration. ................................................................... 6
Figure 3.3 – SPI Slave Data Read Cycle. .......................................................................................... 9
Figure 3.4 – SPI Slave Data Write Cycle. ....................................................................................... 10
Figure 3.5 – SPI Slave Data Timing Diagrams................................................................................. 11
Figure 3.6 - FIFO Read Cycle. ....................................................................................................... 13
Figure 3.7 - FIFO Write Cycle. ...................................................................................................... 14
Figure 5.1 VDIP1 Dimensions (Top View) ....................................................................................... 16
Figure 5.2 VDIP1 Dimensions (Side View) ...................................................................................... 16
Figure 6.1 Additional USB Port Configuration .................................................................................. 17
Figure 7.1 - Schematic Diagram ................................................................................................... 19
List of Tables
Table 3.1 - Pin Signal Descriptions .................................................................................................. 5
Table 3.2 - VDIP1 Port Selection Jumper Pins ................................................................................... 6
Table 3.4 - Default I/O Pin Configuration – UART Interface ................................................................ 8
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave Interface ........................................ 9
Table 3.6 - SPI Slave Data Timing ................................................................................................ 11
Table 3.7 - SPI Slave Status Register (ADD=’1’) ............................................................................. 11
Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface ............................ 12
Table 3.9 FIFO Read Cycle Timing ................................................................................................. 13
Table 3.10 - FIFO Write Cycle Timing ............................................................................................ 14
Copyright © 2010 Future Technology Devices International Limited
22
Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.02
Clearance No.: FTDI# 131
`
Appendix C – Revision History
Version 0.91
Initial Datasheet Created
Version 0.92
Datasheet Updated
Version 1.0
Datasheet Updated (Reformatted)
August 2006
March 2007
th
10
December 2009
Datasheet Updated (Mechanical Drawings)
Added Appendix A
Added schematic
Version 1.01
Corrected Table 3.1 (pin 18, 19, 20, 21)
31st May 2010
Version 1.02
Corrected figure 7.1 (C8 & C9 changed to 68pF)
14th June 2011
Copyright © 2010 Future Technology Devices International Limited
23