PIC16F1516 DATA SHEET (06/07/2016) DOWNLOAD

PIC16(L)F1516/7/8/9
28/40/44-Pin Flash Microcontrollers with XLP Technology
Devices Included In This Data Sheet
• PIC16F1516
• PIC16LF1516
• PIC16F1517
• PIC16LF1517
• PIC16F1518
• PIC16LF1518
• PIC16F1519
• PIC16LF1519
High-Performance RISC CPU
• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 20 MHz clock input @ 2.5V
- DC – 16 MHz clock input @ 1.8V
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Memory
• Up to 28 Kbytes Linear Program Memory
Addressing
• Up to 1024 Bytes Linear Data Memory
Addressing
• High Endurance Flash Data Memory (HEF):
- 128B of nonvolatile data storage
• 100K Erase/Write Cycles
Flexible Oscillator Structure
• 16 MHz Internal Oscillator Block:
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• External Oscillator Block with:
- Four crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Two-Speed Oscillator Start-up
• Oscillator Start-up Timer (OST)
 2010-2016 Microchip Technology Inc.
Analog Features
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Up to 28 channels
- Auto acquisition capability
- Conversion available during Sleep
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
• Temperature Indicator
eXtreme Low-Power (XLP) Management
PIC16LF1516/7/8/9 with XLP
•
•
•
•
Sleep mode: 20 nA @ 1.8V, typical
Watchdog Timer: 300 nA @ 1.8V, typical
Secondary Oscillator: 600 nA @ 32 kHz
Operating Current: 30 A/MHz @ 1.8V, typical
Special Microcontroller Features
• Operating Voltage Range:
- 2.3V-5.5V (PIC16F1516/7/8/9)
- 1.8V-3.6V (PIC16LF1516/7/8/9)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Low-Power Brown-out Reset (LPBOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Enhanced Low-Voltage Programming (LVP)
• Programmable Code Protection
• Low-Power Sleep mode
Peripheral Highlights
• Up to 35 I/O Pins and 1 Input-Only Pin:
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable
interrupt-on-change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Low-power 32 kHz secondary oscillator driver
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture/Compare (CCP) modules
DS40001452F-page 1
PIC16(L)F1516/7/8/9
• Master Synchronous Serial Port (MSSP) with SPI
and I2C with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
- Auto-wake-up on start
Note:
Debug(1)
XLP
PIC16(L)F1512
(1)
2048
128
128
25
17
Y
2/1
1
1
PIC16(L)F1513
(1)
4096
256
128
25
17
Y
2/1
1
1
PIC16(L)F1516
(2)
8192
512
128
25
17
N
2/1
1
1
PIC16(L)F1517
(2)
8192
512
128
36
28
N
2/1
1
1
PIC16(L)F1518
(2)
16384
1024
128
25
17
N
2/1
1
1
PIC16(L)F1519
(2)
16384
1024
128
36
28
N
2/1
1
1
PIC16(L)F1526
(3)
8192
768
128
54
30
N
6/3
2
2
PIC16(L)F1527
(3)
16384
1536
128
54
30
N
6/3
2
2
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001624
PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS40001452
PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs.
3: DS40001458
PIC16(L)F1526/27 Data Sheet, 64-Pin Flash, 8-bit MCUs.
CCP
MSSP (I2C/SPI)
EUSART
Timers
(8/16-bit)
Advanced Control
10-bit (ch)
ADC
I/O’s(2)
High Endurance Flash
(bytes)
Data SRAM
(bytes)
Program Memory
Flash (words)
Device
Data Sheet Index
PIC16(L)F151X/152X Family Types
2
2
2
2
2
2
10
10
I
I
I
I
I
I
I
I
Y
Y
Y
Y
Y
Y
Y
Y
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001452F-page 2
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 1:
28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16(L)F1516/1518
28-Pin SPDIP, SOIC, SSOP
1
28
RB7/ICSPDAT
RA0
2
27
RB6/ICSPCLK
RA1
3
26
RB5
RA2
4
25
RB4
RA3
5
24
RB3
RA4
6
23
RB2
RA5
7
RB1
VSS
8
22
21
RA7
9
20
VDD
RA6
10
19
VSS
RC0
11
18
RC7
RC1
12
17
RC6
RC2
13
16
RC5
RC3
14
15
RC4
PIC16F1516/1518
PIC16LF1516/1518
VPP/MCLR/RE3
RB0
Note: See Table 1 for location of all peripheral functions.
FIGURE 2:
28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16(L)F1516/1518
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28-Pin UQFN
21
20
19
PIC16F1516/1518
18
PIC16LF1516/1518
17
16
15
8
9
10
11
12
13
14
1
2
3
4
5
6
7
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5
VSS
RA7
RA6
Note 1:
2:
See Table 1 for location of all peripheral functions.
It is recommended that the exposed bottom pad be connected to VSS.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 3
PIC16(L)F1516/7/8/9
FIGURE 3:
28-PIN QFN (6X6) PACKAGE DIAGRAM FOR PIC16(L)F1516/1518
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28-Pin QFN
21
20
19
PIC16F1516/1518
18
PIC16LF1516/1518
17
16
15
8
9
10
11
12
13
14
1
2
3
4
5
6
7
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5
VSS
RA7
RA6
Note 1:
2:
See Table 1 for location of all peripheral functions.
It is recommended that the exposed bottom pad be connected to VSS.
DS40001452F-page 4
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 4:
40-PIN PDIP PACKAGE DIAGRAM FOR PIC16(L)F1517/1519
40-Pin PDIP
1
40
RB7/ICSPDAT
RA0
2
39
RB6/ICSPCLK
RA1
3
38
RB5
RA2
4
37
RB4
RA3
5
36
RB3
RA4
6
35
RB2
RA5
7
34
RB1
RE0
8
33
RB0
RE1
9
32
VDD
RE2
10
31
VSS
VDD
11
30
RD7
VSS
12
29
RD6
RA7
13
28
RD5
RA6
14
27
RD4
RC0
15
26
RC7
RC1
16
25
RC6
RC2
17
24
RC5
RC3
18
23
RC4
RD0
19
22
RD3
21
RD2
RD1
Note 1:
20
PIC16F1517/1519
PIC16LF1517/1519
VPP/MCLR/RE3
See Table 1 for location of all peripheral functions.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 5
PIC16(L)F1516/7/8/9
FIGURE 5:
40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16(L)F1517/1519
40
39
38
37
36
35
34
33
32
31
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
40-Pin UQFN
1
2
3
4
5
6
7
8
9
10
PIC16F1517/1519
PIC16LF1517/1519
30
29
28
27
26
25
24
23
22
21
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
11
12
13
14
15
16
17
18
19
20
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
Note 1:
2:
See Table 1 for location of all peripheral functions.
It is recommended that the exposed bottom pad be connected to VSS.
FIGURE 6:
44-PIN TQFP PACKAGE DIAGRAM FOR PIC16(L)F1517/1519
PIC16F1517/1519
PIC16LF1517/1519
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
RE3
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RC7
RD4
RD5
RD6
RD7
VSS
VDD
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
44-Pin TQFP
Note:
DS40001452F-page 6
See Table 1 for location of all peripheral functions.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
40-Pin UQFN
44-Pin TQFP
ADC
Timers
CCP
EUSART
MSSP
27
2
17
19
AN0
—
—
—
SS(2)
—
—
—
RA1
3
28
3
18
20
AN1
—
—
—
—
—
—
—
Basic
40-Pin PDIP
2
Pull-up
28-Pin QFN, UQFN
RA0
Interrupt
28-Pin SPDIP, SOIC, SSOP
28/40/44-PIN ALLOCATION TABLE
I/O
TABLE 1:
RA2
4
1
4
19
21
AN2
—
—
—
—
—
—
—
RA3
5
2
5
20
22
AN3/VREF+
—
—
—
—
—
—
—
RA4
6
3
6
21
23
—
T0CKI
—
—
—
—
—
—
RA5
7
4
7
22
24
AN4
—
—
—
SS(1)
—
—
VCAP
RA6
10
7
14
29
31
—
—
—
—
—
—
—
OSC2/CLKOUT
RA7
9
6
13
28
30
—
—
—
—
—
—
—
OSC1/CLKIN
RB0
21
18
33
8
8
AN12
—
—
—
—
INT/IOC
Y
—
RB1
22
19
34
9
9
AN10
—
—
—
—
IOC
Y
—
—
RB2
23
20
35
10
10
AN8
—
—
—
—
IOC
Y
RB3
24
21
36
11
11
AN9
—
CCP2(2)
—
—
IOC
Y
—
RB4
25
22
37
12
14
AN11
—
—
—
—
IOC
Y
—
RB5
26
23
38
13
15
AN13
T1G
—
—
—
IOC
Y
—
RB6
27
24
39
14
16
—
—
—
—
—
IOC
Y
ICSPCLK/ICDCLK
ICSPDAT/ICDDAT
RB7
28
25
40
15
17
—
—
—
—
—
IOC
Y
RC0
11
8
15
30
32
—
SOSCO/T1CKI
—
—
—
—
—
—
RC1
12
9
16
31
35
—
SOSCI
CCP2(1)
—
—
—
—
—
RC2
13
10
17
32
36
AN14
—
CCP1
—
—
—
—
—
RC3
14
11
18
33
37
AN15
—
—
—
SCK/SCL
—
—
—
RC4
15
12
23
38
42
AN16
—
—
—
SDI/SDA
—
—
—
RC5
16
13
24
39
43
AN17
—
—
—
SDO
—
—
—
RC6
17
14
25
40
44
AN18
—
—
TX/CK
—
—
—
—
RC7
18
15
26
1
1
AN19
—
—
RX/DT
—
—
—
—
RD0(3)
—
—
19
34
38
AN20
—
—
—
—
—
—
—
RD1(3)
—
—
20
35
39
AN21
—
—
—
—
—
—
—
RD2(3)
—
—
21
36
40
AN22
—
—
—
—
—
—
—
RD3(3)
—
—
22
37
41
AN23
—
—
—
—
—
—
—
RD4(3)
—
—
27
2
2
AN24
—
—
—
—
—
—
—
RD5(3)
—
—
28
3
3
AN25
—
—
—
—
—
—
—
RD6(3)
—
—
29
4
4
AN26
—
—
—
—
—
—
—
RD7(3)
—
—
30
5
5
AN27
—
—
—
—
—
—
—
RE0(3)
—
—
8
23
25
AN5
—
—
—
—
—
—
—
RE1(3)
—
—
9
24
26
AN6
—
—
—
—
—
—
—
RE2(3)
—
—
10
25
27
AN7
—
—
—
—
—
—
—
RE3
1
26
1
16
18
—
—
—
—
—
—
Y
MCLR/VPP
VDD
20
17
11,
32
7,
26
7,
28
—
—
—
—
—
—
—
—
VSS
8,
19
5, 12, 6,
16 31 27
6,
29
—
—
—
—
—
—
—
—
NC
—
—
12,
13,
33,
34
—
—
—
—
—
—
—
—
Note 1:
—
—
Peripheral pin location selected using APFCON register. Default location.
2:
Peripheral pin location selected using APFCON register. Alternate location.
3:
PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 7
PIC16(L)F1516/7/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 10
2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 15
3.0 Memory Organization ................................................................................................................................................................. 17
4.0 Device Configuration .................................................................................................................................................................. 41
5.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 47
6.0 Resets ........................................................................................................................................................................................ 62
7.0 Interrupts .................................................................................................................................................................................... 70
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 80
9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 84
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 85
11.0 Flash Program Memory Control ................................................................................................................................................. 89
12.0 I/O Ports ................................................................................................................................................................................... 105
13.0 Interrupt-on-Change ................................................................................................................................................................. 124
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 128
15.0 Temperature Indicator Module ................................................................................................................................................. 130
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 132
17.0 Timer0 Module ......................................................................................................................................................................... 145
18.0 Timer1 Module with Gate Control............................................................................................................................................. 148
19.0 Timer2 Module ......................................................................................................................................................................... 159
20.0 Capture/Compare/PWM Modules ............................................................................................................................................ 163
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 171
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 222
23.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 251
24.0 Instruction Set Summary .......................................................................................................................................................... 253
25.0 Electrical Specifications............................................................................................................................................................ 267
26.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 298
27.0 Development Support............................................................................................................................................................... 330
28.0 Packaging Information.............................................................................................................................................................. 334
Appendix A: Data Sheet Revision History.......................................................................................................................................... 355
The Microchip Website....................................................................................................................................................................... 356
Customer Change Notification Service .............................................................................................................................................. 356
Customer Support .............................................................................................................................................................................. 356
Product Identification System............................................................................................................................................................. 358
DS40001452F-page 8
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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 2010-2016 Microchip Technology Inc.
DS40001452F-page 9
PIC16(L)F1516/7/8/9
1.0
DEVICE OVERVIEW
The PIC16(L)F1516/7/8/9 are described within this data
sheet. Figure 1-1 shows a block diagram of the
PIC16(L)F1516/7/8/9 devices. Table 1-2 shows the
pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
Peripheral
PIC16(L)F1517
PIC16(L)F1518
PIC16(L)F1519
DEVICE PERIPHERAL
SUMMARY
PIC16(L)F1516
TABLE 1-1:
Analog-to-Digital Converter (ADC)
●
●
●
●
Fixed Voltage Reference (FVR)
●
●
●
●
Temperature Indicator
●
●
●
●
CCP1
●
●
●
●
CCP2
●
●
●
●
EUSART ●
●
●
●
Capture/Compare/PWM Modules
EUSARTs
Master Synchronous Serial Ports
MSSP
●
●
●
●
Timer0
●
●
●
●
Timer1
●
●
●
●
Timer2
●
●
●
●
Timers
DS40001452F-page 10
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 1-1:
PIC16(L)F1516/7/8/9 BLOCK DIAGRAM
Program
Flash Memory
RAM
OSC2/CLKOUT
OSC1/CLKIN
PORTA
PORTB
Timing
Generation
CPU
INTRC
Oscillator
PORTC
(Figure 2-1)
MCLR
PORTD(3)
PORTE(4)
Note
1:
2:
3:
4:
CCP1
Timer0
Temp.
Indicator
ADC
10-Bit
FVR
CCP2
MSSP
Timer1
Timer2
EUSART
See applicable chapters for more information on peripherals.
See Table 1-1 for peripherals available on specific devices.
PIC16(L)F1517/9 only.
RE<2:0>, PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 11
PIC16(L)F1516/7/8/9
TABLE 1-2:
PINOUT DESCRIPTION
Name
RA0/AN0/SS(2)
Function
Input
Type
RA0
TTL
AN0
AN
SS
ST
RA1/AN1
RA1
TTL
AN1
AN
RA2/AN2
RA2
TTL
AN2
AN
RA3/AN3/VREF+
RA3
TTL
RA4/T0CKI
(1)
RA5/AN4/SS /VCAP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN12/INT
RB1/AN10
ADC Channel 0 input.
—
Slave Select input.
CMOS General purpose I/O.
—
ADC Channel 1 input.
CMOS General purpose I/O.
—
ADC Channel 2 input.
CMOS General purpose I/O.
AN
—
ADC Channel 3 input.
—
ADC Positive Voltage Reference input.
RA4
TTL
T0CKI
ST
RA5
TTL
AN4
AN
CMOS General purpose I/O.
—
Timer0 clock input.
CMOS General purpose I/O.
—
SS
ST
—
VCAP
Power
Power
RA6
TTL
OSC2
—
ADC Channel 4 input.
Slave Select input.
Filter capacitor for Voltage Regulator (PIC16F1516/7/8/9 only).
CMOS General purpose I/O.
XTAL
Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
CLKOUT
—
RA7
TTL
OSC1
XTAL
—
Crystal/Resonator (LP, XT, HS modes).
CLKIN
ST
—
External clock input (EC mode).
CMOS General purpose I/O.
RB0
TTL
AN12
AN
—
ADC Channel 12 input.
INT
ST
—
External interrupt.
RB1
TTL
AN
TTL
AN8
AN
RB3/AN9/CCP2(2)
RB3
TTL
RB7/ICSPDAT
—
AN
RB2
RB6/ICSPCLK
CMOS General purpose I/O.
AN3
AN10
RB5/AN13/T1G
Description
VREF+
RB2/AN8
RB4/AN11
Output
Type
CMOS General purpose I/O with IOC and WPU.
CMOS General purpose I/O with IOC and WPU.
—
ADC Channel 10 input.
CMOS General purpose I/O with IOC and WPU.
—
ADC Channel 8 input.
CMOS General purpose I/O with IOC and WPU.
AN9
AN
CCP2
ST
CMOS Capture/Compare/PWM 2.
CMOS General purpose I/O with IOC and WPU.
RB4
TTL
AN11
AN
—
—
ADC Channel 9 input.
ADC Channel 11 input.
RB5
TTL
AN13
AN
CMOS General purpose I/O with IOC and WPU.
—
ADC Channel 13 input.
T1G
ST
—
Timer1 Gate input.
RB6
TTL
CMOS General purpose I/O with IOC and WPU.
ICSPCLK
ST
CMOS In-Circuit Data I/O.
RB7
TTL
CMOS General purpose I/O with IOC and WPU.
ICSPDAT
ST
CMOS ICSP™ Data I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
DS40001452F-page 12
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 1-2:
PINOUT DESCRIPTION (CONTINUED)
Name
RC0/SOSCO/T1CKI
RC1/SOSCI/CCP2(1)
RC2/AN14/CCP1
RC3/AN15/SCK/SCL
RC4/AN16/SDI/SDA
RC5/AN17/SDO
RC6/AN18/TX/CK
RC7/AN19/RX/DT
RD0(3)/AN20
RD1(3)/AN21
RD2(3)/AN22
RD3(3)/AN23
RD4(3)/AN24
RD5(3)/AN25
RD6(3)/AN26
Function
Input
Type
RC0
ST
Output
Type
Description
CMOS General purpose I/O.
SOSCO
—
XTAL
T1CKI
ST
—
RC1
ST
SOSCI
—
Secondary oscillator connection.
Timer1 clock input.
CMOS General purpose I/O.
XTAL
Secondary oscillator connection.
CCP2
ST
CMOS Capture/Compare/PWM 2.
RC2
ST
CMOS General purpose I/O.
AN14
AN
CCP1
ST
CMOS Capture/Compare/PWM 1.
CMOS General purpose I/O.
RC3
ST
AN15
AN
SCK
ST
SCL
I2C
—
—
ADC Channel 14 input.
ADC Channel 15 input.
CMOS SPI clock.
OD
I2C clock.
RC4
ST
AN16
AN
CMOS General purpose I/O.
—
ADC Channel 16 input.
SDI
ST
—
SPI data input.
SDA
I2C
OD
I2C data input/output.
RC5
ST
AN17
AN
CMOS General purpose I/O.
SDO
—
CMOS SPI data output.
RC6
ST
CMOS General purpose I/O.
AN18
AN
TX
—
—
—
ADC Channel 17 input.
ADC Channel 18 input.
CMOS USART asynchronous transmit.
CK
ST
CMOS USART synchronous clock.
RC7
ST
CMOS General purpose I/O.
AN19
AN
—
ADC Channel 19 input.
RX
ST
—
USART asynchronous input.
DT
ST
CMOS USART synchronous data.
RD0
ST
CMOS General purpose I/O.
AN20
AN
RD1
ST
AN21
AN
RD2
ST
AN22
AN
RD3
ST
AN23
AN
RD4
ST
AN24
AN
RD5
ST
AN25
AN
RD6
ST
AN26
AN
—
ADC Channel 20 input.
CMOS General purpose I/O.
—
ADC Channel 21 input.
CMOS General purpose I/O.
—
ADC Channel 22 input.
CMOS General purpose I/O.
—
ADC Channel 23 input.
CMOS General purpose I/O.
—
ADC Channel 24 input.
CMOS General purpose I/O.
—
ADC Channel 25 input.
CMOS General purpose I/O.
—
ADC Channel 26 input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 13
PIC16(L)F1516/7/8/9
TABLE 1-2:
PINOUT DESCRIPTION (CONTINUED)
Name
RD7(3)/AN27
Function
Input
Type
RD7
ST
Output
Type
Description
CMOS General purpose I/O.
AN27
AN
RE0(3)/AN5
RE0
ST
—
ADC Channel 27 input.
AN5
AN
RE1(3)/AN6
RE1
ST
AN6
AN
RE2(3)/AN7
RE2
ST
AN7
AN
—
ADC Channel 7 input.
RE3/MCLR/VPP
RE3
ST
—
General purpose input with WPU.
CMOS General purpose I/O.
—
ADC Channel 5 input.
CMOS General purpose I/O.
—
ADC Channel 6 input.
CMOS General purpose I/O.
MCLR
ST
—
Master Clear with internal pull-up.
VPP
HV
—
Programming voltage.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
DS40001452F-page 14
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
2.0
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
FIGURE 2-1:
•
•
•
•
Automatic Interrupt Context Saving
16-level Stack with Overflow and Underflow
File Select Registers
Instruction Set
CORE BLOCK DIAGRAM
15
Configuration
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
8
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Direct Addr 7
5
Indirect
Addr
12
12
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W reg
Internal
Oscillator
Block
VDD
 2010-2016 Microchip Technology Inc.
VSS
DS40001452F-page 15
PIC16(L)F1516/7/8/9
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-Level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See Section 3.6 “Stack” for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.7 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 24.0 “Instruction Set Summary” for more
details.
DS40001452F-page 16
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
3.2
High-Endurance Flash
This device has a 128-byte section of high-endurance
Program Flash Memory (PFM) in lieu of data
EEPROM. This area is especially well suited for
nonvolatile data storage that is expected to be
updated frequently over the life of the end product.
See Section 11.2 “Flash Program Memory
Overview” for more information on writing data to
PFM. See Section 3.2.1.2 “Indirect Read with FSR”
for more information about using the FSR registers to
read byte data stored in PFM.
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
3.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for these devices. Accessing a location
above these boundaries will cause a wrap-around within
the implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 3-1 and Figure 3-2).
TABLE 3-1:
Device
DEVICE SIZES AND ADDRESSES
Program Memory
Space (Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range (1)
8,192
1FFFh
1F80h-1FFFh
16,384
3FFFh
3F80h-3FFFh
PIC16F1516
PIC16LF1516
PIC16F1827
PIC16LF1517
PIC16F1939
PIC16LF1518
PIC16LF1933
PIC16LF1519
Note 1: High-endurance Flash applies to the low byte of each address in the range.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 17
PIC16(L)F1516/7/8/9
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1516/7
FIGURE 3-2:
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1518/9
PC<14:0>
15
Stack Level 0
Stack Level 1
CALL, CALLW
15
RETURN, RETLW
Interrupt, RETFIE
Stack Level 0
Stack Level 1
Stack Level 15
Stack Level 15
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
Page 0
Page 0
07FFh
0800h
07FFh
0800h
Page 1
On-chip
Program
Memory
Page 1
0FFFh
1000h
Page 2
Page 3
Rollover to Page 0
17FFh
1800h
On-chip
Program
Memory
0FFFh
1000h
Page 2
Page 3
1FFFh
2000h
Page 4
Page 7
Rollover to Page 0
Rollover to Page 3
DS40001452F-page 18
7FFFh
Rollover to Page 7
17FFh
1800h
1FFFh
2000h
3FFFh
4000h
7FFFh
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.2.1
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.2.1.1
RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create such a table is shown in Example 3-1.
EXAMPLE 3-1:
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
DW DATA0
;First constsnt
DW DATA1
;Second constant
DW DATA2
;
DW DATA3
;
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
MOVWF
LOW constants
MOVWF
FSR1H
MOVLW
HIGH constants ;MSB is set
;automatically
MOVWF
FSR1H
BTFSC
STATUS,C
;carry from ADDLW?
INCF
FSR1H,f
;yes
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
CALL constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very
simple to implement. If the code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.2.1.2
Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 19
PIC16(L)F1516/7/8/9
3.3
Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
•
•
•
•
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.7 “Indirect
Addressing” for more information.
Data Memory uses a 12-bit address. The upper five bits
of the address define the Bank address, and the lower
seven bits select the individual SFR, GPR and common
RAM locations in that bank.
DS40001452F-page 20
3.3.1
CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-7.
TABLE 3-2:
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.3.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
3.4
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 24.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
Register Definitions: Status
REGISTER 3-1:
U-0
STATUS: STATUS REGISTER
U-0
—
U-0
—
R-1/q
—
TO
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
Z
DC(1)
C(1)
PD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 21
PIC16(L)F1516/7/8/9
3.4.1
SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.4.2
FIGURE 3-3:
7-bit Bank Offset
0Bh
0Ch
GENERAL PURPOSE RAM
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
1Fh
20h
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.7.2
“Linear Data Memory” for more information.
3.4.3
Memory Region
00h
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.4.2.1
BANKED MEMORY
PARTITIONING
General Purpose RAM
(80 bytes maximum)
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.4.4
DEVICE MEMORY MAPS
The memory maps for PIC16(L)F1516/7 and
PIC16(L)F1518/9 are as shown in Table 3-3 and
Table 3-4, respectively.
DS40001452F-page 22
 2010-2016 Microchip Technology Inc.
 2010-2016 Microchip Technology Inc.
TABLE 3-3:
PIC16(L)F1516/7 MEMORY MAP
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
PORTA
PORTB
PORTC
08Bh
08Ch
08Dh
08Eh
TRISA
TRISB
TRISC
10Bh
10Ch
10Dh
10Eh
LATA
LATB
LATC
18Bh
18Ch
18Dh
18Eh
ANSELA
ANSELB
ANSELC
20Bh
20Ch
20Dh
20Eh
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
LATE(1)
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON(2)
—
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
19Fh
1A0h
BAUDCON
PORTE
PIR1
PIR2
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
—
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
PIE2
—
—
OPTION_REG
PCON
WDTCON
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
01Fh
020h
—
09Fh
0A0h
—
11Fh
120h
General
Purpose
Register
80 Bytes
06Fh
070h
Common RAM
07Fh
DS40001452F-page 23
Legend:
Note 1:
2:
0FFh
Common RAM
(Accesses
70h – 7Fh)
—
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
0EFh
0F0h
—
—
—
—
—
BORCON
FVRCON
—
—
—
—
—
APFCON
—
16Fh
170h
17Fh
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’.
PIC16F/LF1516/7/8/9 only.
PIC16F1516/7 only.
1FFh
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
—
WPUB
—
28Bh
28Ch
28Dh
28Eh
—
—
—
30Bh
30Ch
30Dh
30Eh
—
—
—
38Bh
38Ch
38Dh
38Eh
—
—
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
—
—
—
—
—
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
CCPR1L
CCPR1H
CCP1CON
—
—
—
—
CCPR2L
CCPR2H
CCP2CON
—
—
—
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
21Fh
220h
—
29Fh
2A0h
—
General
Purpose
Register
80 Bytes
1EFh
1F0h
BANK 6
300h
General
Purpose
Register
80 Bytes
26Fh
270h
27Fh
Common RAM
(Accesses
70h – 7Fh)
General
Purpose
Register
80 Bytes
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h – 7Fh)
31Fh
—
39Fh
320h General Purpose 3A0h
Register
16 Bytes
32Fh
330h
36Fh
370h
37Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
3EFh
3F0h
3FFh
—
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1516/7/8/9
00Bh
00Ch
00Dh
00Eh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
BANK 5
280h
PIC16(L)F1516/7 MEMORY MAP (CONTINUED)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
Unimplemented
Read as ‘0’
46Fh
470h
Common RAM
(Accesses
70h – 7Fh)
47Fh
Core Registers
(Table 3-2)
48Bh
48Ch
4EFh
4F0h
4FFh
BANK 16
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
86Fh
870h
87Fh
Common RAM
(Accesses
70h – 7Fh)
8EFh
8F0h
8FFh
 2010-2016 Microchip Technology Inc.
C7Fh
Legend:
Common RAM
(Accesses
70h – 7Fh)
96Fh
970h
97Fh
CFFh
Common RAM
(Accesses
70h – 7Fh)
9FFh
Common RAM
(Accesses
70h – 7Fh)
A7Fh
AEFh
AF0h
AFFh
B6Fh
B70h
B7Fh
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
F0Bh
F0Ch
Unimplemented
Read as ‘0’
F6Fh
F70h
F7Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 23
Core Registers
(Table 3-2)
B8Bh
B8Ch
BANK 30
Unimplemented
Read as ‘0’
EFFh
7FFh
Unimplemented
Read as ‘0’
B80h
F00h
Common RAM
(Accesses
70h – 7Fh)
7EFh
7F0h
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
EEFh
EF0h
78Bh
78Ch
Core Registers
(Table 3-2)
BANK 29
Unimplemented
Read as ‘0’
E7Fh
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
BANK 22
Unimplemented
Read as ‘0’
E8Bh
E8Ch
Common RAM
(Accesses
70h – 7Fh)
77Fh
Common RAM
(Accesses
70h – 7Fh)
B0Bh
B0Ch
E80h
E0Bh
E0Ch
76Fh
770h
Unimplemented
Read as ‘0’
B00h
A8Bh
A8Ch
Common RAM
(Accesses
70h – 7Fh)
70Bh
70Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
E6Fh
E70h
Common RAM
(Accesses
70h – 7Fh)
BANK 15
780h
Core Registers
(Table 3-2)
BANK 21
BANK 28
Unimplemented
Read as ‘0’
DFFh
6FFh
Unimplemented
Read as ‘0’
A80h
E00h
Common RAM
(Accesses
70h – 7Fh)
6EFh
6F0h
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
DEFh
DF0h
68Bh
68Ch
Core Registers
(Table 3-2)
A6Fh
A70h
BANK 14
700h
Core Registers
(Table 3-2)
BANK 20
BANK 27
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A0Bh
A0Ch
D8Bh
D8Ch
= Unimplemented data memory locations, read as ‘0’.
67Fh
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
D7Fh
66Fh
670h
Unimplemented
Read as ‘0’
A00h
D80h
Common RAM
(Accesses
70h – 7Fh)
60Bh
60Ch
Core Registers
(Table 3-2)
9EFh
9F0h
BANK 13
680h
Core Registers
(Table 3-2)
BANK 19
BANK 26
D6Fh
D70h
Common RAM
(Accesses
70h – 7Fh)
98Bh
98Ch
D0Bh
D0Ch
Common RAM
(Accesses
70h – 7Fh)
5FFh
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
CEFh
CF0h
5EFh
5F0h
Unimplemented
Read as ‘0’
980h
D00h
C8Bh
C8Ch
58Bh
58Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
C6Fh
C70h
Common RAM
(Accesses
70h – 7Fh)
BANK 12
600h
Core Registers
(Table 3-2)
BANK 18
BANK 25
Core Registers
(Table 3-2)
Common RAM
(Accesses
70h – 7Fh)
90Bh
90Ch
C80h
C0Bh
C0Ch
57Fh
Unimplemented
Read as ‘0’
BANK 24
C00h
56Fh
570h
Unimplemented
Read as ‘0’
900h
88Bh
88Ch
80Bh
80Ch
50Bh
50Ch
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
BANK 11
580h
Core Registers
(Table 3-2)
BANK 17
880h
800h
BANK 10
500h
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1516/7/8/9
DS40001452F-page 24
TABLE 3-3:
 2010-2016 Microchip Technology Inc.
TABLE 3-3:
PIC16(L)F1516/7 MEMORY MAP (CONTINUED)
Bank 31
F80h
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
FF0h
STKPTR
TOSL
TOSH
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’,
DS40001452F-page 25
PIC16(L)F1516/7/8/9
FFFh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
PIC16(L)F1518/9 MEMORY MAP
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
BANK 2
100h
Core Registers
(Table 3-2)
BANK 3
180h
Core Registers
(Table 3-2)
BANK 4
200h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
PORTA
PORTB
PORTC
08Bh
08Ch
08Dh
08Eh
TRISA
TRISB
TRISC
10Bh
10Ch
10Dh
10Eh
LATA
LATB
LATC
18Bh
18Ch
18Dh
18Eh
ANSELA
ANSELB
ANSELC
20Bh
20Ch
20Dh
20Eh
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
PIR2
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
—
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
PIE2
—
—
OPTION_REG
PCON
WDTCON
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE(1)
—
—
—
—
—
BORCON
FVRCON
—
—
—
—
—
APFCON
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON(2)
—
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
01Fh
020h
—
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCON
General
Purpose
Register
80 Bytes
 2010-2016 Microchip Technology Inc.
06Fh
070h
0EFh
0F0h
07Fh
16Fh
170h
Accesses
70h – 7Fh
Common RAM
Legend:
Note 1:
2:
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
0FFh
Accesses
70h – 7Fh
17Fh
= Unimplemented data memory locations, read as ‘0’.
DSTEMP only.
PIC16F1518/9 only.
Core Registers
(Table 3-2)
BANK 7
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
28Bh
28Ch
28Dh
28Eh
—
—
—
30Bh
30Ch
30Dh
30Eh
—
—
—
38Bh
38Ch
38Dh
38Eh
—
—
—
20Fh
—
28Fh
—
30Fh
—
38Fh
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
—
—
—
—
—
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
CCPR1L
CCPR1H
CCP1CON
—
—
—
—
CCPR2L
CCPR2H
CCP2CON
—
—
—
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
21Fh
220h
—
29Fh
2A0h
—
31Fh
320h
—
39Fh
3A0h
—
General
Purpose
Register
80 Bytes
26Fh
270h
Accesses
70h – 7Fh
1FFh
BANK 6
300h
—
WPUB
—
General
Purpose
Register
80 Bytes
1EFh
1F0h
BANK 5
280h
General
Purpose
Register
80 Bytes
27Fh
36Fh
370h
2EFh
2F0h
Accesses
70h – 7Fh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
2FFh
General
Purpose
Register
80 Bytes
3EFh
3F0h
Accesses
70h – 7Fh
37Fh
Accesses
70h – 7Fh
3FFh
PIC16(L)F1516/7/8/9
DS40001452F-page 26
TABLE 3-4:
 2010-2016 Microchip Technology Inc.
TABLE 3-5:
PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
40Bh
40Ch
Core Registers
(Table 3-2)
48Bh
48Ch
Unimplemented
Read as ‘0’
41Fh
420h
47Fh
Common RAM
(Accesses
70h – 7Fh)
4EFh
4F0h
4FFh
8FFh
5EFh
5F0h
5FFh
97Fh
67Fh
9FFh
Common RAM
(Accesses
70h – 7Fh)
6FFh
A7Fh
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
76Fh
770h
77Fh
AFFh
Common RAM
(Accesses
70h – 7Fh)
7EFh
7F0h
7FFh
BANK 23
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as ‘0’
B6Fh
B70h
B7Fh
Common RAM
(Accesses
70h – 7Fh)
B80h
B0Bh
B0Ch
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
BANK 22
Unimplemented
Read as ‘0’
AEFh
AF0h
79Fh
7A0h
B00h
A8Bh
A8Ch
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
78Bh
78Ch
71Fh
720h
Common RAM
(Accesses
70h – 7Fh)
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 21
Core Registers
(Table 3-2)
A6Fh
A70h
70Bh
70Ch
A80h
A0Bh
A0Ch
Common RAM
(Accesses
70h – 7Fh)
6EFh
6F0h
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 20
Unimplemented
Read as ‘0’
9EFh
9F0h
Unimplemented
Read as ‘0’
A00h
98Bh
98Ch
Common RAM
(Accesses
70h – 7Fh)
66Fh
670h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
68Bh
68Ch
61Fh
69Fh
620h General Purpose 6A0h
Register
48 Bytes
64Fh
650h
BANK 14
700h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
BANK 19
Core Registers
(Table 3-2)
96Fh
970h
Common RAM
(Accesses
70h – 7Fh)
980h
90Bh
90Ch
Common RAM
(Accesses
70h – 7Fh)
General
Purpose
Register
80 Bytes
BANK 18
Unimplemented
Read as ‘0’
8EFh
8F0h
Common RAM
(Accesses
70h – 7Fh)
900h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
57Fh
BANK 17
88Bh
88Ch
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
56Fh
570h
Core Registers
(Table 3-2)
60Bh
60Ch
59Fh
5A0h
BANK 13
680h
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h – 7Fh)
DS40001452F-page 27
PIC16(L)F1516/7/8/9
80Bh
80Ch
87Fh
Common RAM
(Accesses
70h – 7Fh)
880h
Core Registers
(Table 3-2)
58Bh
58Ch
51Fh
520h
BANK 12
600h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
BANK 16
800h
86Fh
870h
50Bh
50Ch
49Fh
4A0h
BANK 11
580h
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
General
Purpose
Register
80 Bytes
46Fh
470h
BANK 10
500h
PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
C0Bh
C0Ch
Core Registers
(Table 3-2)
C8Bh
C8Ch
Unimplemented
Read as ‘0’
C6Fh
C70h
C7Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 26
D00h
Core Registers
(Table 3-2)
D0Bh
D0Ch
Unimplemented
Read as ‘0’
CEFh
CF0h
CFFh
Common RAM
(Accesses
70h – 7Fh)
D7Fh
Common RAM
(Accesses
70h – 7Fh)
Bank 31
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as ‘0’
 2010-2016 Microchip Technology Inc.
FFFh
Legend:
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
D6Fh
D70h
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’.
BANK 28
E00h
D8Bh
D8Ch
F80h
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
FF0h
BANK 27
D80h
Core Registers
(Table 3-2)
E0Bh
E0Ch
Unimplemented
Read as ‘0’
DEFh
DF0h
DFFh
Common RAM
(Accesses
70h – 7Fh)
BANK 29
E80h
Core Registers
(Table 3-2)
E8Bh
E8Ch
Unimplemented
Read as ‘0’
E6Fh
E70h
E7Fh
Common RAM
(Accesses
70h – 7Fh)
BANK 30
F00h
Core Registers
(Table 3-2)
F0Bh
F0Ch
Unimplemented
Read as ‘0’
EEFh
EF0h
EFFh
Common RAM
(Accesses
70h – 7Fh)
Unimplemented
Read as ‘0’
F6Fh
F70h
F7Fh
Common RAM
(Accesses
70h – 7Fh)
PIC16(L)F1516/7/8/9
DS40001452F-page 28
TABLE 3-6:
PIC16(L)F1516/7/8/9
3.4.5
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-7 can be
addressed from any Bank.
TABLE 3-7:
Addr
Name
CORE FUNCTION REGISTERS SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Bank 0-31
x00h or
INDF0
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
Program Counter (PC) Least Significant Byte
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
—
—
—
TO
PD
Z
DC
C
x04h or
FSR0L
x84h
Indirect Data Memory Address 0 Low Pointer
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
Indirect Data Memory Address 0 High Pointer
0000 0000
0000 0000
x06h or
FSR1L
x86h
Indirect Data Memory Address 1 Low Pointer
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
Indirect Data Memory Address 1 High Pointer
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
—
x09h or
WREG
x89h
—
BSR4
BSR3
BSR2
BSR1
BSR0
Working Register
x0Ah or
PCLATH
x8Ah
—
x0Bh or
INTCON
x8Bh
GIE
Legend:
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 29
PIC16(L)F1516/7/8/9
3.4.6
SPECIAL FUNCTION REGISTERS
SUMMARY
The Special Function registers are listed in Table 3-8.
TABLE 3-8:
Addr
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 0
00Ch PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
00Dh PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
00Eh PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
00Fh PORTD
PORTD Data Latch when written: PORTD pins when read
011h
PIR1
xxxx xxxx uuuu uuuu
—
—
—
—
RE3
RE2(3)
RE1(3)
RE0(3)
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
0--- 0--0 0--- 0--0
010h PORTE
012h PIR2
---- xxxx ---- uuuu
013h —
Unimplemented
—
—
014h —
Unimplemented
—
—
015h TMR0
Holding Register for the 8-bit Timer0 Count
xxxx xxxx uuuu uuuu
016h TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
018h T1CON
TMR1CS<1:0>
019h T1GCON
TMR1GE
T1CKPS<1:0>
T1GPOL
T1GTM
01Ah TMR2
Timer 2 Module Register
01Bh PR2
Timer 2 Period Register
01Ch T2CON
T1GSPM
xxxx xxxx uuuu uuuu
T1OSCEN
T1SYNC
—
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
TMR1ON 0000 00-0 uuuu uu-u
0000 0x00 uuuu uxuu
0000 0000 0000 0000
1111 1111 1111 1111
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
01Dh —
Unimplemented
—
—
01Eh —
Unimplemented
—
—
01Fh —
Unimplemented
—
—
Bank 1
08Ch TRISA
PORTA Data Direction Register
1111 1111 1111 1111
08Dh TRISB
PORTB Data Direction Register
1111 1111 1111 1111
08Eh TRISC
PORTC Data Direction Register
1111 1111 1111 1111
08Fh TRISD(2)
PORTD Data Direction Register
1111 1111 1111 1111
—
—
—
—
—(3)
091h PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
092h PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
0--- 0--0 0--- 0--0
090h TRISE
TRISE2(2) TRISE1(2) TRISE0(2) ---- 1111 ---- 1111
093h —
Unimplemented
—
—
094h —
Unimplemented
—
—
095h OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
096h PCON
STKOVF
STKUNF
—
RWDT
—
—
097h WDTCON
098h —
SOSCR
—
OSTS
ADC Result Register Low
09Ch ADRESH
ADC Result Register High
09Dh ADCON0
—
09Eh ADCON1
ADFM
1:
2:
3:
POR
1111 1111 1111 1111
BOR
00-1 11qq qq-q qquu
SWDTEN --01 0110 --01 0110
—
IRCF<3:0>
09Bh ADRESL
Note
RI
WDTPS<4:0>
—
09Ah OSCSTAT
Legend:
RMCLR
PS<2:0>
Unimplemented
099h OSCCON
09Fh —
PSA
HFIOFR
—
—
—
LFIOFR
HFIOFS
—
-011 1-00 -011 1-00
0-q0 --00 q-qq --0q
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS<4:0>
ADCS<2:0>
SCS<1:0>
GO/DONE
—
—
ADON
ADPREF<1:0>
Unimplemented
-000 0000 -000 0000
0000 --00 0000 --00
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F1516/7/8/9 only.
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
DS40001452F-page 30
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 3-8:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bank 2
10Ch LATA
PORTA Data Latch
xxxx xxxx uuuu uuuu
10Dh LATB
PORTB Data Latch
xxxx xxxx uuuu uuuu
10Eh LATC
PORTC Data Latch
xxxx xxxx uuuu uuuu
10Fh LATD(2)
PORTD Data Latch
110h
LATE(2)
—
—
xxxx xxxx uuuu uuuu
—
—
—
LATE2
LATE1
LATE0
111h
to —
115h
Unimplemented
116h
BORCON
SBOREN
BORFS
—
—
—
—
—
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR<1:0>
118h
to —
11Ch
—
—
0q00 --00 0q00 --00
—
—
—
—
—
—
SSSEL
—
BORRDY 10-- ---q uu-- ---u
Unimplemented
11Dh APFCON
---- -xxx ---- -uuu
—
CCP2SEL ---- --00 ---- --00
11Eh —
Unimplemented
—
—
11Fh
Unimplemented
—
—
—
Bank 3
18Ch ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
--1- 1111 --1- 1111
18Dh ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111 --11 1111
18Eh ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
—
—
1111 11-- 1111 11--
18Fh ANSELD(2)
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111 1111 1111
—
—
—
—
—
ANSE2
ANSE1
ANSE0
---- -111 ---- -111
190h ANSELE(2)
191h PMADRL
192h PMADRH
193h PMDATL
Program Memory Address Register Low Byte
—(3)
—
—
195h PMCON1
—(3)
CFGS
197h VREGCON(1)
1000 0000 1000 0000
Program Memory Data Register Low Byte
194h PMDATH
196h PMCON2
0000 0000 0000 0000
Program Memory Address Register High Byte
xxxx xxxx uuuu uuuu
Program Memory Data Register High Byte
LWLO
--xx xxxx --uu uuuu
FREE
WRERR
WREN
—
—
—
WR
RD
Program Memory control register 2
—
—
—
198h —
Unimplemented
199h RCREG
USART Receive Data Register
19Ah TXREG
USART Transmit Data Register
1000 x000 1000 q000
0000 0000 0000 0000
VREGPM Reserved ---- --01 ---- --01
—
—
0000 0000 0000 0000
0000 0000 0000 0000
19Bh SPBRG
BRG<7:0>
19Ch SPBRGH
BRG<15:8>
0000 0000 0000 0000
0000 0000 0000 0000
19Dh RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 0000 0010
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
01-0 0-00 01-0 0-00
19Fh BAUDCON
Legend:
Note
1:
2:
3:
0000 000x 0000 000x
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F1516/7/8/9 only.
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 31
PIC16(L)F1516/7/8/9
TABLE 3-8:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
Value on
POR, BOR
Value on
all other
Resets
—
—
Bank 4
20Ch —
Unimplemented
20Dh WPUB
WPUB7
WPUB6
1111 1111 1111 1111
20Eh —
Unimplemented
—
—
20Fh —
Unimplemented
—
—
210h WPUE
211h
SSPBUF
—
—
—
—
WPUE3
—
—
—
---- 1--- ---- 1---
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 0000 0000
213h SSPMSK
Synchronous Serial Port (I2C mode) Address Mask Register
214h SSPSTAT
SMP
215h SSPCON1
216h SSPCON2
217h SSPCON3
218h
to —
21Fh
CKE
D/A
WCOL
SSPOV
SSPEN
CKP
GCEN
ACKSTAT
ACKDT
ACKTIM
PCIE
SCIE
P
1111 1111 1111 1111
S
R/W
UA
BF
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
BOEN
SDAHT
SBCDE
AHEN
DHEN
0000 0000 0000 0000
SSPM<3:0>
0000 0000 0000 0000
0000 0000 0000 0000
Unimplemented
—
—
28Ch
to —
290h
Unimplemented
—
—
291h CCPR1L
Capture/Compare/PWM Register 1 (LSB)
292h CCPR1H
Capture/Compare/PWM Register 1 (MSB)
Bank 5
293h CCP1CON
—
—
xxxx xxxx uuuu uuuu
294h
to —
297h
Unimplemented
298h CCPR2L
Capture/Compare/PWM Register 2 (LSB)
299h CCPR2H
Capture/Compare/PWM Register 2 (MSB)
29Ah CCP2CON
29Bh
to —
29Fh
—
xxxx xxxx uuuu uuuu
DC1B<1:0>
CCP1M<3:0>
--00 0000 --00 0000
—
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
DC2B<1:0>
CCP2M<3:0>
--00 0000 --00 0000
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
Bank 6
30Ch
to —
31Fh
Bank 7
38Ch
to —
393h
394h IOCBN
IOCBP<7:0>
0000 0000 0000 0000
395h IOCBN
IOCBN<7:0>
0000 0000 0000 0000
396h IOCBF
IOCBF<7:0>
0000 0000 0000 0000
397h
to —
39Fh
Unimplemented
—
—
Unimplemented
—
—
Bank 8-30
x0Ch
or
x8Ch
to —
x1Fh
or
x9Fh
Legend:
Note
1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F1516/7/8/9 only.
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
DS40001452F-page 32
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 3-8:
Addr
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
—
—
Bank 31
F8Ch
to —
FE3h
Unimplemented
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
—
—
—
—
—
Z
DC
C
Working Register Shadow
—
—
—
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
—
Bank Select Register Shadow
Program Counter Latch High Register Shadow
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
FE8h FSR0L_SHAD
Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD
Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD
Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD
Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
FECh —
Unimplemented
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Legend:
Note
1:
2:
3:
—
—
—
—
Current Stack pointer
Top of Stack Low byte
—
Top of Stack High byte
—
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F1516/7/8/9 only.
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 33
PIC16(L)F1516/7/8/9
3.5
3.5.2
PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
FIGURE 3-4:
14
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
0
PC
6
7
8
0
PCLATH
Instruction with
PCL as
Destination
ALU Result
14
PCH
PCL
0
GOTO, CALL
PC
6 4
0
PCLATH
11
OPCODE <10:0>
14
PCH
PCL
0
PC
6
7
0
PCLATH
CALLW
W
14
PCH
PCL
0
PC
BRW
15
PC + W
14
PCH
PCL
PC
0
BRA
15
PC + OPCODE <8:0>
3.5.1
A computed GOTO is accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, Implementing a Table Read (DS00556).
3.5.3
COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
3.5.4
8
COMPUTED GOTO
BRANCHING
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL
register, all 15 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.
DS40001452F-page 34
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.6
3.6.1
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of
the PC. To access the stack, adjust the value of
STKPTR, which will position TOSH:TOSL, then
read/write to TOSH:TOSL. STKPTR is five bits to allow
detection of overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0’ (Configuration Words). This
means that after the stack has been PUSHed 16 times,
the 17th PUSH overwrites the value that was stored
from the first PUSH. The 18th PUSH overwrites the
second PUSH (and so on). The STKOVF and STKUNF
flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement STKPTR.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
FIGURE 3-5:
ACCESSING THE STACK
Reference Figure 3-5 through 3-8 for examples of
accessing the stack.
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F
STKPTR = 0x1F
Stack Reset Disabled
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
 2010-2016 Microchip Technology Inc.
0x1F
0x0000
STKPTR = 0x1F
Stack Reset Enabled
(STVREN = 1)
DS40001452F-page 35
PIC16(L)F1516/7/8/9
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-7:
0x00
Return Address
STKPTR = 0x00
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001452F-page 36
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 3-8:
ACCESSING THE STACK EXAMPLE 4
TOSH:TOSL
3.6.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the 16th level or POPed beyond the
first level, setting the appropriate bits (STKOVF or
STKUNF, respectively) in the PCON register.
3.7
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
 2010-2016 Microchip Technology Inc.
DS40001452F-page 37
PIC16(L)F1516/7/8/9
FIGURE 3-9:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x1FFF
0x0FFF
Reserved
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
0x7FFF
0x8000
Reserved
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001452F-page 38
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.7.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
4
BSR
0
6
Indirect Addressing
From Opcode
0
7
0
Bank Select
Location Select
FSRxH
0
0
0
7
FSRxL
0
0
Bank Select
00000 00001 00010
11111
Bank 0 Bank 1 Bank 2
Bank 31
Location Select
0x00
0x7F
 2010-2016 Microchip Technology Inc.
DS40001452F-page 39
PIC16(L)F1516/7/8/9
3.7.2
3.7.3
LINEAR DATA MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-11:
7
FSRnH
0 0 1
LINEAR DATA MEMORY
MAP
0
7
FSRnL
0
PROGRAM FLASH MEMORY
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location is accessible
via INDF. Writing to the program Flash memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-12:
7
1
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
7
FSRnL
0x8000
0
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS40001452F-page 40
0xF6F
0xFFFF
0x7FFF
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
4.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note:
The DEBUG bit in Configuration Words is
managed
automatically
by
device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 41
PIC16(L)F1516/7/8/9
4.2
Register Definitions: Configuration Words
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
U-1
—
bit 13
bit 8
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit
If FOSC Configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins
DS40001452F-page 42
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
U-1
LVP
DEBUG
LPBOR
BORV
STVREN
—
bit 13
U-1
U-1
—
bit 8
U-1
—
—
R/P-1
VCAPEN
(1)
U-1
U-1
—
—
bit 7
R/P-1
R/P-1
WRT<1:0>
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit
1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power BOR
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit(2)
1 = Brown-out Reset voltage (Vbor), low trip point selected.
0 = Brown-out Reset voltage (Vbor), high trip point selected.
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-5
Unimplemented: Read as ‘1’
bit 4
VCAPEN: Voltage Regulator Capacitor Enable bits(1)
If PIC16LF1516/7/8/9 (regulator disabled):
These bits are ignored. All VCAP pin functions are disabled.
If PIC16F1516/7/8/9 (regulator enabled):
0 = VCAP functionality is enabled on RA5
1 = All VCAP pin functions are disabled
bit 3-2
Unimplemented: Read as ‘1’
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16(L)F1516/7 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16(L)F1518/9 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
Note
1:
2:
PIC16F1516/7/8/9 only.
See Vbor parameter for specific trip point voltages.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 43
PIC16(L)F1516/7/8/9
4.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.4
“Write
Protection” for more information.
4.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5
User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16(L)F151X/152X Memory
Programming Specification” (DS41442).
DS40001452F-page 44
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
4.6
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7
Register Definitions: Device
REGISTER 4-3:
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
DEV<8:3>
bit 13
R
R
bit 8
R
R
R
DEV<2:0>
R
R
R
REV<4:0>
bit 7
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
bit 13-5
‘0’ = Bit is cleared
DEV<8:0>: Device ID bits
DEVID<13:0> Values
Device
bit 4-0
DEV<8:0>
REV<4:0>
PIC16F1519
01 0110 111
x xxxx
PIC16F1518
01 0110 110
x xxxx
PIC16F1827
01 0110 101
x xxxx
PIC16F1516
01 0110 100
x xxxx
PIC16LF1519
01 0111 111
x xxxx
PIC16LF1518
01 0111 110
x xxxx
PIC16LF1517
01 0111 101
x xxxx
PIC16LF1516
01 0111 100
x xxxx
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
 2010-2016 Microchip Technology Inc.
DS40001452F-page 45
PIC16(L)F1516/7/8/9
5.0
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
5.1
Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
• Fast start-up oscillator allows internal circuits to
power up and stabilize before switching to the 16
MHz HFINTOSC
DS40001452F-page 46
The oscillator module can be configured in one of eight
clock modes.
1.
2.
3.
4.
5.
6.
7.
8.
ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)
ECH – External Clock High-Power mode
(4 MHz to 20 MHz)
LP – 32 kHz Low-Power Crystal mode.
XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)
RC – External Resistor-Capacitor (RC)
INTOSC – Internal oscillator (31 kHz to 16 MHz)
Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.
The INTOSC internal oscillator block produces a low
and high-frequency clock source, designated
LFINTOSC and HFINTOSC. (see Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
Low-Power Mode
Event Switch
(SCS<1:0>)
Primary Oscillator
OSC2
Primary
Oscillator
(OSC)
2
OSC1
Primary Clock
00
SOSCO/
T1CKI
SOSCI
Secondary
Oscillator
(SOSC)
Secondary Clock
INTOSC
01
1x
Clock Switch MUX
Secondary Oscillator
Internal Oscillator
IRCF<3:0>
4
Start-Up Osc
LF-INTOSC
(31.25 kHz)
 2010-2016 Microchip Technology Inc.
INTOSC
Divide Circuit
16 MHz
Primary Osc
/1
/2
/4
/8
/16
HF-16 MHz
HF-8 MHz
/32
HF-500 kHz
/64
HF-250 kHz
HF-4 MHz
HF-2 MHz
HF-1 MHz
/128
HF-125 kHz
/256
HF-62.5 kHz
/512
HF-31.25 kHz
LF-31 kHz
1111
1110
1101
1100
1011
1010/
0111
1001/
0110
1000/
0101
0100
0011
0010
0001
0000
Internal Oscillator MUX
Start-up
Control
Logic
4
DS40001452F-page 47
PIC16(L)F1516/7/8/9
5.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
Internal clock sources are contained within the oscillator
module. The internal oscillator block has two internal
oscillators that are used to generate the internal system
clock sources: the 16 MHz High-Frequency Internal
Oscillator and the 31 kHz Low-Frequency Internal
Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
5.2.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Secondary oscillator during run time, or
- An external clock source determined by the
value of the FOSC bits.
See Section 5.3 “Clock Switching”for more information.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
Configuration Words:
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 5-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
FOSC/4 or I/O(1)
Note 1:
5.2.1.2
OSC2/CLKOUT
Output depends upon CLKOUTEN bit of the
Configuration Words.
LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
• High power, 4-20 MHz (FOSC = 111)
• Medium power, 0.5-4 MHz (FOSC = 110)
• Low power, 0-0.5 MHz (FOSC = 101)
DS40001452F-page 48
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC® MCU
PIC® MCU
OSC1/CLKIN
C1
To Internal
Logic
Quartz
Crystal
C2
Note 1:
2:
OSC1/CLKIN
RS(1)
RF(2)
C1
Sleep
OSC2/CLKOUT
A series resistor (RS) may be required for
quartz crystals with low drive level.
RP(3)
C2 Ceramic
RS(1)
Resonator
Note 1:
The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices (DS00826)
• AN849, Basic PIC® Oscillator Design
(DS00849)
• AN943, Practical PIC® Oscillator
Analysis and Design (DS00943)
• AN949, Making Your Oscillator Work
(DS00949)
 2010-2016 Microchip Technology Inc.
To Internal
Logic
RF(2)
Sleep
OSC2/CLKOUT
A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended,
unless either FSCM or Two-Speed Start-up are
enabled. In this case, code will continue to execute at
the selected INTOSC frequency while the OST is
counting. The OST ensures that the oscillator circuit,
using a quartz crystal resonator or ceramic resonator,
has started and is providing a stable system clock to
the oscillator module.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-Up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
DS40001452F-page 49
PIC16(L)F1516/7/8/9
5.2.1.4
5.2.1.5
Secondary Oscillator
External RC Mode
The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz
crystal connected between the SOSCO and SOSCI
device pins.
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The secondary oscillator can be used as an alternate
system clock source and can be selected during run
time using clock switching. Refer to Section 5.3
“Clock Switching” for more information.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC® MCU
Internal
Clock
CEXT
To Internal
Logic
32.768 kHz
Quartz
Crystal
VSS
FOSC/4 or I/O(1)
SOSCO
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices (DS00826)
• AN849, Basic PIC® Oscillator Design
(DS00849)
• AN943, Practical PIC® Oscillator
Analysis and Design (DS00943)
• AN949, Making Your Oscillator Work
(DS00949)
• TB097, Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS (DS91097)
• AN1288, Design Practices for
Low-Power External Oscillators
(DS01288)
DS40001452F-page 50
VDD
EXTERNAL RC MODES
OSC1/CLKIN
SOSCI
C2
FIGURE 5-6:
REXT
PIC® MCU
C1
Figure 5-6 shows the external RC mode connections.
OSC2/CLKOUT
Recommended values: 10 k  REXT  100 k, <3V
3 k  REXT  100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1:
Output depends upon CLKOUTEN bit of the
Configuration Words.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of the external RC components used.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
5.2.2
INTERNAL CLOCK SOURCES
The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:
• Program the FOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run time. See Section 5.3
“Clock Switching”for more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words.
The internal oscillator block has two independent
oscillators that provides the internal system clock
source.
1.
2.
The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz.
The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
5.2.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
5.2.2.2
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
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5.2.2.3
Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The outputs of the 16 MHz HFINTOSC postscaler and
the LFINTOSC connects to a multiplexer (see
Figure 5-1). The Internal Oscillator Frequency Select
bits IRCF<3:0> of the OSCCON register select the
frequency output of the internal oscillators. One of the
following frequencies can be selected via software:
•
•
•
•
•
•
•
•
•
•
•
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz (default after Reset)
250 kHz
125 kHz
62.5 kHz
31.25 kHz
31 kHz (LFINTOSC)
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes
that use the same oscillator source.
DS40001452F-page 52
5.2.2.4
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1.
2.
3.
4.
5.
6.
7.
IRCF<3:0> bits of the OSCCON register are
modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
The new clock is now active.
The OSCSTAT register is updated as required.
Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator tables of Section 25.0 “Electrical
Specifications”.
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FIGURE 5-7:
HFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (FSCM and WDT disabled)
HFINTOSC
Oscillator Delay (1)
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC
2-cycle Sync
Running
LFINTOSC
0
IRCF <3:0>
0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Oscillator Delay (1) 2-cycle Sync
Running
HFINTOSC
IRCF <3:0>
=0
0
System Clock
Note 1: See Table 5-1 for more information.
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5.3
Clock Switching
5.3.3
SECONDARY OSCILLATOR
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.
• Default system oscillator determined by FOSC
bits in Configuration Words
• Secondary oscillator 32 kHz crystal
• Internal Oscillator Block (INTOSC)
The secondary oscillator is enabled using the
T1OSCEN control bit in the T1CON register. See
Section 18.0 “Timer1 Module with Gate Control” for
more information about the Timer1 peripheral.
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Words.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
5.3.4
SECONDARY OSCILLATOR READY
(SOSCR) BIT
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIMER
STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OSTS does not
reflect the status of the secondary oscillator.
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5.4
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up provides benefits when the
oscillator module is configured for LP, XT or HS
modes. The Oscillator Start-up Timer (OST) is
enabled for these modes and must count 1024
oscillations before the oscillator can be used as the
system clock source.
5.4.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Words) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Words
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the oscillator module is configured for any mode
other than LP, XT, or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT
register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-1:
OSCILLATOR SWITCHING DELAYS
Switch From
Any clock source
Switch To
Oscillator Delay
LFINTOSC
1 cycle of each clock source
HFINTOSC
2 s (approx.)
ECH, ECM, ECL, EXTRC
2 cycles
LP, XT, HS
1024 Clock Cycles (OST)
Secondary Oscillator
1024 Secondary Oscillator Cycles
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5.4.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
5.4.3
Wake-up from Power-on Reset or Sleep.
Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the
internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
FIGURE 5-8:
CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC - N
PC
PC + 1
System Clock
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5.5
5.5.3
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, RC and
secondary oscillator).
FIGURE 5-9:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
External
Clock
LFINTOSC
Oscillator
÷ 64
31 kHz
(~32 s)
488 Hz
(~2 ms)
S
Q
R
Q
Sample Clock
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64 (see Figure 5-9). Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
5.5.4
Clock
Failure
Detected
FAIL-SAFE CONDITION CLEARING
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
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FIGURE 5-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS40001452F-page 58
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5.6
Register Definitions: Oscillator Control
REGISTER 5-1:
U-0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
IRCF<3:0>
—
U-0
R/W-0/0
—
bit 7
R/W-0/0
SCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz
1110 = 8 MHz
1101 = 4 MHz
1100 = 2 MHz
1011 = 1 MHz
1010 = 500 kHz(1)
1001 = 250 kHz(1)
1000 = 125 kHz(1)
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz
000x = 31 kHz LF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.
Note 1:
Duplicate frequency derived from HFINTOSC.
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REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
U-0
R-q/q
R-0/q
U-0
U-0
R-0/q
R-0/q
SOSCR
—
OSTS
HFIOFR
—
—
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Conditional
bit 7
SOSCR: Secondary Oscillator Ready bit
If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6
Unimplemented: Read as ‘0’
bit 5
OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
HFIOFR: High Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3-2
Unimplemented: Read as ‘0’
bit 1
LFIOFR: Low Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0
HFIOFS: High Frequency Internal Oscillator Stable bit
1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
—
SOSCR
—
OSTS
HFIOFR
—
—
LFIOFR
HFIOFS
60
PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
76
PIR2
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
78
T1OSCEN
T1SYNC
—
TMR1ON
155
TMR1CS<1:0>
CONFIG1
Legend:
59
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3:
Name
T1CKPS<1:0>
SCS<1:0>
Register
on Page
OSCSTAT
T1CON
—
Bit 0
OSCCON
Legend:
IRCF<3:0>
Bit 2
Bits
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
FCMEN
IESO
CLKOUTEN
CP
MCLRE
PWRTE
13:8
7:0
Bit 10/2
Bit 9/1
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Bit 8/0
—
Register
on Page
42
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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6.0
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
RESETS
There are multiple ways to reset this device:
•
•
•
•
•
•
•
•
•
Power-On Reset (POR)
Brown-Out Reset (BOR)
Low-Power Brown-Out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP™ Programming Mode
Exit
RESET Instruction
Stack
Pointer
MCLRE
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
R
PWRT
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1:
See Table for BOR active conditions.
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6.1
Power-On Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
6.1.1
•
•
•
•
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting (DS00607).
TABLE 6-1:
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
BOR is always ON
BOR is off when in Sleep
BOR is controlled by software
BOR is always OFF
Refer to Table for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
BOR OPERATING MODES
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
X
X
Active
10
X
01
00
Awake
Active
Sleep
Disabled
1
X
Active
0
X
Disabled
X
X
Disabled
Instruction Execution upon:
Release of POR or Wake-up from Sleep
Waits for BOR ready(1) (BORRDY = 1)
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready(1) (BORRDY = 1)
Begins immediately (BORRDY = x)
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The
BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN<1:0> bits.
6.2.1
BOR IS ALWAYS ON
When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always ON. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device startup is not delayed by the BOR ready condition or the
VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
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FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
6.3
TPWRT(1)
TPWRT delay only if PWRTE bit is programmed to ‘0’.
Register Definitions: BOR Control
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit(1)
If BOREN <1:0> in Configuration Words  01:
SBOREN is read/write, but has no effect on the BOR
If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1:
BOREN<1:0> bits are located in Configuration Words.
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6.4
Low Power Brown-Out Reset
(LPBOR)
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.4.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to
the PCON register and to the power control block.
6.5
MCLR
6.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer (WDT)” for more information.
6.7
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table for
default conditions after a RESET instruction has
occurred.
6.8
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.6.2 “Overflow/Underflow
Reset” for more information.
6.9
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.10
TABLE 6-2:
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
MCLR CONFIGURATION
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
x
1
Enabled
6.5.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
6.5.2
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.6 “PORTE Registers”
for more information.
DS40001452F-page 64
Power-up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
6.11
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
3.
Power-up Timer runs to completion (if enabled).
Oscillator start-up timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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6.12
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table and Table show the Reset conditions of
these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT
RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
1
1
1
0
x
1
1
Power-on Reset
0
0
1
1
1
0
x
0
x
Illegal, TO is set on POR
0
0
1
1
1
0
x
x
0
Illegal, PD is set on POR
0
0
u
1
1
u
0
1
1
Brown-out Reset
u
u
0
u
u
u
u
0
u
WDT Reset
u
u
u
u
u
u
u
0
0
WDT Wake-up from Sleep
u
u
u
u
u
u
u
1
0
Interrupt Wake-up from Sleep
u
u
u
0
u
u
u
u
u
MCLR Reset during normal operation
u
u
u
0
u
u
u
1
0
MCLR Reset during Sleep
u
u
u
u
0
u
u
u
u
RESET Instruction Executed
1
u
u
u
u
u
u
u
u
Stack Overflow Reset (STVREN = 1)
u
1
u
u
u
u
u
u
u
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
MCLR Reset during normal operation
0000h
---u uuuu
uu-- 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-- uuuu
Condition
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
PC + 1(1)
---1 0uuu
uu-- uuuu
RESET Instruction Executed
0000h
---u uuuu
uu-- u0uu
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-- uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-- uuuu
Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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6.13
Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14
Register Definitions: Power Control
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q
R/W/HS-0/q
U-0
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
STKOVF: Stack Overflow Flag bit
1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6
STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5
Unimplemented: Read as ‘0’
bit 4
RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2
RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)
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TABLE 6-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON SBOREN
BORFS
—
—
—
—
—
BORRDY
63
PCON
STKOVF
STKUNF
—
RWDT
RMCLR
RI
POR
BOR
67
STATUS
—
—
—
TO
PD
Z
DC
C
21
WDTCON
—
—
SWDTEN
86
Name
Bit 7
WDTPS<4:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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7.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
•
•
•
•
•
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
 2010-2016 Microchip Technology Inc.
GIE
DS40001452F-page 69
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7.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIEx register)
7.2
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.
The INTCON, PIR1 and PIR2 registers record individual
interrupts via interrupt flag bits. Interrupt flag bits will be
set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC-1
PC
2 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3 Cycle Instruction at PC
 2010-2016 Microchip Technology Inc.
PC+2
NOP
NOP
DS40001452F-page 71
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FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
Interrupt Latency (2)
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC – 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT not available in all oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
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7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 8.0 “PowerDown Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
•
•
•
•
•
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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7.6
Register Definitions: Interrupt Control
REGISTER 7-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
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REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt
bit 6
ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
R/W-0/0
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6-4
Unimplemented: Read as ‘0’
bit 3
BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2-1
Unimplemented: Read as ‘0’
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
DS40001452F-page 76
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 7-4:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: ADC Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3
SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2
CCP1IF: CCP1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 77
PIC16(L)F1516/7/8/9
REGISTER 7-5:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
U-0
U-0
U-0
R/W-0/0
U-0
U-0
R/W-0/0
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6-4
Unimplemented: Read as ‘0’
bit 3
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 2-1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TMR0IF
Bit 1
Bit 0
INTF
IOCIF
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
78
OPTION_REG
Legend:
PS<2:0>
74
146
— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
DS40001452F-page 78
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
8.0
POWER-DOWN MODE (SLEEP)
8.1
Wake-up from Sleep
The Power-Down mode is entered by executing a
SLEEP instruction.
The device can wake-up from Sleep through one of the
following events:
Upon entering Sleep mode, the following conditions
exist:
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
9.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
Timer1 and peripherals that operate from
Timer1 continue operation in Sleep when the
Timer1 clock source selected is:
• LFINTOSC
• T1CKI
• Secondary oscillator
ADC is unaffected, if the dedicated FRC
oscillator is selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
•
•
•
•
•
•
External Reset input on MCLR pin, if enabled
BOR Reset, if enabled
POR Reset
Watchdog Timer, if enabled
Any external interrupt
Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to
Section 6.12 “Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
Modules using secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 14.0
“Fixed Voltage Reference (FVR)” for more
information on this module.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 79
PIC16(L)F1516/7/8/9
8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared
FIGURE 8-1:
• If the interrupt occurs during or after the execution of a SLEEP instruction
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(3)
CLKOUT(2)
Interrupt flag
Interrupt Latency (4)
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
TOST=1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4 “TwoSpeed Clock Start-up Mode”).
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
DS40001452F-page 80
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
8.2
Low-Power Sleep Mode
The PIC16F1516/7/8/9 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1516/7/8/9 allows the user to optimize the operating current in Sleep, depending on the application
requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal configuration and stabilize.
8.2.2
PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the normal power
mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these
peripherals:
•
•
•
•
•
Brown-Out Reset (BOR)
Watchdog Timer (WDT)
External interrupt pin/Interrupt-on-change pins
Timer1 (with external clock source)
CCP (Capture mode)
Note:
The PIC16LF1516/7/8/9 does not have a
configurable Low-Power Sleep mode.
PIC16LF1516/7/8/9 is an unregulated
device and is always in the lowest power
state when in Sleep, with no wake-up time
penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F1516/7/8/9. See Section 25.0
“Electrical Specifications” for more
information.
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 81
PIC16(L)F1516/7/8/9
8.3
Register Definitions: Voltage Regulator Control
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
—
—
—
—
—
—
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1:
2:
PIC16F1516/7/8/9 only.
See Section 25.0 “Electrical Specifications”.
TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
125
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
125
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
125
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
IOCBP
PIE1
PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
78
STATUS
—
—
—
TO
PD
Z
DC
C
21
VREGCON(1)
—
—
—
—
—
—
VREGPM
Reserved
82
WDTCON
—
—
SWDTEN
86
Legend:
Note 1:
WDTPS<4:0>
— = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
PIC16F1516/7/8/9 only.
DS40001452F-page 82
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
9.0
LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F1516/7/8/9 has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF1516/7/8/9 operates at a maximum VDD of
3.6V and does not incorporate an LDO.
On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on the constant current rate, refer to the
LDO Regulator Characteristics Table in Section 25.0
“Electrical Specifications”.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability.
The VCAPEN bit of Configuration Words enables or
disables the VCAP pin. Refer to Table 9-1.
TABLE 9-1:
VCAPEN SELECT BIT
VCAPEN
Pin
0
RA5
TABLE 9-2:
Name
CONFIG2
Legend:
Note 1:
SUMMARY OF CONFIGURATION WORD WITH LDO
Bits
Bit -/7
Bit -/6
13:8
7:0
—
—
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
LVP
DEBUG
LPBOR
BORV
STVREN
—
—
VCAPEN
—
—
WRT<1:0>
Register
on Page
43
— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
PIC16F1516/7/8/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 83
PIC16(L)F1516/7/8/9
10.0
WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always ON
- WDT is OFF when in Sleep
- WDT is controlled by software
- WDT is always OFF
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 10-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
DS40001452F-page 84
WDTPS<4:0>
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
10.1
Independent Clock Source
10.3
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 25.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
10.4
10.2
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Table .
10.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always ON.
WDT protection is active during Sleep.
10.2.2
WDT IS OFF IN SLEEP
WDT protection is not active during Sleep.
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table for
more details.
TABLE 10-1:
WDT OPERATING MODES
WDTE<1:0>
SWDTE
N
11
X
10
X
X
Active
Active
Sleep
Disabled
X
0
00
WDT
Mode
Awake
1
01
TABLE 10-2:
Device
Mode
X
X
Clearing the WDT
The WDT is cleared when any of the following
conditions occur:
•
•
•
•
•
•
•
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Oscillator Start-up Timer (OST) is running
See Table 10-2 for more information.
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is ON, except in Sleep.
10.2.3
Time-Out Period
10.5
Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (with Fail-Safe Clock Monitor)” for more
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” and
The STATUS register (Register 3-1) for more
information.
Active
Disabled
Disabled
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
 2010-2016 Microchip Technology Inc.
Cleared until the end of OST
Unaffected
DS40001452F-page 85
PIC16(L)F1516/7/8/9
10.6
Register Definitions: Watchdog Control
REGISTER 10-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
bit 0
Note 1:
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1:8388608 (223) (Interval 256s nominal)
1:4194304 (222) (Interval 128s nominal)
1:2097152 (221) (Interval 64s nominal)
1:1048576 (220) (Interval 32s nominal)
1:524288 (219) (Interval 16s nominal)
1:262144 (218) (Interval 8s nominal)
1:131072 (217) (Interval 4s nominal)
1:65536 (Interval 2s nominal) (Reset value)
1:32768 (Interval 1s nominal)
1:16384 (Interval 512 ms nominal)
1:8192 (Interval 256 ms nominal)
1:4096 (Interval 128 ms nominal)
1:2048 (Interval 64 ms nominal)
1:1024 (Interval 32 ms nominal)
1:512 (Interval 16 ms nominal)
1:256 (Interval 8 ms nominal)
1:128 (Interval 4 ms nominal)
1:64 (Interval 2 ms nominal)
1:32 (Interval 1 ms nominal)
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
DS40001452F-page 86
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 10-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7
Bit 6
OSCCON
—
STATUS
—
—
WDTCON
—
—
Legend:
CONFIG1
Legend:
Bit 4
Bit 3
IRCF<3:0>
—
Bit 2
—
TO
PD
Bit 1
Bit 0
SCS<1:0>
Z
DC
WDTPS<4:0>
Register
on Page
59
C
21
SWDTEN
86
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 10-4:
Name
Bit 5
Bits
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
FCMEN
IESO
CLKOUTEN
CP
MCLRE
PWRTE
13:8
7:0
Bit 10/2
Bit 9/1
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Bit 8/0
—
Register
on Page
42
— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 87
PIC16(L)F1516/7/8/9
11.0
FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the
device.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration
Words).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Words.
11.1
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
DS40001452F-page 88
11.1.1
PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
11.2
Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory.
However, any unprogrammed locations
can be written without first erasing the
row. In this case, it is not necessary to
save and rewrite the other previously
programmed locations.
See Table 11-1 for Erase Row size and the number of
write latches for Flash program memory.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 11-1:
Device
FLASH MEMORY
ORGANIZATION BY DEVICE
Row Erase
(words)
Write
Latches
(words)
32
32
PIC16(L)F1516
PIC16(L)F1517
PIC16(L)F1518
PIC16(L)F1519
11.2.1
READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1.
2.
3.
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
 2010-2016 Microchip Technology Inc.
FIGURE 11-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation
(RD = 1)
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
Data read now in
PMDATH:PMDATL
End
Read Operation
DS40001452F-page 89
PIC16(L)F1516/7/8/9
FIGURE 11-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PC
+3
PC+3
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 5
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 11-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWL
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; Select Bank for PMCON registers
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
Do not select Configuration Space
Initiate read
Ignored (Figure 11-2)
Ignored (Figure 11-2)
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
DS40001452F-page 90
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
11.2.2
FLASH MEMORY UNLOCK
SEQUENCE
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write
programming or erasing. The sequence must be
executed and completed without interruption to
successfully complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to
program memory
• Write of program memory write latches to User
IDs
The unlock sequence consists of the following steps:
FIGURE 11-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
Write 055h to
PMCON2
Write 0AAh to
PMCON2
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
Initiate
Write or Erase operation
(WR = 1)
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
End
Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 91
PIC16(L)F1516/7/8/9
11.2.3
ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 11-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
FIGURE 11-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 11-3
(FIGURE
x-x)
CPU stalls while
Erase operation completes
(2ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
DS40001452F-page 92
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
EXAMPLE 11-2:
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
PMCON1,WREN
INTCON,GIE
 2010-2016 Microchip Technology Inc.
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase
Write 55h
Write AAh
Set WR bit to begin erase
NOP instructions are forced as processor starts
row erase of program memory.
The processor stalls until the erase process is complete
after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
DS40001452F-page 93
PIC16(L)F1516/7/8/9
11.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the
row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
Note:
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-5 (row writes to program memory with 32
write latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower five bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1.
2.
3.
Set the WREN bit of the PMCON1 register.
Clear the CFGS bit of the PMCON1 register.
Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 11-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
DS40001452F-page 94
 2010-2016 Microchip Technology Inc.
7
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
6
0 7
5 4
PMADRH
-
r9
r8
r7
r6
r5
7
0
PMADRL
r4
r3
r2
r1
r0
c4
c3
c2
c1
c0
5
-
0
7
PMDATH
6
0
PMDATL
8
14
10
Program Memory Write Latches
5
14
Write Latch #0
00h
PMADRL<4:0>
14
CFGS = 0
 2010-2016 Microchip Technology Inc.
PMADRH<6:0>
:PMADRL<7:5>
Row
Address
Decode
14
14
Write Latch #1
01h
14
Write Latch #30 Write Latch #31
1Eh
1Fh
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0020h
0021h
003Eh
003Fh
002h
0040h
0041h
005Eh
005Fh
3FEh
7FC0h
7FC1h
7FDEh
7FDFh
3FFh
7FE0h
7FE1h
7FFEh
7FFFh
Flash Program Memory
400h
CFGS = 1
8000h - 8003h
8004h - 8005h
8006h
8007h - 8008h
8009h - 801Fh
USER ID 0 - 3
reserved
DEVID
REVID
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1516/7/8/9
DS40001452F-page 95
FIGURE 11-5:
PIC16(L)F1516/7/8/9
FIGURE 11-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt)
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
Update the word counter
(word_cnt--)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure11-3
x-x)
Figure
Select Write Operation
(FREE = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Increment Address
(PMADRH:PMADRL++)
Write Latches to Flash
(LWLO = 0)
Unlock Sequence
(Figure11-3
x-x)
Figure
CPU stalls while Write
operation completes
(2ms typical)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
DS40001452F-page 96
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
EXAMPLE 11-3:
;
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:
1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
stored in little endian format
3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable ints so required sequences will execute properly
Bank 3
Load initial address
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Load initial data address
Load initial data address
Not configuration space
Enable writes
Only Load Write Latches
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
PMCON1,WREN
INTCON,GIE
 2010-2016 Microchip Technology Inc.
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor
loads program memory write latches
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor writes
all the program memory write latches simultaneously
to program memory.
After NOPs, the processor
stalls until the self-write process in complete
after write processor continues with 3rd instruction
Disable writes
Enable interrupts
DS40001452F-page 97
PIC16(L)F1516/7/8/9
11.3
Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it
must first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be
modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
FIGURE 11-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
(Figure11-2
x.x)
Figure
An image of the entire row read
must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure11-4
x.x)
Figure
Write Operation
use RAM image
(Figure11-5
x.x)
Figure
End
Modify Operation
DS40001452F-page 98
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
11.4
User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table .
When read access is initiated on an address outside
the parameters listed in Table , the PMDATH:PMDATL
register pair is cleared, reading back ‘0’s.
TABLE 11-1:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
User IDs
Yes
Yes
8006h
Device ID/Revision ID
Yes
No
8007h-8008h
Configuration Words 1 and 2
Yes
No
EXAMPLE 11-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space
Disable interrupts
Initiate read
Executed (See Figure 11-2)
Ignored (See Figure 11-2)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
 2010-2016 Microchip Technology Inc.
DS40001452F-page 99
PIC16(L)F1516/7/8/9
11.5
Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with
the intended data stored in RAM after the last write is
complete.
FIGURE 11-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
(Figure
x.x)
Figure
11-2
PMDAT =
RAM image
?
Yes
No
No
Fail
Verify Operation
Last
Word ?
Yes
End
Verify Operation
DS40001452F-page 100
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
11.6
Register Definitions: Flash Program Memory Control
REGISTER 11-2:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 11-3:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-4:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
PMADR<7:0>: Specifies the Least Significant bits for program memory address
bit 7-0
REGISTER 11-5:
U-1
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
—(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘1’
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1:
Unimplemented, read as ‘1’.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 101
PIC16(L)F1516/7/8/9
REGISTER 11-6:
U-1
(1)
—
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
R/W-0/0
R/W-0/0
R/W/HC-0/0
R/W/HC-x/q(2)
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1:
2:
3:
Unimplemented bit, read as ‘1’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1) .
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
DS40001452F-page 102
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 11-7:
W-0/0
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 11-2:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
102
PMCON1
(1)
—
PMCON2
Program Memory Control Register 2
103
PMADRL
PMADRL<7:0>
101
(1)
PMADRH
—
PMADRH<6:0>
PMDATL
PMDATH
Legend:
Note 1:
—
CONFIG1
CONFIG2
Legend:
—
101
PMDATH<5:0>
101
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Unimplemented, read as ‘1’.
TABLE 11-3:
Name
101
PMDATL<7:0>
Bits
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bit -/7
Bit -/6
13:8
7:0
CP
MCLRE
13:8
7:0
—
—
Bit 13/5
Bit 12/4
Bit 11/3
FCMEN
IESO
CLKOUTEN
PWRTE
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
WDTE<1:0>
—
FOSC<2:0>
LVP
DEBUG
—
BORV
—
VCAPEN(1)
—
—
STVREN
—
WRT<1:0>
Register
on Page
42
43
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 103
PIC16(L)F1516/7/8/9
12.0
I/O PORTS
FIGURE 12-1:
GENERIC I/O PORT
OPERATION
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
Read LATx
D
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELx (analog select)
• WPUx (weak pull-up)
Q
CK
VDD
Data Register
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
PORTC
●
●
●
PIC16(L)F1517/9
●
●
●
I/O pin
Read PORTx
To peripherals
VSS
PORTE
PORTB
PIC16(L)F1516/8
PORTD
Device
Data Bus
ANSELx
PORT AVAILABILITY PER
DEVICE
PORTA
TABLE 12-1:
Write LATx
Write PORTx
TRISx
●
●
●
The Data Latch (LATx register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.
DS40001452F-page 104
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON)
registers are used to steer specific peripheral input and
output functions between different pins. The APFCON
registers are shown in Register 12-1. For this device
family, the following functions can be moved between
different pins.
• SS (Slave Select)
• CCP2
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
REGISTER 12-1:
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
SSSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
SSSEL: Pin Selection bit
0 = SS function is on RA5
1 = SS function is on RA0
bit 0
CCP2SEL: Pin Selection bit
0 = CCP2 function is on RC1
1 = CCP2 function is on RB3
 2010-2016 Microchip Technology Inc.
DS40001452F-page 105
PIC16(L)F1516/7/8/9
12.2
12.2.1
PORTA Registers
DATA REGISTER
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 12-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 12-1 shows how to
initialize an I/O port.
Reading the PORTA register (Register 12-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
12.2.2
DIRECTION CONTROL
The TRISA register (Register 12-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
12.2.3
ANALOG CONTROL
The ANSELA register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
EXAMPLE 12-1:
;
;
;
;
This code example illustrates
initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
12.2.4
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, are not shown in
the priority lists. These inputs are active when the I/O
pin is set for Analog mode using the ANSELx registers.
Digital output functions may control the pin when it is in
Analog mode with the priority shown in the priority list.
TABLE 12-2:
PORTA OUTPUT PRIORITY
Pin Name
Function Priority(1)
RA0
RA0
RA1
RA1
RA2
RA2
RA3
RA3
RA4
RA4
RA5
VCAP (PIC16F1516/7/8/9 only)
RA5
RA6
CLKOUT
OSC2
RA6
RA7
RA7
Note 1:
DS40001452F-page 106
INITIALIZING PORTA
Priority listed from highest to lowest.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-2:
PORTA: PORTA REGISTER
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RA<7:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is the
return of actual I/O pin values.
REGISTER 12-3:
TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
 2010-2016 Microchip Technology Inc.
DS40001452F-page 107
PIC16(L)F1516/7/8/9
REGISTER 12-4:
LATA: PORTA DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
LATA<7:0>: PORTA Output Latch Value bits(1)
bit 7-4
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is the
return of actual I/O pin values.
REGISTER 12-5:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 4
Unimplemented: Read as ‘0’
bit 3-0
ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001452F-page 108
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 12-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
108
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
105
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
108
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
107
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
107
Name
LATA
OPTION_REG
PORTA
TRISA
Legend:
CONFIG1
Legend:
146
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-4:
Name
PS<2:0>
Bits
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
FCMEN
IESO
CLKOUTEN
CP
MCLRE
PWRTE
13:8
7:0
Bit 10/2
WDTE<1:0>
Bit 9/1
Bit 8/0
BOREN<1:0.>
—
FOSC<2:0>
Register
on Page
42
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 109
PIC16(L)F1516/7/8/9
12.3
12.3.1
PORTB Registers
DATA REGISTER
PORTB is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 12-7). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Reading the PORTB register (Register 12-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
12.3.2
DIRECTION CONTROL
12.3.4
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-5.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
TABLE 12-5:
PORTB OUTPUT PRIORITY
Pin Name
Function Priority(1)
RB0
RB0
RB1
RB1
RB2
RB2
The TRISB register (Register 12-7) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
RB3
CCP2
RB3
RB4
RB4
RB5
RB5
RB6
12.3.3
ICDCLK
RB6
RB7
ICDDAT
RB7
ANALOG CONTROL
The ANSELB register (Register 12-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
Note 1:
Priority listed from highest to lowest.
The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected
port.
Note:
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
DS40001452F-page 110
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-6:
PORTB: PORTB REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RB<7:0>: PORTB General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the
return of actual I/O pin values.
REGISTER 12-7:
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 12-8:
LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATB<7:0>: PORTB Output Latch Value bits(1)
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the
return of actual I/O pin values.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 111
PIC16(L)F1516/7/8/9
REGISTER 12-9:
ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
112
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
105
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
111
LATB
Bit 0
Register
on Page
Bit 7
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
111
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
112
OPTION_REG
Legend:
PS<2:0>
146
111
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS40001452F-page 112
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.4
12.4.1
PORTC Registers
DATA REGISTER
PORTC is a 8-bit wide bidirectional port. The
corresponding data direction register is TRISC
(Register 12-12). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Reading the PORTC register (Register 12-11) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
12.4.2
DIRECTION CONTROL
The TRISC register (Register 12-12) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
12.4.3
ANALOG CONTROL
The ANSELC register (Register 12-14) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when
executing read-modify-write instructions on the affected
port.
Note:
The ANSELC bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
 2010-2016 Microchip Technology Inc.
12.4.4
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-7.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in the priority list.
TABLE 12-7:
PORTC OUTPUT PRIORITY
Pin Name
Function Priority(1)
RC0
SOSCO
RC0
RC1
SOSCI
CCP2
RC1
RC2
CCP1
RC2
RC3
SCL
SCK
RC3(2)
RC4
SDA
RC4(2)
RC5
SDO
RC5
RC6
CK
TX
RC6
RC7
DT
RC7
Note 1:
2:
Priority listed from highest to lowest.
RC3 and RC4 read the I2C ST input when
I2C mode is enabled.
DS40001452F-page 113
PIC16(L)F1516/7/8/9
REGISTER 12-11: PORTC: PORTC REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the
return of actual I/O pin values.
REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATC<7:0>: PORTC Output Latch Value bits(1)
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the
return of actual I/O pin values.
DS40001452F-page 114
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-14: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
ANSC7
ANSC6
ANSC3
ANSC3
ANSC3
ANSC2
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
ANSC<7:2>: Analog Select between Analog or Digital Function on pins RC<7:2>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
—
—
115
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
105
LATC
Bit 1
Bit 0
Register
on Page
Bit 7
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
114
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
114
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 115
PIC16(L)F1516/7/8/9
12.5
12.5.1
PORTD Registers
(PIC16F1517/1519 only)
DATA REGISTER
12.5.4
PORTD FUNCTIONS AND OUTPUT
PRIORITIES
PORTD has no peripheral outputs, so the PORTD
output has no priority function.
PORTD is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 12-16). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Reading the PORTD register (Register 12-15) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATD).
12.5.2
DIRECTION CONTROL
The TRISD register (Register 12-16) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISD register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
12.5.3
ANALOG CONTROL
The ANSELD register (Register 12-18) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELD bits has no effect on digital output functions. A pin with TRIS clear and ANSELD set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when
executing read-modify-write instructions on the affected
port.
Note:
The ANSELD bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
DS40001452F-page 116
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-15: PORTD: PORTD REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RD<7:0>: PORTD General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is the
return of actual I/O pin values.
REGISTER 12-16: TRISD: PORTD TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISD7
TRISD6
TRISD5
TRISD4
TRISD5
TRISD5
TRISD5
TRISD4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISD<7:0>: PORTD Tri-State Control bits
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
REGISTER 12-17: LATD: PORTD DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATD<7:0>: PORTD Output Latch Value bits(1)
Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is the
return of actual I/O pin values.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 117
PIC16(L)F1516/7/8/9
REGISTER 12-18: ANSELD: PORTD ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
ANSD<7:0>: Analog Select between Analog or Digital Function on pins RD<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-9:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELD
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
118
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
117
Name
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
117
TRISD
TRISD7
TRISD6
TRISB5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
117
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTD.
PIC16F1517/1519 only.
DS40001452F-page 118
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.6
12.6.1
12.6.3
PORTE Registers
DATA REGISTER
PORTE is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 12-1 shows how to initialize an I/O port.
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
PORTE has no peripheral outputs, so the PORTE
output has no priority function.
Reading the PORTE register (Register 12-19) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is
modified and then written to the PORT data latch
(LATE). RE3 reads ‘0’ when MCLRE = 1.
Note:
12.6.2
RE<2:0> and TRISE<2:0> pins
available on PIC16(L)F1517/9 only.
are
ANALOG CONTROL
The ANSELE register (Register 12-22) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELE bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
The TRISE register (Register 12-20) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Note:
The ANSELE bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 119
PIC16(L)F1516/7/8/9
REGISTER 12-19: PORTE: PORTE REGISTER
U-0
U-0
—
—
U-0
—
U-0
—
R-x/u
R/W-x/u
RE3
RE2(1)
R/W-x/u
RE1
(1)
bit 7
R/W-x/u
RE0(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RE<3:0>: PORTE I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1:
RE<2:0> are not implemented on the PIC16(L)F1516/8. Read as ‘0’. Writes to RE<2:0> are actually written to corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values.
REGISTER 12-20: TRISE: PORTE TRI-STATE REGISTER
U-0
U-0
—
—
U-0
—
U-0
—
U-1(2)
R/W-1
R/W-1
R/W-1
—
TRISE2(1)
TRISE1(1)
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
Unimplemented: Read as ‘1’
bit 2-0
TRISE<2:0>: RE<2:0> Tri-State Control bits(1)
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
Note 1:
2:
TRISE<2:0> are not implemented on the PIC16(L)F1517/9. Read as ‘0’.
Unimplemented, read as ‘1’.
DS40001452F-page 120
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-21: LATE: PORTE DATA LATCH REGISTER(2)
U-0
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
LATE2
LATE1
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
LATE<2:0>: PORTE Output Latch Value bits(1)
Note 1:
2:
Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is the
return of actual I/O pin values.
PIC16(L)F1517/9 only.
REGISTER 12-22: ANSELE: PORTE ANALOG SELECT REGISTER(2)
U-0
U-0
—
U-0
—
—
U-0
—
U-0
R/W-1
R/W-1
R/W-1
—
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 121
PIC16(L)F1516/7/8/9
REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER(1,2)
U-0
U-0
U-0
U-0
R/W-1/1
U-0
U-0
U-0
—
—
—
—
WPUE3
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WPUE: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0
Unimplemented: Read as ‘0’
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
Note 1:
2:
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
(1)
ANSELE
—
—
CCPxCON
—
—
—
LATE
—
—
PORTE
Bit 3
Bit 2
CHS<4:0>
—
ADCON0
Bit 4
—
—
—
—
ANSE2
DCxB<1:0>
—
—
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
137
ANSE1
ANSE0
121
CCPxM<3:0>
168
—
LATE2(1)
LATE1(1)
LATE0(1)
121
—
RE3
RE2(1)
RE1(1)
RE0(1)
120
TRISE2(1)
TRISE1(1)
TRISE0(1)
120
—
—
—
122
—
TRISE
—
—
—
—
—(2)
WPUE
—
—
—
—
WPUE3
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.
Note 1: These bits are not implemented on the PIC16(L)F1516/8 devices, read as ‘0’.
2: Unimplemented, read as ‘1’.
TABLE 12-11: SUMMARY OF CONFIGURATION WORD WITH PORTE
Name
CONFIG1
Legend:
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
FCMEN
IESO
CLKOUTEN
CP
MCLRE
PWRTE
13:8
7:0
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
—
Register
on Page
42
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.
DS40001452F-page 122
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
13.0
INTERRUPT-ON-CHANGE
The PORTB pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTB pin, or
combination of PORTB pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
•
•
•
•
Interrupt on Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
Figure 13-1 is a block diagram of the IOC module.
13.1
Enabling the Module
To allow individual PORTB pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
13.3
Interrupt Flags
The IOCBFx bits located in the IOCBF register are
status flags that correspond to the interrupt-on-change
pins of PORTB. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCBFx bits.
13.4
Clearing Interrupt Flags
The individual status flags, (IOCBFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 13-1:
13.2
Individual Pin Configuration
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCBPx bit of the IOCBP
register is set. To enable a pin to detect a falling edge,
the associated IOCBNx bit of the IOCBN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers,
respectively.
MOVLW
XORWF
ANDWF
13.5
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 123
PIC16(L)F1516/7/8/9
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCBNx
D
Q4Q1
Q
CK
Edge
Detect
R
RBx
IOCBPx
D
Data Bus =
0 or 1
Q
write IOCBFx
CK
D
S
Q
To Data Bus
IOCBFx
CK
IOCIE
R
Q2
From all other
IOCBFx individual
Pin Detectors
Q1
Q2
Q3
Q4
Q4Q1
DS40001452F-page 124
Q1
Q1
Q2
Q2
Q3
Q4
Q4Q1
IOC Interrupt
to CPU core
Q3
Q4
Q4
Q4Q1
Q4Q1
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
13.6
Register Definitions: Interrupt-on-change Control
REGISTER 13-1:
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set
upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2:
IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be
set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3:
IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-0
IOCBF7:0>: Interrupt-on-Change PORTB Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge
was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 125
PIC16(L)F1516/7/8/9
TABLE 13-1:
Name
ANSELB
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
112
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
IOCBF
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
125
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
125
IOCBP
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
125
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
111
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
DS40001452F-page 126
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
14.0
FIXED VOLTAGE REFERENCE
(FVR)
14.1
Independent Gain Amplifiers
The output of the FVR supplied to the ADC module is
routed through a programmable gain amplifier. The
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x, to produce the three possible
voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 16.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
• ADC positive reference
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
To minimize current consumption when the FVR is
disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
14.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 25.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
x2
x4
FVR BUFFER1
(To ADC Module)
1.024V Fixed
Reference
+
FVREN
-
FVRRDY
Any peripheral requiring
the Fixed Reference
(See Table 14-1)
TABLE 14-1:
Peripheral
HFINTOSC
BOR
LDO
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Conditions
Description
FOSC<2:0> = 100 and
IRCF<3:0> = 000x
INTOSC is active and device is not in Sleep
BOREN<1:0> = 11
BOR always enabled
BOREN<1:0> = 10 and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1
BOR under software control, BOR Fast Start enabled
All PIC16F1516/7/8/9 devices, when
VREGPM = 1 and not in Sleep
The device runs off of the low-power regulator when in Sleep
mode.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 127
PIC16(L)F1516/7/8/9
14.3
Register Definitions: FVR Control
REGISTER 14-1:
R/W-0/0
FVREN(1)
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R-q/q
R/W-0/0
(2)
FVRRDY
TSEN
(3)
R/W-0/0
TSRNG
(3)
U-0
U-0
—
—
R/W-0/0
R/W-0/0
ADFVR<1:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit(1)
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(2)
0 = Fixed Voltage Reference output is not ready or not enabled
1 = Fixed Voltage Reference output is ready for use
bit 5
TSEN: Temperature Indicator Enable bit(3)
0 = Temperature Indicator is disabled
1 = Temperature Indicator is enabled
bit 4
TSRNG: Temperature Indicator Range Selection bit(3)
0 = VOUT = VDD - 2VT (Low Range)
1 = VOUT = VDD - 4VT (High Range)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADFVR<1:0>: ADC FVR Buffer Gain Selection bits(1)
11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(4)
10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(4)
01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR
00 = ADC FVR Buffer is off
Note 1:
2:
3:
4:
To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
FVRRDY is always ‘1’ on PIC16F1516/7/8/9 only.
See Section 15.0 “Temperature Indicator Module” for additional information.
Fixed Voltage Reference output cannot exceed VDD.
TABLE 14-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
128
Shaded cells are unused by the Fixed Voltage Reference module.
DS40001452F-page 128
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
15.0
TEMPERATURE INDICATOR
MODULE
FIGURE 15-1:
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
TEMPERATURE CIRCUIT
DIAGRAM
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, Use and Calibration of the Internal
Temperature Indicator (DS01333) for more details
regarding the calibration process.
15.1
Circuit Operation
Figure 15-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 15-1 describes the output characteristics of
the temperature indicator.
EQUATION 15-1:
VOUT RANGES
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
VOUT
15.2
To ADC
Minimum Operating VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Table 15-1 shows the recommended minimum VDD vs.
range setting.
TABLE 15-1:
RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
15.3
Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 16.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 129
PIC16(L)F1516/7/8/9
15.4
ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
TABLE 15-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
128
Shaded cells are unused by the temperature indicator module.
DS40001452F-page 130
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
16.0
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake up the
device from Sleep.
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 16-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 16-1:
ADC BLOCK DIAGRAM
VDD
ADPREF = 0x
FVR
ADPREF = 11
VREF+
AN0
00000
AN1
00001
AN2
00010
VREF+/AN3
00011
ADPREF = 10
ADC
10
GO/DONE
AN27
11011
Reserved
Reserved
Temp Indicator
11100
FVR Buffer1
11111
11101
ADFM
0 = Left Justify
1 = Right Justify
ADON(1)
16
11110
VSS
ADRESH
ADRESL
CHS<4:0>(2)
Note 1:
2:
When ADON = 0, all multiplexer inputs are disconnected.
See ADCON0 register (Register 16-1) for detailed analog channel selection per device.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 131
PIC16(L)F1516/7/8/9
16.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
16.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 “I/O Ports” for more information.
Note:
16.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are up to 30 channel selections available:
•
•
•
•
AN<19:8, 4:0> pins (PIC16(L)F1516/8 only)
AN<27:0> pins (PIC16(L)F1517/9 only)
Temperature Indicator
FVR (Fixed Voltage Reference) Output
16.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal FRC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods as shown in Figure 16-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the ADC conversion requirements in Section 25.0 “Electrical Specifications” for
more information. Table gives examples of appropriate
ADC clock selections.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
Refer to Section 14.0 “Fixed Voltage Reference
(FVR)” and Section 15.0 “Temperature Indicator
Module” for more information on these channel
selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
DS40001452F-page 132
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 16-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
200 ns
(2)
(2)
(2)
Fosc/8
001
400 ns(2)
0.5 s(2)
Fosc/16
101
800 ns
Fosc/32
010
Fosc/64
FRC
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
1.0 s
2.0 s
4.0 s
16.0 s(3)
1.6 s
2.0 s
4.0 s
8.0 s(3)
32.0 s(3)
110
3.2 s
4.0 s
16.0 s
64.0 s(3)
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
250 ns
500 ns
8.0 s
(3)
1.0-6.0 s(1,4)
(3)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is
derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions
are to be performed with the device in Sleep mode.
FIGURE 16-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b8
b3
b9
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 133
PIC16(L)F1516/7/8/9
16.1.5
INTERRUPTS
16.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 16-3:
10-BIT ADC CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit ADC Result
(ADFM = 1)
Unimplemented: Read as ‘0’
MSB
bit 7
Unimplemented: Read as ‘0’
DS40001452F-page 134
bit 0
LSB
bit 0
bit 7
bit 0
10-bit ADC Result
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
16.2
16.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
16.2.2
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 16.2.6 “ADC Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
16.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
16.2.4
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC oscillator source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
16.2.5
SPECIAL EVENT TRIGGER
The Special Event Trigger of the CCPx module allows
periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is
set by hardware and the Timer1 counter resets to zero.
TABLE 16-2:
Device
SPECIAL EVENT TRIGGER
CCP
PIC16(L)F1516
PIC16(L)F1517
PIC16(L)F1518
CCP2
PIC16(L)F1519
Using the Special Event Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
Refer to Section 20.0 “Capture/Compare/PWM
Modules” for more information.
 2010-2016 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
16.2.6
ADC CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
• Disable weak pull-ups, either globally (Refer
to the OPTION_REG register) or individually
(Refer to the appropriate WPUx register)
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 16-1:
ADC CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B’11110000’ ;Right justify, Frc
;clock
MOVWF
ADCON1
;Vdd and Vss Vref
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
WPUA
BCF
WPUA, 0
;Disable weak pullup on RA0
BANKSEL
ADCON0
;
MOVLW
B’00000001’ ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “ADC Acquisition Requirements”.
DS40001452F-page 136
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
16.3
Register Definitions: ADC Control
REGISTER 16-1:
U-0
ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1)
11110 = Temperature Indicator(2).
11101 = Reserved. No channel connected.
11100 = Reserved. No channel connected.
11011 = AN27(3)
•
•
•
10100 = AN20(3)
10011 = AN19
10010 = AN18
10001 = AN17
10000 = AN16
01111 = AN15
01110 = AN14
01101 = AN13
01100 = AN12
01011 = AN11
01010 = AN10
01001 = AN9
01000 = AN8
00111 = AN7(3)
00110 = AN6(3)
00101 = AN5(3)
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1
GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
2:
3:
See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
See Section 15.0 “Temperature Indicator Module” for more information.
AN<7:5> and AN<27:20> are PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 137
PIC16(L)F1516/7/8/9
REGISTER 16-2:
R/W-0/0
ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
—
—
R/W-0/0
R/W-0/0
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: ADC Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: ADC Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated FRC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated FRC oscillator)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
00 = VREF is connected to VDD
01 = Reserved
10 = VREF is connected to external VREF+ pin(1)
11 = VREF is connected to internal Fixed Voltage Reference (FVR) module(1)
Note 1:
When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 25.0 “Electrical Specifications” for details.
DS40001452F-page 138
 2010-2016 Microchip Technology Inc.
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REGISTER 16-3:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 16-4:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
bit 5-0
Reserved: Do not use.
 2010-2016 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
REGISTER 16-5:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Reserved: Do not use.
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 16-6:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result
DS40001452F-page 140
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
16.4
ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 16-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 16-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To
calculate the minimum acquisition time, Equation 16-1
may be used. This equation assumes that 1/2 LSb error
is used (1,024 steps for the ADC). The 1/2 LSb error is
the maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
 = V CHOLD
V AP PLIE D  1 – -------------------------n+1

2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------

RC
V AP PLIE D  1 – e  = V CHOLD


;[2] VCHOLD charge response to VAPPLIED
– Tc
---------

1
RC
 ;combining [1] and [2]
V AP PLIE D  1 – e  = V A PP LIED  1 – -------------------------n+1




2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 13.5pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.20 µs
Therefore:
T AC Q = 2µs + 1.20µs +   50°C- 25°C   0.05 µs/°C  
= 4.45µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 141
PIC16(L)F1516/7/8/9
FIGURE 16-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Rs
VT  0.6V
CPIN
5 pF
VA
RIC  1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT  0.6V
CHOLD = 10 pF
VSS/VREF-
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
Legend: CHOLD
CPIN
RSS
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
RIC
RSS
= Resistance of Sampling Switch
= Sampling Switch
SS
5 6 7 8 9 10 11
Sampling Switch
(k)
= Threshold Voltage
VT
Note 1: Refer to Section 25.0 “Electrical Specifications”.
FIGURE 16-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
VREF-
DS40001452F-page 142
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
VREF+
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 16-3:
Name
ADCON0
ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
Bit 6
Bit 5
—
Bit 4
Bit 3
Bit 2
CHS<4:0>
ADFM
ADCS<2:0>
ADRESH
ADC Result Register High
ADRESL
ADC Result Register Low
—
—
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
137
ADPREF<1:0>
138
139, 140
139, 140
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
108
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
112
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
—
—
115
ANSELD(1)
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
118
ANSELE(1)
—
—
—
—
—
ANSE2
ANSE1
ANSE0
CCP1CON
—
—
DC1B<1:0>
CCP1M<3:0>
168
CCP2CON
—
—
DC2B<1:0>
CCP2M<3:0>
168
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
107
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
117
—
—(2)
TRISE2(1)
TRISE1(1)
TRISE0(1)
120
TRISE
Legend:
Note 1:
—
—
—
ADFVR<1:0>
121
128
— = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
PIC16(L)F1517/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 143
PIC16(L)F1516/7/8/9
17.0
17.1.2
TIMER0 MODULE
In 8-Bit Counter mode, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin.
The Timer0 module is an 8-bit timer/counter with the
following features:
•
•
•
•
•
•
8-BIT COUNTER MODE
8-bit timer/counter register (TMR0)
8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
TMR0 can be used to gate Timer1
8-Bit Counter mode, using the T0CKI pin, is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
Figure 17-1 is a block diagram of the Timer0 module.
17.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
17.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 17-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
8
T0CKI
1
Sync
2 TCY
1
TMR0
0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
Set Flag bit TMR0IF
on Overflow
Overflow to Timer1
8
PS<2:0>
DS40001452F-page 144
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
17.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS<2:0> bits of the
OPTION_REG register. In order to have a 1:1 prescaler
value for the Timer0 module, the prescaler must be
disabled by setting the PSA bit of the OPTION_REG
register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
17.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The
Timer0 interrupt enable is the TMR0IE bit of the
INTCON register.
Note:
17.1.5
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
17.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
 2010-2016 Microchip Technology Inc.
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17.2
Register Definitions: Option Register
REGISTER 17-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
TABLE 17-1:
Name
INTCON
OPTION_REG
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
TMR0
TRISA
Legend:
*
PS<2:0>
146
Timer0 Module Register
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
144*
TRISA2
TRISA1
TRISA0
107
— = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
DS40001452F-page 146
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
18.0
•
•
•
•
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
Figure 18-1 is a block diagram of the Timer1 module.
•
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
2-bit prescaler
32 kHz secondary oscillator circuit
Optionally synchronized comparator out
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 18-1:
Gate Toggle mode
Gate Single-pulse mode
Gate Value Status
Gate Event Interrupt
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
0
T1G_IN
01
T1GVAL
0
From Timer2
Match PR2
10
Reserved
11
Single Pulse
D
CK Q
R
TMR1ON
T1GPOL
Q
T1GTM
1
Acq. Control
1
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
det
Set
TMR1GIF
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
Q
D
T1CLK
Synchronized
clock input
0
1
TMR1CS<1:0>
SOSCO/T1CKI
Secondary
Oscillator
SOSCI
T1SYNC
OUT
LFINTOSC
11
1
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
To Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 147
PIC16(L)F1516/7/8/9
18.1
Timer1 Operation
18.2
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 18-2 displays the clock source selections.
18.2.1
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and increments on every selected edge of the external source.
INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 18-1 displays the Timer1 enable
selections.
TABLE 18-1:
Clock Source Selection
TIMER1 ENABLE
SELECTIONS
The following asynchronous source may be used:
Timer1
Operation
TMR1ON
TMR1GE
0
0
Off
0
1
Off
18.2.2
1
0
Always On
1
1
Count Enabled
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
• Asynchronous event on the T1G pin to Timer1
gate
EXTERNAL CLOCK SOURCE
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. This
external clock source can be synchronized to the
microcontroller system clock and run asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the secondary oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•
•
•
•
TABLE 18-2:
Timer1 enabled after POR
Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON =0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
CLOCK SOURCE SELECTIONS
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
1
1
x
LFINTOSC
1
0
1
Secondary Oscillator Circuit on SOSCI/SOSCO Pins
1
0
0
External Clocking on T1CKI Pin
0
1
x
System Clock (FOSC)
0
0
x
Instruction Clock (FOSC/4)
DS40001452F-page 148
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
18.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
18.4
Secondary Oscillator
Timer1 uses the low-power secondary oscillator circuit
on pins SOSCI and SOSCO. The secondary oscillator
is designed to use an external 32.768 kHz crystal.
The secondary oscillator circuit is enabled by setting
the T1OSCEN bit of the T1CON register. The oscillator
will continue to run during Sleep.
Note:
18.5
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 18.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
 2010-2016 Microchip Technology Inc.
18.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register
pair.
18.6
Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
18.6.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 18-3 for timing details.
TABLE 18-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G

0
0
Counts

0
1
Holds Count

1
0
Holds Count

1
1
Counts
18.6.2
Timer1 Operation
TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
DS40001452F-page 149
PIC16(L)F1516/7/8/9
TABLE 18-4:
TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
Timer2 match PR2
11
Reserved
18.6.2.1
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
18.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
18.6.2.3
Timer2 Match PR2 Operation
When Timer2 increments and matches PR2, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
18.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single-level
pulse.
The Timer1 gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 18-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
18.6.4
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
DS40001452F-page 150
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 18-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
gate source to be measured. See Figure 18-6 for timing
details.
18.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control
value. The value is stored in the T1GVAL bit in the
T1GCON register. The T1GVAL bit is valid even when
the Timer1 gate is not enabled (TMR1GE bit is
cleared).
18.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
18.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, the user must
set these bits:
•
•
•
•
TMR1ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Note:
18.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
18.9
CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For
more
information,
see
“Capture/Compare/PWM Modules”.
Section 20.0
18.10 CCP Special Event Trigger
When the CCP is configured to trigger a special event,
the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
The CCP module may still be configured to generate a
CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1
can cause a Special Event Trigger to be missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
For more information, see Section 16.2.5 “Special
Event Trigger”.
Timer1 secondary oscillator will continue to operate in
Sleep regardless of the T1SYNC bit setting.
FIGURE 18-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 151
PIC16(L)F1516/7/8/9
FIGURE 18-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
N
FIGURE 18-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
DS40001452F-page 152
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 18-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
N
Cleared by software
 2010-2016 Microchip Technology Inc.
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by
software
DS40001452F-page 153
PIC16(L)F1516/7/8/9
FIGURE 18-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001452F-page 154
N
Cleared by software
N+1
N+2
N+3
N+4
Set by hardware on
falling edge of T1GVAL
Cleared by
software
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
18.11 Register Definitions: Timer1 Control
REGISTER 18-1:
R/W-0/u
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
—
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Timer1 clock source is LFINTOSC
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
1 = Secondary oscillator circuit enabled for Timer1
0 = Secondary oscillator circuit disabled for Timer1
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X:
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X:
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 gate flip-flop
 2010-2016 Microchip Technology Inc.
DS40001452F-page 155
PIC16(L)F1516/7/8/9
REGISTER 18-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
11 = Reserved
10 = Timer2 Match PR2
01 = Timer0 overflow output
00 = Timer1 gate pin
DS40001452F-page 156
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 18-5:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
112
CCP1CON
—
—
DC1B<1:0>
CCP1M<3:0>
CCP2CON
—
—
DC2B<1:0>
CCP2M<3:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
151*
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
151*
Name
INTCON
PIE1
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
T1CON
T1GCON
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TRISB3
TRISB2
TRISB1
TRISC3
TRISC2
T1OSCEN T1SYNC
T1GGO/
DONE
T1GVAL
168
168
TRISB0
112
TRISC1
TRISC0
115
—
TMR1ON
155
T1GSS<1:0>
156
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 157
PIC16(L)F1516/7/8/9
19.0
TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
• Optional use as the shift clock for the MSSP
modules
See Figure 19-1 for a block diagram of Timer2.
FIGURE 19-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
EQ
Postscaler
1:1 to 1:16
T2CKPS<1:0>
PR2
4
T2OUTPS<3:0>
DS40001452F-page 158
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
19.1
Timer2 Operation
The clock input to the Timer2 modules is the system
instruction clock (FOSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
Section 19.2
“Timer2
counter/postscaler
(see
Interrupt”).
19.3
Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP1 module, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 21.0
“Master Synchronous Serial Port (MSSP) Module”
19.4
Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
•
•
•
•
•
•
•
•
•
a write to the TMR2 register
a write to the T2CON register
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note:
19.2
TMR2 is not cleared when T2CON is
written.
Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 159
PIC16(L)F1516/7/8/9
19.5
Register Definitions: Timer2 Control
REGISTER 19-1:
U-0
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
bit 7
R/W-0/0
T2CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is ON
0 = Timer2 is OFF
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1
DS40001452F-page 160
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 19-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name
Bit 7
Bit 6
CCP1CON
—
—
CCP2CON
Bit 5
Bit 4
Bit 3
DC1B<1:0>
Bit 2
Bit 1
Bit 0
CCP1M<3:0>
168
—
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PR2
Timer2 Module Period Register
INTCON
T2CON
TMR2
—
DC2B<1:0>
Register
on Page
T2OUTPS<3:0>
CCP2M<3:0>
168
158*
TMR2ON
T2CKPS<1:0>
Holding Register for the 8-bit TMR2 Register
160
158*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 161
PIC16(L)F1516/7/8/9
20.0
CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
This family of devices contains two standard Capture/
Compare/PWM modules (CCP1 and CCP2).
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
Figure 20-1 shows a simplified diagram of the Capture
operation.
20.1.1
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP2 pin function can be moved to
alternative pins using the APFCON register. Refer to
Register 12-1 for more details.
Note:
PWM RESOURCES
Device Name
CCP1
CCP2
PIC16(L)F1516/7/8/9
Standard PWM
Standard PWM
20.1
Capture Mode
The Capture mode function described in this section is
available and identical for CCP modules CCP1 and
CCP2.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
•
•
•
•
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 20-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
 1, 4, 16
Set Flag bit CCPxIF
(PIRx register)
CCPx
pin
CCPRxH
and
Edge Detect
CCPRxL
Capture
Enable
TMR1H
TMR1L
CCPxM<3:0>
System Clock (FOSC)
20.1.2
TABLE 20-1:
CCP PIN CONFIGURATION
TIMER1 MODE RESOURCE
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
See Section 18.0 “Timer1 Module with Gate
Control” for more information on configuring Timer1.
20.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
DS40001452F-page 162
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Example 20-1 demonstrates the code to
perform this function.
EXAMPLE 20-1:
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 20-2 shows a simplified diagram of the
Compare operation.
FIGURE 20-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON
CLRF
MOVLW
MOVWF
20.1.5
;Set Bank bits to point
;to CCPxCON
CCPxCON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
CCPxCON
;Load CCPxCON with this
;value
CCPxM<3:0>
Mode Select
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
20.1.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
20.2
CCPx
Pin
Q
Compare Mode
The Compare mode function described in this section
is available and identical for CCP modules CCP1 and
CCP2.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
 2010-2016 Microchip Technology Inc.
S
R
Output
Logic
Match
Comparator
TMR1H
TRIS
Output Enable
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
TMR1L
Special Event Trigger
20.2.1
CCPX PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
The CCP2 pin function can be moved to alternate pins
using the APFCON register (Register 12-1). Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Note:
20.2.2
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 18.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
DS40001452F-page 163
PIC16(L)F1516/7/8/9
20.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
20.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an ADC conversion
(if the ADC module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
TABLE 20-2:
SPECIAL EVENT TRIGGER
Device
PIC16(L)F1516/7/8/9
CCPx
CCP2
Refer to Section 16.2.5 “Special Event Trigger” for
more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
20.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
20.2.6
ALTERNATE PIN LOCATIONS
20.3
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 20-3 shows a typical waveform of the PWM
signal.
20.3.1
STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
•
•
•
•
PR2 registers
T2CON registers
CCPRxL registers
CCPxCON registers
Figure 20-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function”for
more information.
DS40001452F-page 164
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 20-3:
CCP PWM OUTPUT SIGNAL
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
6.
Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below.
• Enable the CCPx pin output driver by clearing the associated TRIS bit.
Note:
TMR2 = 0
FIGURE 20-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers
20.3.3
20.3.4
CCPRxH(2) (Slave)
CCPx
R
Comparator
(1)
Q
S
PR2
Note 1:
2:
20.3.2
Clear Timer,
toggle CCPx pin and
latch duty cycle
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
two bits of the prescaler, to create the 10-bit
time base.
In PWM mode, CCPRxH is a read-only register.
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for standard PWM operation:
1.
2.
3.
4.
5.
Disable the CCPx pin output driver by setting the
associated TRIS bit.
Load the PR2 register with the PWM period
value.
Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
cycle value.
Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIRx register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
 2010-2016 Microchip Technology Inc.
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 20-1.
EQUATION 20-1:
TRIS
Comparator
TIMER2 TIMER RESOURCE
The PWM standard mode makes use of the 8-bit
Timer2 timer resources to specify the PWM period.
CCPRxL
TMR2
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
PWM PERIOD
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note 1:
TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
20.3.5
The Timer postscaler (see Section 19.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
DS40001452F-page 165
PIC16(L)F1516/7/8/9
Equation 20-2 is used to calculate the PWM pulse
width.
Equation 20-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 20-2:
20.3.6
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
PULSE WIDTH
Pulse Width =  CCPRxL:CCPxCON<5:4>  
T OSC  (TMR2 Prescale Value)
EQUATION 20-3:
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 20-4).
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 20-4.
DUTY CYCLE RATIO
EQUATION 20-4:
 CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = ----------------------------------------------------------------------4  PR2 + 1 
log  4  PR2 + 1  
Resolution = ------------------------------------------ bits
log  2 
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Note:
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
TABLE 20-3:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 20-4:
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
DS40001452F-page 166
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.3.7
OPERATION IN SLEEP MODE
20.3.10
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
20.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
20.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 20-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
CCP1CON
—
—
INTCON
DC1B<1:0>
CCP1M<3:0>
Register
on Page
105
168
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
78
PR2
T2CON
TMR2
TRISA
Timer2 Period Register
—
158*
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Timer2 Module Register
TRISA7
TRISA6
74
160
158
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
107
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 167
PIC16(L)F1516/7/8/9
20.4
Register Definitions: CCPx Control
REGISTER 20-1:
CCPxCON: CCPx CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode: toggle output on match
0011 = Reserved
0100 =
0101 =
0110 =
0111 =
Capture mode: every falling edge
Capture mode: every rising edge
Capture mode: every 4th rising edge
Capture mode: every 16th rising edge
1000 =
1001 =
1010 =
1011 =
Compare mode: set output on compare match (set CCPxIF)
Compare mode: clear output on compare match (set CCPxIF)
Compare mode: generate software interrupt only
Compare mode: the CCPxIF bit is set, CCPx pin is unaffected, CCPx resets TMR1
[Special Event Trigger also starts an ADC conversion if the ADC module is enabled and the
CCP module in Table 20-2 is selected (see Section 20.2.4, Special Event Trigger)]
11xx = PWM mode
DS40001452F-page 168
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
21.1
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
•
•
•
•
•
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
Figure 21-1 is a block diagram of the SPI interface
module.
FIGURE 21-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read
Write
SSPBUF Reg
SDI
SDO_out
SSPSR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SCK_out
SSPM<3:0>
4
SCK
Edge
Select
TRIS bit
 2010-2016 Microchip Technology Inc.
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPADD)
DS40001452F-page 169
PIC16(L)F1516/7/8/9
The I2C interface supports the following modes and
features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
Figure 21-2 is a block diagram of the I2C interface
module in Master mode. Figure 21-3 is a diagram of the
I2C interface module in Slave mode.
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus
Read
[SSPM<3:0>]
Write
SSPxBUF
Shift
Clock
SDA in
Receive Enable (RCEN)
SCL
SCL in
Bus Collision
DS40001452F-page 170
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPCON2)
Start bit detect,
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Clock Cntl
SSPSR
MSb
(Hold off clock source)
SDA
Baud rate
generator
(SSPADD)
Clock arbitrate/BCOL detect
FIGURE 21-2:
Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPCON2)
Set SSPIF, BCLIF
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 21-3:
MSSP BLOCK DIAGRAM (I2C SLAVE MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
21.2
SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a Chip Select known as Slave
Select.
The SPI bus specifies four signal connections:
•
•
•
•
Serial Clock (SCK)
Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 21-1 shows the block diagram of the MSSP
module when operating in SPI mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection is required from the master device to each
slave device.
Figure 21-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
 2010-2016 Microchip Technology Inc.
Set, Reset
S, P bits
(SSPSTAT Reg)
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 21-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected
to, and received by, the master's SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
DS40001452F-page 171
PIC16(L)F1516/7/8/9
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift
register (on its SDO pin) and the master device is
reading this bit and saving it as the LSb of its shift
register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
FIGURE 21-4:
• Master sends useful data and slave sends
dummy data.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must
disregard the clock and transmission signals and must
not transmit out any data of its own.
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDI
SDO
General I/O
General I/O
SS
General I/O
SCK
SDI
SDO
SPI Slave
#1
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
21.2.1
SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
•
•
•
•
•
•
MSSP STATUS register (SSPSTAT)
MSSP Control register 1 (SSPCON1)
MSSP Control register 3 (SSPCON3)
MSSP Data Buffer register (SSPBUF)
MSSP Address register (SSPADD)
MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower six bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
DS40001452F-page 172
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in
Section 21.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in
and out. SSPBUF provides indirect access to the
SSPSR register. SSPBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.2.2
SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of
the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the
SSPCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
FIGURE 21-5:
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full Detect bit, BF
of the SSPSTAT register, and the interrupt flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write
to
the
SSPBUF
register
during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the SSPBUF
register to complete successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
(BUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
SCK
General I/O
Processor 1
 2010-2016 Microchip Technology Inc.
SDO
Serial Clock
Slave Select
(optional)
Shift Register
(SSPSR)
MSb
LSb
SCK
SS
Processor 2
DS40001452F-page 173
PIC16(L)F1516/7/8/9
21.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 21-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 21-6, Figure 21-8, Figure 21-9 and
Figure 21-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
•
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 * TCY)
FOSC/64 (or 16 * TCY)
Timer2 output/2
Fosc/(4 * (SSPADD + 1))
Figure 21-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 21-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS40001452F-page 174
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.2.4
SPI SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up
from Sleep.
21.2.4.1
Daisy-Chain Configuration
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is connected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
Figure 21-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPCON3 register will enable writes
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
21.2.5
SLAVE SELECT
SYNCHRONIZATION
The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100).
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the
application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 175
PIC16(L)F1516/7/8/9
FIGURE 21-7:
SPI DAISY-CHAIN CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDI
SPI Slave
#1
SDO
General I/O
SS
SCK
SDI
SPI Slave
#2
SDO
SS
SCK
SDI
SPI Slave
#3
SDO
SS
FIGURE 21-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS40001452F-page 176
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 21-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 21-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 7
bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
 2010-2016 Microchip Technology Inc.
DS40001452F-page 177
PIC16(L)F1516/7/8/9
21.2.6
SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
TABLE 21-1:
Name
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
108
ANSELC
ANSC7
ANSC6
ANSC5
ANSC4
ANSC3
ANSC2
—
—
115
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
105
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
172*
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
216
SSPCON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
218
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
215
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
107
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
Legend:
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
DS40001452F-page 178
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.3
I2C MODE OVERVIEW
FIGURE 21-11:
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
VDD
SCL
The I2C bus specifies two signal connections:
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 21-1 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 21-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
 2010-2016 Microchip Technology Inc.
I2C MASTER/
SLAVE CONNECTION
SCL
VDD
Master
Slave
SDA
SDA
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while
the SCL line is held high.
In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I2C bus specifies three message protocols;
• Single message where a master writes data to a
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
DS40001452F-page 179
PIC16(L)F1516/7/8/9
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
21.3.1
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
21.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDA data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
DS40001452F-page 180
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins
arbitration. When two master devices send messages
to the same slave address, and addresses can
sometimes refer to multiple slaves, the arbitration
process must continue into the data stage.
21.4
I2C MODE OPERATION
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL,
are exercised by the module to communicate with
other external I2C devices.
21.4.1
BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an acknowledge value on the next clock pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
21.4.2
DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
21.4.3
SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Note: Data is tied to output zero when an I2C
mode is enabled.
21.4.4
SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.4.5
TABLE 21-1:
Term
I2C BUS TERMS
Description
START CONDITION
2
The I C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 21-12 shows wave
forms for Start and Stop conditions.
Transmitter
The device which shifts data out
onto the bus.
Receiver
The device which shifts data in
from the bus.
Master
The device that initiates a transfer,
generates clock signals and terminates a transfer.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification
that states no bus collision can occur on a Start.
Slave
The device addressed by the master.
21.4.6
Multi-master
A bus with more than one device
that can initiate data transfers.
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
Arbitration
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
Write Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is outputting and expected high state.
 2010-2016 Microchip Technology Inc.
STOP CONDITION
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
21.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 21-13 shows the wave form for a
Restart condition.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address
match fails.
21.4.8
START/STOP CONDITION
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.
DS40001452F-page 181
PIC16(L)F1516/7/8/9
I2C START AND STOP CONDITIONS
FIGURE 21-12:
SDA
SCL
S
Start
Condition
FIGURE 21-13:
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Condition
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
21.4.9
ACKNOWLEDGE SEQUENCE
I2C
The 9th SCL pulse for any transferred byte in
is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
Restart
Condition
Data Allowed
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the
SSPCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
DS40001452F-page 182
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.5
I2C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of four modes
selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop
condition.
21.5.1
SLAVE MODE ADDRESSES
21.5.2
SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF
register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON1 register
is set. The BOEN bit of the SSPCON3 register modifies
this operation. For more information see Register 21-6.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
The SSPADD register (Register 21-8) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the software that anything happened.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 21.2.3 “SPI Master Mode”
for more detail.
The SSP Mask register (Register 21-7) affects the
address matching process. See Section 21.5.9 “SSP
Mask Register” for more information.
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hardware or software and their effect on reception.
Figure 21-14 and Figure 21-15 is used as a visual
reference for this description.
21.5.1.1
I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
21.5.1.2
I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8
0’. A9 and A8 are the two MSb of the 10-bit address
and stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPADD. Even if there is not an address
match; SSPIF and UA are set, and SCL is held low
until SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
 2010-2016 Microchip Technology Inc.
21.5.2.1
7-bit Addressing Reception
This is a step by step process of what typically must
be done to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Start bit detected.
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears SSPIF.
Software reads the received byte from SSPBUF
clearing BF.
Steps 8-12 are repeated for all received bytes
from the master.
Master sends Stop condition, setting P bit of
SSPSTAT, and the bus goes idle.
DS40001452F-page 183
PIC16(L)F1516/7/8/9
21.5.2.2
7-bit Reception with AHEN and
DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I2C communication. Figure 21-16 displays a module using both
address and data holding. Figure 21-17 includes the
operation with the SEN bit of the SSPCON2 register
set.
1.
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSPIF.
4. Slave can look at the ACKTIM bit of the SSPCON3 register to determine if the SSPIF was
after or before the ACK.
5. Slave reads the address value from SSPBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPIF.
Note: SSPIF is still set after the 9th falling edge of
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to Master is SSPIF not set
11. SSPIF set and CKP cleared after 8th falling
edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSPCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
DS40001452F-page 184
 2010-2016 Microchip Technology Inc.
 2010-2016 Microchip Technology Inc.
SSPOV
BF
SSPIF
S
1
A7
2
A6
3
A5
4
A4
5
A3
Receiving Address
6
A2
7
A1
8
9
ACK
1
D7
2
D6
4
5
D3
6
D2
7
D1
SSPBUF is read
Cleared by software
3
D4
Receiving Data
D5
8
9
2
D6
First byte
of data is
available
in SSPBUF
1
D0 ACK D7
4
5
D3
6
D2
7
D1
SSPOV set because
SSPBUF is still full.
ACK is not sent.
Cleared by software
3
D4
Receiving Data
D5
8
D0
9
P
SSPIF set on 9th
falling edge of
SCL
ACK = 1
FIGURE 21-14:
SCL
SDA
From Slave to Master
Bus Master sends
Stop condition
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001452F-page 185
DS40001452F-page 186
CKP
SSPOV
BF
SSPIF
1
SCL
S
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
9
R/W=0 ACK
SEN
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
CKP is written to ‘1’ in software,
releasing SCL
SSPBUF is read
Cleared by software
Clock is held low until CKP is set to ‘1’
1
D7
Receive Data
9
ACK
SEN
3
D5
4
D4
5
D3
First byte
of data is
available
in SSPBUF
6
D2
7
D1
SSPOV set because
SSPBUF is still full.
ACK is not sent.
Cleared by software
2
D6
CKP is written to 1 in software,
releasing SCL
1
D7
Receive Data
8
D0
9
ACK
SCL is not held
low because
ACK= 1
SSPIF set on 9th
falling edge of SCL
P
FIGURE 21-15:
SDA
Receive Address
Bus Master sends
Stop condition
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2010-2016 Microchip Technology Inc.
 2010-2016 Microchip Technology Inc.
P
S
ACKTIM
CKP
ACKDT
BF
SSPIF
S
Receiving Address
1
3
5
6
7
8
ACK the received
byte
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPIF is set
4
ACKTIM set by hardware
on 8th falling edge of SCL
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
2
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
3
4
5
6
7
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPIF is set on
9th falling edge of
SCL, after ACK
1
8
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
1
2
4
5
6
ACKTIM set by hardware
on 8th falling edge of SCL
CKP set by software,
SCL is released
8
Slave software
sets ACKDT to
not ACK
7
Cleared by software
3
D7 D6 D5 D4 D3 D2 D1 D0
Data is read from SSPBUF
9
ACK
9
P
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 21-16:
SCL
SDA
Master Releases SDA
to slave for ACK sequence
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS40001452F-page 187
DS40001452F-page 188
P
S
ACKTIM
CKP
ACKDT
BF
SSPIF
S
Receiving Address
4
5
6 7
8
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Slave software clears
ACKDT to ACK
the received byte
Received
address is loaded into
SSPBUF
2 3
ACKTIM is set by hardware
on 8th falling edge of SCL
1
A7 A6 A5 A4 A3 A2 A1
9
ACK
Receive Data
2 3
4
5
6 7
8
ACKTIM is cleared by hardware
on 9th rising edge of SCL
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPBUF
Cleared by software
1
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Receive Data
1
3 4
5
6 7
8
Set by software,
release SCL
Slave sends
not ACK
SSPBUF can be
read any time before
next byte is loaded
2
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
CKP is not cleared
if not ACK
No interrupt after
if not ACK
from Slave
P
Master sends
Stop condition
FIGURE 21-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.5.3
SLAVE TRANSMISSION
21.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the 9th bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish a standard transmission.
Figure 21-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 21.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1.
The transmit data must be loaded into the SSPBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the 9th SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the 9th clock pulse.
21.5.3.1
Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPCON3 register is set, the
BCLIF bit of the PIR register is set. Once a bus collision
is detected, the slave goes idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
 2010-2016 Microchip Technology Inc.
Master sends a Start condition on SDA and
SCL.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPIF bit.
4. Slave hardware generates an ACK and sets
SSPIF.
5. SSPIF bit is cleared by user.
6. Software reads the received address from SSPBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
DS40001452F-page 189
DS40001452F-page 190
P
S
D/A
R/W
ACKSTAT
CKP
BF
SSPIF
S
1
2
5
6
7
Received address
is read from SSPBUF
4
Indicates an address
has been received
R/W is copied from the
matching address byte
When R/W is set
SCL is always
held low after 9th SCL
falling edge
3
8
9
Automatic
2
3
4
5
Set by software
Data to transmit is
loaded into SSPBUF
Cleared by software
1
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
2
3
4
5
7
8
CKP is not
held for not
ACK
6
Masters not ACK
is copied to
ACKSTAT
BF is automatically
cleared after 8th falling
edge of SCL
1
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data
9
ACK
P
FIGURE 21-18:
SCL
SDA
R/W = 1 Automatic
A7 A6 A5 A4 A3 A2 A1
ACK
Receiving Address
Master sends
Stop condition
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been
clocked in, CKP is cleared and the SSPIF interrupt is
set.
Figure 21-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1.
2.
Bus starts Idle.
Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is generated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit, releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 191
DS40001452F-page 192
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPIF
S
Receiving Address
2
4
5
6
7
8
Slave clears
ACKDT to ACK
address
ACKTIM is set on 8th falling
edge of SCL
9
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPBUF
3
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
1
A7 A6 A5 A4 A3 A2 A1
3
4
5
6
Cleared by software
2
Set by software,
releases SCL
Data to transmit is
loaded into SSPBUF
1
7
8
9
Transmitting Data
Automatic
D7 D6 D5 D4 D3 D2 D1 D0 ACK
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
1
3
4
5
6
7
after not ACK
CKP not cleared
Master’s ACK
response is copied
to SSPSTAT
BF is automatically
cleared after 8th falling
edge of SCL
2
8
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
P
Master sends
Stop condition
FIGURE 21-19:
SCL
SDA
Master releases SDA
to slave for ACK sequence
PIC16(L)F1516/7/8/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.5.4
SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Figure 21-20 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
Bus starts Idle.
Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
Slave sends ACK and SSPIF is set.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
Slave loads low address into SSPADD,
releasing SCL.
Master sends matching low address byte to the
slave; UA bit is set.
21.5.5
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 21-21 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 21-22 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
9.
Slave sends ACK and SSPIF is set.
Note: If the low address does not match, SSPIF
and UA are still set so that the slave software can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 193
DS40001452F-page 194
CKP
UA
BF
SSPIF
S
1
1
2
1
5
6
7
0 A9 A8
8
Set by hardware
on 9th falling edge
4
1
When UA = 1;
SCL is held low
If address matches
SSPADD it is loaded into
SSPBUF
3
1
Receive First Address Byte
9
ACK
1
3
4
5
6
7
8
Software updates SSPADD
and releases SCL
2
9
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receive Second Address Byte
1
3
4
5
6
7
8
9
1
3
4
5
6
7
Data is read
from SSPBUF
SCL is held low
while CKP = 0
2
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPBUF
Cleared by software
2
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Receive Data
P
FIGURE 21-20:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1516/7/8/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
 2010-2016 Microchip Technology Inc.
 2010-2016 Microchip Technology Inc.
ACKTIM
CKP
UA
ACKDT
BF
2
1
5
0
6
A9
7
A8
Set by hardware
on 9th falling edge
4
1
8
R/W = 0
ACKTIM is set by hardware
on 8th falling edge of SCL
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Slave software clears
ACKDT to ACK
the received byte
3
1
Receive First Address Byte
9
ACK
UA
2
3
A5
4
A4
6
A2
7
A1
Update to SSPADD is
not allowed until 9th
falling edge of SCL
SSPBUF can be
read anytime before
the next received byte
5
A3
Receive Second Address Byte
A6
Cleared by software
1
A7
8
A0
9
ACK
UA
2
D6
3
D5
4
D4
6
D2
Set CKP with software
releases SCL
7
D1
Update of SSPADD,
clears UA and releases
SCL
5
D3
Receive Data
Cleared by software
1
D7
8
9
2
Received data
is read from
SSPBUF
1
D6 D5
Receive Data
D0 ACK D7
FIGURE 21-21:
SSPIF
1
SCL
S
1
SDA
PIC16(L)F1516/7/8/9
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
DS40001452F-page 195
DS40001452F-page 196
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPIF
4
5
6
7
Set by hardware
3
Indicates an address
has been received
UA indicates SSPADD
must be updated
SSPBUF loaded
with received address
2
8
9
1
SCL
S
Receiving Address R/W = 0
1 1 1 1 0 A9 A8
ACK
1
3
4
5
6
7 8
After SSPADD is
updated, UA is cleared
and SCL is released
Cleared by software
2
9
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receiving Second Address Byte
1
4
5
6
7 8
Set by hardware
2 3
R/W is copied from the
matching address byte
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
High address is loaded
back into SSPADD
Received address is
read from SSPBUF
Sr
1 1 1 1 0 A9 A8
Receive First Address Byte
9
ACK
2
3
4
5
6
7
8
Masters not ACK
is copied
Set by software
releases SCL
Data to transmit is
loaded into SSPBUF
1
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data Byte
9
P
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 21-22:
SDA
Master sends
Restart event
PIC16(L)F1516/7/8/9
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.5.6
CLOCK STRETCHING
21.5.6.2
Clock stretching occurs when a device on the bus
holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more
time to handle data or prepare a response for the master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and handled by the hardware that generates SCL.
The CKP bit of the SSPCON1 register is used to control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
21.5.6.1
Normal Clock Stretching
Following an ACK if the R/W bit of SSPSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
FIGURE 21-23:
10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
21.5.6.3
Byte NACKing
When AHEN bit of SSPCON3 is set; CKP is cleared by
hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
21.5.7
CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 21-23).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX ‚ – 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPCON1
 2010-2016 Microchip Technology Inc.
DS40001452F-page 197
PIC16(L)F1516/7/8/9
21.5.8
GENERAL CALL ADDRESS
SUPPORT
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 21-24 shows a General Call reception
sequence.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
FIGURE 21-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
SCL
S
1
2
3
4
5
6
7
8
9
1
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SSPIF
BF (SSPSTAT<0>)
Cleared by software
GCEN (SSPCON2<7>)
SSPBUF is read
’1’
21.5.9
SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 21-7) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
DS40001452F-page 198
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PIC16(L)F1516/7/8/9
21.6
I2C MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I 2C bus may be taken when the P bit is set, or the
bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
•
•
•
•
•
Start condition detected
Stop condition detected
Data transfer byte transmitted/received
Acknowledge transmitted/received
Repeated Start generated
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queueing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur
21.6.1
I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 21.7 “Baud
Rate Generator” for more detail.
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 199
PIC16(L)F1516/7/8/9
21.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 21-25).
FIGURE 21-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX ‚ – 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
21.6.3
WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not idle.
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPCON2
is disabled until the Start condition is
complete.
DS40001452F-page 200
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PIC16(L)F1516/7/8/9
21.6.4
I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 21-26), the user
sets the Start Enable bit, SEN bit of the SSPCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT
register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by hardware; the
Baud Rate Generator is suspended, leaving the SDA
line held low and the Start condition is complete.
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already sampled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
2: The Philips I2C Specification states that a
bus collision cannot occur on a Start.
FIGURE 21-26:
FIRST START BIT TIMING
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
SDA
1st bit
2nd bit
TBRG
SCL
S
 2010-2016 Microchip Technology Inc.
TBRG
DS40001452F-page 201
PIC16(L)F1516/7/8/9
21.6.5
I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 21-27) occurs when
the RSEN bit of the SSPCON2 register is programmed
high and the master state machine is no longer active.
When the RSEN bit is set, the SCL pin is asserted low.
When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is
released (brought high) for one Baud Rate Generator
count (TBRG). When the Baud Rate Generator times
out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the
Baud Rate Generator is reloaded and begins counting.
SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the SSPCON2 register will be automatically cleared and the
Baud Rate Generator will not be reloaded, leaving the
SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
FIGURE 21-27:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
SCL
Sr
TBRG
Repeated Start
DS40001452F-page 202
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.6.6
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the 8th bit
is shifted out (the falling edge of the 8th clock), the BF
flag is cleared and the master releases SDA. This
allows the slave device being addressed to respond
with an ACK bit during the 9th bit time if an address
match occurred, or if data was received properly. The
status of ACK is written into the ACKSTAT bit on the rising edge of the 9th clock. If the master receives an
Acknowledge, the Acknowledge Status bit, ACKSTAT,
is cleared. If not, the bit is set. After the 9th clock, the
SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded
into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 21-28).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the 8th clock, the master will release
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the 9th clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the 9th clock
transmission of the address, the SSPIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float.
21.6.6.1
BF Status Flag
21.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
21.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Typical transmit sequence:
The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
SSPIF is set by hardware on completion of the
Start.
SSPIF is cleared by software.
The MSSP module will wait the required start
time before any other operation takes place.
The user loads the SSPBUF with the slave
address to transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
The MSSP module generates an interrupt at the
end of the 9th clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
Steps 8-11 are repeated for all transmitted data
bytes.
The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all eight bits are shifted out.
21.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 203
DS40001452F-page 204
S
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared by software
2
6
7
8
9
After Start condition, SEN cleared by hardware
SSPBUF written
1
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W
start transmit
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written by software
Cleared by software service routine
from SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From slave, clear ACKSTAT bit SSPCON2<6>
P
Cleared by software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 21-28:
SEN = 0
Write SSPCON2<0> SEN = 1
Start condition begins
PIC16(L)F1516/7/8/9
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.6.7
I2C MASTER MODE RECEPTION
Master mode reception (Figure 21-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSPCON2 register.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the 8th clock, the
receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
21.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
21.6.7.2
SSPOV Status Flag
21.6.7.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
13.
14.
21.6.7.3
15.
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
 2010-2016 Microchip Technology Inc.
Typical Receive Sequence:
The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
SSPIF is set by hardware on completion of the
Start.
SSPIF is cleared by software.
User writes SSPBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
The MSSP module generates an interrupt at the
end of the 9th clock cycle by setting the SSPIF
bit.
User sets the RCEN bit of the SSPCON2 register
and the master clocks in a byte from the slave.
After the 8th falling edge of SCL, SSPIF and BF
are set.
Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
Master sets ACK value sent to slave in ACKDT
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
Masters ACK is clocked out to the slave and
SSPIF is set.
User clears SSPIF.
Steps 8-13 are repeated for each received byte
from the slave.
Master sends a not ACK or Stop to end
communication.
DS40001452F-page 205
DS40001452F-page 206
RCEN
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
S
1
A7
2
4
5
6
Cleared by software
3
A6 A5 A4 A3 A2
Transmit Address to Slave
7
8
9
ACK
2
3
5
6
7
8
D0
9
ACK
2
3
4
RCEN cleared
automatically
5
6
7
Cleared by software
Set SSPIF interrupt
at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
1
ACK from Master
SDA = ACKDT = 0
Cleared in
software
Set SSPIF at end
of receive
9
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
SSPOV is set because
SSPBUF is still full
8
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1, start
next receive
ACK from Master
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared by software
Set SSPIF interrupt
at end of receive
4
Cleared by software
1
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
A1 R/W
ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
FIGURE 21-29:
SCL
SDA
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<0> (SEN = 1),
begin Start condition
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16(L)F1516/7/8/9
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.6.8
ACKNOWLEDGE SEQUENCE
TIMING
21.6.9
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the 9th clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 21-31).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 21-30).
21.6.8.1
21.6.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 21-30:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
ACK
D0
SCL
8
9
SSPIF
SSPIF set at
the end of receive
Cleared in
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 21-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 207
PIC16(L)F1516/7/8/9
21.6.10
SLEEP OPERATION
21.6.13
2
While in Sleep mode, the I C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
21.6.11
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
21.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 21-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 21-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
DS40001452F-page 208
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.6.13.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 21-33).
SCL is sampled low before SDA is asserted low
(Figure 21-34).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 21-35). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 21-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master
is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 21-33:
The reason that bus collision is not a factor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
S
SSPIF
SSPIF and BCLIF are
cleared by software
 2010-2016 Microchip Technology Inc.
DS40001452F-page 209
PIC16(L)F1516/7/8/9
FIGURE 21-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
’0’
’0’
SSPIF
’0’
’0’
FIGURE 21-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
SCL
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
S
SCL pulled low after BRG
time-out
SEN
BCLIF
Set SSPIF
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
DS40001452F-page 210
Interrupts cleared
by software
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.6.13.2
Bus Collision During a Repeated
Start Condition
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 21-36.
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
A low level is sampled on SDA when SCL goes
from low level to high level (Case 1).
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’ (Case 2).
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 21-37.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 21-36:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
S
’0’
SSPIF
’0’
FIGURE 21-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S
’0’
SSPIF
 2010-2016 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
21.6.13.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 21-38). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 21-39).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
FIGURE 21-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCLIF
SDA asserted low
SCL
PEN
BCLIF
P
’0’
SSPIF
’0’
FIGURE 21-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high,
set BCLIF
PEN
BCLIF
P
’0’
SSPIF
’0’
DS40001452F-page 212
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 21-2:
SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIE2
OSFIE
—
—
—
BCLIE
—
—
CCP2IE
76
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
PIR2
OSFIF
—
—
—
BCLIF
—
—
CCP2IF
78
SSPADD
ADD<7:0>
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1
219
172*
WCOL
SSPOV
SSPEN
CKP
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
217
SSPCON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
218
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
219
SSPMSK
SSPSTAT
TRISA
Legend:
*
SSPM<3:0>
216
SMP
CKE
D/A
P
S
R/W
UA
BF
215
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
107
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.
Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 213
PIC16(L)F1516/7/8/9
21.7
BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator
available for clock generation in both I2C and SPI
Master modes. The Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Register 21-8). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting
down.
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 21-2 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 21-1: BRG CLOCK FREQUENCY
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1   4 
An internal signal “Reload” in Figure 21-40 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 21-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPM<3:0>
Reload
SSPADD<7:0>
Reload
Control
SCL
SSPCLK
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 21-2:
Note 1:
MSSP CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
16 MHz
4 MHz
09h
400 kHz(1)
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
I2C
I2C
The
interface does not conform to the 400 kHz
specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS40001452F-page 214
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.8
Register Definitions: MSSP Control
REGISTER 21-3:
SSPSTAT: SSP STATUS REGISTER
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
 2010-2016 Microchip Technology Inc.
DS40001452F-page 215
PIC16(L)F1516/7/8/9
REGISTER 21-4:
SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Bit is set by hardware
C = User cleared
bit 7
WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSPADD values of 0, 1 or 2 are not supported for I2C mode.
SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.
DS40001452F-page 216
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 21-5:
SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
 2010-2016 Microchip Technology Inc.
DS40001452F-page 217
PIC16(L)F1516/7/8/9
REGISTER 21-6:
SSPCON3: SSP CONTROL REGISTER 3
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
DS40001452F-page 218
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 21-7:
R/W-1/1
SSPMSK: SSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 21-8:
R/W-0/0
SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address Byte:
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address Byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
ADD<7:1>: 7-bit address
bit 0
Not used: Unused in this mode. Bit state is a “don’t care”.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 219
PIC16(L)F1516/7/8/9
22.0
The EUSART module includes the following capabilities:
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
•
•
•
•
•
•
•
•
•
•
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Programmable clock polarity in synchronous
modes
• Sleep operation
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 22-1:
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 22-1 and Figure 22-2.
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
• • •
0
Pin Buffer
and Control
TRMT
SPEN
Transmit Shift Register (TSR)
TXEN
Baud Rate Generator
FOSC
TX9
n
BRG16
+1
SPBRGH
÷n
SPBRGL
DS40001452F-page 220
Multiplier
x4
x16 x64
SYNC
1 X 0 0
0
BRGH
X 1 1 0
0
BRG16
X 1 0 1
0
TX9D
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
RX/DT pin
Baud Rate Generator
Data
Recovery
FOSC
BRG16
+1
SPBRGH
SPBRGL
RSR Register
MSb
Pin Buffer
and Control
Multiplier
x4
x16 x64
SYNC
1 X 0 0
0
BRGH
X 1 1 0
0
BRG16
X 1 0 1
0
Stop
RCIDL
OERR
(8)
•••
7
1
LSb
0 Start
RX9
÷n
n
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 22-1,
Register 22-2 and Register 22-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 221
PIC16(L)F1516/7/8/9
22.1
EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive
standard baud rate frequencies from the system
oscillator. See Table 22-4 for examples of baud rate
configurations.
22.1.1.2
Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
22.1.1.3
Transmit Data Polarity
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the 9th data
bit.
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit Idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true Idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 22.5.1.2
“Clock Polarity”.
22.1.1
22.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 22-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
22.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag
bit is not cleared immediately upon writing TXREG.
TXIF becomes valid in the second instruction cycle
following the write execution. Polling TXIF immediately
following the TXREG write will return invalid results. The
TXIF bit is read-only, it cannot be set or cleared by
software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
Note 1: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
DS40001452F-page 222
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22.1.1.5
TSR Status
22.1.1.7
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
Note:
22.1.1.6
1.
2.
3.
The TSR register is not mapped in data
memory, so it is not available to the user.
4.
5.
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the 9th,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eight Least Significant bits into the TXREG. All nine
bits of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 22.1.2.7 “Address
Detection” for more information on the address mode.
FIGURE 22-3:
Write to TXREG
BRG Output
(Shift Clock)
8.
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
FIGURE 22-4:
7.
Initialize the SPBRGH, SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 22.4 “EUSART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9 control bit. A set 9th data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
Set SCKP bit if inverted transmit is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the 9th bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
ASYNCHRONOUS TRANSMISSION
TX/CK
pin
TRMT bit
(Transmit Shift
Reg. Empty Flag)
6.
Asynchronous Transmission Setup:
1 TCY
Word 1
Transmit Shift Reg.
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
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TABLE 22-1:
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
232
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
231
Name
BAUDCON
INTCON
RCSTA
SPBRGL
BRG<7:0>
233*
SPBRGH
BRG<15:8>
233*
TRISC
TXREG
TXSTA
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
EUSART Transmit Data Register
CSRC
TX9
TXEN
114
222*
SYNC
SENDB
BRGH
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
DS40001452F-page 224
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.1.2
EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 22-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
22.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input.
Note 1: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
22.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 22.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
Note:
22.1.2.3
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 22.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
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22.1.2.4
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
22.1.2.5
22.1.2.7
Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the 9th data bit set will be transferred to the receive
FIFO buffer, thereby setting the RCIF interrupt bit. All
other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
22.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
9th and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from
the receive FIFO buffer, the RX9D data bit must be
read before reading the eight Least Significant bits from
the RCREG.
DS40001452F-page 226
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.1.2.8
Asynchronous Reception Setup:
22.1.2.9
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the 9th
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 22-5:
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the 9th bit set is transferred from
the RSR to the receive buffer. An interrupt will be
generated if the RCIE interrupt enable bit was
also set.
9. Read the RCSTA register to get the error flags.
The 9th data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
9-bit Address Detection Mode Setup
bit 1
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
bit 7/8 Stop
bit
Start
bit
Word 1
RCREG
bit 0
bit 7/8 Stop
bit
Start
bit
bit 7/8 Stop
bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
 2010-2016 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
TABLE 22-2:
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
232
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
Name
BAUDCON
INTCON
RCREG
RCSTA
EUSART Receive Data Register
SPEN
RX9
SREN
SPBRGL
CREN
ADDEN
FERR
OERR
RX9D
BRG<7:0>
SPBRGH
TRISC
TRISC7
TRISC6
TXSTA
CSRC
TX9
TXEN
231
233*
BRG<15:8>
TRISC5
77
225*
233*
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
SYNC
SENDB
BRGH
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.
DS40001452F-page 228
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.2
Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate.
The Auto-Baud Detect feature (see Section 22.4.1,
Auto-Baud Detect) can be used to compensate for
changes in the INTOSC frequency.
There may not be fine enough resolution when
adjusting the Baud Rate Generator to compensate for
a gradual change in the peripheral clock frequency.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 229
PIC16(L)F1516/7/8/9
22.3
Register Definitions: EUSART Control
REGISTER 22-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
SREN/CREN overrides TXEN in Sync mode.
DS40001452F-page 230
 2010-2016 Microchip Technology Inc.
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REGISTER 22-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and 9th bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
 2010-2016 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
REGISTER 22-3:
BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
Unimplemented: Read as ‘0’
bit 4
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Transmit data changes on the falling edge of the clock. Received data is sampled on the rising
edge of the clock.
0 = Transmit data changes on the rising edge of the clock. Received data is sampled on the falling
edge of the clock.
bit 3
BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2
Unimplemented: Read as ‘0’
bit 1
WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, RCIF bit will be set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS40001452F-page 232
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.4
EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH, SPBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 22-4 contains the formulas for determining the
baud rate. Example 22-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for user’s
convenience and are shown in Table 22-4. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
EXAMPLE 22-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
F OS C
Desired Baud Rate = -----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1 
Solving for SPBRGH:SPBRGL:
FOSC
--------------------------------------------Desired Baud Rate
X = --------------------------------------------- – 1
64
16000000
-----------------------9600
= ------------------------ – 1
64
=  25.042  = 25
16000000
Calculated Baud Rate = --------------------------64  25 + 1 
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
 9615 – 9600 
= ---------------------------------- = 0.16%
9600
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 233
PIC16(L)F1516/7/8/9
TABLE 22-4:
BAUD RATE FORMULAS
Configuration Bits
SYNC
BRG16
BRGH
BRG/EUSART Mode
Baud Rate Formula
FOSC/[64 (n+1)]
0
0
0
8-bit/Asynchronous
0
0
1
8-bit/Asynchronous
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair.
TABLE 22-3:
Name
BAUDCON
RCSTA
SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ABDOVF
RCIDL
—
SCKP
BRG16
SPEN
RX9
SREN
CREN
ADDEN
Bit 1
Bit 0
Register
on Page
—
WUE
ABDEN
232
FERR
OERR
RX9D
231
Bit 2
SPBRGL
BRG<7:0>
233*
SPBRGH
BRG<15:8>
233*
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001452F-page 234
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 22-4:
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
—
1221
—
1.73
—
255
—
1200
—
0.00
—
239
—
1202
—
0.16
—
207
—
1200
—
0.00
—
143
2400
2404
0.16
129
2400
0.00
119
2404
0.16
103
2400
0.00
71
9600
9470
-1.36
32
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
29
10286
-1.26
27
10417
0.00
23
10165
-2.42
16
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
8
57.6k
—
—
—
—
—
—
57.60k
—
0.00
7
—
—
—
—
—
—
57.60k
—
0.00
2
—
—
115.2k
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
—
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
—
1202
—
0.16
—
103
300
1202
0.16
0.16
207
51
300
1200
0.00
191
47
300
1202
0.16
0.16
51
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
—
—
—
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
0.00
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9615
0.16
12
—
—
—
9600
0.00
5
—
—
—
10417
10417
0.00
11
10417
0.00
5
—
—
—
—
—
—
19.2k
—
—
—
—
—
—
19.20k
0.00
2
—
—
—
57.6k
—
—
—
—
—
—
0
—
—
—
115.2k
—
—
—
—
—
—
57.60k
—
0.00
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
300
1200
FOSC = 20.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 16.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9600
—
0.00
—
71
2400
—
—
—
—
—
—
—
—
—
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.82k
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.64k
-1.36
10
115.2k
0.00
9
111.1k
-3.55
8
115.2k
0.00
5
 2010-2016 Microchip Technology Inc.
DS40001452F-page 235
PIC16(L)F1516/7/8/9
TABLE 22-4:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 4.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 3.6864 MHz
Actual
Rate
FOSC = 1.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
—
—
—
—
—
—
—
1202
—
0.16
—
207
—
1200
—
0.00
—
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
—
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
-0.01
-0.03
4166
1041
300.0
1200
0.00
0.00
3839
959
300.03
1200.5
0.01
0.04
3332
832
300.0
1200
0.00
0.00
2303
575
2400
2399
-0.03
520
2400
0.00
479
2398
-0.08
416
2400
0.00
287
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.818
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.636
-1.36
10
115.2k
0.00
9
111.11k
-3.55
8
115.2k
0.00
5
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
299.9
1199
-0.02
-0.08
1666
416
300.1
1202
0.04
0.16
832
207
300.0
1200
0.00
0.00
767
191
300.5
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
DS40001452F-page 236
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 22-4:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 16.000 MHz
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200.1
0.00
0.01
13332
3332
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.02
2082
2400
0.00
1919
2399.5
-0.02
1666
2400
0.00
1151
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9597
-0.03
520
9600
0.00
479
9592
-0.08
416
9600
0.00
287
10417
10417
0.00
479
10425
0.08
441
10417
0.00
383
10433
0.16
264
19.2k
19.23k
0.16
259
19.20k
0.00
239
19.23k
0.16
207
19.20k
0.00
143
57.6k
57.47k
-0.22
86
57.60k
0.00
79
57.97k
0.64
68
57.60k
0.00
47
115.2k
116.3k
0.94
42
115.2k
0.00
39
114.29k
-0.79
34
115.2k
0.00
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
-0.02
6666
1666
300.0
1200
0.01
0.04
3332
832
300.0
1200
0.00
0.00
3071
767
300.1
1202
0.04
0.16
832
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
0
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
—
—
—
115.2k
117.6k
2.12
16
111.1k
-3.55
8
115.2k
0.00
7
—
—
—
 2010-2016 Microchip Technology Inc.
DS40001452F-page 237
PIC16(L)F1516/7/8/9
22.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 22.4.3 “Auto-Wake-up on
Break”).
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 22-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table . The fifth rising edge will occur on the RX pin at
the end of the 8th bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRGL
register pair.
TABLE 22-5:
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table . During ABD, both
the SPBRGH and SPBRGL registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
FIGURE 22-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
FOSC/64
FOSC/512
0
1
FOSC/16
FOSC/128
1
0
FOSC/16
FOSC/128
1
FOSC/4
FOSC/32
1
Note:
During the ABD sequence, SPBRGL and
SPBRGH registers are both used as a
16-bit counter, independent of BRG16
setting.
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
BRG Value
BRG COUNTER CLOCK RATES
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto-Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001452F-page 238
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.4.2
AUTO-BAUD OVERFLOW
22.4.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDxCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPxBRGH:SPxBRGL
register pair. The overflow condition will set the RCIF
flag. The counter continues to count until the fifth rising
edge is detected on the RX pin. The RCIDL bit will
remain false ('0') until the fifth rising edge at which time
the RCIDL bit will be set. If the RCREG is read after the
overflow occurs but before the fifth rising edge then the
fifth rising edge will set the RCIF again.
Break Character
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
sync character fifth rising edge. If any falling edges of
the sync character have not yet occurred when the
ABDEN bit is cleared then those will be falsely detected
as Start bits. The following steps are recommended to
clear the overflow condition:
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
1.
2.
3.
Read RCREG to clear RCIF
If RCIDL is zero then wait for RCIF and repeat
step 1.
Clear the ABDOVF bit.
22.4.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the baud rate generator is
inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
To avoid character errors or character fragments
during a wake-up event, the wake-up character must
be all zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS mode). The Sync Break (or
wake-up signal) character must be of sufficient length,
and be followed by a sufficient interval, to allow enough
time for the selected oscillator to start and provide
proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 22-7), and asynchronously if
the device is in Sleep mode (Figure 22-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 239
PIC16(L)F1516/7/8/9
FIGURE 22-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto-Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Note 1:
Cleared due to User Read of RCREG
The EUSART remains in Idle while the WUE bit is set.
FIGURE 22-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto-Cleared
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
Cleared due to User Read of RCREG
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001452F-page 240
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.4.4
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 22-9 for the timing of
the Break character sequence.
22.4.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1.
2.
3.
4.
5.
22.4.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 22.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to enable the
Break sequence.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
FIGURE 22-9:
Write to TXREG
SEND BREAK CHARACTER SEQUENCE
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
 2010-2016 Microchip Technology Inc.
SENDB Sampled Here
Auto Cleared
DS40001452F-page 241
PIC16(L)F1516/7/8/9
22.5
EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and
transmit shift registers. Since the data line is
bidirectional, synchronous operation is half-duplex
only. Half-duplex refers to the fact that master and
slave devices can receive and transmit data but not
both simultaneously. The EUSART can operate as
either a master or slave device.
Start and Stop bits are not used in synchronous
transmissions.
22.5.1
SYNCHRONOUS MASTER MODE
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
22.5.1.3
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the previous character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character commences immediately following the transfer of the data
to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
22.5.1.4
Synchronous Master Transmission
Setup:
The following bits are used to configure the EUSART
for synchronous master operation:
•
•
•
•
•
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
22.5.1.1
22.5.1.2
1.
2.
3.
4.
5.
6.
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device
configured as a master transmits the clock on the
TX/CK line. The TX/CK pin output driver is
automatically enabled when the EUSART is configured
for synchronous transmit or receive operation. Serial
data bits change on the leading edge to ensure they
are valid at the trailing edge of each clock. One clock
cycle is generated for each data bit. Only as many
clock cycles are generated as there are data bits.
Synchronous Master Transmission
7.
8.
Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Disable Receive mode by clearing bits SREN
and CREN.
Enable Transmit mode by setting the TXEN bit.
If 9-bit transmission is desired, set the TX9 bit.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is selected, the 9th bit
should be loaded in the TX9D bit.
Start transmission by loading data to the
TXREG register.
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
DS40001452F-page 242
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
Note:
‘1’
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 22-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 22-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Bit 7
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
INTCON
RCSTA
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
—
WUE
ABDEN
232
IOCIE
TMR0IF
INTF
IOCIF
74
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
CREN
ADDEN
FERR
OERR
RX9D
231
Bit 5
Bit 4
Bit 3
RCIDL
—
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
SPEN
RX9
SREN
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TRISC
TRISC7
TRISC6
TXREG
TXSTA
Legend:
*
TRISC5
TRISC4
TRISC3
233*
233*
TRISC2
TRISC1
TRISC0
EUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
114
222*
TRMT
TX9D
230
— = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 243
PIC16(L)F1516/7/8/9
22.5.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
Note:
22.5.1.6
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
Note:
22.5.1.7
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be
cleared.
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
22.5.1.8
Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
9th, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
22.5.1.9
Synchronous Master Reception
Setup:
1.
Initialize the SPBRGH, SPBRGL register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
DS40001452F-page 244
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 22-6:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
232
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
SPEN
RX9
SREN
OERR
RX9D
Name
BAUDCON
INTCON
RCREG
RCSTA
EUSART Receive Data Register
CREN
ADDEN
FERR
225*
231
SPBRGL
BRG<7:0>
233*
SPBRGH
BRG<15:8>
233*
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 245
PIC16(L)F1516/7/8/9
22.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
•
•
•
•
•
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
22.5.2.1
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
5.
22.5.2.2
1.
EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
Section 22.5.1.3
modes
are
identical
(see
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
2.
3.
4.
5.
6.
7.
8.
TABLE 22-7:
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Synchronous Slave Transmission
Setup:
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start transmission by writing the Least
Significant 8 bits to the TXREG register.
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
232
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
231
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
Name
BAUDCON
INTCON
TXREG
TXSTA
EUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
222*
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
DS40001452F-page 246
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.5.2.3
EUSART Synchronous Slave
Reception
22.5.2.4
The operation of the Synchronous Master and Slave
modes is identical (Section 22.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
1.
2.
3.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
4.
5.
6.
7.
8.
9.
TABLE 22-8:
Name
Bit 6
ABDOVF
GIE
PIE1
PIR1
BAUDCON
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Bit 7
INTCON
Synchronous Slave Reception
Setup:
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
—
WUE
ABDEN
232
IOCIE
TMR0IF
INTF
IOCIF
74
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
75
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
77
Bit 5
Bit 4
Bit 3
RCIDL
—
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE
RCIE
TMR1GIF
ADIF
RCIF
RCREG
EUSART Receive Data Register
225*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
231
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
114
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
230
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 247
PIC16(L)F1516/7/8/9
22.6
EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
22.6.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 22.5.2.4 “Synchronous Slave
Reception Setup:”).
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by
reading RCREG to unload any pending
characters in the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
22.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for synchronous slave transmission
(see Section 22.5.2.2 “Synchronous Slave
Transmission Setup:”).
• The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON register.
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
DS40001452F-page 248
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
23.0
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the program memory, user IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC16(L)F151X/152X Memory
Programming Specification”, (DS41442).
23.1
High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
23.2
Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1.
2.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
23.3
Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 23-1.
FIGURE 23-1:
VDD
ICD RJ-11 STYLE
CONNECTOR INTERFACE
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VPP/MCLR
VSS
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 23-2.
For additional interface recommendations, refer to the
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 23-3 for more
information.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 249
PIC16(L)F1516/7/8/9
FIGURE 23-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
*
FIGURE 23-3:
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
DS40001452F-page 250
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
24.0
INSTRUCTION SET SUMMARY
Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The
opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most
varied instruction word format.
Table lists the instructions recognized by the
MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of four oscillator cycles;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
24.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 24-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
TABLE 24-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
Program Counter
TO
Time-out bit
C
DC
Z
PD
 2010-2016 Microchip Technology Inc.
Description
Carry bit
Digit carry bit
Zero bit
Power-down bit
DS40001452F-page 251
PIC16(L)F1516/7/8/9
FIGURE 24-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
OPCODE
8
7
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLP instruction only
13
OPCODE
7
6
0
k (literal)
k = 7-bit immediate value
MOVLB instruction only
13
OPCODE
5 4
0
k (literal)
k = 5-bit immediate value
BRA instruction only
13
OPCODE
9
8
0
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
OPCODE
7
6
n
5
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
3
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001452F-page 252
 2010-2016 Microchip Technology Inc.
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TABLE 24-3:
INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE-ORIENTED SKIP OPERATIONS
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff
1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
1, 2
1, 2
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 253
PIC16(L)F1516/7/8/9
TABLE 24-3:
INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
INHERENT OPERATIONS
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
0000 0110 0100 TO, PD
Clear Watchdog Timer
1
00
0000 0000 0000
No Operation
1
00
0000 0110 0010
Load OPTION_REG register with W
1
00
0000 0000 0001
Software device Reset
1
00
0000 0110 0011 TO, PD
Go into Standby mode
1
00
0000 0110 0fff
Load TRIS register with W
1
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
11 0001 0nkk kkkk
1
2, 3
00 0000 0001 0nmm Z
MOVIW
n mm
Move Indirect FSRn to W with pre/post inc/dec 1
modifier, mm
k[n]
2
11 1111 0nkk kkkk Z
Move INDFn to W, Indexed Indirect.
1
MOVWI
n mm
2, 3
00 0000 0001 1nmm
Move W to Indirect FSRn with pre/post inc/dec 1
modifier, mm
k[n]
2
11 1111 1nkk kkkk
Move W to INDFn, Indexed Indirect.
1
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS40001452F-page 254
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
24.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32  k  31
n  [ 0, 1]
Operands:
0  k  255
Operation:
(W) .AND. (k)  (W)
Operation:
FSR(n) + k  FSR(n)
Status Affected:
Z
Status Affected:
None
Description:
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
AND W with f
k
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
Add literal and W
ANDWF
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0  f  127
d 0,1
Operation:
(W) .AND. (f)  (destination)
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
k
Operands:
0  k  255
Operation:
(W) + k  (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
ADDWF
Add W and f
f,d
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0  f  127
d 0,1
Operands:
0  f  127
d [0,1]
Operation:
(W) + (f)  (destination)
Operation:
(f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
f,d
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0  f  127
d [0,1]
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
register f
C
f {,d}
Operation:
(W) + (f) + (C)  dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
 2010-2016 Microchip Technology Inc.
f {,d}
DS40001452F-page 255
PIC16(L)F1516/7/8/9
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0  f  127
0b7
Operands:
0  f  127
0b7
Operands:
Operation:
0  (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
0  f  127
0b<7
Operands:
-256  label - PC + 1  255
-256  k  255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a 2-cycle instruction. This branch has a limited range.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W)  PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to
the PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a 2-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0  f  127
0b7
Operation:
1  (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
DS40001452F-page 256
f,b
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0  k  2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k  PC<10:0>,
(PCLATH<6:3>)  PC<14:11>
Operation:
Status Affected:
None
00h  WDT
0  WDT prescaler,
1  TO
1  PD
Description:
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The 11-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a 2-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
Subroutine Call With W
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1  TOS,
(W)  PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0  f  127
d  [0,1]
Operation:
(f)  (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Status Affected:
None
Description:
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
f
f,d
Operands:
0  f  127
Operands:
Operation:
00h  (f)
1Z
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are cleared
and the Z bit is set.
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h  (W)
1Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 257
PIC16(L)F1516/7/8/9
DECFSZ
Decrement f, Skip if 0
INCFSZ
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination);
skip if result = 0
Operation:
(f) + 1  (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
Increment f, Skip if 0
INCFSZ f,d
IORLW k
Operands:
0  k  2047
Operands:
0  k  255
Operation:
k  PC<10:0>
PCLATH<6:3>  PC<14:11>
Operation:
(W) .OR. k  (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) + 1  (destination)
Operation:
(W) .OR. (f)  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Description:
Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
DS40001452F-page 258
INCF f,d
IORWF
f,d
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
LSLF
Logical Left Shift
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0  f  127
d [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f<7>)  C
(f<6:0>)  dest<7:1>
0  dest<0>
Operation:
(f)  (dest)
f {,d}
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
C
register f
0
Z
Description:
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Words:
1
Cycles:
1
Logical Right Shift
Syntax:
[ label ] LSRF
Operands:
0  f  127
d [0,1]
Operation:
0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
f {,d}
 2010-2016 Microchip Technology Inc.
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
register f
MOVF f,d
Status Affected:
Example:
0
Move f
C
DS40001452F-page 259
PIC16(L)F1516/7/8/9
MOVIW
Move INDFn to W
MOVLP
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP k
Operands:
0  k  127
Operation:
k  PCLATH
Status Affected:
None
Operands:
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Description:
The 7-bit literal ‘k’ is loaded into the
PCLATH register.
Operation:
INDFn  W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
Status Affected:
MOVLW
Move literal to W
Syntax:
[ label ]
0  k  255
Operation:
k  (W)
Status Affected:
None
Description:
The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as
‘0’s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB k
Operands:
0  k  31
Operation:
k  BSR
Status Affected:
None
Description:
The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS40001452F-page 260
MOVLW k
Operands:
Z
Predecrement
Move literal to PCLATH
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0  f  127
Operation:
(W)  (f)
0x5A
f
Status Affected:
None
Description:
Move data from W register to register
‘f’.
Words:
1
Cycles:
1
Example:
MOVWF
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn]
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
n  [0,1]
mm  [00,01, 10, 11]
-32  k  31
Description:
No operation.
Words:
1
Cycles:
1
Operands:
Operation:
Status Affected:
W  INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
None
NOP
OPTION
Load OPTION_REG Register
with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)  OPTION_REG
Status Affected:
None
Description:
Move data from W register to
OPTION_REG register.
1
Mode
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Words:
Postdecrement
FSRn--
11
Cycles:
1
Example:
OPTION
Description:
mm
Example:
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
 2010-2016 Microchip Technology Inc.
NOP
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the
RI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to
execute a hardware Reset by software.
DS40001452F-page 261
PIC16(L)F1516/7/8/9
RETFIE
Return from Interrupt
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE
RETURN
Operands:
None
Operands:
Operation:
TOS  PC,
1  GIE
Operation:
TOS  PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.
Words:
1
Cycles:
2
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Return with literal in W
Syntax:
[ label ]
Operands:
0  k  255
Operation:
k  (W);
TOS  PC
Status Affected:
None
Description:
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
Words:
1
Cycles:
2
Example:
TABLE
RETLW k
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Operands:
0  f  127
d  [ 0, 1]
Operation:
See description below
Status Affected:
C
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
RLF
C
CALL TABLE;W contains table
;offset value
•
;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W =
After Instruction
W =
DS40001452F-page 262
Words:
1
Cycles:
1
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
SUBLW
Subtract W from literal
Syntax:
[ label ]
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
See description below
Status Affected:
C, DC, Z
Status Affected:
C
Description:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
The W register is subtracted (2’s complement method) from the 8-bit literal
‘k’. The result is placed in the W register.
RRF f,d
C
SUBLW k
Operands:
0 k 255
Operation:
k - (W) W)
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0>  k<3:0>
DC = 1
W<3:0>  k<3:0>
SLEEP
Enter Sleep mode
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d  [0,1]
SLEEP
Operands:
None
Operation:
00h  WDT,
0  WDT prescaler,
1  TO,
0  PD
Status Affected:
TO, PD
Description:
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
 2010-2016 Microchip Technology Inc.
SUBWF f,d
Operation:
(f) - (W) destination)
Status Affected:
C, DC, Z
Description:
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
C=0
Wf
C=1
Wf
DC = 0
W<3:0>  f<3:0>
DC = 1
W<3:0>  f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
0  f  127
d  [0,1]
Operation:
(f) – (W) – (B) dest
f {,d}
Status Affected:
C, DC, Z
Description:
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DS40001452F-page 263
PIC16(L)F1516/7/8/9
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operation:
SWAPF f,d
(f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Status Affected:
None
Description:
The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS
Load TRIS Register with W
Syntax:
[ label ] TRIS f
XORLW k
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Z
Description:
The contents of the W register are
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
XORWF
f,d
(W) .XOR. (f) destination)
Operands:
5f7
Operation:
(W)  TRIS register ‘f’
Operation:
Status Affected:
None
Status Affected:
Z
Description:
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Description:
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in register ‘f’.
DS40001452F-page 264
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.0
ELECTRICAL SPECIFICATIONS
25.1
Absolute Maximum Ratings(†)
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F1516/7/8/9 .................................................................... -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC16LF1516/7/8/9 .................................................................. -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(2) ............................................................................................................................... 800 mW
Maximum current
on VSS pin for 28-Pin devices(1)
-40°C  TA  +85°C .......................................................................................................................... 350 mA
+85°C  TA  +125°C........................................................................................................................ 120 mA
on VDD pin for 28-Pin devices(1)
-40°C  TA  +85°C ........................................................................................................................ 250 mA
+85°C  TA  +125°C........................................................................................................................ 85 mA
on VSS pin for 40/44-Pin devices(1)
-40°C  TA  +85°C ........................................................................................................................ 350 mA
+85°C  TA  +125°C...................................................................................................................... 120 mA
on VDD pin for 40/44-Pin devices(1)
-40°C  TA  +85°C ........................................................................................................................ 350 mA
+85°C  TA  +125°C...................................................................................................................... 120 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 50 mA
Maximum output current sourced by any I/O pin .............................................................................................. 50 mA
Note 1:
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 25-5 to calculate device
specifications.
Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x
IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 265
PIC16(L)F1516/7/8/9
25.2
Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF1516/7/8/9
VDDMIN (FOSC  16 MHz) ......................................................................................................... +1.8V
VDDMIN (16 MHz FOSC  20 MHz).......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F1516/7/8/9
VDDMIN (FOSC  16 MHz) ......................................................................................................... +2.3V
VDDMIN (16 MHz FOSC  20 MHz).......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1:
See Parameter D001, DC Characteristics: Supply Voltage.
DS40001452F-page 266
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
PIC16F1516/7/8/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
FIGURE 25-1:
VDD (V)
5.5
2.5
2.3
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
PIC16LF1516/7/8/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
VDD (V)
FIGURE 25-2:
3.6
2.5
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 267
PIC16(L)F1516/7/8/9
FIGURE 25-3:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
-15% to +12.5%
Temperature (°C)
85
60
± 8%
25
± 6.5%
0
-20
-40
1.8
-15% to +12.5%
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001452F-page 268
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.3
DC Characteristics: Supply Voltage
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param.
No.
D001
Sym.
VDD
Characteristic
VDR
Typ†
Max.
Units
Conditions
1.8
2.5
—
—
3.6
3.6
V
V
FOSC  16 MHz:
FOSC  20 MHz
2.3
2.5
—
—
5.5
5.5
V
V
FOSC  16 MHz:
FOSC  20 MHz
Supply Voltage (VDDMIN, VDDMAX)
D001
D002*
Min.
RAM Data Retention Voltage(1)
D002*
D002A* VPOR
Power-on Reset Release Voltage
D002B* VPORR
Power-on Reset Rearm Voltage
D002B*
D003
VADFVR
Fixed Voltage Reference Voltage for
ADC
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
1.5
—
—
V
Device in Sleep mode
1.7
—
—
V
Device in Sleep mode
—
1.6
—
V
V
—
0.8
—
—
1.42
—
V
-8
—
6
%
0.05
—
—
V/ms
1.024V, VDD  2.5V
2.048V, VDD  2.5V
4.096V, VDD  4.75V
See Section 6.1 “Power-On Reset
(POR)” for details.
*
†
Note
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 269
PIC16(L)F1516/7/8/9
FIGURE 25-4:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS40001452F-page 270
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.4
DC Characteristics: Supply Current (IDD)
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
Note
VDD
Supply Current (IDD)(1, 2, 3)
—
8.0
14
A
1.8
—
12.0
31
A
3.0
—
11
28
A
2.3
—
13
38
A
3.0
—
14
45
A
5.0
—
60
95
A
1.8
—
110
180
A
3.0
—
92
170
A
2.3
—
140
230
A
3.0
—
170
350
A
5.0
D012
—
150
240
A
1.8
—
260
430
A
3.0
D012
—
190
450
A
2.3
—
310
500
A
3.0
—
370
650
A
5.0
—
25
31
A
1.8
—
35
50
A
3.0
—
25
40
A
2.3
—
35
55
A
3.0
—
40
60
A
5.0
—
120
210
A
1.8
—
210
380
A
3.0
—
160
250
A
2.3
—
260
380
A
3.0
—
330
480
A
5.0
D010
D010
D011
D011
D013
D013
D014
D014
*
†
Note 1:
2:
3:
4:
FOSC = 32 kHz
LP Oscillator
-40°C  TA  +85°C
FOSC = 32 kHz
LP Oscillator
-40°C  TA  +85°C
FOSC = 1 MHz
XT Oscillator
FOSC = 1 MHz
XT Oscillator
FOSC = 4 MHz
XT Oscillator
FOSC = 4 MHz
XT Oscillator
FOSC = 500 kHz
EC Oscillator
Low-Power mode
FOSC = 500 kHz
EC Oscillator
Low-Power mode
FOSC = 4 MHz
EC Oscillator
Medium-Power mode
FOSC = 4 MHz
EC Oscillator
Medium-Power mode
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
0.1 F capacitor on VCAP pin, PIC16F1516/7/8/9 only.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 271
PIC16(L)F1516/7/8/9
25.4
DC Characteristics: Supply Current (IDD) (Continued)
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
VDD
Note
Supply Current (IDD)(1, 2, 3)
D014A
—
1.0
1.5
mA
3.0
—
1.2
2.0
mA
3.6
—
1.4
1.5
mA
3.0
—
1.7
2.0
mA
5.0
—
5.0
12
A
1.8
—
10
31
A
3.0
—
18
25
A
2.3
—
24
35
A
3.0
—
25
40
A
5.0
—
110
380
A
1.8
—
150
400
A
3.0
—
150
330
A
2.3
—
210
360
A
3.0
—
335
400
A
5.0
D017
—
0.41
0.90
mA
1.8
—
0.70
1.00
mA
3.0
D017
—
0.35
0.75
mA
2.3
—
0.69
1.00
mA
3.0
—
0.75
1.10
mA
5.0
—
0.65
1.30
mA
1.8
—
1.10
1.50
mA
3.0
—
0.70
1.30
mA
2.3
—
1.00
1.50
mA
3.0
—
1.20
1.70
mA
5.0
D014A
D015
D015
D016
D016
D018
D018
*
†
Note 1:
2:
3:
4:
FOSC = 20 MHz
EC Oscillator
High-Power mode
FOSC = 20 MHz
EC Oscillator
High-Power mode
FOSC = 31 kHz
LFINTOSC
-40°C  TA  +85°C
FOSC = 31 kHz
LFINTOSC
-40°C  TA  +85°C
FOSC = 500 kHz
HFINTOSC
FOSC = 500 kHz
HFINTOSC
FOSC = 8 MHz
HFINTOSC
FOSC = 8 MHz
HFINTOSC
FOSC = 16 MHz
HFINTOSC
FOSC = 16 MHz
HFINTOSC
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
0.1 F capacitor on VCAP pin, PIC16F1516/7/8/9 only.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
DS40001452F-page 272
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.4
DC Characteristics: Supply Current (IDD) (Continued)
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
VDD
Note
Supply Current (IDD)(1, 2, 3)
D020
D020
D021
D021
*
†
Note 1:
2:
3:
4:
—
1.0
1.80
mA
3.0
—
1.2
2.10
mA
3.6
—
1.4
1.70
mA
3.0
—
1.7
2.10
mA
5.0
—
150
220
A
1.8
—
250
380
A
3.0
—
165
330
A
2.3
—
280
420
A
3.0
—
350
500
A
5.0
FOSC = 20 MHz
HS Oscillator
FOSC = 20 MHz
HS Oscillator
FOSC = 4 MHz
EXTRC (Note 4)
FOSC = 4 MHz
EXTRC (Note 4)
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
0.1 F capacitor on VCAP pin, PIC16F1516/7/8/9 only.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 273
PIC16(L)F1516/7/8/9
25.5
DC Characteristics: Power-Down Currents (IPD)
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device Characteristics
Power-down Currents
Min.
Conditions
Max.
+85°C
Max.
+125°C
Units
0.02
1.0
8.0
A
1.8
Typ†
VDD
Note
(IPD)(2, 4)
D022
Base IPD
—
—
0.03
2.0
9.0
A
3.0
D022
Base IPD
—
0.20
3.0
10
A
2.3
—
0.30
4.0
12
A
3.0
—
0.47
6.0
15
A
5.0
—
0.50
6.0
14
A
1.8
—
0.80
7.0
17
A
3.0
—
0.50
6.0
15
A
2.3
—
0.77
7.0
20
A
3.0
—
0.85
8.0
22
A
5.0
—
8.5
23
25
A
1.8
—
8.5
24
27
A
3.0
—
18
26
30
A
2.3
—
19
27
37
A
3.0
—
20
29
45
A
5.0
D024
—
8.0
17
20
A
3.0
BOR Current (Note 1)
D024
—
8.0
17
30
A
3.0
BOR Current (Note 1)
—
9.0
20
40
A
5.0
D024A
—
0.30
4.0
8.0
A
3.0
LPBOR Current
D024A
—
0.30
4.0
14
A
3.0
LPBOR Current (Note 1)
—
0.45
8.0
17
A
5.0
—
0.3
5.0
9.0
A
1.8
—
0.5
8.5
12
A
3.0
—
1.1
6.0
10
A
2.3
—
1.3
8.5
20
A
3.0
D023
D023
D023A
D023A
D025
D025
D026
D026
*
†
Note 1:
2:
3:
4:
—
1.4
10
25
A
5.0
—
0.10
1.0
9.0
A
1.8
—
0.10
2.0
10
A
3.0
—
0.16
3.0
10
A
2.3
—
0.40
4.0
11
A
3.0
—
0.50
6.0
16
A
5.0
WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive
WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive,
Low-power regulator active
LPWDT Current (Note 1)
LPWDT Current (Note 1)
FVR current (Note 1)
FVR current (Note 1)
SOSC Current (Note 1)
SOSC Current (Note 1)
ADC Current (Note 1, 3),
no conversion in progress
ADC Current (Note 1, 3),
no conversion in progress
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values should be
used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
ADC clock source is FRC.
VREGPM = 1, PIC16F1516/7/8/9 only.
DS40001452F-page 274
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.5
DC Characteristics: Power-Down Currents (IPD) (Continued)
PIC16LF1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1516/7/8/9
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Device Characteristics
Power-down Currents (IPD)
D026A*
D026A*
*
†
Note 1:
2:
3:
4:
Min.
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
VDD
Note
(2, 4)
—
250
—
—
A
1.8
—
250
—
—
A
3.0
—
280
—
—
A
2.3
—
280
—
—
A
3.0
—
280
—
—
A
5.0
ADC Current (Note 1, 3),
conversion in progress
ADC Current (Note 1, 3),
conversion in progress
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values should be
used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
ADC clock source is FRC.
VREGPM = 1, PIC16F1516/7/8/9 only.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 275
PIC16(L)F1516/7/8/9
25.6
DC Characteristics: I/O Ports
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Min.
Typ†
Max.
Units
Conditions
with TTL buffer
—
—
0.8
V
4.5V  VDD  5.5V
—
—
0.15 VDD
V
1.8V  VDD  4.5V
with Schmitt Trigger buffer
—
—
0.2 VDD
V
2.0V  VDD  5.5V
Input Low Voltage
I/O PORT:
D030
D030A
D031
2
with I C levels
—
—
0.3 VDD
V
with SMBus levels
—
—
0.8
V
2.7V  VDD  5.5V
—
—
0.2 VDD
V
(Note 1)
—
—
0.3 VDD
V
—
—
D032
MCLR, OSC1 (RC
D033
OSC1 (HS mode)
VIH
mode)(1)
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
with
I2C
levels
with SMBus levels
2.0
—
—
V
4.5V  VDD 5.5V
0.25 VDD +
0.8
—
—
V
1.8V  VDD  4.5V
0.8 VDD
—
—
V
2.0V  VDD  5.5V
0.7 VDD
—
—
V
2.1
—
—
V
2.7V  VDD  5.5V
D042
MCLR
0.8 VDD
—
—
V
D043A
OSC1 (HS mode)
0.7 VDD
—
—
V
OSC1 (RC mode)
0.9 VDD
—
—
V
VDD > 2.0V (Note 1)
D043B
IIL
Input Leakage Current(2)
D060
I/O ports
—
±5
± 125
nA
±5
± 1000
nA
VSS  VPIN  VDD, Pin at highimpedance at 85°C
125°C
D061
MCLR(3)
—
± 50
± 200
nA
VSS  VPIN  VDD at 85°C
25
25
100
140
200
300
A
A
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
—
—
0.6
V
IOL = 8 mA, VDD = 5V
IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
IPUR
Weak Pull-up Current
D070*
VOL
D080
Output Low Voltage(4)
I/O ports
*
†
Note 1:
2:
3:
4:
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
DS40001452F-page 276
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.6
DC Characteristics: I/O Ports (Continued)
DC CHARACTERISTICS
Param
No.
Sym.
VOH
D090
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Min.
Typ†
Max.
Units
VDD - 0.7
—
—
V
—
—
15
pF
—
—
50
pF
Conditions
Output High Voltage(4)
I/O ports
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 pin
D101A* CIO
All I/O pins
In XT, HS and LP modes when
external clock is used to drive
OSC1
VCAP Capacitor Charging
D102*
Charging current
—
—
200
A
D102A*
Source/Sink capability when
charging complete
—
—
0.0
mA
*
†
Note 1:
2:
3:
4:
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 277
PIC16(L)F1516/7/8/9
25.7
Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
8.0
—
9.0
V
Conditions
Program Memory Programming
Specifications
D110
VIHH
Voltage on MCLR/VPP pin
D111
IDDP
Supply Current during Programming
—
—
10
mA
D112
VBE
VDD for Bulk Erase
2.7
—
VDDMAX
V
D113
VPEW
VDD for Write or Row Erase
VDDMIN
—
VDDMAX
V
D114
IPPPGM Current on MCLR/VPP during Erase/
Write
—
1.0
—
mA
D115
IDDPGM Current on VDD during Erase/Write
—
5.0
—
mA
(Note 2)
Program Flash Memory
D121
EP
Cell Endurance
D122
VPRW
VDD for Read/Write
D123
TIW
Self-timed Write Cycle Time
D124
TRETD
Characteristic Retention
D125
EHEFC
High-Endurance Flash Cell
100K
†
Note 1:
2:
-40C to +85C (Note 1)
10K
—
—
E/W
VDDMIN
—
VDDMAX
V
—
2
2.5
ms
—
40
—
Year
Provided no other
specifications are violated
—
—
E/W
0C to +60C lower byte, last
128 addresses
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Self-write and Block Erase.
Required only if single-supply programming is disabled.
DS40001452F-page 278
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.8
Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
Sym.
Characteristic
JA
Thermal Resistance Junction to Ambient
Typ.
Units
69.7
C/W
60.0
C/W
71.0
C/W
27.5
C/W
27.5
C/W
47.2
C/W
41.0
C/W
49.8
C/W
TH02
JC
Thermal Resistance Junction to Case
18.9
C/W
29.0
C/W
24.0
C/W
24.0
C/W
24.0
C/W
24.7
C/W
5.5
C/W
26.7
C/W
TH03
TJMAX
Maximum Junction Temperature
150
C
TH04
PD
Power Dissipation
—
W
TH05
PINTERNAL Internal Power Dissipation
—
W
TH06
PI/O
I/O Power Dissipation
—
W
TH07
PDER
Derated Power
—
W
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature.
TH01
 2010-2016 Microchip Technology Inc.
Conditions
28-pin SOIC package
28-pin SPDIP package
28-pin SSOP package
28-pin UQFN (4x4mm) package
28-pin QFN (6x6mm) package
40-pin PDIP package
40-pin UQFN (5x5mm) package
44-pin TQFP package
28-pin SOIC package
28-pin SPDIP package
28-pin SSOP package
28-pin UQFN (4x4mm) package
28-pin QFN (6x6mm) package
40-pin PDIP package
40-pin UQFN (5x5mm) package
44-pin TQFP package
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD(1)
PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
PDER = PDMAX (TJ - TA)/JA(2)
DS40001452F-page 279
PIC16(L)F1516/7/8/9
25.9
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDIx
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 25-5:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
DS40001452F-page 280
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.10 AC Characteristics
FIGURE 25-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 25-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
OS01
Sym.
FOSC
Characteristic
Min.
Typ†
Max.
Units
Conditions
External CLKIN Frequency(1)
DC
—
0.5
MHz EC Oscillator mode (low)
DC
—
4
MHz EC Oscillator mode (medium)
DC
—
20
MHz EC Oscillator mode (high)
Oscillator Frequency(1)
—
32.768
—
kHz
LP Oscillator mode
0.1
—
4
MHz XT Oscillator mode
1
—
4
MHz HS Oscillator mode
1
—
20
MHz HS Oscillator mode, VDD > 2.7V
DC
—
4
MHz RC Oscillator mode, VDD > 2.0V
OS02
TOSC
External CLKIN Period(1)
27
—

s
LP Oscillator mode
250
—

ns
XT Oscillator mode
50
—

ns
HS Oscillator mode
50
—

ns
EC Oscillator mode
—
30.5
—
s
LP Oscillator mode
Oscillator Period(1)
250
—
10,000
ns
XT Oscillator mode
50
—
1,000
ns
HS Oscillator mode
250
—
—
ns
RC Oscillator mode
OS03
TCY
Instruction Cycle Time(1)
200
TCY
DC
ns
TCY = FOSC/4
OS04*
TosH,
External CLKIN High,
2
—
—
s
LP oscillator
TosL
External CLKIN Low
100
—
—
ns
XT oscillator
20
—
—
ns
HS oscillator
OS05*
TosR,
External CLKIN Rise,
0
—

ns
LP oscillator
TosF
External CLKIN Fall
0
—

ns
XT oscillator
0
—

ns
HS oscillator
*
These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 281
PIC16(L)F1516/7/8/9
TABLE 25-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
Param
No.
Sym.
-40°C TA +125°C
Characteristic
Freq.
Tolerance
Min.
Typ†
Max.
Units
Conditions
OS08
HFOSC
Internal-Calibrated HFINTOSC
Frequency(1)
6.5%
—
16.0
—
MHz
VDD = 3.0V at +25°C
(Note 2)
OS09
LFOSC
Internal LFINTOSC Frequency
—
—
31
—
kHz
(Note 3)
OS10*
TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
—
—
5
15
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 25-3.
3: See Figures 26-60 and 26-61.
FIGURE 25-7:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS40001452F-page 282
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 25-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
—
—
70
ns
VDD = 3.3-5.0V
—
—
72
ns
VDD = 3.3-5.0V
FOSC to CLKOUT (1)
OS11
TosH2ckL
OS12
TosH2ckH FOSC to CLKOUT
(1)
OS13
TckL2ioV
CLKOUT to Port out valid
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18
TioR
Port input valid before CLKOUT(1)
Fosc (Q1 cycle) to Port out valid
Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
Port output rise time
OS19
TioF
Port output fall time
(1)
—
—
20
ns
TOSC + 200 ns
—
50
—
50
—
—
70*
—
ns
ns
ns
20
—
—
ns
—
—
—
—
25
25
40
15
28
15
—
—
72
32
55
30
—
—
ns
OS20* Tinp
OS21* Tioc
INT pin input high or low time
Interrupt-on-change new input level
time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
FIGURE 25-8:
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
VDD = 1.8V
VDD = 3.3-5.0V
ns
ns
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 283
PIC16(L)F1516/7/8/9
FIGURE 25-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
DS40001452F-page 284
33
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 25-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
2
—
—
s
10
16
27
ms
Oscillator Start-up Timer Period(1)
—
1024
—
Tosc
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.0
s
35
VBOR
Brown-out Reset Voltage(2)
2.55
2.35
1.80
2.70
2.45
1.90
2.85
2.58
2.00
V
V
V
36*
VHYST
Brown-out Reset Hysteresis
0
25
60
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
1
3
35
s
VDD  VBOR
38
VLPBOR Low-Power Brown-out Reset
Voltage
1.8
2.1
2.5
V
LPBOR = 0
30
TMCL
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
MCLR Pulse Width (low)
32
TOST
33*
VDD = 3.3V-5V,
1:512 Prescaler used
BORV = 0
BORV = 1 (PIC16F1516/7/8/9)
BORV = 1 (PIC16LF1516/7/8/9)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 25-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
 2010-2016 Microchip Technology Inc.
DS40001452F-page 285
PIC16(L)F1516/7/8/9
TABLE 25-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
40*
TT0H
T0CKI High Pulse Width
41*
TT0L
T0CKI Low Pulse Width
42*
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous,
with Prescaler
Asynchronous
T1CKI Low Synchronous, No Prescaler
Time
Synchronous, with Prescaler
Asynchronous
T1CKI Input Synchronous
Period
46*
47*
48
49*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Min.
Typ†
Max.
Units
0.5 TCY + 20
10
0.5 TCY + 20
10
Greater of:
20 or TCY + 40
N
0.5 TCY + 20
15
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
ns
ns
Conditions
N = prescale value
(2, 4, ..., 256)
30
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
30
—
—
ns
TT1P
Greater of:
—
—
ns N = prescale value
30 or TCY + 40
(1, 2, 4, 8)
N
Asynchronous
60
—
—
ns
Secondary Oscillator Input Frequency Range
32.4
32.768 33.1
kHz
FT1
(oscillator enabled by setting bit T1OSCEN)
2 TOSC
—
7 TOSC
— Timers in Sync
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TT1L
DS40001452F-page 286
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP
(Capture mode)
CC01
CC02
CC03
Note:
Refer to Figure 25-5 for load conditions.
TABLE 25-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C  TA  +125°C
Param
Sym.
No.
Characteristic
CC01* TccL
CCP Input Low Time
CC02* TccH
CCP Input High Time
CC03* TccP
*
†
CCP Input Period
Min.
Typ†
Max.
Units
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
3TCY + 40
N
—
—
ns
No Prescaler
Conditions
N = prescale value (1, 4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 287
PIC16(L)F1516/7/8/9
TABLE 25-7:
ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS:(1,2,3)
Standard Operating Conditions (unless otherwise stated)
Operating temperature Tested at +25°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
AD01
NR
Resolution
—
—
10
AD02
EIL
Integral Error
—
±1
±1.7
AD03
EDL
Differential Error
—
±1
±1
AD04
EOFF Offset Error
—
±1
±2.5
LSb VREF = 3.0V
AD05
EGN
—
±1
±2.0
LSb VREF = 3.0V
AD06
VREF Reference Voltage(4)
1.8
—
VDD
V
AD07
VAIN
Full-Scale Range
VSS
—
VREF
V
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
—
—
10
k
*
†
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
VREF = (VREF+ minus VREF-)
Can go higher if external 0.01F capacitor is
present on input pin.
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Total Absolute Error includes integral, differential, offset and gain errors.
The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR selected as the reference
input, the FVR Buffer1 output selection must be 2.048V or 4.096V, (ADFVR<1:0> = 1x).
TABLE 25-8:
ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
ADC Clock Period
1.0
—
9.0
s
FOSC-based
FRC Oscillator Period
1.0
2.5
6.0
s
ADCS<1:0> = 11
(FRC Oscillator mode)
Conversion Time (not including
Acquisition Time)(1)
—
11
—
TAD
Set GO/DONE bit to conversion
complete
AD132* TACQ
Acquisition Time
—
5.0
—
s
AD133* THCD
Holding Capacitor Disconnect
—
0.5*TAD + 40 ns
(0.5*TAD + 40 ns)
to
(0.5*TAD + 40 ns)
—
ADCS<2:0> = X11 (FOSC-based)
—
ADCS<2:0> = X11 (ADC FRC mode)
AD130* TAD
AD131
TCNV
—
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
DS40001452F-page 288
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-12:
ADC CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
ADC CLK
7
ADC Data
6
4
5
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
Note 1: If the ADC clock source is selected as FRC oscillator, a time of TCY is added before the ADC clock starts. This
allows the SLEEP instruction to be executed.
FIGURE 25-13:
ADC CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
ADC CLK
7
ADC Data
6
5
4
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the ADC clock source is selected as FRC oscillator, a time of TCY is added before the ADC clock starts. This
allows the SLEEP instruction to be executed.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 289
PIC16(L)F1516/7/8/9
TABLE 25-9:
LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
LDO01
LDO Regulation Voltage
—
3.0
—
V
LDO02
LDO External Capacitor
0.1
—
1
F
†
Conditions
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 25-14:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
US122
US120
Note:
Refer to Figure 25-5 for load conditions.
TABLE 25-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
—
80
ns
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
1.8-5.5V
—
100
ns
US121 TCKRF
Clock out rise time and fall time
(Master mode)
3.0-5.5V
—
45
ns
1.8-5.5V
—
50
ns
US122 TDTRF
Data-out rise time and fall time
3.0-5.5V
—
45
ns
1.8-5.5V
—
50
ns
DS40001452F-page 290
Conditions
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-15:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
Note: Refer to Figure 25-5 for load conditions.
TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
No.
Symbol
Characteristic
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time)
US126 TCKL2DTL
Data-hold after CK  (DT hold time)
 2010-2016 Microchip Technology Inc.
Min.
Max.
Units
10
—
ns
15
—
ns
Conditions
DS40001452F-page 291
PIC16(L)F1516/7/8/9
FIGURE 25-16:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SSx
SP70
SCKx
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDOx
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 25-5 for load conditions.
FIGURE 25-17:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SSx
SP81
SCKx
(CKP = 0)
SP71
SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
SP78
LSb
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 25-5 for load conditions.
DS40001452F-page 292
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-18:
SPI SLAVE MODE TIMING (CKE = 0)
SSx
SP70
SCKx
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCKx
(CKP = 1)
SP80
MSb
SDOx
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 25-5 for load conditions.
FIGURE 25-19:
SSx
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SP83
SCKx
(CKP = 0)
SP71
SP72
SCKx
(CKP = 1)
SP80
SDOx
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDIx
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 25-5 for load conditions.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 293
PIC16(L)F1516/7/8/9
TABLE 25-12: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Unit
Conditions
s
Min.
Typ†
Max.
SP70* TSSL2SCH, SSx to SCKx or SCKx input
TSSL2SCL
2.25 TCY
—
—
ns
SP71* TSCH
SCKx input high time (Slave mode)
TCY + 20
—
—
ns
SP72* TSCL
SCKx input low time (Slave mode)
TCY + 20
—
—
ns
100
—
—
ns
100
—
—
ns
SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge
TDIV2SCL
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDIx data input to SCKx edge
SP75* TDOR
SDO data output rise time
SP76* TDOF
3.0-5.5V
—
10
25
ns
1.8-5.5V
—
25
50
ns
—
10
25
ns
SDOx data output fall time
SP77* TSSH2DOZ
SSx to SDOx output high-impedance
10
—
50
ns
SP78* TSCR
SCKx output rise time
(Master mode)
3.0-5.5V
—
10
25
ns
1.8-5.5V
—
25
50
ns
SP79* TSCF
SCKx output fall time (Master mode)
—
10
25
ns
3.0-5.5V
—
—
50
ns
1.8-5.5V
—
—
145
ns
SP81* TDOV2SCH SDOx data output setup to SCKx edge
,
TDOV2SCL
Tcy
—
—
ns
SDOx data output valid after SS edge
—
—
50
ns
1.5TCY +
40
—
—
ns
SP80* TSCH2DOV, SDOx data output valid after
TSCL2DOV SCKx edge
SP82* TSSL2DOV
SP83* TSCH2SSH, SSx after SCKx edge
TSCL2SSH
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40001452F-page 294
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-20:
I2C BUS START/STOP BITS TIMING
SCLx
SP93
SP91
SP90
SP92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 25-5 for load conditions.
TABLE 25-13: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
SP90*
TSU:STA
SP91*
SP92*
SP93
THD:STA
TSU:STO
Characteristic
Typ
Max.
Unit
s
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
Start condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
Start condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
THD:STO Stop condition
Hold time
*
Min.
Conditions
ns
ns
These parameters are characterized but not tested.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 295
PIC16(L)F1516/7/8/9
FIGURE 25-21:
I2C BUS DATA TIMING
SP103
SCLx
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SP92
SDAx
In
SP110
SP109
SP109
SDAx
Out
Note: Refer to Figure 25-5 for load conditions.
TABLE 25-14: I2C BUS DATA REQUIREMENTS
Param.
No.
SP100*
Symbol
THIGH
Characteristic
Clock high time
Min.
Max.
Units
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
SSP module
SP101*
TLOW
Clock low time
1.5TCY
—
—
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
SSP module
SP102*
SP103*
SP106*
TR
TF
THD:DAT
1.5TCY
—
—
SDAx and SCLx rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1CB
300
ns
SDAx and SCLx fall
time
100 kHz mode
—
250
ns
400 kHz mode
20 + 0.1CB
250
ns
Data input hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
—
ns
SP107*
TSU:DAT
Data input setup time
100 kHz mode
250
400 kHz mode
100
—
ns
SP109*
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus free time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
—
400
pF
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Bus capacitive loading
Conditions
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the
SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before
the SCLx line is released.
DS40001452F-page 296
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
26.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 297
PIC16(L)F1516/7/8/9
FIGURE 26-1:
IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16LF1516/7/8/9 ONLY
30
Max: 85°C + 3ı
Typical: 25°C
25
Max.
IDD (μA)
20
15
Typical
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-2:
IDD, LP OSCILLATOR MODE, FOSC = 32 kHz, PIC16F1516/7/8/9 ONLY
40
Max.
Max: 85°C + 3ı
Typical: 25°C
35
30
Typical
IDD (μA)
25
20
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 298
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-3:
IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1516/7/8/9 ONLY
350
Typical: 25°C
300
4 MHz XT
IDD (μA)
250
200
150
1 MHz XT
100
50
1 MHz EXTRC
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-4:
IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1516/7/8/9 ONLY
400
Max: 85°C + 3ı
350
4 MHz XT
300
IDD (μA)
250
200
150
1 MHz XT
100
50
1 MHz EXTRC
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 299
PIC16(L)F1516/7/8/9
FIGURE 26-5:
IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1516/7/8/9 ONLY
450
400
4 MHz XT
Typical: 25°C
350
4 MHz EXTRC
IDD (μA)
300
250
1 MHz XT
200
150
100
1 MHz EXTRC
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 26-6:
IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1516/7/8/9 ONLY
500
4 MHz XT
Max: 85°C + 3ı
450
400
4 MHz EXTRC
350
IDD (μA)
300
1 MHz XT
250
200
150
1 MHz EXTRC
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 300
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-7:
IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz,
PIC16LF1516/7/8/9 ONLY
25
Max.
Max: 85°C + 3ı
Typical: 25°C
20
IDD (μA)
15
Typical
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-8:
IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz,
PIC16F1516/7/8/9 ONLY
35
Max.
Max: 85°C + 3ı
Typical: 25°C
30
IDD (μA)
25
Typical
20
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 301
PIC16(L)F1516/7/8/9
FIGURE 26-9:
IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz,
PIC16LF1516/7/8/9 ONLY
60
Max.
Max: 85°C + 3ı
Typical: 25°C
50
IDD (μA)
40
Typical
30
20
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-10:
IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz,
PIC16F1516/7/8/9 ONLY
70
Max.
Max: 85°C + 3ı
Typical: 25°C
60
Typical
IDD (μA)
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 302
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-11:
IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16LF1516/7/8/9 ONLY
300
4 MHz
Typical: 25°C
250
IDD (μA)
200
150
100
1 MHz
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.4
3.6
3.8
VDD (V)
FIGURE 26-12:
IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE,
PIC16LF1516/7/8/9 ONLY
350
4 MHz
Max: 85°C + 3ı
300
IDD (μA)
250
200
150
1 MHz
100
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 303
PIC16(L)F1516/7/8/9
FIGURE 26-13:
IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1516/7/8/9 ONLY
350
4 MHz
Typical: 25°C
300
IDD (μA)
250
200
1 MHz
150
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 26-14:
IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC16F1516/7/8/9 ONLY
400
350
Max: 85°C + 3ı
4 MHz
300
IDD (μA)
250
200
1 MHz
150
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 304
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-15:
IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1516/7/8/9 ONLY
1.6
Typical: 25°C
1.4
20 MHz
1.2
16 MHz
IDD (mA)
1.0
0.8
0.6
8 MHz
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-16:
IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16LF1516/7/8/9 ONLY
1.8
1.6
Max: 85°C + 3ı
20 MHz
1.4
IDD (mA)
1.2
16 MHz
1.0
0.8
0.6
8 MHz
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 305
PIC16(L)F1516/7/8/9
FIGURE 26-17:
IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1516/7/8/9 ONLY
1.6
20 MHz
Typical: 25°C
1.4
1.2
16 MHz
IDD (mA)
1.0
0.8
8 MHz
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 26-18:
IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC16F1516/7/8/9 ONLY
1.8
Max: 85°C + 3ı
1.6
20 MHz
1.4
16 MHz
IDD (mA)
1.2
1.0
0.8
8 MHz
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 306
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-19:
IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16LF1516/7/8/9 ONLY
30
Max: 85°C + 3ı
Typical: 25°C
25
Max.
IDD (μA)
20
15
Typical
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-20:
IDD, LFINTOSC MODE, FOSC = 31 kHz, PIC16F1516/7/8/9 ONLY
35
Max.
30
IDD (μA)
25
Typical
20
15
10
Max: 85°C + 3ı
Typical: 25°C
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 307
PIC16(L)F1516/7/8/9
FIGURE 26-21:
IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16LF1516/7/8/9 ONLY
350
Max.
Max: 85°C + 3ı
Typical: 25°C
300
IDD (μA)
Typical
250
200
150
100
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-22:
IDD, MFINTOSC MODE, FOSC = 500 kHz, PIC16F1516/7/8/9 ONLY
450
Max.
Max: 85°C + 3ı
Typical: 25°C
400
Typical
IDD (μA)
350
300
250
200
150
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 308
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-23:
IDD TYPICAL, HFINTOSC MODE, PIC16LF1516/7/8/9 ONLY
1.4
16 MHz
Typical: 25°C
1.2
IDD (mA)
1.0
8 MHz
0.8
4 MHz
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.6
3.8
VDD (V)
FIGURE 26-24:
IDD MAXIMUM, HFINTOSC MODE, PIC16LF1516/7/8/9 ONLY
1.6
16 MHz
1.4
Max: 85°C + 3ı
IDD (mA)
1.2
1.0
8 MHz
0.8
4 MHz
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 309
PIC16(L)F1516/7/8/9
FIGURE 26-25:
IDD TYPICAL, HFINTOSC MODE, PIC16F1516/7/8/9 ONLY
1.4
16 MHz
Typical: 25°C
1.2
1.0
IDD (mA)
8 MHz
0.8
4 MHz
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
VDD (V)
FIGURE 26-26:
IDD MAXIMUM, HFINTOSC MODE, PIC16F1516/7/8/9 ONLY
1.6
1.4
16 MHz
Max: 85°C + 3ı
1.2
IDD (mA)
1.0
8 MHz
0.8
4 MHz
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
DS40001452F-page 310
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-27:
IDD TYPICAL, HS OSCILLATOR, PIC16LF1516/7/8/9 ONLY
1.8
Typical: 25°C
1.6
20 MHz
1.4
IDD (mA)
1.2
1
0.8
8 MHz
0.6
4 MHz
0.4
0.2
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
3.4
3.6
3.8
VDD (V)
FIGURE 26-28:
IDD MAXIMUM, HS OSCILLATOR, PIC16LF1516/7/8/9 ONLY
2.0
1.8
Max: 85°C + 3ı
20 MHz
1.6
1.4
IDD (mA)
1.2
1.0
8 MHz
0.8
0.6
4 MHz
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 311
PIC16(L)F1516/7/8/9
FIGURE 26-29:
IDD TYPICAL, HS OSCILLATOR, PIC16F1516/7/8/9 ONLY
2
1.8
Typical: 25°C
20 MHz
1.6
1.4
IDD (mA)
1.2
1
8 MHz
0.8
0.6
4 MHz
0.4
0.2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 26-30:
IDD MAXIMUM, HS OSCILLATOR, PIC16F1516/7/8/9 ONLY
2.5
20 MHz
Max: 85°C + 3ı
2.0
IDD (mA)
1.5
8 MHz
1.0
4 MHz
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 312
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-31:
IPD BASE, SLEEP MODE, PIC16LF1516/7/8/9 ONLY
450
Max: 85°C + 3
M
3ı
Typical: 25°C
400
Max.
350
IPD
D (nA)
300
250
200
150
100
Typical
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-32:
IPD BASE, LOW-POWER SLEEP MODE (VREGPM = 1), PIC16F1516/7/8/9 ONLY
600
Max.
Max: 85°C + 3ı
Typical: 25°C
500
IPD (nA)
400
300
Typical
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 313
PIC16(L)F1516/7/8/9
FIGURE 26-33:
IPD, WATCHDOG TIMER (WDT), PIC16LF1516/7/8/9 ONLY
1.4
Max: 85°C + 3ı
Typical: 25°C
1.2
Max.
IPD (μA
(μA)
1.0
0
8
0.8
Typical
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-34:
IPD, WATCHDOG TIMER (WDT), PIC16F1516/7/8/9 ONLY
1.2
Max: 85°C + 3ı
Typical: 25°C
1.0
Max.
IPD (μA
A)
0.8
Typical
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 314
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-35:
IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1516/7/8/9 ONLY
25
Max.
Typical
20
IPD (μA
A)
15
10
Max: 85°C + 3ı
Typical: 25°C
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-36:
IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1516/7/8/9 ONLY
30
Max.
25
IPD (μA)
20
Typical
15
10
Max: 85°C + 3ı
Typical: 25°C
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 315
PIC16(L)F1516/7/8/9
FIGURE 26-37:
IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1516/7/8/9 ONLY
12
Max.
Max: 85°C + 3ı
Typical: 25°C
10
8
IPD
D (μA)
Typical
6
4
2
0
16
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 26-38:
IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1516/7/8/9 ONLY
14
Max
Max.
Max: 85°C + 3ı
Ma
Typical: 25°C
12
IPD (μA)
10
Typical
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 316
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-39:
IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1516/7/8/9 ONLY
6.0
Max: 85°C + 3ı
Typical: 25°C
5.0
Max.
IPD (μA
A)
4.0
3.0
Typical
2.0
1.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-40:
IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1516/7/8/9 ONLY
12
Max: 85°C + 3ı
Typical: 25°C
10
Max.
IPD (μA)
8
Typical
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 317
PIC16(L)F1516/7/8/9
FIGURE 26-41:
VOH VS. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1516/7/8/9 ONLY
6
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
5
VOH (V)
4
Min. (-40°C)
3
Typical (25°C)
2
Max. (125°C)
1
0
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
IOH (mA)
FIGURE 26-42:
VOL VS. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1516/7/8/9 ONLY
5
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
4
Max. (125°C)
VOL (V)
Typical (25°C)
3
Min. (-40°C)
2
1
0
0
10
DS40001452F-page 318
20
30
40
50
IOL (mA)
60
70
80
90
100
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-43:
VOH VS. IOH OVER TEMPERATURE, VDD = 3.0V
3.5
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
3.0
VOH (V)
2.5
2.0
1.5
1.0
Min. (-40°C)
Typical (25°C)
Max. (125°C)
0.5
0.0
-15
-13
-11
-9
-7
-5
-3
-1
IOH (mA)
FIGURE 26-44:
VOL VS. IOL OVER TEMPERATURE, VDD = 3.0V
3.0
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
2.5
VOL (V)
2.0
Max. (125°C)
Typical (25°C)
Min. (-40°C)
1.5
1.0
0.5
0.0
0
5
10
15
20
25
30
35
40
IOL (mA)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 319
PIC16(L)F1516/7/8/9
FIGURE 26-45:
VOH VS. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1516/7/8/9 ONLY
2.0
1.8
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
1.6
VOH (V)
1.4
1.2
Min. (-40°C)
Max. (125°C)
Typical (25°C)
1.0
0.8
0.6
0.4
0.2
0.0
-4.5
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
IOH (mA)
FIGURE 26-46:
VOL VS. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1516/7/8/9 ONLY
1.8
Max: 125°C + 3ı
Typical: 25°C
Min: -40°C - 3ı
1.6
1.4
VOL (V)
1.2
1.0
0.8
Max. (125°C)
Min. (-40°C)
Typical (25°C)
0.6
0.4
0.2
0.0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
DS40001452F-page 320
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-47:
POR RELEASE VOLTAGE
1.70
1.68
Max.
1.66
Voltage (V)
1.64
Typical
1.62
Min.
1.60
1.58
1.56
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
1.54
1.52
1.50
-60
-40
-20
0
20
40
60
80
100
120
140
120
140
Temperature (°C)
FIGURE 26-48:
POR REARM VOLTAGE, PIC16F1516/7/8/9 ONLY
1.54
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
1.52
1.50
Max.
Voltage (V)
1.48
1.46
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 321
PIC16(L)F1516/7/8/9
FIGURE 26-49:
BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1516/7/8/9 ONLY
2.00
Max.
Voltage (V)
1.95
Typical
1.90
1.85
Min.
Max: Typical + 3ı
Min: Typical - 3ı
1.80
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 26-50:
BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1516/7/8/9 ONLY
60
50
Max.
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
40
Typical
30
20
Min.
10
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
DS40001452F-page 322
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-51:
BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1516/7/8/9 ONLY
2.60
Max.
2.55
Voltage (V)
2.50
Typical
2.45
Min.
2.40
Max: Typical + 3ı
Min: Typical - 3ı
2.35
2.30
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 26-52:
BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1516/7/8/9 ONLY
70
Max.
60
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
50
40
Typical
30
20
Min.
10
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 323
PIC16(L)F1516/7/8/9
FIGURE 26-53:
BROWN-OUT RESET VOLTAGE, BORV = 0
2.80
2.75
Voltage (V)
Max.
2.70
Typical
2.65
Min.
Max: Typical + 3ı
Min: Typical - 3ı
2.60
2.55
-60
-40
-20
0
20
40
60
80
100
120
140
120
140
Temperature (°C)
FIGURE 26-54:
BROWN-OUT RESET HYSTERESIS, BORV = 0
90
80
Min.
70
Voltage (mV)
60
Typical
50
40
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
30
20
Max.
10
0
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
DS40001452F-page 324
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-55:
LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0
2.50
Max.
Max: Typical + 3ı
Min: Typical - 3ı
2.40
Voltage (V)
2.30
Typical
2.20
2.10
2.00
Min.
1.90
1.80
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 26-56:
LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0
45
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
40
35
Max.
Typical
Voltage (mV)
30
25
Min.
20
15
10
5
0
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 325
PIC16(L)F1516/7/8/9
FIGURE 26-57:
WDT TIME-OUT PERIOD
24
22
Max.
Time (ms)
20
18
Typical
16
Min.
14
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
12
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 26-58:
PWRT PERIOD
100
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
90
Max.
Time (ms)
80
70
Typical
60
Min.
50
40
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001452F-page 326
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 26-59:
FVR STABILIZATION PERIOD
40
35
Max: Typical + 3ı
Typical: statistical mean @ 25°C
Max.
Time (us)
30
Typical
25
20
15
Note:
The FVR Stabilization Period applies when:
1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from Reset.
10
5
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
 2010-2016 Microchip Technology Inc.
DS40001452F-page 327
PIC16(L)F1516/7/8/9
FIGURE 26-60:
LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE,
PIC16LF1516/7/8/9 ONLY
36
34
Max.
Frequency (kHz)
32
30
Typical
28
Min.
26
24
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
22
20
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 26-61:
LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE,
PIC16F1516/7/8/9 ONLY
36
34
Max.
Frequency (kHz)
32
30
Typical
28
26
Min.
24
Max: Typical + 3ı (-40°C to +125°C)
Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
22
20
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
DS40001452F-page 328
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
27.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
27.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
 2010-2016 Microchip Technology Inc.
DS40001452F-page 329
PIC16(L)F1516/7/8/9
27.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
27.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
27.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS40001452F-page 330
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PIC16(L)F1516/7/8/9
27.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
27.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
 2010-2016 Microchip Technology Inc.
27.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
27.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
27.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS40001452F-page 331
PIC16(L)F1516/7/8/9
27.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
27.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS40001452F-page 332
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
28.0
PACKAGING INFORMATION
28.1
Package Marking Information
28-Lead SOIC (7.50 mm)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
Example
PIC16F1516-E/SO e3
1248017
YYWWNNN
28-Lead SPDIP (.300”)
Example
PIC16F1516-E/SP e3
1248017
28-Lead SSOP (5.30 mm)
Example
PIC16F1516
-E/SS e3
1248017
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 333
PIC16(L)F1516/7/8/9
Package Marking Information (Continued)
28-Lead UQFN (4x4x0.5 mm)
PIN 1
Example
PIN 1
PIC16
F1516
E/MV e3
248017
28-Lead QFN (6x6x0.9 mm)
PIN 1
Example
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
40-Lead PDIP (600 mil)
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
16F1518
-I/ML e3
1248107
Example
PIC16F1517-E/P
1248107
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001452F-page 334
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Package Marking Information (Continued)
40-Lead UQFN (5x5x0.5 mm)
PIN 1
Example
PIN 1
44-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
PIC16
LF1517
-E/MV e3
1248017
Example
PIC16F1517
-E/PT e3
1248017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 335
PIC16(L)F1516/7/8/9
28.2
Package Details
The following sections give the technical details of the packages.
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001452F-page 336
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2016 Microchip Technology Inc.
DS40001452F-page 337
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001452F-page 338
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
!"
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
6&!
'!
9'&!
7"')
%!
7,8.
7
7
7:
;
<
&
&
&
=
=
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-
1!&
&
=
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"#&
"#>#&
.
-
--
##4>#&
.
<
: 9&
-
-?
&
&
9
-
9#4!!
<
)
)
<
1
=
=
69#>#&
9
*9#>#&
: *+
1,
-
!"
!"#$%&"' ()"&'"!&)
&#*&&&#
+%&,&!&
- '!
!#.#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#/!#
'!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
* ,1
 2010-2016 Microchip Technology Inc.
DS40001452F-page 339
PIC16(L)F1516/7/8/9
#$
%
&'
%
!"
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
D
N
E
E1
1 2
NOTE 1
b
e
c
A2
A
φ
A1
L
L1
6&!
'!
9'&!
7"')
%!
99..
7
7
7:
;
<
&
: 8&
=
?1,
=
##44!!
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<
&#
%%
=
=
: >#&
.
<
<
##4>#&
.
-
?
: 9&
3
&9&
9
3
&&
9
.3
9#4!!
=
3
&
@
@
<@
9#>#&
)
=
-<
!"
!"#$%&"' ()"&'"!&)
&#*&&&#
'!
!#.#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#''!#
- '!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
.32 %'!
("!"*&
"&&
(%
%
'&
"
!!
* ,-1
DS40001452F-page 340
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2016 Microchip Technology Inc.
DS40001452F-page 341
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001452F-page 342
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2016 Microchip Technology Inc.
DS40001452F-page 343
PIC16(L)F1516/7/8/9
DS40001452F-page 344
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
 2010-2016 Microchip Technology Inc.
DS40001452F-page 345
PIC16(L)F1516/7/8/9
DS40001452F-page 346
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
()*!+,-.-()!
/#'&&0+#
!"
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
 2010-2016 Microchip Technology Inc.
DS40001452F-page 347
PIC16(L)F1516/7/8/9
1-
!"
3
&'
!&"&4#*!(!!&
4%&
&#&
&&255***'
'54
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
6&!
'!
9'&!
7"')
%!
7,8.
7
7
7:
;
&
&
&
=
=
##44!!
=
1!&
&
=
=
"#&
"#>#&
.
=
?
##4>#&
.
<
=
<
: 9&
<
=
&
&
9
=
9#4!!
<
=
)
-
=
)
=
-
1
=
=
69#>#&
9
*9#>#&
: *+
1,
!"
!"#$%&"' ()"&'"!&)
&#*&&&#
+%&,&!&
- '!
!#.#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#/!#
'!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
* ,?1
DS40001452F-page 348
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2016 Microchip Technology Inc.
DS40001452F-page 349
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001452F-page 350
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010-2016 Microchip Technology Inc.
DS40001452F-page 351
PIC16(L)F1516/7/8/9
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
D1
NOTE 2
B
(DATUM A)
(DATUM B)
E1
A
NOTE 1
2X
0.20 H A B
E
A
N
2X
1 2 3
0.20 H A B
TOP VIEW
4X 11 TIPS
0.20 C A B
A
A2
C
SEATING PLANE
0.10 C
SIDE VIEW
A1
1 2 3
N
NOTE 1
44 X b
0.20
e
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
DS40001452F-page 352
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
L
θ
(L1)
SECTION A-A
Notes:
Units
Dimension Limits
N
Number of Leads
e
Lead Pitch
A
Overall Height
Standoff
A1
A2
Molded Package Thickness
E
Overall Width
Molded Package Width
E1
D
Overall Length
D1
Molded Package Length
b
Lead Width
c
Lead Thickness
Lead Length
L
Footprint
L1
Foot Angle
θ
MIN
0.05
0.95
0.30
0.09
0.45
0°
MILLIMETERS
NOM
44
0.80 BSC
1.00
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.37
0.60
1.00 REF
3.5°
MAX
1.20
0.15
1.05
0.45
0.20
0.75
7°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076C Sheet 2 of 2
 2010-2016 Microchip Technology Inc.
DS40001452F-page 353
PIC16(L)F1516/7/8/9
44-Lead Plastic Thin Quad Flatpack (PT) - 10X10X1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
44
1
2
G
C2
Y1
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X44)
X1
Contact Pad Length (X44)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.80 BSC
11.40
11.40
MAX
0.55
1.50
0.25
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2076B
DS40001452F-page 354
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (12/2010)
Original release.
Revision B (05/2011)
Initial public release of device family.
Revision C (09/2012)
Update to Electrical Specifications and release of
Characterization Data.
Revision D (07/2013)
Updated the Notes in Figures 2 and 4; Updated Table
5-1, Register 14-1, Register 20-1 and Table 21-4;
Updated Section 22.2; Updated Figure 25-9 and Table
25-7; Updated Section 26, DC and AC Characteristics
Graphs and Charts; Updated the Packaging section;
Other minor corrections.
Revision E (05/2015)
Added 28-pin QFN (6x6) packaging. Updated Product
Identification section.
Added Figure 2 and Section 3.2.
Updated Example 3-2. Updated Register 22-3.
Updated Sections 22.4.2, 25.0, 25.6, and 28.1.
Updated Table 1 and 25-12.
Revision F (06/2016)
Updated the ‘High-Performance RISC CPU’ section
and added the Memory section; Updated Figures 5-7
and 8-1 and Table 25-4; Other minor corrections.
 2010-2016 Microchip Technology Inc.
DS40001452F-page 355
PIC16(L)F1516/7/8/9
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://www.microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS40001452F-page 356
 2010-2016 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
Device:
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
c)
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
ML
MV
P
PT
SO
SP
SS
Pattern:
PIC16F1516T - I/MV 301
Tape and Reel,
Industrial temperature,
UQFN package,
QTP pattern #301
PIC16F1519 - I/P
Industrial temperature
PDIP package
PIC16F1518 - E/SS
Extended temperature,
SSOP package
(Industrial)
(Extended)
Thin Quad Flat, no lead (QFN)
Ultra Thin Quad Flat, no lead (UQFN)
Plastic DIP (PDIP)
TQFP
SOIC
Skinny Plastic DIP (SPDIP)
SSOP
QTP, SQTP, Code or Special Requirements
(blank otherwise)
 2010-2016 Microchip Technology Inc.
a)
b)
PIC16F1516, PIC16LF1516
PIC16F1517, PIC16LF1517
PIC16F1518, PIC16LF1518
PIC16F1519, PIC16LF1519
=
=
=
=
=
=
=
Examples:
Note 1:
2:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
For other small form-factor package
availability and marking information, please
visit www.microchip.com/packaging or
contact your local sales office.
DS40001452F-page 357
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001452F-page 358
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0681-5
 2010-2016 Microchip Technology Inc.
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07/14/15
 2010-2016 Microchip Technology Inc.
DS40001452F-page 359