PIC16(L)F151X/152X Memory Programming Specification

PIC16(L)F151X/152X
PIC16(L)F151X/152X Memory Programming Specification
This document includes the
programming specifications for the
following devices:
1.1.2
LOW-VOLTAGE ICSP
PROGRAMMING
• PIC16F1512
• PIC16LF1512
• PIC16F1513
• PIC16LF1513
• PIC16F1516
• PIC16LF1516
In Low-Voltage ICSP™ mode, these devices can be
programmed using a single VDD source in the
operating range. The MCLR/VPP pin does not have to
be brought to a different voltage, but can instead be left
at the normal operating voltage.
• PIC16F1517
• PIC16LF1517
1.1.2.1
• PIC16F1518
• PIC16LF1518
• PIC16F1519
• PIC16LF1519
• PIC16F1526
• PIC16LF1526
• PIC16F1527
• PIC16LF1527
1.0
OVERVIEW
The
PIC16(L)F151X/152X
devices
can
be
programmed using either the high-voltage In-Circuit
Serial Programming™ (ICSP™) method or the lowvoltage ICSP™ method.
1.1
1.1.1
Hardware Requirements
HIGH-VOLTAGE ICSP
PROGRAMMING
In High-Voltage ICSP™ mode, these devices require
two programmable power supplies; one for VDD and
one for the MCLR/VPP pin.
 2010-2011 Microchip Technology Inc.
Single-Supply ICSP Programming
The LVP bit in Configuration Word 2 enables singlesupply (low-voltage) ICSP programming. The LVP bit
defaults to a ‘1’ (enabled) from the factory. The LVP bit
may only be programmed to ‘0’ by entering the HighVoltage ICSP mode, where the MCLR/VPP pin is raised
to VIHH. Once the LVP bit is programmed to a ‘0’, only
the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP pin.
2: While in Low-Voltage ICSP mode, MCLR
is always enabled, regardless of the
MCLRE bit, and the port pin can no
longer be used as a general purpose
input.
Advance Information
DS41442B-page 1
PIC16(L)F151X/152X
1.2
Pin Utilization
Five pins are needed for ICSP™ programming. The
pins are listed in Table 1-1 and Table 1-2.
TABLE 1-1:
Pin Name
PIN DESCRIPTIONS DURING PROGRAMMING – PIC16(L)F1526 AND PIC16(L)F1527
During Programming
Function
Pin Type
RB6
ICSPCLK
I
RB7
ICSPDAT
I/O
RG5/MCLR/VPP
VDD
VSS
Legend:
Note 1:
Pin Description
Clock Input – Schmitt Trigger Input
Data Input/Output – Schmitt Trigger Input
(1)
Program Mode Select/Programming Power Supply
VDD
P
Power Supply
VSS
P
Ground
Program/Verify mode
P
I = Input, O = Output, P = Power
The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be
applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current.
TABLE 1-2:
Pin Name
RB6
RB7
PIN DESCRIPTIONS DURING PROGRAMMING – PIC16(L)F1512, PIC16(L)F1513,
PIC16(L)F1516, PIC16(L)F1517, PIC16(L)F1518 and PIC16(L)F1519
During Programming
Function
Pin Type
ICSPCLK
I
Pin Description
Clock Input – Schmitt Trigger Input
ICSPDAT
I/O
Data Input/Output – Schmitt Trigger Input
Program/Verify mode
P(1)
Program Mode Select/Programming Power Supply
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
RE3/MCLR/VPP
Legend:
Note 1:
I = Input, O = Output, P = Power
The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be
applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current.
DS41442B-page 2
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
2.0
DEVICE PINOUTS
The pin diagrams for the PIC16(L)F151X/152X family
are shown in Figure 2-1 through Figure 2-7. The pins
that are required for programming are listed in Table 1-1
and shown in bold lettering in the pin diagrams.
FIGURE 2-1:
28-PIN SPDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1512, PIC16(L)F1513,
PIC16(L)F1516 AND PIC16(L)F1518
SPDIP, SOIC, SSOP
1
28
RB7/ICSPDAT
RA0
2
27
RB6/ICSPCLK
VPP/MCLR/RE3
3
26
RB5
4
25
RA3
5
24
RB4
RB3
RA4
6
RA5
VSS
RA7
7
8
9
PIC16(L)F1512
PIC16(L)F1513
PIC16(L)F1516
PIC16(L)F1518
RA1
RA2
23
RB2
22
21
RB1
20
VDD
RB0
19
VSS
RC7
RA6
10
RC0
11
18
RC1
12
17
RC6
RC2
13
16
RC5
RC3
14
15
RC4
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 3
PIC16(L)F151X/152X
FIGURE 2-2:
28-PIN UQFN DIAGRAM FOR PIC16(L)F1512, PIC16(L)F1513, PIC16(L)F1516
AND PIC16(L)F1518
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
UQFN
PIC16(L)F1512
PIC16(L)F1513
PIC16(L)F1516
PIC16(L)F1518
8
9
10
11
12
13
14
1
2
3
4
5
6
7
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RA2
RA3
RA4
RA5
VSS
RA7
RA6
DS41442B-page 4
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
FIGURE 2-3:
40-PIN PDIP DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
PDIP
FIGURE 2-4:
VPP/MCLR/RE3
1
40
RB7/ICSPDAT/ICDDAT
RA0
2
39
RB6/ICSPCLK/ICDCLK
RA1
3
38
RB5
RA2
4
37
RB4
36
RA4
6
35
RB2
RA5
7
34
RB1
RE0
8
33
RB0
RE1
9
32
VDD
RE2
10
31
VSS
VDD
11
30
RD7
29
RD6
PIC16(L)F1519
5
PIC16(L)F1517
RA3
RB3
VSS
12
RA7
13
28
RD5
RA6
14
27
RD4
RC0
15
26
RC7
RC1
16
25
RC6
RC2
17
24
RC5
RC3
18
23
RC4
RD0
19
22
RD3
RD1
20
21
RD2
40-PIN UQFN DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
40
39
38
37
36
35
34
33
32
31
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
UQFN
1
2
3
4
5
6
7
8
9
10
PIC16(L)F1517
PIC16(L)F1519
30
29
28
27
26
25
24
23
22
21
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
ICDCLK/ICSPCLK/RB6
ICDDAT/ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
11
12
13
14
15
16
17
18
19
20
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 5
PIC16(L)F151X/152X
FIGURE 2-5:
44-PIN TQFP DIAGRAM FOR PIC16(L)F1517 AND PIC16(L)F1519
PIC16(L)F1517
PIC16(L)F1519
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
NC
NC
RB4
RB5
ICDCLK/ICSPCLK/RB6
ICDDAT/ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
TQFP
DS41442B-page 6
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
FIGURE 2-6:
64-PIN QFN DIAGRAM FOR PIC16(L)F1526 AND PIC16(L)F1527
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC16(L)F1526
PIC16(L)F1527
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK/ICDCLK
VSS
RA6
RA7
VDD
RB7/ICSPDAT/ICDDAT
RC5
RC4
RC3
RC2
RF1
RF0
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA5
RA4
RC1
RC0
RC6
RC7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FIGURE 2-7:
64-PIN TQFP DIAGRAM FOR PIC16(L)F1526 AND PIC16(L)F1527
RD0
VDD
VSS
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC16(L)F1526
PIC16(L)F1527
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK/ICDCLK
VSS
RA6
RA7
VDD
RB7/ICSPDAT/ICDDAT
RC5
RC4
RC3
RC2
RF1
VRF0
AVDD
AVSS
RA3
RA2
RA1
RA0
VSS
VDD
RA5
RA4
RC1
RC0
RC6
RC7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 7
PIC16(L)F151X/152X
3.0
MEMORY MAP
The
memory
for
the
PIC16(L)F151X/152X
devices is broken into two sections: program memory
and configuration memory. Only the size of the
program memory changes between devices, the
configuration memory remains the same.
FIGURE 3-1:
PIC16(L)F1512 PROGRAM MEMORY MAPPING
2 KW
0000h
Implemented
07FFh
Maps to
0-07FFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FFh
Configuration Memory
FFFFh
800Bh-81FFh
DS41442B-page 8
Reserved
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
FIGURE 3-2:
PIC16(L)F1513 PROGRAM MEMORY MAPPING
4 KW
0000h
Implemented
0FFFh
Maps to
0-0FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FFh
Configuration Memory
FFFFh
800Bh-81FFh
 2010-2011 Microchip Technology Inc.
Reserved
Advance Information
DS41442B-page 9
PIC16(L)F151X/152X
FIGURE 3-3:
PIC16(L)F1526, PIC16(L)F1516 AND PIC16(L)F1517 PROGRAM MEMORY MAPPING
8 KW
0000h
Implemented
1FFFh
Maps to
0-1FFFh
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FFh
Configuration Memory
FFFFh
800Bh-81FFh
DS41442B-page 10
Reserved
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
FIGURE 3-4:
PIC16(L)F1527, PIC16(L)F1518 AND PIC16(L)F1519 PROGRAM MEMORY
MAPPING
16KW
0000h
Implemented
3FFFh
Program Memory
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Reserved
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
Maps to
0-3FFFh
7FFFh
8000h
Implemented
8200h
Maps to
8000-81FFh
Configuration Memory
FFFFh
800Bh-81FFh
 2010-2011 Microchip Technology Inc.
Reserved
Advance Information
DS41442B-page 11
PIC16(L)F151X/152X
3.1
User ID Location
MPLAB® IDE only displays the 7 Least
Significant bits (LSb) of each user ID
location, the upper bits are not read. It is
recommended that only the 7 LSbs be
used if MPLAB IDE is the primary tool
used to read these addresses.
Note:
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 8000h-8003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
3.2
Device ID
The device ID word is located at 8006h. This location is
read-only and cannot be erased or modified.
REGISTER 3-1:
DEVICE ID: DEVICE ID REGISTER(1)
R
R
R
R
R
R
DEV<8:3>
bit 13
R
R
bit 8
R
R
R
DEV<2:0>
R
R
R
REV<4:0>
bit 7
bit 0
Legend:
P = Programmable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
x = Bit is unknown
bit 13-5
DEV<8:0>: Device ID bits
These bits are used to identify the part number.
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision.
Note 1:
This location cannot be written.
DS41442B-page 12
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
TABLE 3-1:
DEVICE ID VALUES
DEVICE
DEVICE ID VALUES
DEV
REV
PIC16F1527
0001 0101 101
x xxxx
PIC16F1526
0001 0101 100
x xxxx
PIC16LF1527
0001 0101 111
x xxxx
PIC16LF1526
0001 0101 110
x xxxx
PIC16F1519
0001 0110 111
x xxxx
PIC16F1518
0001 0110 110
x xxxx
PIC16F1517
0001 0110 101
x xxxx
PIC16F1516
0001 0110 100
x xxxx
PIC16F1513
0001 0110 010
x xxxx
PIC16F1512
0001 0111 000
x xxxx
PIC16LF1519
0001 0111 111
x xxxx
PIC16LF1518
0001 0111 110
x xxxx
PIC16LF1517
0001 0111 101
x xxxx
PIC16LF1516
0001 0111 100
x xxxx
PIC16LF1513
0001 0111 010
x xxxx
PIC16LF1512
0001 0111 001
x xxxx
3.3
Configuration Words
There are two Configuration Words, Configuration Word
1 (8007h) and Configuration Word 2 (8008h). The
individual bits within these Configuration Words are
used to enable or disable device functions such as the
Brown-out Reset, code protection and Power-up Timer.
3.4
Calibration Words
The internal calibration values are factory calibrated
and stored in Calibration Words 1 and 2 (8009h,
800Ah).
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 13
PIC16(L)F151X/152X
REGISTER 3-2:
CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
U-1
—
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
bit 8
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit
1 = CLKOUT function is disabled. I/O or oscillator function on CLKOUT pin.
0 = CLKOUT function is enabled on CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register.
bit 5
PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode: on CLKIN pin
110 = ECM: External Clock, Medium-Power mode: on CLKIN pin
101 = ECL: External Clock, Low-Power mode: on CLKIN pin
100 = INTOSC oscillator: I/O function on OSC1 pin
011 = EXTRC oscillator: RC function on OSC1 pin
010 = HS oscillator: High-speed crystal/resonator on OSC2 pin and OSC1 pin
001 = XT oscillator: Crystal/resonator on OSC2 pin and OSC1 pin
000 = LP oscillator: Low-power crystal on OSC2 pin and OSC1 pin
Note
1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
DS41442B-page 14
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
REGISTER 3-3:
CONFIGURATION WORD 2
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
U-1
LVP
DEBUG
LPBOR
BORV
STVREN
—
bit 13
bit 8
U-1
U-1
U-1
R/P-1
U-1
U-1
—
—
—
VCAPEN(2)
—
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = Low-voltage programming enabled
0 = HV on MCLR/VPP must be used for programming
bit 12
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power BOR
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage (VBOR), low trip point selected
0 = Brown-out Reset voltage (VBOR), high trip point selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8-5
Unimplemented: Read as ‘1’
bit 4
VCAPEN: Voltage Regulator Capacitor Enable bits(1)
0 = VCAP functionality is enabled on VCAP pin
1 = All VCAP pin functions are disabled
bit 3-2
Unimplemented: Read as ‘1’
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory (PIC16(L)F1512):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = 000h to 7FFh write-protected, no addresses may be modified by PMCON control
4 kW Flash memory (PIC16(L)F1513):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory (PIC16F/LF1516/1517/1526):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16F/LF1518/1519/1527):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
Note 1:
2:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
Applies to PIC16F151X/152X devices only. On PIC16LF151X/152X, the VCAPEN bit is unimplemented.
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DS41442B-page 15
PIC16(L)F151X/152X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and latched on the falling edge. In
Program/Verify mode both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1
High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
• VPP – First entry mode
• VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD FROM 0V to the
desired operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when Configuration Word 1 has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and ICSPCLK and ICSPDAT pins are
driven by the user application, the device will execute
code. Since this may prevent entry, VPP-first entry
mode is strongly recommended. See the timing
diagram in Figure 8-2.
4.1.2
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2
Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16(L)F151X/152X devices to be programmed using
VDD only, without high voltage. When the LVP bit of
Configuration Word 2 register is set to ‘1’, the lowvoltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
1.
2.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figure 8-8
and Figure 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figure 8-8 and Figure 8-9.
Note:
To enter LVP mode, the LSB of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method
the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired
operating voltage.
Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
DS41442B-page 16
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PIC16(L)F151X/152X
4.3
Program/Verify Commands
The
PIC16(L)F151X/152X
implements
10
programming commands; each six bits in length. The
commands are summarized in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
TABLE 4-1:
COMMAND MAPPING
Mapping
Command
Data/Note
Binary (MSb … LSb)
Hex
Load Configuration
x
0
0
0
0
0
00h
0, data (14), 0
Load Data For Program Memory
x
0
0
0
1
0
02h
0, data (14), 0
Read Data From Program Memory
x
0
0
1
0
0
04h
0, data (14), 0
Increment Address
x
0
0
1
1
0
06h
—
Reset Address
x
1
0
1
1
0
16h
—
Begin Internally Timed Programming
x
0
1
0
0
0
08h
—
Begin Externally Timed Programming
x
1
1
0
0
0
18h
—
End Externally Timed Programming
x
0
1
0
1
0
0Ah
—
Bulk Erase Program Memory
x
0
1
0
0
1
09h
Internally Timed
Row Erase Program Memory
x
1
0
0
0
1
11h
Internally Timed
4.3.1
LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (User ID Locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the address to 8000h and
loads the data latches with one word of data (see
Figure 4-1).
Note:
The only way to get back to the program memory
(address 0) is to exit Program/Verify mode or issue the
Reset Address command after the configuration memory
has been accessed by the Load Configuration command.
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed
Programming or Begin Externally Timed Programming
command.
FIGURE 4-1:
Externally timed writes are not supported
for Configuration and Calibration bits. Any
externally timed write to the Configuration
or Calibration Word will have no effect on
the targeted word.
LOAD CONFIGURATION
1
2
3
4
5
2
1
6
15
16
TDLY
ICSPCLK
ICSPDAT
0
0
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0
0
0
X
0
Advance Information
LSb
MSb 0
DS41442B-page 17
PIC16(L)F151X/152X
4.3.2
LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used
to load one 14-bit word into the data latches. The word
programs into program memory after the Begin
Internally Timed Programming or Begin Externally
Timed Programming command is issued (see
Figure 4-2).
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
4
3
5
2
1
6
16
15
TDLY
ICSPCLK
0
ICSPDAT
4.3.3
1
0
0
0
0
X
LSb
MSb 0
READ DATA FROM PROGRAM
MEMORY
The Read Data from Program Memory command will
transmit data bits out of the program memory map
currently accessed, starting with the second rising edge
of the clock input. The ICSPDAT pin will go into Output
mode on the first falling clock edge, and it will revert to
Input mode (high-impedance) after the 16th falling edge
of the clock. If the program memory is code-protected
(CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3:
READ DATA FROM PROGRAM MEMORY
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
0
0
1
0
0
ICSPDAT
(from device)
X
x
Input
DS41442B-page 18
Advance Information
LSb
MSb
Output
Input
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PIC16(L)F151X/152X
4.3.4
INCREMENT ADDRESS
The address is incremented when this command is
received. It is not possible to decrement the address.
To reset this counter, the user must use the Reset
Address command or exit Program/Verify mode and reenter it. If the address is incremented from address
7FFFh, it will wrap-around to location 0000h. If the
address is incremented from FFFFh, it will wrap-around
to location 8000h.
FIGURE 4-4:
INCREMENT ADDRESS
Next Command
1
2
4
3
2
1
6
5
3
TDLY
ICSPCLK
0
ICSPDAT
1
1
0
0
X
X
Address
4.3.5
X
X
Address + 1
RESET ADDRESS
The Reset Address command will reset the address to
0000h, regardless of the current value. The address is
used in program memory or the configuration memory.
FIGURE 4-5:
RESET ADDRESS
Next Command
1
2
4
3
5
6
2
1
3
TDLY
ICSPCLK
ICSPDAT
0
Address
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1
1
0
1
X
N
Advance Information
X
X
X
0000h
DS41442B-page 19
PIC16(L)F151X/152X
4.3.6
BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time,
TPINT, for the programming to complete.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
The program memory address that is being
programmed is not erased prior to being programmed.
FIGURE 4-6:
BEGIN INTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
1
2
3
6
TPINT
ICSPCLK
ICSPDAT
4.3.7
0
0
0
0
1
X
X
X
X
BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. To complete the programming the End
Externally Timed Programming command must be sent
in the specified time window defined by TPEXT (see
Figure 4-7).
Externally timed writes are not supported for
Configuration and Calibration bits. Any externally timed
write to the Configuration or Calibration Word will have
no effect on the targeted word.
FIGURE 4-7:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
4
3
5
6
2
1
3
TPEXT
ICSPCLK
ICSPDAT
DS41442B-page 20
0
0
0
1
1
X
Advance Information
0
1
0
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PIC16(L)F151X/152X
4.3.8
END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands
(see Figure 4-8).
FIGURE 4-8:
END EXTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
2
1
3
6
TDIS
ICSPCLK
4.3.9
1
0
ICSPDAT
0
1
1
BULK ERASE PROGRAM MEMORY
X
X
X
X
After receiving the Bulk Erase Program Memory
command the erase will not complete until the time
interval, TERAB, has expired.
The Bulk Erase Program Memory command performs
two different functions dependent on the current state
of the address.
Note:
Address 0000h-7FFFh:
Program Memory is erased
The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
Configuration Words are erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
A Bulk Erase Program Memory command should not
be issued when the address is greater than 8008h.
FIGURE 4-9:
BULK ERASE PROGRAM MEMORY
1
2
3
4
5
Next Command
2
1
3
6
TERAB
ICSPCLK
ICSPDAT
1
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0
0
1
0
X
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X
X
X
DS41442B-page 21
PIC16(L)F151X/152X
4.3.10
ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase
an individual row. Refer to Table 4-2 for row sizes of
specific devices and the PC bits used to address them.
If the program memory is code-protected the Row
Erase Program Memory command will be ignored.
When the address is 8000h-8008h the Row Erase
Program Memory command will only erase the user ID
locations regardless of the setting of the CP
Configuration bit.
After receiving the Row Erase Program Memory
command the erase will not complete until the time
interval, TERAR, has expired.
TABLE 4-2:
PROGRAMMING ROW SIZE AND LATCHES
Devices
PIC16(L)F151X/152X
FIGURE 4-10:
PC
Row Size
Number of Latches
<15:5>
32
32
ROW ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
2
1
3
6
TERAR
ICSPCLK
ICSPDAT
DS41442B-page 22
1
0
0
0
1
X
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X
X
X
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PIC16(L)F151X/152X
5.0
PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store
the 14-bit words used for programming. Refer to
Table 4-2 for specific latch information. The data
latches allow the user to write the program words with
a single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration command is
used to load a single data latch. The data latch will hold
the data until the Begin Externally Timed Programming
or Begin Internally Timed Programming command is
given.
The data latches are aligned with the LSbs of the
address. The PC’s address at the time the Begin
Externally Timed Programming or Begin Internally
Timed Programming command is given will determine
which location(s) in memory are written. Writes cannot
cross the physical boundary. For example, with the
PIC16F1527, attempting to write from address 0002h0009h will result in data being written to 0008h-000Fh.
If more than the maximum number of data latches are
written without a Begin Externally Timed Programming
or Begin Internally Timed Programming command, the
data in the data latches will be overwritten. The
following figures show the recommended flowcharts for
programming.
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DS41442B-page 23
PIC16(L)F151X/152X
FIGURE 5-1:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory(1)
Write User IDs
Verify Program
Memory
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1:
See Figure 5-2.
2:
See Figure 5-5.
DS41442B-page 24
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PIC16(L)F151X/152X
FIGURE 5-2:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
Memory(1, 2)
Program Cycle(3)
Read Data
from
Program Memory
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
All Locations
Done?
Yes
Done
Note 1:
This step is optional if device has already been erased or has not been previously programmed.
2:
If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 5-6.
3:
See Figure 5-3 or Figure 5-4.
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DS41442B-page 25
PIC16(L)F151X/152X
FIGURE 5-3:
ONE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)(1)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
Note 1:
Externally timed writes are not supported for Configuration and Calibration bits.
DS41442B-page 26
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PIC16(L)F151X/152X
FIGURE 5-4:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Latch 1
Increment
Address
Command
Load Data
for
Program Memory
Latch 2
Increment
Address
Command
Load Data
for
Program Memory
Latch n
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
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PIC16(L)F151X/152X
FIGURE 5-5:
CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
One-word
Program Cycle(2)
(User ID)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
8004h?
Yes
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 1)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 2)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Note
1:
This step is optional if device is erased or not previously programmed.
2:
See Figure 5-3.
DS41442B-page 28
Advance Information
Done
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PIC16(L)F151X/152X
FIGURE 5-6:
ERASE FLOWCHART
Start
Load Configuration
Bulk Erase
Program Memory
Done
Note:
This sequence does not erase the Calibration Words.
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PIC16(L)F151X/152X
6.0
CODE PROTECTION
7.0
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as all ‘0’. Further programming is disabled for the
program memory (0000h-7FFFh).
HEX FILE USAGE
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
In the hex file there are two bytes per program word
stored in the Intel® INHX32 hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: Configuration
Word 1 is stored at 8007h on the PIC16(L)F151X/
152X. In the hex file this will be referenced as 1000Eh1000Fh).
6.1
7.1
Program Memory
Code protection is enabled by programming the CP bit
in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
Configuration Word
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
7.2
Device ID and Revision
If a device ID is present in the hex file at 1000Ch1000Dh (8006h on the part), the programmer should
verify the device ID (excluding the revision) against the
value read from the part. On a mismatch condition the
programmer should generate a warning message.
DS41442B-page 30
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PIC16(L)F151X/152X
7.3
Checksum Computation
The checksum is calculated by two different methods
dependent on the setting of the CP Configuration bit.
TABLE 7-1:
CONFIGURATION WORD
MASK VALUES
Config. Word 1
Mask
Config. Word 2
Mask
PIC16F1512
3EFFh
3E13h
PIC16F1513
3EFFh
3E13h
PIC16F1516
3EFFh
3E13h
PIC16F1517
3EFFh
3E13h
PIC16F1518
3EFFh
3E13h
PIC16F1519
3EFFh
3E13h
PIC16LF1512
3EFFh
3E03h
PIC16LF1513
3EFFh
3E03h
PIC16LF1516
3EFFh
3E03h
PIC16LF1517
3EFFh
3E03h
PIC16LF1518
3EFFh
3E03h
PIC16LF1519
3EFFh
3E03h
PIC16F1526
3EFFh
3E13h
PIC16F1527
3EFFh
3E13h
PIC16LF1526
3EFFh
3E03h
PIC16LF1527
3EFFh
3E03h
Device
7.3.1
PROGRAM CODE PROTECTION
DISABLED
With the program code protection disabled, the
checksum is computed by reading the contents of the
PIC16(L)F151X/152X program memory locations and
adding up the program memory data starting at address
0000h, up to the maximum user addressable location.
Any Carry bit exceeding 16 bits are ignored.
Additionally, the relevant bits of the Configuration Words
are added to the checksum. All unimplemented
Configuration bits are masked to ‘0’.
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PIC16(L)F151X/152X
EXAMPLE 7-1:
PIC16F1527
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16F1527, BLANK DEVICE
Sum of Memory addresses 0000h-3FFFh(1)
(2)
C000h
Configuration Word 1
3FFFh
Configuration Word 1 mask(3)
3EFFh
(2)
Configuration Word 2
3FFFh
Configuration Word 2 mask(3)
3E13h
Checksum
= C000h + (3FFFh and 3EFFh) + (3FFFh and 3E13h)
= C000h + 3EFFh + 3E13h
= 3D12h
Note 1:
2:
3:
Sum of memory addresses = (Total number of program memory address locations) x (3FFFh) = C000h,
truncated to 16 bits.
Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
Configuration Word 1 and 2 Mask = all bits are set to ‘1’, except for unimplemented bits that are ‘0’.
EXAMPLE 7-2:
PIC16LF1527
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16LF1527, 00AAh AT FIRST AND LAST ADDRESS
Sum of Memory addresses 0000h-3FFFh(1)
(2)
4156h
Configuration Word 1
3FFFh
Configuration Word 1 mask(3)
3EFFh
Configuration Word
2(2)
3FFFh
Configuration Word 2 mask(4)
Checksum
3E03h
= 4156h + (3FFFh and 3EFFh) + (3FFFh and 3E03h)
= 4156h + 3EFFh + 3E03h
= BE58h
Note 1:
2:
3:
4:
Total number of Program memory address locations: 3FFFh + 1 = 4000h. Then, 4000h - 2 = 3FFEh.
Thus, [(3FFEh x 3FFFh) + (2 x 00AAh)] = 4156h, truncated to 16 bits.
Configuration Word 1 and 2 = all bits are ‘1’; thus, code-protect is disabled.
Configuration Word 1 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented bits
that are ‘0’.
On the PIC16LF1527 device, the VCAPEN bit is not implemented in Configuration Word 2; Thus, all
unimplemented bits are ‘0’.
DS41442B-page 32
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PIC16(L)F151X/152X
7.3.2
PROGRAM CODE PROTECTION
ENABLED
With the program code protection enabled, the
checksum is computed in the following manner: The
Least Significant nibble of each user ID is used to
create a 16-bit value. The masked value of user ID
location 8000h is the Most Significant nibble. This sum
of user IDs is summed with the Configuration Words (all
unimplemented Configuration bits are masked to ‘0’).
EXAMPLE 7-3:
PIC16F1527
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16F1527, BLANK DEVICE
Configuration Word 1(2)
3F7Fh
Configuration Word 1 mask(3)
3EFFh
Configuration Word 2(2)
3FFFh
Configuration Word 2 mask(3)
3E13h
User ID (8000h)(1)
0006h
(8001h)(1)
0007h
User ID (8002h)(1)
0001h
User ID
User ID (8003h)
(1)
Sum of User IDs(4)
0002h
= (0006h and 000Fh) << 12 + (0007h and 000Fh) << 8 +
(0001h and 000Fh) << 4 + (0002h and 000Fh)
= 6000h + 0700h + 0010h + 0002h
= 6712h
Checksum
= (3F7Fh and 3EFFh) + (3FFFh and 3E13h) + Sum of User IDs
= 3E7Fh +3713h + 6712h
= DCA4h
Note 1:
2:
3:
4:
User ID values in this example are random values.
Configuration Word 1 and 2 = all bits are ‘1’ except the code-protect enable bit.
Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented
bits which read ‘0’.
<< = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on, until
the LSb of the last user ID value becomes the LSb of the sum of user IDs.
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 33
PIC16(L)F151X/152X
EXAMPLE 7-4:
PIC16LF1527
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16LF1527, 00AAh AT FIRST AND LAST ADDRESS
Configuration Word 1(2)
3F7Fh
Configuration Word 1 mask
(3)
Configuration Word 2(2)
3EFFh
3FFFh
Configuration Word 2 mask
(3), (5)
3E03h
User ID (8000h)(1)
000Eh
User ID (8001h)(1)
0008h
User ID (8002h)(1)
0005h
User ID (8003h)
(1)
Sum of User IDs(4)
0008h
= (000Eh and 000Fh) << 12 + (0008h and 000Fh) << 8 +
(0005h and 000Fh) << 4 + (0008h and 000Fh)
= E000h + 0800h + 0050h + 0008h
= E858h
Checksum
= (3F7Fh and 3EFFh) + (3FFFh and 3E03h) + Sum of User IDs
= 3E7Fh +3E03h + E858h
= 64DAh
Note 1:
2:
3:
4:
5:
User ID values in this example are random values.
Configuration Word 1 and 2 = all bits are ‘1’ except the code-protect enable bit.
Configuration Word 1 and 2 Mask = all Configuration Word bits are set to ‘1’, except for unimplemented
bits which read ‘0’.
<< = shift left, thus the LSb of the first user ID value is the MSb of the sum of user IDs and so on, until
the LSb of the last user ID value becomes the LSb of the sum of user IDs.
On the PIC16LF1527 device, the VCAPEN bit is not implemented in Configuration Word 2; thus, all
unimplemented bits are ‘0’.
DS41442B-page 34
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
8.0
ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute
maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
5.5
V
3.6
V
VDDMAX
VDDMAX
V
V
VPEW
VPBE
Supply Voltages and Currents
PIC16F151X
2.3
—
PIC16F152X
Supply Voltage
(VDDMIN, VDDMAX)
PIC16LF151X
1.8
—
PIC16LF152X
Read/Write and Row Erase operations
VDDMIN
—
Bulk Erase operations
2.7
—
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
3.0
mA
VDD
Conditions/Comments
VPP
IPP
Current on MCLR/VPP
—
—
600
A
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
—
—
1.0
s
0.8 VDD
—
—
V
—
VDD-0.7
VDD-0.7
VDD-0.7
—
0.2 VDD
V
—
—
V
—
—
VSS+0.6
VSS+0.6
VSS+0.6
V
I/O pins
VIH
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input high
level
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
ICSPDAT output high level
VOH
ICSPDAT output low level
VOL
Programming Mode Entry and Exit
Programing mode entry setup time: ICSPCLK,
TENTS
100
—
—
ICSPDAT setup time before VDD or MCLR
Programing mode entry hold time: ICSPCLK,
TENTH
250
—
—
ICSPDAT hold time after VDD or MCLR
Serial Program/Verify
TCKL
Clock Low Pulse Width
100
—
—
Clock High Pulse Width
100
—
—
TCKH
TDS
Data in setup time before clock
100
—
—
TDH
Data in hold time after clock
100
—
—
Clock to data out valid (during a
0
—
80
TCO
Read Data command)
Clock to data low-impedance (during a
TLZD
0
—
80
Read Data command)
Clock to data high-impedance (during a
THZD
0
—
80
Read Data command)
Data input not driven to next clock input (delay
TDLY
required between command/data or command/
1.0
—
—
command)
Bulk Erase cycle time
—
—
5
TERAB
TERAR
Row Erase cycle time
—
—
2.5
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
 2010-2011 Microchip Technology Inc.
Advance Information
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
ns
s
ns
ns
ns
ns
ns
ns
ns
s
ms
ms
DS41442B-page 35
PIC16(L)F151X/152X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Internally timed programming operation time
TPINT
TPEXT
Min.
Typ.
Max.
Units
—
—
1.0
—
—
—
2.5
5
2.1
ms
ms
ms
Externally timed programming pulse
Time delay from program to compare
300
—
—
TDIS
(HV discharge time)
TEXIT
Time delay when exiting Program/Verify mode
1
—
—
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
8.1
AC Timing Diagrams
FIGURE 8-1:
FIGURE 8-3:
PROGRAMMING MODE
ENTRY – VDD FIRST
TENTS
Conditions/Comments
Program memory
Configuration Words
Note 1
s
s
PROGRAMMING MODE
EXIT – VPP LAST
TEXIT
VIHH
TENTH
VPP
VIHH
VIL
VPP
VDD
VIL
ICSPDAT
VDD
ICSPCLK
ICSPDAT
ICSPCLK
FIGURE 8-4:
PROGRAMMING MODE
EXIT – VDD LAST
TEXIT
FIGURE 8-2:
PROGRAMMING MODE
ENTRY – VPP FIRST
TENTS
VIHH
VPP
VIL
VDD
TENTH
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
ICSPDAT
ICSPCLK
DS41442B-page 36
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
FIGURE 8-5:
CLOCK AND DATA
TIMING
TCKL
TCKH
ICSPCLK
TDS TDH
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
FIGURE 8-6:
WRITE COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
X
X
X
X
X
1
6
2
15
16
ICSPCLK
ICSPDAT
0 LSb
X
0
Next
Command
Payload
Command
FIGURE 8-7:
MSb
READ COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
X
ICSPDAT
(from Programmer)
X
X
X
X
6
2
1
15
16
ICSPCLK
X
x
ICSPDAT
(from Device)
Command
 2010-2011 Microchip Technology Inc.
Advance Information
LSb
MSb
Payload
0
Next
Command
DS41442B-page 37
PIC16(L)F151X/152X
FIGURE 8-8:
LVP ENTRY (POWERED)
VDD
MCLR
TENTS
TENTH
33 clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
LSb of Pattern
0
ICSPDAT
FIGURE 8-9:
MSb of Pattern
1
2
...
31
LVP ENTRY (POWERING UP)
VDD
MCLR
TENTH
33 Clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
LSb of Pattern
0
ICSPDAT
Note 1:
1
2
...
MSb of Pattern
31
Sequence matching can start with no edge on MCLR first.
DS41442B-page 38
Advance Information
 2010-2011 Microchip Technology Inc.
PIC16(L)F151X/152X
APPENDIX A:
REVISION HISTORY
Revision A (08/2010)
Original release of this document.
Revision B (09/2011)
Added PIC16(L)F1512/1513 devices; Added new
Figures 3-1 and 3-2; Updated Registers 3-1, 3-2 and 33 to new format; Updated Register 3-3 to add 2 kW and
4 kW Flash memory; Added Notes to Examples 7-1 to
7-4; Updated Table 8-1; Other minor corrections.
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 39
PIC16(L)F151X/152X
NOTES:
DS41442B-page 40
Advance Information
 2010-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-635-8
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010-2011 Microchip Technology Inc.
Advance Information
DS41442B-page 41
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DS41442B-page 42
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Advance Information
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