PIC16(L)F177X Memory Programming

PIC16(L)F177X
PIC16(L)F177X Memory Programming Specification
This document includes the programming specifications for the following devices:
• PIC16F1773
• PIC16LF1773
• PIC16F1776
• PIC16LF1776
• PIC16F1777
• PIC16LF1777
• PIC16F1778
• PIC16LF1778
• PIC16F1779
• PIC16LF1779
1.0
OVERVIEW
The device can be programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the
low-voltage ICSP method.
1.1
1.1.1
Hardware Requirements
HIGH-VOLTAGE ICSP PROGRAMMING
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/
VPP pin.
1.1.2
LOW-VOLTAGE ICSP PROGRAMMING
In Low-Voltage ICSP mode, the PIC16(L)F177X devices can be programmed using a single VDD source in the operating
range. The MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal
operating voltage.
1.1.2.1
Single-Supply ICSP Programming
The LVP bit in Configuration Word 2 enables single-supply (Low-Voltage) ICSP programming. The LVP bit defaults to
‘1’ (enabled) from the factory. The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode,
where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to ‘0’, only the High-Voltage ICSP mode is
available and only the High-Voltage ICSP mode can be used to program the device.
Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH
to the MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port pin
can no longer be used as a general purpose input.
 2015 Microchip Technology Inc.
DS40001792A-page 1
PIC16(L)F177X
1.2
Pin Utilization
Five pins are needed for ICSP programming. The pins are listed in Table 1-1.
TABLE 1-1:
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
ICSPCLK
ICSPCLK
I
ICSPDAT
ICSPDAT
I/O
MCLR/VPP
Program/Verify mode
Pin Description
Clock Input – Schmitt Trigger Input
Data Input/Output – Schmitt Trigger Input
(1)
Program Mode Select/Programming Power Supply
P
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
DS40001792A-page 2
 2015 Microchip Technology Inc.
PIC16(L)F177X
2.0
DEVICE PINOUTS
The pin diagrams for the PIC16L(F)1773/6/8 family are shown in Figure 2-1 and Figure 2-2.
The pin diagrams for the PIC16L(F)1777/9 family are shown in Figure 2-3, Figure 2-4 and Figure 2-5.
The pins that are required for programming are listed in Table 1-1 and shown in bold lettering in the pin diagrams.
28-PIN SPDIP, SOIC, SSOP
28
RB7/ICSPDAT
RA0
2
27
RB6/ICSPCLK
RA1
3
26
RB5
RA2
4
25
RB4
RA3
5
24
RB3
RA4
6
23
RB2
22
RB1
21
RB0
20
AVDD
19
VSS
18
RC7
RC6
RA5
AVSS
7
8
RA7
9
RA6
10
RC0
11
RC1
12
17
RC2
13
16
RC5
14
15
RC4
RC3
28-PIN UQFN (6x6x0.5 mm)
RA1
RA0
FIGURE 2-2:
PIC16(L)F1773/6/8
1
VPP/MCLR/RE3
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
FIGURE 2-1:
28 27 26 25 24 23 22
 2015 Microchip Technology Inc.
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
AVDD
VSS
RC7
RC1
RC2
RC3
RC4
RC5
RC6
1
2
3
PIC16(L)F1773/6/8
4
5
6
7
8 9 10 11 12 13 14
RC0
RA2
RA3
RA4
RA5
AVSS
RA7
RA6
DS40001792A-page 3
PIC16(L)F177X
VPP/MCLR/RE3
1
40
RB7/ICSPDAT
RA0
2
39
RB6/ICSPCLK
RA1
3
38
RB5
RA2
4
37
RB4
RA3
5
36
RB3
RA4
6
35
RB2
RA5
RE0
7
34
RB1
8
33
RB0
RE1
9
RE2
10
AVDD
11
AVSS
12
32
VDD
31
VSS
30
RD7
29
RD6
28
RD5
RA7
13
RA6
14
27
RD4
RC0
15
26
RC7
RC1
16
25
RC6
RC2
17
24
RC5
RC3
18
23
RD0
19
22
RC4
RD3
RD1
20
21
RD2
40-PIN UQFN (6x6x0.5 mm)
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
FIGURE 2-4:
40-PIN PDIP
PIC16(L)F1777/9
FIGURE 2-3:
RC7 1
RD4 2
40 39 38 37 36 35 34 33 32 31
30
RD5 3
RD6 4
RD7 5
AVSS
AVDD
RB0
RB1
RB2
6
29
28
27
PIC16(L)F1777/9
26
7
25
8
24
23
9
22
21
10
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
DS40001792A-page 4
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
11 12 13 14 15 16 17 18 19 20
 2015 Microchip Technology Inc.
PIC16(L)F177X
44-PIN TQFP
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
FIGURE 2-5:
RC7
RD4
RD5
RD6
RD7
AVSS
AVDD
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
PIC16(L)F1777/9
27
26
25
24
23
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
 2015 Microchip Technology Inc.
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
AN0/RA0
AN1/RA1
RA2
RA3
NC
12 13 14 15 16 17 18 19 20 21 22
DS40001792A-page 5
PIC16(L)F177X
3.0
MEMORY MAP
The memory is separated into two sections: program memory and configuration memory.
FIGURE 3-1:
PIC16(L)F1773 PROGRAM MEMORY MAPPING
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Reserved
800Fh
Calibration Word 5
8010h
Calibration Word 6
8011h
Calibration Word 7
8012h
Calibration Word 8
8013h
Calibration Word 9(1)
8014h
Calibration Word 10
8015h
Calibration Word 11
8016h
Calibration Word 12
8017h
Calibration Word 13
8018h
Calibration Word 14
8019h - 81FFh
4 KW
0000h
0FFFh
Implemented
Maps to
0-0FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FF
Configuration Memory
FFFFh
Reserved
Note 1: This location is reserved in the PIC16(L)F1773.
DS40001792A-page 6
 2015 Microchip Technology Inc.
PIC16(L)F177X
FIGURE 3-2:
PIC16(L)F1776/7 PROGRAM MEMORY MAPPING
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Reserved
800Fh
Calibration Word 5
8010h
Calibration Word 6
8011h
Calibration Word 7
8012h
Calibration Word 8
8013h
Calibration Word 9
8014h
Calibration Word 10
8015h
Calibration Word 11
8016h
Calibration Word 12
8017h
Calibration Word 13
8018h
Calibration Word 14
8 KW
0000h
1FFFh
Implemented
Maps to
0-1FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FF
Configuration Memory
FFFFh
8019h - 81FFh
 2015 Microchip Technology Inc.
Reserved
DS40001792A-page 7
PIC16(L)F177X
FIGURE 3-3:
PIC16(L)F1778/9 PROGRAM MEMORY MAPPING
16 KW
8000h
User ID Location
8001h
User ID Location
8002h
User ID Location
8003h
User ID Location
8004h
Reserved
8005h
Revision ID
8006h
Device ID
8007h
Configuration Word 1
8008h
Configuration Word 2
8009h
Calibration Word 1
800Ah
Calibration Word 2
800Bh
Calibration Word 3
800Ch
Calibration Word 4
800Dh
Reserved
800Eh
Reserved
800Fh
Calibration Word 5
8010h
Calibration Word 6
8011h
Calibration Word 7
8012h
Calibration Word 8
8013h
Calibration Word 9
8014h
Calibration Word 10
8015h
Calibration Word 11
8016h
Calibration Word 12
8017h
Calibration Word 13
8018h
Calibration Word 14
8019h - 81FFh
0000h
3FFFh
Implemented
Maps to
0-1FFFh
7FFFh
8000h
Program Memory
Implemented
8200h
Maps to
8000-81FF
Configuration Memory
FFFFh
Reserved
Note 1: This location is reserved in the PIC16(L)F1778/9.
DS40001792A-page 8
 2015 Microchip Technology Inc.
PIC16(L)F177X
3.1
User ID Location
A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to
8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location
may be read with code protection enabled or disabled.
MPLAB® IDE only displays the seven Least Significant bits (LSb) of each user ID location; the upper bits
are not read. It is recommended that only the seven LSbs be used, if MPLAB IDE is the primary tool for
reading these addresses.
Note:
3.2
Device/Revision ID
The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are
read-only and cannot be erased or modified.
REGISTER 3-1:
DEVICEID: DEVICE ID REGISTER(1)
R
R
R
R
R
R
DEV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
x = Bit is unknown
‘1’ = Bit is set
DEV<13:0>: Device ID bits
Refer to Table 3-1 to determine what these bits will read on which device. A value of 3FFFh is invalid.
Note 1:
This location cannot be written.
REGISTER 3-2:
REVISIONID: REVISION ID REGISTER(1)
R
R
R
R
R
R
REV<13:8>
bit 13
R
R
bit 8
R
R
R
R
R
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
bit 13-0
‘1’ = Bit is set
x = Bit is unknown
REV<13:0>: Revision ID bits
These bits are used to identify the device revision.
Note 1: This location cannot be written.
 2015 Microchip Technology Inc.
DS40001792A-page 9
PIC16(L)F177X
TABLE 3-1:
DEVICE ID VALUES
Device
Device ID
Revision ID
PIC16F1773
308Ah
2xxxh
PIC16LF1773
308Ch
2xxxh
PIC16F1776
308Bh
2xxxh
PIC16LF1776
308Dh
2xxxh
PIC16F1777
308Eh
2xxxh
PIC16LF1777
3091h
2xxxh
PIC16F1778
308Fh
2xxxh
PIC16LF1778
3092h
2xxxh
PIC16F1779
3090h
2xxxh
PIC16LF1779
3093h
2xxxh
3.3
Configuration Words
The device has two Configuration Words, Configuration Word 1 (8007h) and Configuration Word 2 (8008h). The individual
bits within these Configuration Words are used to enable or disable device functions such as the Brown-out Reset, code
protection and Power-up Timer.
3.4
Calibration Words
The internal calibration values are factory calibrated and stored in the Calibration Word locations. See Figure 3-1 for
address information.
The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration
Words.
REGISTER 3-3:
CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
U-1
—
bit 8
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = ON
Fail-Safe Clock Monitor is enabled
0 = OFF Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit
1 = ON
Internal/External Switchover mode is enabled
0 = OFF Internal/External Switchover mode is disabled
Note 1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
DS40001792A-page 10
 2015 Microchip Technology Inc.
PIC16(L)F177X
REGISTER 3-3:
CONFIGURATION WORD 1 (CONTINUED)
bit 11
CLKOUTEN: Clock Out Enable bit
1 = OFF CLKOUT function is disabled. I/O or oscillator function on CLKOUT
0 = ON
CLKOUT function is enabled on CLKOUT
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = ON
BOR enabled
10 = SLEEP
BOR enabled during operation and disabled in Sleep
01 = SBODEN
BOR controlled by SBOREN bit of the BORCON register
00 = OFF
BOR disabled
bit 8
Unimplemented: Read as ‘1’
bit 7
CP: Code Protection bit(2)
1 = OFF Program memory code protection is disabled
0 = ON
Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1 (ON):
This bit is ignored.
If LVP bit = 0 (OFF):
1 = ON
MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = OFF MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under
control of port pin’s WPU control bit.
bit 5
PWRTE: Power-up Timer Enable bit(1)
1 = OFF PWRT disabled
0 = ON
PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11 = ON
WDT enabled
10 = SLEEP
WDT enabled while running and disabled in Sleep
01 = SWDTEN
WDT controlled by the SWDTEN bit in the WDTCON register
00 = OFF
WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = ECH
External Clock, High-Power mode: CLKIN on OSC1/CLKIN
110 = ECM
External Clock, Medium-Power mode: CLKIN on OSC1/CLKIN
101 = ECL
External Clock, Low-Power mode: CLKIN on OSC1/CLKIN
100 = INTOSC
Internal HFINTOSC, I/O function on OSC1/CLKIN
011 = EXTRC
External RC oscillator, RC function on OSC1/CLKIN
010 = HS
High-speed crystal/resonator on OSC2/CLKOUT pin and OSC1/CLKIN
001 = XT
Crystal/resonator on OSC2/CLKOUT pin and OSC1/CLKIN
000 = LP
Low-power crystal on OSC2/CLKOUT pin and OSC1/CLKIN
Note 1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
 2015 Microchip Technology Inc.
DS40001792A-page 11
PIC16(L)F177X
REGISTER 3-4:
CONFIGURATION WORD 2
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
bit 13
bit 8
R/P-1
U-1
U-1
U-1
U-1
R/P-1
ZCD
—
—
—
—
PPS1WAY
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = ON
Low-voltage programming enabled
0 = OFF
MCLR/VPP must be used for programming high voltage
bit 12
DEBUG: In-Circuit Debugger Mode bit
1 = OFF
In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = ON
In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power Brown-out Reset Enable bit
1 = OFF
Low-Power Brown-out Reset is disabled
0 = ON
Low-Power Brown-out Reset is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit(2)
1 = LOW
Brown-out Reset voltage (VBOR), low trip point selected
0 = HIGH Brown-out Reset voltage (VBOR), high trip point selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON
Stack Overflow or Underflow will cause a Reset
0 = OFF
Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1 = ON
4xPLL enabled
0 = OFF
4xPLL disabled
bit 7
ZCD: Zero-Cross Detect Enable bit
1 = OFF
Zero-cross detection is disabled on POR. Zero-cross detection can be controlled by
software.
0 = ON
Zero-cross detection is always enabled. Software cannot disable zero-cross detection.
bit 6-3
Unimplemented: Read as ‘1’
bit 2
PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = ON
The PPSLOCK bit is permanently set after the first access sequence that sets it.
0 = OFF
The PPSLOCK bit can be set and cleared as needed by the PPSLOCK access sequence.
Note 1:
2:
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
See VBOR parameter for specific trip point voltages.
DS40001792A-page 12
 2015 Microchip Technology Inc.
PIC16(L)F177X
REGISTER 3-4:
bit 1-0
Note 1:
2:
CONFIGURATION WORD 2 (CONTINUED)
WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW Flash memory (PIC16(L)F1773):
11 = OFF Write protection off
10 = BOOT 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = HALF 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = ALL 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory (PIC16(L)F1776/7):
11 = OFF Write protection off
10 = BOOT 0000h to 03FFh write-protected, 0400h to 1FFFh may be modified by PMCON
control
01 = HALF 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON
control
00 = ALL 0000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16(L)F1778/9):
11 = OFF Write protection off
10 = BOOT 0000h to 01FFh write-protected, 0200h to 3FFFh may be modified by PMCON
control
01 = HALF 0000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON
control
00 = ALL 0000h to 3FFFh write-protected, no addresses may be modified by PMCON control
The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
See VBOR parameter for specific trip point voltages.
 2015 Microchip Technology Inc.
DS40001792A-page 13
PIC16(L)F177X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in
serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data
words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge.
In Program/Verify mode, both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the
device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all
I/Os are automatically configured as high-impedance inputs and the address is cleared.
4.1
High-Voltage Program/Verify Mode Entry and Exit
There are two different methods of entering Program/Verify mode via high-voltage:
• VPP – First Entry mode
• VDD – First Entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method, the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired operating voltage.
The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, when
the Configuration Word has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal
oscillator is selected (FOSC = 100), and RA0 and RA1 are driven by the user application, the device will execute code.
Since this may prevent entry, VPP-First Entry mode is strongly recommended. See the timing diagram in Figure 8-2.
4.1.2
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method, the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired operating voltage.
Raise the voltage on MCLR from VDD or below to VIHH.
The VDD-first method is useful when programming the device when VDD is already applied, for it is not necessary to
disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-1.
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figure 8-3 and Figure 8-4.
Note:
In systems where the VDD and MCLR/VPP signals can be controlled independently the VPP-last method of
exit should be used to keep the device in Reset, thereby preventing any issues that may be caused by
program execution.
DS40001792A-page 14
 2015 Microchip Technology Inc.
PIC16(L)F177X
4.2
Low-Voltage Programming (LVP) Mode
The Low-Voltage Programming mode allows the PIC16(L)F177X devices to be programmed using VDD only, without
high voltage. When the LVP bit of the Configuration Word 2 register is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done
while in the High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps:
MCLR is brought to VIL.
A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.
1.
2.
The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily
remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least
Significant bit of the Least Significant nibble must be shifted in first.
Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained.
For low-voltage programming timing, see Figure 8-8 and Figure 8-9.
Exiting Program/Verify mode is done by no longer driving MCLR to VIL. See Figure 8-8 and Figure 8-9.
Note:
4.3
To enter LVP mode, the LSb of the Least Significant nibble must be shifted in first. This differs from entering
the key sequence on other parts.
Program/Verify Commands
These devices implement 13 programming commands, each six bits in length. The commands are summarized in
Table 4-1.
Commands that have data associated with them are specified to have a minimum delay of TDLY between the command
and the data. After this delay, 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock
is for the Start bit and the last clock is for the Stop bit.
TABLE 4-1:
COMMAND MAPPING
Mapping
Command
Data/Note
Binary (MSb … LSb)
Hex
Load Configuration
x
0
0
0
0
0
00h
0, data (14), 0
Load Data for Program Memory
x
0
0
0
1
0
02h
0, data (14), 0
Read Data from Program Memory
x
0
0
1
0
0
04h
0, data (14), 0
Increment Address
x
0
0
1
1
0
06h
—
Reset Address
x
1
0
1
1
0
16h
—
Begin Internally Timed Programming
x
0
1
0
0
0
08h
—
Begin Externally Timed Programming
x
1
1
0
0
0
18h
—
End Externally Timed Programming
x
0
1
0
1
0
0Ah
—
Bulk Erase Program Memory
x
0
1
0
0
1
09h
Internally Timed
Row Erase Program Memory
x
1
0
0
0
1
11h
Internally Timed
 2015 Microchip Technology Inc.
DS40001792A-page 15
PIC16(L)F177X
4.3.1
LOAD CONFIGURATION
The Load Configuration command is used to access the configuration memory (User ID Locations, Configuration Words,
Calibration Words). The Load Configuration command sets the address to 8000h and loads the data latches with one
word of data (see Figure 4-1).
After issuing the Load Configuration command, use the Increment Address command until the proper address to be
programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or
Begin Externally Timed Programming command.
Note:
Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write
to the Configuration or Calibration Word will have no effect on the targeted word.
The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address
command after the configuration memory has been accessed by the Load Configuration command.
FIGURE 4-1:
LOAD CONFIGURATION
1
2
3
5
4
2
1
6
16
15
TDLY
ICSPCLK
ICSPDAT
4.3.2
0
0
0
0
0
LSb
0
X
MSb 0
LOAD DATA FOR PROGRAM MEMORY
The Load Data for Program Memory command is used to load one 14-bit word into the data latches. The word programs
into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is
issued (see Figure 4-2).
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
3
4
5
2
1
6
15
16
TDLY
ICSPCLK
ICSPDAT
DS40001792A-page 16
0
1
0
0
0
X
0
LSb
MSb 0
 2015 Microchip Technology Inc.
PIC16(L)F177X
4.3.3
READ DATA FROM PROGRAM MEMORY
The Read Data from Program Memory command will transmit data bits out of the program memory map currently
accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first
falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program
memory is code-protected (CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3:
READ DATA FROM PROGRAM MEMORY
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
0
1
0
0
0
X
ICSPDAT
(from device)
x
MSb
Input
Output
Input
4.3.4
LSb
INCREMENT ADDRESS
The address is incremented when this command is received. It is not possible to decrement the address. To reset this
counter, the user must use the Reset Address command or exit Program/Verify mode and re-enter it.
If the address is incremented from address 7FFFh, it will wrap-around to location 0000h. If the address is incremented
from FFFFh, it will wrap-around to location 8000h (see Figure 4-4).
FIGURE 4-4:
INCREMENT ADDRESS
Next Command
1
2
3
4
2
1
6
5
3
TDLY
ICSPCLK
0
1
1
0
0
ICSPDAT
Address
 2015 Microchip Technology Inc.
X
X
X
X
Address + 1
DS40001792A-page 17
PIC16(L)F177X
4.3.5
RESET ADDRESS
The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in
program memory or the configuration memory. See Figure 4-5.
FIGURE 4-5:
RESET ADDRESS
Next Command
1
2
4
3
5
2
1
6
3
TDLY
ICSPCLK
0
1
1
0
1
X
X
X
X
ICSPDAT
4.3.6
0000h
N
Address
BEGIN INTERNALLY TIMED PROGRAMMING
A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming
command. Programming of the addressed memory will begin after this command is received. An internal timing
mechanism executes the write. The user must allow for the program cycle time, TPINT, in order for the programming to
complete.
The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used
to start the programming.
The program memory address that is being programmed is not erased prior to being programmed. See Figure 4-6.
FIGURE 4-6:
BEGIN INTERNALLY TIMED PROGRAMMING
1
2
5
4
3
Next Command
1
2
3
6
TPINT
ICSPCLK
ICSPDAT
DS40001792A-page 18
0
0
0
1
0
X
X
X
X
 2015 Microchip Technology Inc.
PIC16(L)F177X
4.3.7
BEGIN EXTERNALLY TIMED PROGRAMMING
A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming
command. Programming of the addressed memory will begin after this command is received. To complete the
programming, the End Externally Timed Programming command must be sent in the specified time window defined by
TPEXT. See Figure 4-7.
Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write to the
Configuration or Calibration Word will have no effect on the targeted word.
FIGURE 4-7:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
5
4
3
1
6
2
3
TPEXT
ICSPCLK
0
ICSPDAT
4.3.8
0
0
1
0
X
1
1
0
END EXTERNALLY TIMED PROGRAMMING
This command is required after a Begin Externally Timed Programming command is given. This command must be sent
within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent.
After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending
the next command. This delay is longer than the delay ordinarily required between other commands. See Figure 4-8.
FIGURE 4-8:
END EXTERNALLY TIMED PROGRAMMING
1
2
4
3
5
Next Command
2
1
3
6
TDIS
ICSPCLK
ICSPDAT
 2015 Microchip Technology Inc.
0
1
0
1
1
X
X
X
X
DS40001792A-page 19
PIC16(L)F177X
4.3.9
BULK ERASE PROGRAM MEMORY
The Bulk Erase Program Memory command performs two different functions, dependent on the current state of the
address.
Address 0000h-7FFFh:
Program Memory is erased
Configuration Words are erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
A Bulk Erase Program Memory command should not be issued when the address is greater than 8008h.
After receiving the Bulk Erase Program Memory command, the erase will not complete until the time interval, TERAB,
has expired. See Figure 4-9.
Note:
The Code Protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command.
FIGURE 4-9:
BULK ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
1
2
3
6
TERAB
ICSPCLK
ICSPDAT
4.3.10
1
0
0
0
1
X
X
X
X
ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase an individual row. Refer to Table 4-2 for row sizes of specific
devices and the PC bits used to address them. If the program memory is code-protected, the Row Erase Program
Memory command will be ignored. When the address is 8000h-8008h, the Row Erase Program Memory command will
only erase the user ID locations regardless of the setting of the CP Configuration bit.
After receiving the Row Erase Program Memory command, the erase will not complete until the time interval, TERAR,
has expired. See Figure 4-10.
FIGURE 4-10:
ROW ERASE PROGRAM MEMORY
1
2
5
4
3
Next Command
2
1
3
6
TERAR
ICSPCLK
ICSPDAT
DS40001792A-page 20
1
0
0
0
1
X
X
X
X
 2015 Microchip Technology Inc.
PIC16(L)F177X
TABLE 4-2:
PROGRAMMING ROW AND LATCH SIZES
Devices
PC
Erase Row Size
(Number of 14-bit Words)
Write Row Size
(Number of 14-bit Latches)
<15:5>
32
32
PIC16F1773
PIC16F1776
PIC16F1777
PIC16F1778
PIC16F1779
PIC16LF1773
PIC16LF1776
PIC16LF1777
PIC16LF1778
PIC16LF1779
 2015 Microchip Technology Inc.
DS40001792A-page 21
PIC16(L)F177X
5.0
PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store the 14-bit words used for programming. Refer to Table 4-2 for
specific latch information. The data latches allow the user to write the program words with a single Begin Externally
Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load
Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally
Timed Programming or the Begin Internally Timed Programming commands are given.
The data latches are aligned with the LSbs of the address. The PC address bits indicated in Table 4-2 at the time the
Begin Externally Timed Programming or the Begin Internally Timed Programming commands are given will determine
which memory row is written. Writes cannot cross a physical row boundary. For example, attempting to write from
address 0002h-0021h in a 32-latch device will result in data being written to 0020h-003Fh.
If more than the maximum number of latches are written without a Begin Externally Timed Programming or a Begin
Internally Timed Programming command, the data in the data latches will be overwritten. Figure 5-1 through
Figure 5-6 show the recommended flowcharts for programming.
FIGURE 5-1:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory(1)
Write User IDs
Verify Program
Memory
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1:
See Figure 5-2.
2:
See Figure 5-5.
DS40001792A-page 22
 2015 Microchip Technology Inc.
PIC16(L)F177X
FIGURE 5-2:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
Memory(1, 2)
Program Cycle(3)
Read Data
from
Program Memory
No
Data Correct?
Report
Programming
Failure
Yes
Increment
Address
Command
No
All Locations
Done?
Yes
Done
Note 1:
This step is optional if the device has already been erased or has not been previously programmed.
2:
If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6.
3:
See Figure 5-3 or Figure 5-4.
 2015 Microchip Technology Inc.
DS40001792A-page 23
PIC16(L)F177X
FIGURE 5-3:
ONE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Begin
Programming
Command
(Internally timed)
Wait TPINT
Begin
Programming
Command
(Externally timed)(1)
Wait TPEXT
End
Programming
Command
Wait TDIS
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
DS40001792A-page 24
 2015 Microchip Technology Inc.
PIC16(L)F177X
FIGURE 5-4:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Latch 1
Increment
Address
Command
Load Data
for
Program Memory
Latch 2
Increment
Address
Command
Load Data
for
Program Memory
Latch 32
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End
Programming
Command
Wait TDIS
 2015 Microchip Technology Inc.
DS40001792A-page 25
PIC16(L)F177X
FIGURE 5-5:
CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
One-word
Program Cycle(2)
(User ID)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
No
Address =
8004h?
Yes
Increment
Address
Command
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 1)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 2)
Read Data
From Program
Memory Command
Data Correct?
No
Report
Programming
Failure
Yes
Note
1:
This step is optional if the device is erased or not previously programmed.
2:
See Figure 5-3.
DS40001792A-page 26
Done
 2015 Microchip Technology Inc.
PIC16(L)F177X
FIGURE 5-6:
ERASE FLOWCHART
Start
Load Configuration
Bulk Erase
Program Memory
Done
Note:
This sequence does not erase the Calibration Words.
 2015 Microchip Technology Inc.
DS40001792A-page 27
PIC16(L)F177X
6.0
CODE PROTECTION
Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program
memory locations (0000h-7FFFh) read as ‘0’. Further programming is disabled for the program memory (0000h-7FFFh).
Program memory can still be programmed and read during program execution.
The user ID locations and Configuration Words can be programmed and read out regardless of the code protection
settings.
6.1
Program Memory
Code protection is enabled by programming the CP bit in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the Bulk Erase Program Memory command.
7.0
HEX FILE USAGE
In the hex file there are two bytes per program word stored in the Intel® INHX32 hex format. Data is stored LSB first,
MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program
memory. (Example: The Configuration Word 1 is stored at 8007h. In the hex file this will be referenced as
1000Eh-1000Fh).
7.1
Configuration Word
To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words
and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple
warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should
be included.
7.2
Device ID
If a device ID is present in the hex file at 1000Ch-1000Dh (8006h on the part), the programmer should verify the device
ID against the value read from the part. On a mismatch condition, the programmer should generate a warning message.
DS40001792A-page 28
 2015 Microchip Technology Inc.
PIC16(L)F177X
7.3
Checksum Computation
The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit.
TABLE 7-1:
CONFIGURATION WORD MASK VALUES
Device
PIC16F1773
Config. Word 1 Mask
Config. Word 2 Mask
3EFFh
3F87h
PIC16LF1773
3EFFh
3F87h
PIC16F1776
3EFFh
3F87h
PIC16LF1776
3EFFh
3F87h
PIC16F1777
3EFFh
3F87h
PIC16LF1777
3EFFh
3F87h
PIC16F1778
3EFFh
3F87h
PIC16LF1778
3EFFh
3F87h
PIC16F1779
3EFFh
3F87h
PIC16LF1779
3EFFh
3F87h
7.3.1
PROGRAM CODE PROTECTION DISABLED
With the program code protection disabled, the checksum is computed by reading the contents of the PIC16(L)F177X
program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user
addressable location (e.g., FFFh for the PIC16F1773). Any Carry bits exceeding 16 bits are ignored. Additionally, the
relevant bits of the Configuration Words are added to the checksum. All unimplemented Configuration bits are masked
to ‘0’.
7.3.2
PROGRAM CODE PROTECTION ENABLED
When the MPLAB® IDE check box for Configure  ID Memory...  Use Unprotected Checksum is checked, then the
16-bit checksum of the equivalent unprotected device is computed and stored in the user ID. Each nibble of the
unprotected checksum is stored in the Least Significant nibble of each of the four user ID locations. The Most
Significant checksum nibble is stored in the user ID at location 8000h, the second Most Significant nibble is stored at
location 8001h, and so forth for the remaining nibbles and ID locations. The protected checksums in Table 7-2 assume
that the Use Unprotected Checksum box is checked.
The checksum of a code-protected device is computed in the following manner: the Least Significant nibble of each user
ID is used to create a 16-bit value. The Least Significant nibble of user ID location 8000h is the Most Significant nibble
of the 16-bit value. The Least Significant nibble of user ID location 8001h is the second Most Significant nibble, and so
forth for the remaining user IDs and 16-bit value nibbles. The resulting 16-bit value is summed with the Configuration
Words. All unimplemented Configuration bits are masked to ‘0’.
 2015 Microchip Technology Inc.
DS40001792A-page 29
PIC16(L)F177X
TABLE 7-2:
CHECKSUMS
Config1
Config2
Checksum
Unprotected
Device
Unprotected Protected
Mask
Word
Code-protected
Blank
00AAh
First and
Last
Blank
00AAh
First and
Last
Mask
PIC16F1773
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
6E86h
EFDCh
EC8Ch
6DE2h
PIC16F1776
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
5E86h
DFDCh
DC8Ch
5DE2h
PIC16F1777
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
5E86h
DFDCh
DC8Ch
5DE2h
PIC16F1778
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
3E86h
BFDCh
BC8Ch
3DE2h
PIC16F1779
3FFFh
3F7Fh
3EFFh
3EFFh
3F87h
3E86h
BFDCh
BC8Ch
3DE2h
PIC16LF1773
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
6E86h
EFDCh
EC8Ch
6DE2h
PIC16LF1776
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
5E86h
DFDCh
DC8Ch
5DE2h
PIC16LF1777
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
5E86h
DFDCh
DC8Ch
5DE2h
PIC16LF1778
3FFFh
3F7Fh
3EFFh
3FFFh
3F87h
3E86h
BFDCh
BC8Ch
3DE2h
PIC16LF1779
3FFFh
3F7Fh
3EFFh
3EFFh
3F87h
3E86h
BFDCh
BC8Ch
3DE2h
DS40001792A-page 30
 2015 Microchip Technology Inc.
PIC16(L)F177X
8.0
ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/Comments
Programming Supply Voltages and Currents
VDD
Supply Voltage
(VDDMIN(2), VDDMAX)
PIC16LF177X
1.80
2.50
—
3.60
3.60
V
V
FOSC 16 MHz
FOSC >16 MHz
PIC16F177X
2.30
2.50
—
5.50
5.50
V
V
FOSC 16 MHz
FOSC >16 MHz
V
VPEW
Read/Write and Row Erase operations
VDDMIN
—
VDDMAX
VBE
Bulk Erase operations
2.7
—
VDDMAX
V
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
3.0
mA
VPP
IPP
Current on MCLR/VPP
—
—
600
A
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
—
—
1.0
s
0.8 VDD
—
—
V
I/O pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) input high level
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
ICSPDAT output high level
VOH
—
—
0.2 VDD
V
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
V
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
—
—
VSS + 0.6
VSS + 0.6
VSS + 0.6
V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
—
2.70
—
V
PIC16(L)F177X
—
—
2.40
1.90
—
—
V
V
PIC16F177X
PIC16LF177X
ICSPDAT output low level
VOL
Brown-out Reset Voltage:
BORV = 0 (high trip)
VBOR
BORV = 1 (low trip)
Programming Mode Entry and Exit
TENTS
Programming mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR
100
—
—
ns
TENTH
Programming mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR
250
—
—
s
Serial Program/Verify
TCKL
Clock Low Pulse Width
100
—
—
ns
TCKH
Clock High Pulse Width
100
—
—
ns
TDS
Data in setup time before clock
100
—
—
ns
TDH
Data in hold time after clock
100
—
—
ns
TCO
Clock to data out valid (during a
Read Data command)
0
—
80
ns
Note 1:
2:
Externally timed writes are not supported for Configuration and Calibration bits.
Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85V when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
 2015 Microchip Technology Inc.
DS40001792A-page 31
PIC16(L)F177X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE (CONTINUED)
AC/DC CHARACTERISTICS
Sym.
Characteristics
Standard Operating Conditions
Production tested at 25°C
Min.
Typ.
Max.
Units
Conditions/Comments
TLZD
Clock to data low-impedance (during a
Read Data command)
0
—
80
ns
THZD
Clock to data high-impedance (during a
Read Data command)
0
—
80
ns
TDLY
Data input not driven to next clock input (delay
required between command/data or command/
command)
1.0
—
—
s
TERAB
Bulk Erase cycle time
—
—
5
ms
TERAR
Row Erase cycle time
—
—
2.5
ms
TPINT
Internally timed programming operation time
—
—
—
—
2.5
5
ms
ms
Program memory
Configuration Words
TPEXT
Externally timed programming pulse
1.0
—
2.1
ms
Note 1
TDIS
Time delay from program to compare
(HV discharge time)
300
—
—
s
TEXIT
Time delay when exiting Program/Verify mode
1
—
—
s
Note 1:
2:
Externally timed writes are not supported for Configuration and Calibration bits.
Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85V when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
DS40001792A-page 32
 2015 Microchip Technology Inc.
PIC16(L)F177X
8.1
AC Timing Diagrams
FIGURE 8-1:
PROGRAMMING MODE ENTRY – VDD FIRST
TENTS
TENTH
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
FIGURE 8-2:
PROGRAMMING MODE ENTRY – VPP FIRST
TENTS
TENTH
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
FIGURE 8-3:
PROGRAMMING MODE EXIT – VPP LAST
TEXIT
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
FIGURE 8-4:
PROGRAMMING MODE EXIT – VDD LAST
TEXIT
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
 2015 Microchip Technology Inc.
DS40001792A-page 33
PIC16(L)F177X
FIGURE 8-5:
CLOCK AND DATA TIMING
TCKL
TCKH
ICSPCLK
TDS TDH
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
FIGURE 8-6:
WRITE COMMAND – PAYLOAD TIMING
TDLY
1
2
3
4
5
X
X
X
X
X
2
1
6
15
16
ICSPCLK
0 LSb
X
MSb
ICSPDAT
Command
FIGURE 8-7:
0
Next
Command
Payload
READ COMMAND – PAYLOAD TIMING
TDLY
1
2
3
4
5
X
ICSPDAT
(from Programmer)
X
X
X
X
6
2
1
15
16
ICSPCLK
X
x
LSb
MSb
ICSPDAT
(from Device)
Command
DS40001792A-page 34
Payload
0
Next
Command
 2015 Microchip Technology Inc.
PIC16(L)F177X
FIGURE 8-8:
LVP ENTRY (POWERING-UP)
VDD
MCLR
TENTS
TENTH
33 clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
ICSPDAT
FIGURE 8-9:
LSb of Pattern
0
1
2
...
MSb of Pattern
31
LVP ENTRY (POWERED)
VDD
MCLR
TENTH
33 Clocks
TCKH
TCKL
ICSPCLK
TDH
TDS
ICSPDAT
Note:
LSb of Pattern
0
1
2
...
MSb of Pattern
31
Sequence matching can start with no edge on MCLR first.
 2015 Microchip Technology Inc.
DS40001792A-page 35
PIC16(L)F177X
APPENDIX A:
REVISION HISTORY
Revision A (05/2015)
Initial release of this document.
DS40001792A-page 36
 2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-359-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40001792A-page 37
Worldwide Sales and Service
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01/27/15
DS40001792A-page 38
 2015 Microchip Technology Inc.