PIC18F87K22 Family Silicon Errata and Data Sheet Clarification

PIC18F87K22 FAMILY
PIC18F87K22 Family
Silicon Errata and Data Sheet Clarification
The PIC18F87K22 family devices that you have
received conform functionally to the current Device Data
Sheet (DS39960D), except for the anomalies described
in this document.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
2.
3.
The errata described in this document will be addressed
in future revisions of the PIC18F87K22 silicon.
4.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon revision
(B5, C6).
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard and click the Refresh Debug
Tool Status icon (
).
Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
5.
Data Sheet clarifications and corrections start on page
11, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
Device
ID(1)
PIC18F65K22
530h
PIC18F66K22
52Ch
PIC18F85K22
536h
PIC18F86K22
532h
PIC18F67K22
518h
PIC18F87K22
51Ch
2:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The DEVREV values for the various PIC18F87K22
silicon revisions are shown in Table 1.
SILICON DEVREV VALUES
Part Number
Note 1:
Note:
Revision ID for Silicon Revision(2)
A3
3h
B1
4h
B3
5h
B5
C1
C3
C5
C6
10h
11h
12h
13h
6h
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the “PIC18F6XKXX/8XKXX Family Flash Microcontroller Programming Specification” (DS39947)
for detailed information on Device and Revision IDs for your specific device.
 2010-2015 Microchip Technology Inc.
DS80000507L-page 1
PIC18F87K22 FAMILY
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
No.
Affected Revisions(1)
Issue Summary
A3 B1 B3 B5 C1 C3 C5 C6
Analog-to-Digital
Converter (A/D)
A/D Offset
1.1
The A/D offset is greater than
specified in the data sheet’s A/D
Converter Characteristics table.
Analog-to-Digital
Converter (A/D)
A/D Offset
1.2
The A/D offset is greater than
specified in the data sheet’s A/D
Converter Characteristics table.
Ports
Leakage
2.
I/O port leakage is higher than the
D060 spec in the data sheet.
3.
High/Low-Voltage
HLVD Trip
Detect (HLVD)
ECCP
Auto-Shutdown
EUSART
Synchronous
Transmit
IPD and IDD
Ultra Low-Power
Sleep
Ultra Low-Power
Sleep
Maximum Limit
Sleep Entry
WDT Wake-up
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The high-to-low (VDIRMAG = 0)
setting of the HLVD may send initial
interrupts.
X
X
X
X
X
X
X
X
4.
The tri-state setting of the
auto-shutdown feature in the enhanced
PWM may not successfully drive the
pin to tri-state.
X
X
X
X
X
X
X
X
5.
When using the Synchronous
Transmit mode of the EUSART, at
high baud rates, transmitted data may
become corrupted.
X
X
X
X
X
X
X
X
6.
Maximum current limits may be higher
than specified in Section 31.2 “DC
Characteristics: Power-Down and
Supply Current PIC18F87K22
Family (Industrial)” of the data
sheet.
X
7.1
Entering Ultra Low-Power Sleep
mode, by setting RETEN = 0 and
SRETEN = 1, will cause the part not
to be programmable through ICSP™.
X
X
7.2
Using the WDT to exit Ultra
Low-Power Sleep mode when
VDD>4.5V can cause the part to enter
a Reset state requiring POR to exit.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Resets (BOR)
Enable/Disable
8.
An unexpected Reset may occur if the
Brown-out Reset module (BOR) is
disabled, and then re-enabled, when
the High/Low-Voltage Detection
(HLVD) module is not enabled
(HLVDCON<4> = 0).
RG5 Pin
Leakage
9.
RG5 will cause excess pin leakage
whenever it is driven low.
External Memory
Bus (EMB)
Wait States
10.
The CE signal will not be extended
properly if Wait states are used.
X
X
X
X
X
Primary Oscillator
XT Mode
11.
XT Primary Oscillator mode does not
reliably function when the driving
crystals are above 3 MHz.
X
X
X
X
X
When the timer is operated in
Asynchronous External Input mode,
unexpected interrupt flag generation
may occur.
X
X
X
X
X
Timer1/3/5/7
Note 1:
Interrupt
12.
X
X
Only those issues indicated in the columns labeled B3 and C3 apply to the current silicon revision.
DS80000507L-page 2
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B5, C6).
1. Module: Analog-to-Digital Converter
(A/D)
1.1 The A/D will not meet the Microchip standard
A/D specification. The A/D may be usable if
tested at the user end. The possible issues are
high offset error, high DNL error and multiple
missing codes. The A/D can be tested and used
for relative measurements.
1.2 The A/D will meet the Microchip standard A/D
specification when used as a 10-bit A/D. When
used as a 12-bit A/D, the possible issues include
high offset error (up to a maximum of ±25 LSBs
at 25°C, ±30 LSBs at 85°C, 125°C and -40°C),
high DNL error (up to a maximum of ±4 LSBs)
and multiple missing codes (up to a maximum of
20). Users should evaluate the 12-bit A/D
performance in their application using the
suggested work around below. See Table 3 for
guidance specifications.
A/D Offset:
The A/D may have high offset error, up to a
maximum of ±25 LSBs at 25°C, ±30 LSBs at
85°C, 125°C and -40°C; it can be used if the A/D
is calibrated for the offset.
Work around
A/D Offset
Method to Calibrate for Offset:
The A/D may have a high offset error, up to a
maximum of 50 LSB; it can be used if the A/D is
calibrated for the offset.
In Single-Ended mode, connect A/D +ve input to
ground and take the A/D reading. This will be the
offset of the device and can be used to
compensate for the subsequent A/D readings
on the actual inputs.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect the A/D +ve
input to ground and take the A/D reading. This
will be the offset of the device and can be used
to compensate for the subsequent A/D readings
on the actual inputs.
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
 2010-2015 Microchip Technology Inc.
DS80000507L-page 3
PIC18F87K22 FAMILY
TABLE 3:
A/D CONVERTER CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
—
12
bit
VREF  5.0V
A01
NR
Resolution
A03
EIL
Integral Linearity Error
—
—
±10.0
LSb
VREF  5.0V
A04
EDL
Differential Linearity Error
—
—
+6.0/-4.0
LSb
VREF  5.0V
A06
EOFF
Offset Error
—
—
±25
LSb
VREF  5.0V,
Temperature: 25°C
—
—
±30
LSb
VREF  5.0V,
Temperature:  85°C, -40°C
—
—
±15
LSb
A07
EGN
Gain Error
Monotonicity
(1)
A10
—
A20
VREF Reference Voltage Range
(VREFH – VREFL)
A21
3
—
AVDD – AVSS
V
VREFH Reference Voltage High
AVSS + 3.0V
—
AVDD + 0.3V
V
A22
VREFL Reference Voltage Low
AVSS – 0.3V
—
AVDD – 3.0V
V
A25
VAIN
VREFL
—
VREFH
V
Note 1:
Analog Input Voltage
VREF  5.0V
VSS  VAIN VREF
—
The A/D conversion result never decreases with an increase in the input voltage.
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
DS80000507L-page 4
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
2. Module: Ports
5. Module: EUSART
The input leakage will not match the D060
specification in the data sheet. The leakage will
meet the 200 nA specification at TA = 25°C. At
TA = 85°C, the leakage will be up to a maximum
of 2 µA.
When using the Synchronous Transmit mode of
the EUSART, at high baud rates, transmitted
data may become corrupted. One or more bits of
the intended transmit message may be
incorrect.
Work around
Work around
None.
Since this problem is related to the baud rate
used, adding a fixed delay before loading the
TXREGx may not be a reliable work around.
Lower the baud rate until no errors occur, or
when loading the TXREGx, check that the
TRMT bit inside of the TXSTAx register is set
instead of checking the TXxIF bit.The following
code can be used:
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
X
3. Module: High/Low-Voltage Detect (HLVD)
The high-to-low (VDIRMAG = 0) setting of the
HLVD may send initial interrupts. High trip points
that are close to the intended operating voltage
are susceptible to this behavior.
EXAMPLE 1:
EUSART SYNCHRONOUS
TRANSMIT WORK AROUND
while(!TXSTAxbits.TRMT);
// wait to load TXREGx until TRMT is set
Work around
Select a lower trip voltage that allows consistent
start-up or clear any initial interrupts from the
HLVD on start-up.
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
X
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
X
4. Module: ECCP
The tri-state setting of the auto-shutdown
feature in the enhanced PWM may not
successfully drive the pin to tri-state. The pin will
remain an output and should not be driven
externally. All tri-state settings will be affected.
Work around
None.
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
X
 2010-2015 Microchip Technology Inc.
DS80000507L-page 5
PIC18F87K22 FAMILY
6. Module: IPD and IDD
The IPD and IDD limits will not match the data
sheet. The values, in bold in Section 31.2 “DC
Characteristics: Power-Down and Supply
Current PIC18F87K22 Family (Industrial)”,
reflect the updated silicon maximum limits.
31.2
DC Characteristics:
PIC18F87K22 Family
(Industrial)
Param.
No.
Device
Power-Down and Supply Current
PIC18F87K22 Family (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C  TA  +85°C for industrial
Typ.
Max.
Units
Conditions
10
500
nA
-40°C
20
500
nA
+25°C
120
600
nA
+60°C
630
2000
nA
+85°C
50
700
nA
-40°C
60
900
nA
+25°C
170
1100
nA
+60°C
700
5000
nA
+85°C
Power-Down Current (IPD)(1)
All devices
All devices
All devices
350
1300
nA
-40°C
400
1400
nA
+25°C
550
1500
nA
+60°C
1350
4000
nA
+85°C
3.7
8.5
µA
-40°C
5.4
10
µA
+25°C
6.6
13
µA
+85°C
8.7
18
µA
-40°C
10
20
µA
+25°C
VDD = 1.8V(4)
(Sleep mode)
Regulator Disabled
VDD = 3.3V(4)
(Sleep mode)
Regulator Disabled
VDD = 5V(5)
(Sleep mode)
Regulator Enabled
Supply Current (IDD) Cont.(2,3)
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
12
35
µA
+85°C
60
160
µA
-40°C
90
190
µA
+25°C
100
240
µA
+85°C
VDD = 1.8V(4)
Regulator Disabled
VDD = 3.3V(4)
Regulator Disabled
FOSC = 32 kHz(3)
(SEC_RUN mode,
SOSCSEL = 01)
VDD = 5V(5)
Regulator Enabled
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS,
and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1).
Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN
(CONFIG1L<0>) = 0).
DS80000507L-page 6
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
31.2
DC Characteristics:
PIC18F87K22 Family
(Industrial)
Param.
No.
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C  TA  +85°C for industrial
Device
All devices
All devices
All devices
Note 1:
2:
3:
4:
5:
Power-Down and Supply Current
PIC18F87K22 Family (Industrial) (Continued)
Typ.
Max.
Units
Conditions
1.2
4
µA
-40°C
1.7
5
µA
+25°C
2.6
6
µA
+85°C
1.6
7
µA
-40°C
2.8
9
µA
+25°C
4.1
17
µA
+85°C
60
150
µA
-40°C
80
180
µA
+25°C
100
240
µA
+85°C
VDD = 1.8V(4)
Regulator Disabled
VDD = 3.3V(4)
Regulator Disabled
FOSC = 32 kHz(3)
(SEC_IDLE mode,
SOSCSEL = 01)
VDD = 5V(5)
Regulator Enabled
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS,
and all features that add delta current are disabled (such as WDT, SOSC oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as
I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and
temperature, also have an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CONFIG1L<0>) = 1).
Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN
(CONFIG1L<0>) = 0).
Work around
None.
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
X
 2010-2015 Microchip Technology Inc.
DS80000507L-page 7
PIC18F87K22 FAMILY
7. Module: Ultra Low-Power Sleep
7.1 Entering Ultra Low-Power Sleep mode, by
setting RETEN = 0 and SRETEN = 1, will cause
the part to not be programmable through
ICSP™. This issue occurs when the RETEN
fuse bit in CONFIG1L<0> is cleared to ‘0’, the
SRETEN bit in the WDTCON register is set to ‘1’
and a SLEEP instruction is executed. This
happens within the first 350 µs of code
execution or whenever the above Sleep mode is
entered and MCLR is disabled. Discontinue use
of the MCLR disabled RG5 mode if ICSP
reprogramming is necessary.
Work around
Do not use the Ultra Low-Power Sleep mode
with VDD above 4.5V.
Affected Silicon Revisions
Work around
Use normal Sleep and Low-Power Sleep modes
only, or on any Reset, ensure that at least
350 µs passes before executing a SLEEP
instruction when ULP is enabled. To ensure the
Ultra Low- Power Sleep mode is not enabled,
the RETEN fuse bit in CONFIG1L<0> should be
set to a ‘1’, and the SRETEN bit in the WDTCON
register should be cleared to a ‘0’. The following
code can be used:
EXAMPLE 2:
7.2 Using the WDT to exit Ultra Low-Power Sleep
mode when VDD>4.5V can cause the part to
enter a Reset state that requires a POR to exit.
The issue occurs when the RETEN fuse bit in
CONFIG1L<0> is cleared to ‘0’, the SRETEN bit
in the WDTCON register is set to ‘1’, VDD>4.5V.
Upon entering the failure state, the device
ceases to respond to MCLR events and will only
exit the Reset state upon experiencing a POR.
A3
B1
B3
B5
C1
C3
C5
C6
X
X
X
X
X
X
X
X
ULTRA LOW-POWER SLEEP
WORK AROUND
//This will ensure the RETEN fuse is set
to 1
#pragma config RETEN = OFF
//This will ensure the SRETEN bit is 0
WDTCONbits.SRETEN = 0;
If the Ultra Low-Power Sleep mode is needed,
then the user must ensure that the minimum
time, before the first SLEEP instruction is
executed, is greater than 350 µs.
Affected Silicon Revisions
A3
B1
X
X
B3
DS80000507L-page 8
B5
C1
C3
C5
C6
X
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
8. Module: Resets (BOR)
9. Module: RG5 Pin
An unexpected Reset may occur if the
Brown-out Reset (BOR) module is disabled,
and then re-enabled when the High/
Low-Voltage Detection (HLVD) module is not
enabled ( HLVDCON<4> = 0). This issue
affects BOR modes: BOREN<1:0> = 10
and BOREN<1:0> = 01. In both of these
modes, if the BOR module is re-enabled while
the device is active, unexpected Resets may be
generated.
Work around
If BOR is required, and power consumption is
not an issue, use BOREN<1:0> = 11. For
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep. If
power consumption is an issue and low power is
desired, do not use BOREN<1:0> = 10 mode.
Instead, use BOREN<1:0> = 01 and follow the
steps below when entering and exiting Sleep.
1.
2.
A3
B1
B3
B5
C1
C3
C5
C6
X
10. Module: External Memory Bus (EMB)
The CE signal will not be extended properly if
Wait states are used. The duration of the CE
signal will remain 0 TCY despite the setting in
MEMCON<5:4>.
Affected Silicon Revisions
None.
Enter Sleep mode (if desired).
After exiting Sleep mode (if entered), enable the
HLVD (HLVDCON<4> = 1).
Wait for the internal reference voltage (TIRVST)
to stabilize (typically 25 µs).
Re-enable BOR
(RCON<6> = 1).
by
Disable the HLVD
(HLVDCON<4> = 0).
A3
B1
B3
X
X
X
B5
C1
C3
X
X
C5
C6
11. Module: Primary Oscillator (XT Mode)
setting
SBOREN
On some parts, using the XT oscillator at the top
end of its specified frequency range
(3.0-4.0 MHz) may cause the part to cease
driving the oscillator.
Work around
WDTCONbits.SBOREN = 1;
6.
Affected Silicon Revisions
WDTCONbits.SBOREN = 0;
while(!HLVDCONbits.IRVST);
5.
In power-sensitive applications, using RG5 as
an input, ensure that any input attached to this
pin Idles high.
Work around
HLVDCONbits.HLVDEN = 1;
4.
Work around
Disable BOR by clearing SBOREN
(RCON<6> = 0).
Sleep();
3.
RG5 will cause excess pin leakage whenever it
is driven low. When RG5 is held at 0V, the pin
will typically source an additional 160 µA of
current.
by
clearing
HLVDEN
Use XT mode only for frequencies lower than
3.0 MHz.
HLVDCONbits.HLVDEN = 0;
Use HS mode if frequencies greater than
3.0 MHz on a crystal oscillator are required.
Affected Silicon Revisions
Affected Silicon Revisions
A3
B1
B3
B5
C1
C3
C5
C6
A1
B1
B3
X
X
X
X
X
X
X
X
X
X
X
 2010-2015 Microchip Technology Inc.
B5
C1
C3
X
X
C5
C6
DS80000507L-page 9
PIC18F87K22 FAMILY
12. Module: Timer1/3/5/7
When Timer1, Timer3, Timer5 or Tmer7 is
operated in Asynchronous External Input mode,
unexpected interrupt flag generation may occur
if an external clock edge arrives too soon
following a firmware write to the TMRxH:TMRxL
registers. An unexpected interrupt flag event
may also occur when enabling the module or
switching from Synchronous to Asynchronous
mode.
Work around
This issue only applies when operating the timer
in Asynchronous mode. Whenever possible,
operate the timer module in Synchronous mode
to avoid spurious timer interrupts.
If Asynchronous mode must be used in the
application, potential strategies to mitigate the
issue may include any of the following:
EXAMPLE 3:
• Design the firmware so it does not rely on
the TMRxIF flag or keep the respective
interrupt disabled. The timer still counts
normally and does not reset to 0x0000
when the spurious interrupt flag event is
generated.
• Design the firmware so that it does not
write to the TMRxH:TMRxL registers or
does not periodically disable/enable the
timer, or switch modes. Reading from the
timer does not trigger the spurious interrupt
flag events.
• If the firmware must use the timer
interrupts and must write to the timer (or
disable/enable, or mode switch the timer),
implement code to suppress the spurious
interrupt event, should it occur. This can be
achieved by following the process shown
in Example 3.
ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS
INTERRUPT
//Timer1 update procedure in asynchronous mode
//The code below uses Timer1 as example
T1CONbits.TMR1ON = 0;
PIE1bits.TMR1IE = 0;
TMR1H = 0x00;
TMR1L = 0x00;
T1CONbits.TMR1ON = 1;
//Stop timer from incrementing
//Temporarily disable Timer1 interrupt vectoring
//Update timer value
//Turn on timer
//Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts.
//Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation,
//a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress
//the actual interrupt vectoring, the TMR1IE bit should be kept clear until
//after the "window of opportunity" (for the spurious interrupt flag event has passed).
//After the window is passed, no further spurious interrupts occur, at least
//until the next timer write (or mode switch/enable event).
while(TMR1L < 0x02);
//Wait for 2 timer increments more than the Updated Timer
//value (indicating more than 2 full T1CKI clock periods elapsed)
//Wait two more instruction cycles
NOP();
NOP();
PIR1bits.TMR1IF = 0;
PIE1bits.TMR1IE = 1;
//Clear TMR1IF flag, in case it was spuriously set
//Now re-enable interrupt vectoring for timer 1
Affected Silicon Revisions
A1
B1
B3
X
X
X
DS80000507L-page 10
B5
C1
X
C3 C5
X
C6
X
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS39960D):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
1. Module: Electrical Characteristics
Table 31-27: A/D Converter Characteristics has
been corrected. The changes are shown in bold
in the table below:
TABLE 31-27: A/D CONVERTER CHARACTERISTICS: PIC18F87K22 FAMILY (INDUSTRIAL)
Param.
Sym.
No.
Characteristic
Min.
Typ.
Max.
Units
12
bit
Conditions
VREF  5.0V
A01
NR
Resolution
—
—
A03
EIL
Integral Linearity Error
—
±1
±6.0
LSB VREF  5.0V
A04
EDL
Differential Linearity Error
—
±1
+3.0/-1.0
LSB VREF  5.0V
A06
EOFF
Offset Error
—
±1
±18.0
LSB VREF  5.0V
A07
EGN
Gain Error
—
±1
±8.0
LSB VREF  5.0V
(1)
—
—
—
—
3
—
VDD – VSS
V
VREFH Reference Voltage High
VSS + 3.0V
—
VDD + 0.3V
V
VREFL Reference Voltage Low
VSS – 0.3V
—
VDD – 3.0V
V
A10
—
A20
VREF Reference Voltage Range
(VREFH – VREFL)
Monotonicity
A21
A22
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5
k
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
A
A
Note 1:
2:
VSS  VAIN  VREF
During VAIN acquisition.
During A/D conversion cycle.
The A/D conversion result never decreases with an increase in the input voltage.
VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL
current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
 2010-2015 Microchip Technology Inc.
DS80000507L-page 11
PIC18F87K22 FAMILY
2. Module: Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)
In Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”, the description
of the Regulator Disabled mode has changed.
The changes are shown in bold below:
When the regulator is disabled, the VCAP/
VDDCORE pin must only be tied to a 0.1 µF
capacitor. Refer to Section 31.0 “Electrical
Characteristics” for information on VDD and
VDDCORE.
3. Module: DC Characteristics
(Injection Current)
The following table of specifications for current
injected into the microcontroller will be added to
Section 31.0 “Electrical Characteristics”.
31.4
DC Characteristics: PIC18F87K22 Family (Industrial)
Standard Operating Conditions: 1.8V to 5.5V
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param.
No.
Symbol
D160a
IICL
D160b
Min.
Typ.
Max.
Units
Conditions
Input Low Injection Current
0
—
-5(1)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
SOSCI, SOSCO
IICH
Input High Injection Current
0
—
+5(1)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
SOSCI, SOSCO
D160c
IICT
Total Input Injection Current
(sum of all I/O and control
pins)
-20(1,2)
—
+20(1,2)
mA
Absolute instantaneous
sum of all input injection
currents from all I/O pins
( IICL + IICH)  IICT
Note 1:
2:
Injection currents >  0 can affect the A/D results.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted.
DS80000507L-page 12
Characteristic
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
4. Module: DC Characteristics
(Input Low Voltage and Input
High Voltage)
Input Low Voltage and Input High Voltage have
been corrected. The changes are shown in bold
in the table below:
31.3
DC Characteristics: PIC18F87K22 Family (Industrial/Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA  +125°C
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
Characteristic
Min.
Typ.†
Max.
Units
Conditions
with TTL buffer
—
—
0.8
V
4.5V  VDD  5.5V
—
—
0.15 VDD
V
VDD  4.5V
with Schmitt Trigger buffer
—
—
0.2 VDD
V
with I2C™ levels
—
—
0.3 VDD
V
with SMBus levels
—
—
0.8
V
Input Low Voltage
I/O Ports:
D030
D030A
D031
2.7V  VDD  5.5V
D032
MCLR
—
—
0.2 VDD
V
D033
OSC1
—
—
0.2 VDD
V
D034
SOSCI
—
—
0.3 VDD
V
2.0
—
—
V
4.5V  VDD 5.5V
0.25 VDD
—
—
V
1.8V  VDD  4.5V
0.8 VDD
—
—
V
2.0V  VDD  5.5V
0.7 VDD
—
—
V
2.1
—
—
V
VIH
Input High Voltage
I/O Ports:
D040
D041
with TTL buffer
with Schmitt Trigger buffer
with I
2C™
levels
with SMBus levels
D042
MCLR
0.8 VDD
—
—
V
D043
OSC1 (HS mode)
0.7 VDD
—
—
V
D043A
OSC1 (EC/ECPLL mode)
0.8 VDD
—
—
V
D044
SOSCI
0.7 VDD
—
—
V
 2010-2015 Microchip Technology Inc.
2.7V  VDD  5.5V
DS80000507L-page 13
PIC18F87K22 FAMILY
5. Module: Product Identification System
The Product Identification System should be as
follows:
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:(1,2)
PIC18F65K22, PIC18F65K22T
PIC18F66K22, PIC18F66K22T
PIC18F67K22, PIC18F67K22T
PIC18F85K22, PIC18F85K22T
PIC18F86K22, PIC18F86K22T
PIC18F87K22, PIC18F87K22T
Temperature
Range:
I = -40C to +85C (Industrial)
E = -40C to +125C (Extended)
Package:
PT = TQFP (Plastic Thin Quad Flatpack)
MR = QFN (Plastic Quad Flat)
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
c)
PIC18F87K22-I/PT 301 = Industrial temperature,
TQFP package, QTP pattern #301.
PIC18F87K22T-I/PT = Tape and reel, Industrial
temperature, TQFP package
PIC18F87K22T-E/PT = Tape and reel, Extended
temperature, TQFP package
Note 1: F
2: T
= Standard Voltage Range
= In tape and reel PLCC and
TQFP packages only
3: RSL = Silicon Revision A3 or later
6. Module: Oscillator Configurations
The following section should be included in the
oscillator section of the data sheet, directly
underneath Section 3.6.4.3 “Compensating
with the CCP Module in Capture Mode”.
3.6.5
LFINTOSC OPERATION IN SLEEP
When the Watchdog Timer (WDT) or Real-Time
Clock and Calendar (RTCC) modules are
enabled and configured to use the LFINTOSC,
the LFINTOSC will continue to run when the
device is in Sleep, unlike other internal clock
sources.
While in Sleep, the LFINTOSC has two power
modes, a High-Power and a Low-Power mode,
controlled by the INTOSCSEL bit in the
CONFIG1L
Configuration
Word.
The
High-Power mode is the same as the
LFINTOSC while the part is awake and
conforms to the specifications outlined for that
oscillator. The Low-Power mode consumes less
current, but has a much lower accuracy and is
not
recommended
for
timing-sensitive
applications.
DS80000507L-page 14
 2010-2015 Microchip Technology Inc.
PIC18F87K22 FAMILY
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev L Document (7/2015)
Added silicon revision B5; Other minor corrections.
Rev A Document (6/2010)
Initial release of this document. Silicon issues 1 (A/D),
2 (BOR), 3 (HLVD) and 4 (Ports).
Rev B Document (12/2010)
Removed silicon issue 2 (Brown-out Reset). Changes
were made to silicon issue 3 (HLVD). Added silicon
issues 4 (ECCP), 5 (EUSART) and 6 (IPD and IDD).
Rev C Document (4/2011)
Added silicon issues 7 (Ultra Low-Power Sleep),
8 (Resets – BOR) and 9 (RG5 Pin). Removed data
sheet clarifications 1-3 (Voltage Regulator Pins –
ENVREG and VCAP/VDDCORE). Added data sheet
clarification 1 (Electrical Characteristics).
Rev D Document (2/2012)
Added silicon issue 10 (External Memory Bus – EMB).
Added data sheet clarifications 2 (Voltage Regulator
Pins – ENVREG and VCAP/VDDCORE) and 3 (DC
Characteristics – Injection Current).
Rev E Document (10/2012)
Added MPLAB X IDE; Added Silicon Revision C3.
Data Sheet Clarifications: Added Module 4, DC
Characteristics (Input Low Voltage and Input High
Voltage).
Rev F Document (12/2013)
Added silicon issues 1.2 (Analog-to-Digital Converter)
and 11 (Primary Oscillator - XT Mode); Other minor
corrections.
Rev G Document (3/2014)
Data Sheet Clarifications: Added Module 5; Other
minor corrections.
Rev H Document (9/2014)
Added Module 7.2; Other minor corrections.
Rev J Document (9/2014)
Added silicon revision C5.
Rev K Document (03/2015)
Added silicon revision C6; Other minor corrections.
Added Module 12. Timer1/3/5/7
Data Sheet Clarifications: added Module 6.
 2010-2015 Microchip Technology Inc.
DS80000507L-page 15
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-582-5
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS80000507L-page 16
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
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DS80000507L-page 17