PIC18F66K80
PIC18F66K80 Family
Silicon Errata and Data Sheet Clarification
The PIC18F66K80 family devices that you have
received conform functionally to the current Device
Data Sheet (DS39977F), except for the anomalies
described in this document.
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
2.
3.
The errata described in this document will be addressed
in future revisions of the PIC18F66K80 silicon.
4.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A6).
5.
Data Sheet clarifications and corrections start on
page 10, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard and click the Refresh Debug
Tool Status icon (
).
Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The DEVREV values for the various PIC18F66K80
silicon revisions are shown in Table 1.
SILICON DEVREV VALUES
Part Number
Revision ID for Silicon Revision(2)
Device ID(1)
A2
A3
A4
A6
PIC18F66K80
60E0
PIC18F65K80
6140
PIC18F46K80
6100
PIC18F45K80
6160
PIC18F26K80
6120
PIC18F25K80
6180
2h
3h
4h
6h
PIC18LF66K80
61C0
PIC18LF65K80
6220
PIC18LF46K80
61E0
PIC18LF45K80
6240
PIC18LF26K80
6200
PIC18LF25K80
6260
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of Configuration
memory space. They are shown in hexadecimal in the format, “DEVID DEVREV”.
2: Refer to the “PIC18FXXK80 Family Flash Microcontroller Programming Specification” (DS39972) for
detailed information on Device and Revision IDs for your specific device.
2011-2016 Microchip Technology Inc.
DS80000519K-page 1
PIC18F66K80
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Affected Revisions(1)
Issue Summary
A2
A3
A4
A6
X
X
X
X
X
X
X
X
X
X
X
X
Analog-to-Digital
Converter (A/D)
A/D
Performance
1.
The 12-bit A/D performance is outside the data
sheet’s A/D Converter specifications.
X
EUSART
Synchronous
Transmit
2.
When using the Synchronous Transmit mode,
transmitted data may become corrupted if
using the TXxIF bit to determine when to load
the TXREGx register.
X
ECCP
Auto-Shutdown
3.
The tri-state setting of the auto-shutdown
feature in the enhanced PWM will not
successfully drive the pin to tri-state.
X
ECAN
CAN Clock
Source Selection
4.
The CLKSEL bit in the CIOCON register is
modifiable while the ECAN module is active.
X
Ultra Low-Power
Sleep
Sleep Entry
5.
Entering Ultra Low-Power Sleep mode by
setting RETEN = 0 and SRETEN = 1, will
cause the part to not be programmable
through ICSP™.
X
IPD and IDD
Maximum Limit
6.
Maximum current limits may be higher than
specified in Table 31-2 of the data sheet.
X
Reset (BOR)
Enable/Disable
An unexpected Reset may occur if the
Brown-out Reset module (BOR) is disabled
and then re-enabled, when the High/
Low-Voltage Detection module (HLVD) is not
enabled (HLVDCON<4> = 0).
X
7.
ECAN
EWIN
8.
The enhanced window address feature,
EWIN<4:0>, in the ECANCON register, will not
move the BnCON 0<n<5 registers into the
access window of RAM.
X
MCLRE
Master Clear
Enable
9.
The Master Clear pin will not be readable
when MCLRE is set to off for all 28-pin part
variants (PIC18F2XK80).
X
X
Timer1/Timer3
Gated Enable
10.
Timer1 and Timer3 gate control will not
function up to the speed of FOSC when the
TxCON is set to the system clock
(TxCON<7:6> = 01).
X
X
Timer1/Timer3
Interrupt
11.
When the timer is operated in Asynchronous
External Input mode, unexpected interrupt
flag generation may occur.
X
X
X
Primary Oscillator XT Mode
12.
XT Primary Oscillator mode does not reliably
function when the driving crystals are above
3 MHz.
X
X
X
ECAN
Disable/Sleep
mode
13.
Disable/Sleep mode reverts CANTX control to
TRISx/LATx instead of going to Recessive
state.
X
X
X
X
ECAN
CLKSEL bit
14.
Setting CLKSEL bit of CIOCON can
occasionally lead to missed incoming CAN
messages.
X
X
X
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000519K-page 2
2011-2016 Microchip Technology Inc.
PIC18F66K80
Silicon Errata Issues
Note:
The 12-bit A/D issues will be fixed in future
revisions of this part. Reduced bit resolution
specifications can be derived by dividing, as
appropriate. For instance, 10-bit guidance is
obtained by dividing the parameters in Table 3 by
four.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A6).
A/D Offset
The A/D may have high offset error, up to a
maximum of ±25 LSBs; it can be used if the A/D is
calibrated for the offset.
1. Module: Analog-to-Digital Converter (A/D)
The 12-bit A/D performance is outside the data
sheet’s A/D Converter specifications. When used
as a 12-bit A/D, the possible issues are: high offset
error, up to a maximum of ±25 LSBs at 25°C,
±30 LSBs at 85°C, 125°C and -40°C; high DNL
error, up to a maximum of +6.0/-4.0 LSBs; and
multiple missing codes, up to a maximum of
twenty. Users should evaluate the 12-bit A/D
performance in their application using the
suggested work around below. See Table 3 for
guidance specifications.
TABLE 3:
Work around
Calibrate for offset in Single-Ended mode by
connecting A/D +ve input to ground and taking the
A/D reading. This will be the offset of the device
and can be used to compensate for the
subsequent A/D readings on the actual inputs.
A/D CONVERTER CHARACTERISTICS
Param
Sym.
No.
Characteristic
Min.
Typ.
Max.
Units
12
bit
Conditions
VREF 5.0V
A01
NR
Resolution
—
—
A03
EIL
Integral Linearity Error
—
—
±10.0
LSb VREF 5.0V
A04
EDL
Differential Linearity Error
—
—
+6.0/-4.0
LSb VREF 5.0V
A06
EOFF
Offset Error
—
—
±25
±30
LSb VREF 5.0V, TEMP = 25°C
TEMP 85°C, -40°C
A07
EGN
Gain Error
—
—
±15
LSb VREF 5.0V
Monotonicity(1)
3
—
AVDD – AVSS
V
VSS VAIN VREF
A10
—
A20
VREF Reference Voltage Range
(VREFH – VREFL)
A21
VREFH Reference Voltage High
AVSS + 3.0V
—
AVDD + 0.3V
V
A22
VREFL
Reference Voltage Low
AVSS – 0.3V
—
AVDD – 3.0V
V
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
Note 1:
—
The A/D conversion result never decreases with an increase in the input voltage.
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
2011-2016 Microchip Technology Inc.
DS80000519K-page 3
PIC18F66K80
2. Module: EUSART
In Synchronous Transmit mode, data may be
corrupted if using the TXxIF bit to determine when
to load the TXREGx register. One or more of the
intended transmit messages may be incorrect.
Work around
4. Module: ECAN
The CLKSEL bit in the CIOCON register remains
modifiable while the ECAN module is not in
Configuration mode. Accidental state changes of
this bit will result in immediate bit clock changes
that will affect all nodes on the bus.
A fixed delay added before loading TXREGx may
not be a reliable work around. When loading the
TXREGx, check that the TRMT bit inside of the
TXSTAx register is set instead of checking the
TXxIF bit. The following code can be used:
Work around
while(!TXSTAxbits.TRMT);
// wait to load TXREGx until TRMT is set
Affected Silicon Revisions
Affected Silicon Revisions
A2
A3
A4
A6
While the ECAN module is in Run mode, do not
modify the state of the CLKSEL bit in the CIOCON
register unless the CAN module is first changed
into Configuration mode.
A2
A3
A4
A6
X
5. Module: Ultra Low-Power Sleep
X
3. Module: ECCP
The tri-state setting of the auto-shutdown feature,
in the enhanced PWM will not successfully drive
the pin to tri-state. The pin will remain an output
and should not be driven externally. All tri-state
settings will be affected.
Work around
Use one of the other two auto-shutdown states
available, as outlined in the data sheet.
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
Entering Ultra Low-Power Sleep mode by setting
RETEN = 0 and SRETEN = 1 will cause the part to
not be programmable through ICSP™. This issue
occurs when the RETEN fuse bit in CONFIG1L<0>
is cleared to ‘0’, the SRETEN bit in the WDTCON
register is set to ‘1’ and a SLEEP instruction is executed within the first 350 s of code execution.
This happens after a Reset event, causing the part
to enter Ultra Low-Power Sleep mode.
Work around
Use Normal Sleep and Low-Power Sleep modes
only, or on any Reset, ensure that at least 350 s
pass before executing a SLEEP instruction when
ULP is enabled. To ensure the Ultra Low-Power
Sleep mode is not enabled, the RETEN fuse bit in
CONFIG1L<0> should be set to a ‘1’ and the
SRETEN bit in the WDTCON register should be
cleared to a ‘0’. The following code can be used:
//This will ensure the RETEN fuse is set to 1
#pragma config RETEN = OFF
//This will ensure the SRETEN bit is 0
WDTCONbits.SRETEN = 0;
If the Ultra Low-Power Sleep mode is needed,
then the user must ensure that the minimum time,
before the first SLEEP instruction is executed, is
greater than 350 s.
Affected Silicon Revisions
A2
A3
A4
A6
X
DS80000519K-page 4
2011-2016 Microchip Technology Inc.
PIC18F66K80
6. Module: IPD and IDD
All IDD maximum limits will equal 2.8 times the
value listed in the data sheet.
The IPD and IDD limits do not match the data sheet.
The IPD values, shown in bold in Section 31.2
“DC Characteristics: Power-Down and Supply
Current PIC18F66K80 Family (Industrial/
Extended)” (below), reflect the updated silicon
maximum limits.
31.2
Affected Silicon Revisions
A2
A3
A4
A6
X
DC Characteristics: Power-Down and Supply Current
PIC18F66K80 Family (Industrial/Extended)
PIC18F66K80
(Industrial/Extended)
Param
No.
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Device
Typ.
Max.
Units
Conditions
0.008
7
µA
-40°C
0.013
7
µA
+25°C
0.035
9
µA
+60°C
0.218
10
µA
+85°C
3
12
µA
±125ºC
0.014
8
µA
-40°C
0.034
8
µA
+25°C
0.092
9
µA
+60°C
Power-Down Current (IPD)(1)
PIC18LFXXK80
PIC18LFXXK80
PIC18FXXK80
PIC18FXXK80
Legend:
Note 1:
2:
3:
4:
5:
0.312
10
µA
+85°C
4
16
µA
±125ºC
0.2
9
µA
-40°C
0.23
9
µA
+25°C
0.32
10
µA
+60°C
0.51
11
µA
+85°C
±125ºC
5
18
µA
0.22
10
µA
-40°C
0.24
10
µA
+25°C
0.34
11
µA
+60°C
0.54
12
µA
+85°C
5
20
µA
±125ºC
VDD = 1.8V(4)
(Sleep mode)
Regulator Disabled
VDD = 3.3V(4)
(Sleep mode)
Regulator Disabled
VDD = 3.3V
(Sleep mode)
Regulator Enabled
VDD = 5V(5)
(Sleep mode)
Regulator Enabled
Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, SOSC oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
For LF devices, RETEN (CONFIG1L<0>) = 1.
For F devices, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0.
2011-2016 Microchip Technology Inc.
DS80000519K-page 5
PIC18F66K80
7. Module: Reset (BOR)
8. Module: ECAN
An unexpected Reset may occur if the Brown-out
Reset module (BOR) is disabled, and then reenabled, when the High/Low-Voltage Detection
module
(HLVD)
is
not
enabled
(HLVDCON<4> = 0). This issue affects BOR
modes:
BOREN<1:0> = 10
and
BOREN<1:0> = 01. In both of these modes, if the
BOR module is re-enabled while the device is
active, unexpected Resets may be generated.
Work around
Work around
1.
If BOR is required and power consumption is not
an issue, use BOREN<1:0> = 11. For
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep. If
power consumption is an issue and low power is
desired, do not use BOREN<1:0> = 10 mode.
Instead, use BOREN<1:0> = 01 and follow the
steps below when entering and exiting Sleep.
1.
The enhanced window address feature,
EWIN<4:0>, in the ECANCON register, will not
move the BnCON 0<n<5 registers into the access
window of RAM. The rest of the registers in B0
through B5 will be transferred into the access bank
successfully. This feature is only available in Mode
1 and Mode 2; Mode 0 applications will not be
affected.
2.
Disable BOR by clearing SBOREN
(RCON<6> = 0).
WDTCONbits.SBOREN = 0;
2.
Enter Sleep mode (if desired).
Sleep();
3.
After exiting Sleep mode (if entered), enable the
HLVD bit (HLVDCON<4> = 1).
3.
HLVDCONbits.HLVDEN = 1;
4.
Wait for the internal reference voltage (TIRVST)
to stabilize (typically 25 s).
5.
Re-enable BOR
(RCON<6> = 1).
while(!HLVDCONbits.IRVST);
by
setting
SBOREN
WDTCONbits.SBOREN = 1;
6.
Disable the HLVD
(HLVDCON<4> = 0).
by
clearing
HLVDCONbits.HLVDEN = 0;
Affected Silicon Revisions
HLVDEN
4.
Set the ECANCON register EWIN bits to the
desired buffer.
ECANCONbits.EWIN = Buffer_Selection;
Decode the desired buffer to each individual
Buffer Control register, BnCON 0<n<5.
switch (Buffer_Selection)
{
//EWIN code for Buffer B0
case 18:
break;
//EWIN code for Buffer B5
case 23:
break;
default:
break;
}
Process information in the selected buffer
control register. Note that the BnCON 0<n<5
Control registers can be set up for either
transmit or receive operations.
case 18:
//Save B0CON and clear flags
being processed
temp = B0CON;
//clear any flags
break;
Continue processing the rest of the buffer in the
windowed location.
Affected Silicon Revisions
A2
A3
A4
A6
A2
X
X
X
X
X
DS80000519K-page 6
A3
A4
A6
2011-2016 Microchip Technology Inc.
PIC18F66K80
9. Module: MCLRE
11. Module: Timer1/Timer3
The Master Clear pin will not be readable when
MCLRE is set to off for all 28-pin part variants
(PIC18F2XK80). When the MCLRE bit,
CONFIG3H<7>, is cleared on the 28-pin devices,
the MCLR pin will be disabled but input data will
not be available on RE3.
Work around
None.
When Timer1 or Timer3 is operated in
Asynchronous External Input mode, unexpected
interrupt flag generation may occur if an external
clock edge arrives too soon following a firmware
write to the TMRxH:TMRxL registers. An
unexpected interrupt flag event may also occur
when enabling the module or switching from
Synchronous to Asynchronous mode.
Work around
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
This issue only applies when operating the timer
in Asynchronous mode. Whenever possible,
operate the Timer module in Synchronous mode
to avoid spurious timer interrupts.
10. Module: Timer1/Timer3
Timer1 and Timer3 gate control will not function up
to the speed of FOSC when the TxCON is set to the
system clock (TxCON<7:6> = 01). Results will
always be at the resolution of FOSC/4, although the
internal FOSC has been selected as the clock
source.
Work around
Use the external clock input pin
TxCON<7:6> = 10 and TxCON<3> = 0.
Affected Silicon Revisions
A2
A3
X
X
A4
A6
2011-2016 Microchip Technology Inc.
setting,
If Asynchronous mode must be used in the
application, potential strategies to mitigate the
issue may include any of the following:
• Design the firmware so it does not rely on
the TMRxIF flag or keep the respective
interrupt disabled. The timer still counts
normally and does not reset to 0x0000
when the spurious interrupt flag event is
generated.
• Design the firmware so that it does not
write to the TMRxH:TMRxL registers or
does not periodically disable/enable the
timer, or switch modes. Reading from the
timer does not trigger the spurious interrupt
flag events.
• If the firmware must use the timer interrupts
and must write to the timer (or disable/
enable, or mode switch the timer),
implement code to suppress the spurious
interrupt event, should it occur. This can be
achieved by following the process shown in
Example 1.
DS80000519K-page 7
PIC18F66K80
EXAMPLE 1:
ASYNCHRONOUS TIMER MODE WORK AROUND TO AVOID SPURIOUS
INTERRUPT
//Timer1 update procedure in asynchronous mode
//The code below uses Timer1 as example
T1CONbits.TMR1ON = 0;
PIE1bits.TMR1IE = 0;
TMR1H = 0x00;
TMR1L = 0x00;
T1CONbits.TMR1ON = 1;
//Stop timer from incrementing
//Temporarily disable Timer1 interrupt vectoring
//Update timer value
//Turn on timer
//Now wait at least two full T1CKI periods + 2TCY before re-enabling Timer1 interrupts.
//Depending upon clock edge timing relative to TMR1H/TMR1L firmware write operation,
//a spurious TMR1IF flag event may sometimes assert. If this happens, to suppress
//the actual interrupt vectoring, the TMR1IE bit should be kept clear until
//after the "window of opportunity" (for the spurious interrupt flag event has passed).
//After the window is passed, no further spurious interrupts occur, at least
//until the next timer write (or mode switch/enable event).
while(TMR1L < 0x02);
//Wait for 2 timer increments more than the Updated Timer
//value (indicating more than 2 full T1CKI clock periods elapsed)
//Wait two more instruction cycles
NOP();
NOP();
PIR1bits.TMR1IF = 0;
PIE1bits.TMR1IE = 1;
//Clear TMR1IF flag, in case it was spuriously set
//Now re-enable interrupt vectoring for timer 1
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
12. Module: Primary Oscillator (XT Mode)
On some parts, using the XT oscillator at the top
end of its specified frequency range (3.0-4.0 MHz)
may cause the part to cease driving the oscillator.
Work around
Use the XT mode only for frequencies lower than
3.0 MHz.
Use the HS mode if frequencies greater than
4.0 MHz on a crystal oscillator are required.
Affected Silicon Revisions
A2
A3
A4
X
X
X
DS80000519K-page 8
A6
13. Module: ECAN
When the ECAN module is placed into Disable/
Sleep mode, the CANTX pin will revert to being
controlled by the PORTx/TRISx/LATx registers,
instead of staying in the recessive state as
intended.
Work around
If Disable/Sleep mode of the ECAN is to be used,
set the TRIS bit associated with the TX pin (either
TRISB2 if the CANMX Configuration bit is set,
TRISC6 if the CANMX Configuration bit is cleared
on the 28-pin and 40/44-pin packages, or TRISE4
if the CANMX Configuration bit is cleared on
64-pin packages) and ensure that the CANTX line
has a proper pull up to VDD. This will ensure that,
when the pin is controlled by TRIS/LAT settings, it
will be pulled to the CAN Recessive state and not
cause issues on the CAN bus.
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
2011-2016 Microchip Technology Inc.
PIC18F66K80
14. Module: ECAN
A very small number of CAN applications are
experiencing a low-failure rate when the
microcontroller core is clocked by an oscillator
through a PLL (either the PLLCFG bit is cleared or
the PLLEN bit of OSCTUNE is set) and the ECAN
module is clocked by the same clock without a PLL
(the CLKSEL bit of CIOCON is set). This failure
mechanism is characterized by incoming CAN
messages rarely being missed, with the ECAN
module acknowledging the incoming message on
the bus but not triggering interrupts or transferring
the incoming data into the receive buffers.
Work around
If it is essential that the application never misses a
message, it is recommended that both the ECAN
module and the microcontroller be clocked either
through the PLL or without a PLL. This can be
achieved by ensuring that the CLKSEL bit of
CIOCON remains cleared.
Affected Silicon Revisions
A2
A3
A4
A6
X
X
X
X
2011-2016 Microchip Technology Inc.
DS80000519K-page 9
PIC18F66K80
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS39977F):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
1. Module: A/D Converter Characteristics
The values in Table 31-25 reflect the updated A/D
Converter Characteristics. The new information is
shown in bold text.
TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F66K80 FAMILY
(INDUSTRIAL/EXTENDED)
Param
Sym.
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
A01
NR
Resolution
—
—
12
bit
VREF 5.0V
A03
EIL
Integral Linearity Error
—
<±1
±6.0
LSB
VREF 5.0V
A04
EDL
Differential Linearity Error
—
<±1
+3.0/-1.0
LSB
VREF 5.0V
A06
EOFF
Offset Error
—
<±1
±9.0
LSB
VREF 5.0V
A07
EGN
Gain Error
—
<±1
±8.0
LSB
A10
—
A20
Monotonicity(1)
—
VREF Reference Voltage Range
(VREFH – VREFL)
3
VREF 5.0V
—
VSS VAIN VREF
—
VDD – VSS
V
For 12-bit resolution
A21
VREFH Reference Voltage High
AVSS + 3.0V
—
AVDD + 0.3V
V
For 12-bit resolution
A22
VREFL Reference Voltage Low
AVSS – 0.3V
—
AVDD – 3.0V
V
For 12-bit resolution
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A28
AVDD
Analog Supply Voltage
VDD – 0.3
—
VDD + 0.3
V
A29
AVSS
Analog Supply Voltage
VSS – 0.3
—
VSS + 0.3
V
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5
k
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
A
A
Note 1:
2:
During VAIN acquisition.
During A/D conversion cycle.
The A/D conversion result never decreases with an increase in the input voltage.
VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
2. Module: Electrical Characteristics
Parameter D041 in Section 31.3 “DC
Characteristics:
PIC18F66K80
Family
(Industrial)” on page 555 of the data sheet lists
its minimum value as 0.8. This should be
0.8 VDD.
DS80000519K-page 10
3. Module: A/D Converter
Bits 5-4 of Register 23-2: ADCON1
(VCFG<1:0>) should have the following note
attached:
Note 1: When CHS<4:0> = 11111, a
VCFG<1:0> value of 10 or 11 is not allowed.
2011-2016 Microchip Technology Inc.
PIC18F66K80
4. Module: I/O Ports
4.1 Open-Drain Outputs Description
Page 173 Section 11.1.3 ‘Open-Drain Outputs’
will be revised to:
The output pins for several peripherals are also
equipped with a configurable, open-drain output
option. This allows the peripherals to
communicate with external pull-up voltage.
The open-drain option is implemented on port pins
specifically associated with the data and clock
outputs of the USARTs, the MSSP module (in SPI
mode) and the CCP modules. This option is
selectively enabled by setting the open-drain
control bits in the ODCON register.
When the open-drain option is required, the
output pin must also be tied through an external pull-up resistor provided by the user.
4.2 Open-Drain Outputs Diagram
Figure 11-2: Using the Open-Drain Output
(Usart Shown as Example) on page 173 should
be as follows:
FIGURE 11-2:
USING THE OPEN-DRAIN
OUTPUT (USARTx
SHOWN AS EXAMPLE)
5.5V
+5.5V
PIC18F66K80
VDD
TXX
(at logic ‘1’)
5V
2011-2016 Microchip Technology Inc.
5.5V
DS80000519K-page 11
PIC18F66K80
5. Module: A/D Converter
Bits
2-0
of
Register 23-2
(CHSN<2:0>) should be as follows:
REGISTER 23-2:
ADCON1
ADCON1: A/D CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
TRIGSEL1
TRIGSEL0
VCFG1
VCFG0
VNCFG
CHSN2
CHSN1
CHSN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TRIGSEL<1:0>: Special Trigger Select bits
11 = Selects the special trigger from the CCP2
10 = Selects the special trigger from the Timer1
01 = Selects the special trigger from the CTMU
00 = Selects the special trigger from the ECCP1
bit 5-4
VCFG<1:0>: A/D VREF+ Configuration bits
11 = Internal VREF+ (4.1V)
10 = Internal VREF+ (2.0V)
01 = External VREF+
00 = AVDD
bit 3
VNCFG: A/D VREF- Configuration bit
1 = External VREF
0 = AVSS
bit 2-0
CHSN<2:0>: Analog Negative Channel Select bits
111 = Reserved
110 = Channel 06 (AN5)
101 = Channel 05 (AN4)
100 = Channel 04 (AN3)
011 = Channel 03 (AN2)
010 = Channel 02 (AN1)
001 = Channel 01 (AN0)
000 = Channel 00 (AVSS)
DS80000519K-page 12
x = Bit is unknown
2011-2016 Microchip Technology Inc.
PIC18F66K80
6. Module: A/D Converter
The ADSGN<3:0> bits in Register 23-5 and the
ADSGN<7:4> bits in Register 23-6 are
improperly labeled as Unimplemented. The
correct registers are below:
REGISTER 23-5:
ADRESL: A/D RESULT LOW BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES3
ADRES2
ADRES1
ADRES0
ADSGN3
ADSGN2
ADSGN1
ADSGN0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
ADRES<3:0>: A/D Result Low Byte bits
bit 3-0
ADSGN<3:0>: A/D Result Sign bits
1 = A/D result is negative
0 = A/D result is positive
REGISTER 23-6:
x = Bit is unknown
ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADSGN7
ADSGN6
ADSGN5
ADSGN4
ADRES11
ADRES10
ADRES9
ADRES8
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
ADSGN<7:4>: A/D Result Sign bits
1 = A/D result is negative
0 = A/D result is positive
bit 3-0
ADRES<11:8>: A/D Result High Byte bits
x = Bit is unknown
7. Module: ECCP Compare Mode
The following text should be added to the Compare
Mode section of the data sheet.
19.3.5
COMPARE MODE INTERRUPT
TIMING
For all Compare modes, an interrupt may be triggered
when the selected TIMER register pair matches the
value in the CCPRx register pair. This interrupt will be
triggered upon the timer transitioning from the value of
the CCPRx register pair to the next value.
2011-2016 Microchip Technology Inc.
DS80000519K-page 13
PIC18F66K80
8. Module: Product Identification System
The Product Identification System is missing a
few package type codes. The correct list is as
follows:
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device(1,2)
PIC18LF66K80-I/MR 301 = Industrial temp.,
QFN package, Extended VDD limits, QTP
pattern #301.
PIC18LF66K80-I/PT = Industrial temp., TQFP
package, Extended VDD limits.
PIC18F65K80, PIC18F46K80, PIC18F45K80, PIC18F26K80,
PIC18F25K80, PIC18LF66K80
VDD range 1.8V to 5V
PIC18LF25K80, PIC18LF26K80, PIC18LF45K80,
PIC18LF46K80, PIC18F25K80, PIC18LF66K80
VDD range 1.8V to 3.6V
Temperature Range
I
E
= -40C to +85C
= -40C to +125C
Package
P
MR
=
=
ML
MM
=
=
SO
SP
SS
PT
=
=
=
=
Pattern
a)
DS80000519K-page 14
(Industrial)
(Extended)
PDIP Plastic Dual In-Line
64-Pin QFN Plastic Quad Flat, No Lead
Package
44-Pin QFN Plastic Quad Flat, No Lead Package
28-Pin QFN Plastic Quad Flat, No Lead
Package
SOIC Plastic Small Outline
SPDIP Skinny Plastic Dual In-Line
SSOP Plastic Shrink Small Outline
TQFP Plastic Thin Quad Flatpack
Note 1:
2:
F = Standard Voltage Range
LF = Low Voltage Range
T = in tape and reel, TQFP
packages only.
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2011-2016 Microchip Technology Inc.
PIC18F66K80
9. Module: ECAN
In Register 27-55, CIOCON: CAN I/O Control
Register, Bit 4 has an incorrect description for its
settings. The correct description is as follows:
bit 4
CANCAP: CAN Message Receive Capture Enable bit
1 = Enable CAN capture; CAN message receive signal replaces input in RC2/CCP2
0 = Disable CAN capture; RC2/CCP2 input to CPP2 module
10. Module: Power-Managed Modes
In Table 4-1: Power-Managed Modes, the
column “IDLEN<7>” under “OSCCON Bits”
should instead read ‘IDLEN”.
2011-2016 Microchip Technology Inc.
DS80000519K-page 15
PIC18F66K80
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (2/2011)
Initial release of this document; issued for revision,
A2. Includes silicon issues 1 (Analog-to-Digital
Converter), 2 (EUSART), 3 (ECCP), 4 (ECAN), 5
(Ultra Low-Power Sleep) and 6 (IPD and IDD).
Rev B Document (4/2011)
Added silicon issues 7 (Reset – BOR) and 8 (ECAN).
Added data sheet clarifications 1, 2 (RXFCON
Registers) and 3 (Listen Only Mode).
Rev J Document (7/2015)
Data Sheet Clarifications:
Removed the following modules, data sheet has been
updated: Module 1: RXFCON Registers; Module 2:
RXFCON Registers; Module 3: Listen Only Mode;
Module 5: HLVD; Module 6: Power-up Timer Period.
Renumbered remaining modules.
Rev K Document (04/2016)
Added Silicon Errata Issues 13 and 14. Other minor
corrections.
Data Sheet Clarifications: Added Module 9 (ECAN) and
Module 10 (Power-Managed Modes).
Rev C Document (9/2011)
Added Table 3, 10-Bit A/D Converter Characteristics
to silicon issue 1 (Analog-to-Digital Converter). Added
silicon issues 9 (MCLRE) and 10 (Timer1/Timer3).
Added data sheet clarifications 4 (A/D Converter
Characteristics) and 5 (HLVD).
Rev D Document (12/2011)
Added silicon revision A4; includes issues 1
(Analog-to-Digital Converter – A/D), 3 (ECCP),
7 (Reset – BOR) issues 9 (MCLRE). Added data sheet
clarification 6 (Power-up Timer Period).
Updated data sheet revision level to “D”. All previous
clarifications carried into this revision.
Rev E Document (12/2013)
Added MPLAB X IDE; Updated silicon issue 1
(Analog-to-Digital Converter); Added silicon issue 11
(Primary Oscillator); Other minor corrections;
Data Sheet Clarifications: Added Module 7 (Electrical
Characteristics) and Module 8 (A/D Converter).
Rev F Document (2/2014)
Added Silicon Revision A6; Data Sheet Clarification:
Added Module 9 and 10; Other minor corrections.
Rev G Document (4/2014)
Data Sheet Clarifications: Added Module 11; Other
minor corrections.
Rev H Document (7/2014)
Added Module 11, Timer1/Timer3 to Silicon errata
Issues section.
DS80000519K-page 16
2011-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2011-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0465-1
DS80000519K-page 17
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DS80000519K-page 18
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