PIC18F6XKXX/8XKXX FAMILY Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW 2.1 When programming with the ICSP, the PIC18F6XKXX/ 8XKXX family requires two programmable power supplies: one for VDD and one for MCLR/VPP/RG5. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode” for additional hardware parameters. This document includes the programming specifications for the following devices: • PIC18F65K22 • PIC18F85K22 • PIC18F65K90 • PIC18F85K90 • PIC18F66K22 • PIC18F86K22 • PIC18F66K90 • PIC18F86K90 • PIC18F67K22 • PIC18F87K22 • PIC18F67K90 • PIC18F87K90 2.0 Hardware Requirements 2.1.1 LOW-VOLTAGE ICSP™ PROGRAMMING In Low-Voltage ICSP mode, the PIC18F6XKXX/8XKXX family can be programmed using a VDD source in the operating range. The MCLR/VPP/RG5 does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode” for additional hardware parameters. PROGRAMMING OVERVIEW The PIC18F6XKXX/8XKXX family of devices can be programmed using the In-Circuit Serial Programming™ (ICSP™) method. This programming specification applies to the PIC18F6XKXX/8XKXX family of devices in all package types. 2.2 Pin Diagrams The pin diagrams for the PIC18F6XKXX/8XKXX family are shown in Figure 2-1 and Figure 2-2. TABLE 2-1: Pin Name PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F6XKXX/8XKXX FAMILY During Programming Pin Name Pin Type MCLR/VPP/RG5 VPP P Programming Enable VDD(1) SS(1) VDD P Power Supply VSS P Ground AVDD AVDD P Analog Power Supply AVSS AVSS P Analog Ground RB6 PGC I Serial Clock RB7 PGD I/O Serial Data V Pin Description ENVREG ENVREG P Internal Voltage Regulator Enable VDDCORE/ VCAP VDDCORE P Regulated Power Supply for Microcontroller Core VCAP I Filter Capacitor for On-Chip Voltage Regulator Legend: I = Input, O = Output, P = Power Note 1: All power supply (VDD) and ground (VSS) pins must be connected. 2010 Microchip Technology Inc. DS39947B-page 1 PIC18F6XKXX/8XKXX FAMILY FIGURE 2-1: PIC18F6XKXX FAMILY PIN DIAGRAM RE1 RE0 RG0 RG1 RG2 RG3 MCLR/VPP/RG5 RG4 VSS RD7 RD6 RD5 RD2 RD1 VSS VDD RD0 RE7 RE6 RE5 RE4 RD4 53 52 51 50 49 1 48 2 3 47 46 45 4 5 RF7 RF6 RF5 RF4 6 7 8 9 10 11 12 13 14 RF3 RF2 15 16 VDDCORE/VCAP RE3 RE2 The following devices are included in 64-pin TQFP parts: • PIC18F65K22 • PIC18F65K90 • PIC18F66K22 • PIC18F66K90 • PIC18F67K22 • PIC18F67K90 64 63 62 61 60 59 58 57 56 55 54 RD3 64-Pin TQFP 44 43 42 41 40 PIC18F6XKXX 39 38 37 36 35 34 33 RB0 RB1 RB2 RB3 RB4 RB5 RB6/PGC VSS RA6 RA7 VDD RB7/PGD RC5 RC4 RC3 RC2 DS39947B-page 2 RC7 RC6 RC0 RA4 RC1 RA5 VDD VSS RA0 RA1 RA2 AVSS RA3 AVDD RF1 ENVREG 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY FIGURE 2-2: PIC18F8XKXX FAMILY PIN DIAGRAM RJ1 RJ0 RD7 RD6 RD5 RD4 RD2 RD1 VSS VDD RD0 RE7 RE6 RE5 RE4 RE3 RE2 RH0 RH1 The following devices are included in 80-pin TQFP parts: • PIC18F85K22 • PIC18F85K90 • PIC18F86K22 • PIC18F86K90 • PIC18F87K22 • PIC18F87K90 RD3 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2 RH3 1 2 RE1 RE0 RG0 RG1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RG2 RG3 MCLR/VPP/RG5 RG4 VSS VDDCORE/VCAP RF7 RF6 RF5 RF4 RF3 RF2 RH7 RH6 60 59 58 57 56 55 54 53 52 51 50 PIC18F8XKXX 49 48 47 46 45 44 17 18 19 20 43 42 41 RJ2 RJ3 RB0 RB1 RB2 RB3 RB4 RB5 RB6/PGC VSS RA6 RA7 VDD RB7/PGD RC5 RC4 RC3 RC2 RJ7 RJ6 2010 Microchip Technology Inc. RJ5 RJ4 RC7 RC6 RC0 RA5 RA4 RC1 VDD VSS RA0 RA1 RA2 AVSS RA3 AVDD ENVREG RF1 RH4 RH5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DS39947B-page 3 PIC18F6XKXX/8XKXX FAMILY 2.3 On-Chip Voltage Regulator All of the PIC18F6XKXX/8XKXX devices have dual power requirements. The microcontroller core can be powered from an external source that is separate from VDD, or it can be powered from an on-chip regulator which derives power from VDD. Both sources use the common VDDCORE/VCAP pin. The regulator is enabled by connecting VDD to the ENVREG pin. In this case, a low ESR capacitor must be connected to the VDDCORE/VCAP pin for proper device operation. If the regulator is disabled by connecting VSS to the ENVREG pin, power to the core is supplied directly by VDD. The voltage levels for VDD must not exceed the specified VDDCORE levels. A bypass capacitor should be connected to the VDDCORE/ VCAP pin, but is not required. Whether or not the regulator is used, it is always good design practice to have sufficient capacitance on all supply pins. Examples are shown in Figure 2-3. The specifications for core voltage and capacitance are listed in Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode”. FIGURE 2-3: CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 5V(1) PIC18F6XJXX/8XJXX VDD ENVREG VDDCORE/VCAP CF VSS Regulator Disabled (ENVREG tied to Ground): 3.3V(1) PIC18F6XJXX/8XJXX VDD ENVREG VDDCORE/VCAP(2) VSS Note 1: These are typical operating voltages. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode”. 2: When the regulator is disabled, VDDCORE/ VCAP may be left floating or connected to a bypass capacitor. DS39947B-page 4 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 2.4 Memory Maps For PIC18FX7K90/X7K22 devices, the code memory space extends from 000000h to 01FFFFh (128 Kbytes) in eight 16-Kbyte blocks. For PIC18FX6K90/X6K22 devices, the code memory space extends from 000000h to 00FFFFh (64 Kbytes) in four 16-Kbyte blocks. For PIC18FX5K90/X5K22 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. The size of the Boot Block in PIC18F6XKXX/8XKXX devices can be configured as 1 or 2K words (see Table 5-1). This is done through the BBSIZ0 bit in the Configuration register, CONFIG4L. It is important to note that increasing the size of the Boot Block decreases the size of Block 0. 2010 Microchip Technology Inc. TABLE 2-2: Device IMPLEMENTATION OF CODE MEMORY Code Memory Size (Bytes) PIC18F65K22 PIC18F65K90 PIC18F85K22 000000h-007FFFh (32K) PIC18F85K90 PIC18F66K22 PIC18F66K90 PIC18F86K22 000000h-00FFFFh (64K) PIC18F86K90 PIC18F67K22 PIC18F67K90 PIC18F87K22 000000h-01FFFFh (128K) PIC18F87K90 DS39947B-page 5 PIC18F6XKXX/8XKXX FAMILY FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18F6XKXX/8XKXX DEVICES(1) 000000h 01FFFFh Code Memory Device/Memory Size PIC18FX7K90/X7K22 PIC18FX6K90/X6K22 PIC18FX5K90/X5K22 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Unimplemented Read as ‘0’ Boot Block(2) 2 KW Block 0 6 KW Boot Block(2) Block 0 7 KW Boot Block(2) 2 KW Block 0 6 KW Block 1 8 KW Boot Block(2) Block 0 7 KW Block 1 8 KW Block 0 2 KW Boot Block(2) Block 0 3 KW 0000h 0800h 1000h 1FFFh Block 1 4 KW Block 1 4 KW 2000h 3FFFh Block 2 4 KW Block 2 4 KW 4000h 5FFFh Block 3 4 KW Block 3 4 KW 6000h 7FFFh Block 1 8 KW Block 1 8 KW Block 2 8 KW Block 2 8 KW Block 2 8 KW Block 2 8 KW 8000h BFFFh Block 3 8 KW Block 3 8 KW Block 3 8 KW Block 3 8 KW C000h FFFFh Block 4 8 KW Block 4 8 KW 10000h 13FFFh Block 5 8 KW Block 5 8 KW 14000h 17FFFh Block 6 8 KW Block 6 8 KW 18000h 1BFFFh Block 7 8 KW Block 7 8 KW 1C000h 1FFFFh 200000h Configuration and ID Space Boot Block(2) 2 KW Address 3FFFFFh Note 1: 2: Sizes of memory areas are not to scale. Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>). DS39947B-page 6 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY In addition to the code memory space, there are three blocks in the configuration and ID space that are accessible to the user through table reads and Table Writes. Their locations in the memory map are shown in Figure 2-5. Users may store Identification information (ID) in eight ID registers. These ID registers are mapped in addresses, 200000h through 200007h. The ID locations read out normally, even after code protection is applied. Locations, 300000h through 30000Dh, are reserved for the Configuration bits. These bits select various device options and are described in Section 5.0 “Configuration Word”. These Configuration bits read out normally, even after code protection. Locations, 3FFFFEh and 3FFFFFh, are reserved for the Device ID bits. These bits may be used by the programmer to identify what device type is being programmed and are described in Section 5.0 “Configuration Word”. These Device ID bits read out normally, even after code protection. 2010 Microchip Technology Inc. 2.4.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three Pointer registers: • TBLPTRU, at RAM address 0FF8h • TBLPTRH, at RAM address 0FF7h • TBLPTRL, at RAM address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr<21:16> Addr<15:8> Addr<7:0> The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations. DS39947B-page 7 PIC18F6XKXX/8XKXX FAMILY FIGURE 2-5: CONFIGURATION AND ID LOCATIONS FOR PIC18F6XKXX/8XKXX FAMILY DEVICES 000000h Code Memory 01FFFFh Unimplemented Read as ‘0’ 1FFFFFh Configuration and ID Space 2FFFFFh ID Location 1 200000h ID Location 2 200001h ID Location 3 200002h ID Location 4 200003h ID Location 5 200004h ID Location 6 200005h ID Location 7 200006h ID Location 8 200007h CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. DS39947B-page 8 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 2.5 High-Level Overview of the Programming Process Figure 2-6 shows the high-level overview of the programming process. First, a Block Erase is performed for each block. Next, the code memory, ID locations and data EEPROM are programmed. These memories are then verified to ensure that programming was successful. If no errors are detected, the Configuration bits are then programmed and verified. FIGURE 2-6: HIGH-LEVEL PROGRAMMING FLOW Start Perform Sequential Block Erase Procedure Program Memory Program IDs Program Data EE 2.6 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Figure 2-8, entering High-Voltage ICSP Program/Verify mode requires two steps. First, voltage is applied to the MCLR pin. Second, a 32-bit key sequence is presented on PGD. The programming voltage applied to MCLR is VIHH. VIHH must be applied to MCLR during the transfer of the key sequence. After VIHH is applied to MCLR, an interval of at least P12 must elapse before presenting the key sequence on PGD. The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the most significant nibble must be shifted in first. Once the key sequence is complete, Program/Verify mode is entered, and the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. Exiting Program/Verify mode is done by removing VIHH from MCLR, as shown in Figure 2-10. The only requirement for exit is that an interval, P16, should elapse between the last clock and the program signals on PGC and PGD before removing VIHH. Verify Program Verify IDs Verify Data Program Configuration Bits Verify Configuration Bits Done 2010 Microchip Technology Inc. DS39947B-page 9 PIC18F6XKXX/8XKXX FAMILY FIGURE 2-7: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE P13 P1 VIH VIH MCLR VDD Program/Verify Entry Code = 4D434850h 0 b31 PGD 1 b30 0 b29 0 b28 1 ... b27 0 b3 0 b2 0 b1 0 b0 0 b1 0 b0 PGC P2B P2A P12 FIGURE 2-8: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P1 MCLR VIHH VDD Program/Verify Entry Code = 4D434850h 0 b31 PGD 1 b30 0 b29 0 b8 1 ... b27 0 b3 0 b2 PGC P12 DS39947B-page 10 P2B P2A 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY FIGURE 2-9: EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE P16 P17 VDD Exiting Program/Verify mode is done by grounding the MCLR again, as shown in Figure 2-9. The only requirement for exit is that an interval, P16, should elapse between the last clock and the program signals on PGC and PGD before grounding MCLR. PGD 2.8 MCLR/VPP/RG5 P1 D041 PGD = Input FIGURE 2-10: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 MCLR/VPP/RG5 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC and are Least Significant bit (LSb) first. PGC P17 P1 D110 2.8.1 4-BIT COMMANDS All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-3. Commands and data are entered LSb first. Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data, or 8 bits of input data and 8 bits of output data. VDD PGD PGC PGD = Input 2.7 ing data on PGD. On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command and data are shown Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown <LSB><MSB>. Figure 2-11 demonstrates how to serially present a 20-bit command/operand to the device. Entering and Exiting Low-Voltage ICSP Program/Verify Mode As shown in Figure 2-7, entering low-voltage ICSP Program/Verify mode requires three steps: 1. 2. 3. The MCLR pin is grounded. A 32-bit key sequence is presented on PGD. The MCLR pin is brought to VDD The MCLR pin must be grounded during the transfer of the key sequence. After MCLR is grounded, an interval of at least P12 must elapse before presenting the key sequence on PGD. The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH, or usually VDD, must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. There is no minimum time requirement before present- 2010 Microchip Technology Inc. DS39947B-page 11 PIC18F6XKXX/8XKXX FAMILY 2.8.2 TABLE 2-4: CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as appropriate for use with other commands. TABLE 2-3: COMMANDS FOR PROGRAMMING Core Instruction (shift in16-bit instruction) 0000 Shift out TABLAT register 0010 Table Read 1000 Table Read, Post-Increment 1001 Table Read, Post-Decrement 1010 Table Read, Pre-Increment 1011 Table Write 1100 Table Write, Post-Increment by 2 1101 Table Write, Start Programming, Post-Increment by 2 1110 Table Write, Start Programming 1111 Data Payload 1101 3C 40 Core Instruction Table Write, post-increment by 2 TABLE WRITE, POST-INCREMENT TIMING (1101) P2 1 4-Bit Command 4-Bit Command Description FIGURE 2-11: SAMPLE COMMAND SEQUENCE 2 3 P2A P2B 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 LSB P3 PGD 1 LSb 0 1 1 MSb 4-Bit Command 0 LSb 0 0 0 0 0 MSB 0 1 0 0 0 1 4 C 16-Bit Data Payload 1 1 1 0 3 0 n n n n MSb Fetch Next 4-Bit Command PGD = Input DS39947B-page 12 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 3.0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. In all cases, except ICSP Block Erase, the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). REGISTER 3-1: The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g., erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit only be set immediately prior to a program or erase. EECON1 REGISTER R/W-x EEPGD R/W-x CFGS U-0 — R/W-0 FREE R/W-x (1) WRERR R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase/write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. The RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared Note 1: 2010 Microchip Technology Inc. ‘1’ = Bit is set x = Bit is unknown When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39947B-page 13 PIC18F6XKXX/8XKXX FAMILY 3.1 3.1.1 ICSP Erase TABLE 3-2: ICSP BLOCK ERASE Erasing code or data EEPROM is accomplished by configuring three Block Erase Control registers located at 3C0004h and 3C0006h. Code memory can only be erased, portions at a time. In order to erase the entire device, every block must be erased sequentially. Block Erase operations will also clear any code-protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. Data EEPROM is erased at the same time as all Block Erase commands. In order to erase data EEPROM by itself, the first code sequence in Table 3-1 must be used. If the entire device is being erased, this code is not necessary. TABLE 3-1: BLOCK ERASE OPERATIONS Description Data (3C0006h:3C0004h) Erase Data EEPROM Erase Boot Block Erase Config Bits Erase Code EEPROM Block 0 Erase Code EEPROM Block 1 Erase Code EEPROM Block 2 Erase Code EEPROM Block 3 Erase Code EEPROM Block 4 Erase Code EEPROM Block 5 Erase Code EEPROM Block 6 Erase Code EEPROM Block 7 800004h 800005h 800002h 800104h 800204h 800404h 800804h 801004h 802004h 804004h 808004h The actual Block Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the NOP command), serial execution will cease until the erase completes (Parameter P11). During this time, PGC may continue to toggle but PGD must be held low. The code sequence to erase the entire device is shown in Table 3-2 through Table 3-11, and the flowchart is shown in Figure 3-1. The code sequence to erase just data EEPROM is shown in Table 3-12. Note: A Block Erase is the only way to reprogram code-protect bits from an ON state to an OFF state. DS39947B-page 14 4-Bit Command ERASE BLOCK 0 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 01 0E 6E 80 0000 0000 00 00 00 00 TABLE 3-3: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0000 0000 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 01h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 0 NOP Hold PGD low until erase completes ERASE BLOCK 1 Data Payload 0E 6E 0E 6E 0E 6E 04 0E 6E 02 0E 6E 80 3C F8 00 F7 04 F6 04 05 F6 02 06 F6 80 00 00 00 00 TABLE 3-4: 4-Bit Command 3C F8 00 F7 04 F6 04 05 F6 01 06 F6 80 Core Instruction Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 02h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3c0006h to erase block 1 NOP Hold PGD low until erase completes ERASE BLOCK 2 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 04 0E 6E 80 0000 0000 00 00 00 00 3C F8 00 F7 04 F6 04 05 F6 04 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 04h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 2 NOP Hold PGD low until erase completes 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 3-5: 4-Bit Command ERASE BLOCK 3 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 08 0E 6E 80 0000 0000 00 00 00 00 TABLE 3-6: 4-Bit Command 3C F8 00 F7 04 F6 04 05 F6 08 06 F6 80 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 08h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 3 NOP Hold PGD low until Erase completes ERASE BLOCK 4 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 10 0E 6E 80 0000 0000 00 00 00 00 TABLE 3-7: 4-Bit Command Core Instruction 3C F8 00 F7 04 F6 04 05 F6 10 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 10h to 3C0005h to MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 4 NOP Hold PGD low until Erase completes ERASE BLOCK 5 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 20 0E 6E 80 0000 0000 00 00 00 00 3C F8 00 F7 04 F6 04 05 F6 20 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 20h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 5 NOP Hold PGD low until Erase completes 2010 Microchip Technology Inc. TABLE 3-8: 4-Bit Command ERASE BLOCK 6 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 40 0E 6E 80 0000 0000 00 00 00 00 TABLE 3-9: 4-Bit Command 3C F8 00 F7 04 F6 04 05 F6 40 06 F6 80 MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOFWF TBLPTRL Write 40h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 6 NOP Hold PGD low until Erase completes ERASE BLOCK 7 Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 80 0E 6E 80 0000 0000 00 00 00 00 TABLE 3-10: 4-Bit Command Core Instruction 3C F8 00 F7 04 F6 04 05 F6 80 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 80h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase block 7 NOP Hold PGD low until Erase completes ERASE BOOT BLOCK Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 05 0E 6E 00 0E 6E 80 0000 0000 00 00 00 00 3C F8 00 F7 04 F6 05 05 F6 00 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 05h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 00h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase boot block NOP Hold PGD low until Erase completes DS39947B-page 15 PIC18F6XKXX/8XKXX FAMILY TABLE 3-11: 4-Bit Command ERASE CONFIGURATION FUSES Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 02 0E 6E 00 0E 6E 80 0000 0000 00 00 00 00 DS39947B-page 16 3C F8 00 F7 04 F6 02 05 F6 00 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 02h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 00h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase configuration fuses NOP Hold PGD low until Erase completes TABLE 3-12: 4-Bit Command ERASE DATA EEPROM Data Payload 0000 0000 0000 0000 0000 0000 1100 0000 0000 1100 0000 0000 1100 0E 6E 0E 6E 0E 6E 04 0E 6E 00 0E 6E 80 0000 0000 00 00 00 00 3C F8 00 F7 04 F6 04 05 F6 00 06 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 04h to 3C0004h MOVLW 05h MOVWF TBLPTRL Write 00h to 3C0005h MOVLW 06h MOVWF TBLPTRL Write 80h to 3C0006h to erase Data EEPROM NOP Hold PGD low until Erase completes 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY FIGURE 3-1: BLOCK ERASE FLOW Start Write 04h to 3C0004h Write 01h to 3C0005h Write 80h to 3C0006h to Erase Block 0 Delay P11 + P10 Time Write 04h to 3C0004h Write 02h to 3C0005h Write 80h to 3C0006h to Erase Block 1 Delay P11 + P10 Time Write 04h to 3C0004h Write 04h to 3C0005h Write 80h to 3C0006h to Erase Block 2 Delay P11 + P10 Time Write 04h to 3C0004h Write 08h to 3C0005h Write 80h to 3C0006h to Erase Block 3 Delay P11 + P10 Time Write 04h to 3C0004h Write 10h to 3C0005h Write 80h to 3C0006h to Erase Block 4 Delay P11 + P10 Time 2010 Microchip Technology Inc. Write 04h to 3C0004h Write 20h to 3C0005h Write 80h to 3C0006h to Erase Block 5 Delay P11 + P10 Time Write 04h to 3C0004h Write 40h to 3C0005h Write 80h to 3C0006h to Erase Block 6 Delay P11 + P10 Time Write 04h to 3C0004h Write 80h to 3C0005h Write 80h to 3C0006h to Erase Block 7 Delay P11 + P10 Time Write 05h to 3C0004h Write 00h to 3C0005h Write 80h to 3C0006h to Erase Boot Block Delay P11 + P10 Time Write 02h to 3C0004h Write 00h to 3C0005h Write 80h to 3C0006h to Erase Config. Fuses Delay P11 + P10 Time Done DS39947B-page 17 PIC18F6XKXX/8XKXX FAMILY FIGURE 3-2: BLOCK ERASE TIMING P10 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4 1 2 n n PGC PGD 0 0 1 1 4-Bit Command 1 1 0 0 16-Bit Data Payload P5A P5 P5A P5 0 0 0 0 4-Bit Command 0 0 0 0 16-Bit Data Payload P11 0 0 0 0 4-Bit Command Erase Time 16-Bit Data Payload PGD = Input 3.1.2 ICSP ROW ERASE It is possible to erase one row (64 bytes of data for PIC18FX5KXX and PIC18FX6KXX devices and 128 bytes of data for PIC18FX7KXX devices) provided the block is not code or write-protected. Rows are located at static boundaries, beginning at program memory address, 000000h, extending to the internal program memory limit (see Section 2.4 “Memory Maps”). The code sequence to Row Erase a PIC18F6XKXX/ 8XKXX family device is shown in Table 3-13. The flowchart, shown in Figure 3-3, depicts the logic necessary to completely erase a PIC18F6XKXX/ 8XKXX family device. The timing diagram that details the Start Programming command, and Parameters P9 and P10, are shown in Figure 3-4. Note: The TBLPTR register can point to any byte within the row intended for erase. The Row Erase duration is externally timed and is controlled by PGC. After the WR bit in EECON1 is set, a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. DS39947B-page 18 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 3-13: 4-Bit Command SINGLE ROW ERASE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 0000 8E 7F 9C 7F 84 7F BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 2: Point to first row in code memory. 0000 0000 0000 6A F8 6A F7 6A F6 CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 3: Enable erase and erase single row. 0000 0000 0000 88 7F 82 7F 00 00 BSF EECON1, FREE BSF EECON1, WR NOP – hold PGC high for time P9 and low for time P10. Step 4: Repeat step 3 with Address Pointer incremented by 64 until all rows are erased. FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Start Addr = 0 Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Addr = Addr + 64 Hold PGC Low for Time P10 No All rows done? Yes Done 2010 Microchip Technology Inc. DS39947B-page 19 PIC18F6XKXX/8XKXX FAMILY 3.2 Code Memory Programming The code sequence to program a PIC18F6XKXX/ 8XKXX family device is shown in Table 3-15. The flowchart shown in Figure 3-6 depicts the logic necessary to completely write a PIC18F6XKXX/8XKXX family device. The timing diagram that details the Start Programming command and Parameters P9 and P10 are shown in Figure 3-4. Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write and erase buffer sizes shown in Table 3-14 can be mapped to any location of the same size beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the Table Pointer. Note: The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued (4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9. TABLE 3-14: After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. FIGURE 3-4: The TBLPTR register must point to the same region when initiating the programming sequence as it did when the write buffers were loaded. WRITE AND ERASE BUFFER SIZES All Devices Write Buffer Size in Bytes Erase Buffer Size in Bytes PIC18FX5KXX/ X6KXX 64 64 PIC18FX7KXX 128 128 TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 PGC 2 3 0 0 0 P9 P5A P5 PGD 1 (1) 1 1 1 1 4-Bit Command n n n n n n n n 16-Bit Data Payload 0 0 0 0 4-bit Command Programming Time 16-Bit Data Payload PGD = Input Note 1: Use P9A for User ID and Configuration Word programming. DS39947B-page 20 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY FIGURE 3-5: ERASE AND WRITE BOUNDARIES TBLPTR<21:16> = 1 64-Byte Write Buffer Panel 2 TBLPTR<5:0> = 63 . . . . . TBLPTR<5:0> = 0 Erase Region 64 Bytes Offset = TBLPTR<15:6> TBLPTR<21:16> = 0 64-Byte Write Buffer Panel 1 TBLPTR<5:0> = 63 . . . . . TBLPTR<5:0> = 0 Erase Region 64 Bytes Offset = TBLPTR<15:6> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. 2010 Microchip Technology Inc. DS39947B-page 21 PIC18F6XKXX/8XKXX FAMILY 3.2.1 PROGRAMMING A maximum of 64 bytes can be programmed into the block referenced by TBLPTR<21:6>. The panel that will be written will automatically be enabled based on the value of the Table Pointer. TABLE 3-15: WRITE CODE MEMORY CODE SEQUENCE FOR PROGRAMMING 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 0000 8E 7F 9C 7F 84 7F BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 2: Load write buffer for panel. Step 3: Repeat for all but the last two bytes. Any unused locations should be filled with FFFFh between MOVWF TBLPTRL and Write 2 bytes, and post-increment address by 2. Step 4: Load write buffer for last two bytes. After this, repeat 28 times. 0000 0000 0000 0000 0000 0000 1101 . . . 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[15:8]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> . . . <MSB><LSB> 00 00 MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 . . Repeat 31 times . Write 2 bytes and start programming NOP - hold SCLK high for time P9, low for time P10 To continue writing data, repeat Steps 3 and 4, where the Address Pointer is incremented by 64 at each iteration of the loop. DS39947B-page 22 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY FIGURE 3-6: PROGRAM CODE MEMORY FLOW Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> LoopCount = LoopCount + 1 No All Bytes Written? Yes Start Write Sequence and Hold PGC High Until Done and Wait P9 No All Locations Done? Yes Done 2010 Microchip Technology Inc. DS39947B-page 23 PIC18F6XKXX/8XKXX FAMILY 3.2.2 MODIFYING CODE MEMORY The previous programming example assumed that the device has been erased entirely prior to programming (see Section 3.1.1 “ICSP Block Erase”). It may be the case, however, that the user wishes to modify only a section of an already programmed device. The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Locations”) and buffered. Modifications can be made on this buffer. Then, the block of code memory that was read out must be erased and rewritten with the modified data (see Section 3.2.1 “Programming”). The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence. TABLE 3-16: MODIFYING CODE MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory. Step 2: Read and modify code memory (see Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”). 0000 0000 8E 7F 9C 7F BSF BCF EECON1, EEPGD EECON1, CFGS Step 3: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[8:15]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF <Addr[21:16]> TBLPTRU <Addr[8:15]> TBLPTRH <Addr[7:0]> TBLPTRL Step 4: Enable memory writes and set up an erase. 0000 0000 84 7F 88 7F BSF BSF EECON1, WREN EECON1, FREE Step 5: Initiate erase. 0000 0000 82 7F 00 00 BSF EECON1, WR NOP - hold PGC high for time P9 and low for time P10. Step 6: Direct access to configuration memory. 0000 0000 0000 8E 7F 8C 7F 84 7F BSF BSF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN Step 7: Direct access to code memory and enable writes. 0000 0000 8E 7F 9C 7F BSF BCF EECON1, EEPGD EECON1, CFGS Step 8: Load write buffer. The correct bytes will be selected based on the Table Pointer. 0000 0000 0000 0000 0000 0000 1101 . . . 1111 0000 0E <Addr[21:16]> 6E F8 0E <Addr[8:15]> 6E F7 0E <Addr[7:0]> 6E F6 <MSB><LSB> . . . <MSB><LSB> 00 00 MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[8:15]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat 31 times Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. To continue modifying data, repeat Steps 2 through 8, where the Address Pointer is incremented by the 64 bytes at each iteration of the loop. Step 9: Disable writes. 0000 94 7F DS39947B-page 24 BCF EECON1, WREN 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 3.3 Data EEPROM Programming FIGURE 3-7: PROGRAM DATA FLOW Data EEPROM is accessed one byte at a time via an Address Pointer (register pair: EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is written by loading EEADRH:EEADR with the desired memory location, EEDATA with the data to be written and initiating a memory write by appropriately configuring the EECON1 register (Register 3-1). A byte write automatically erases the location and writes the new data (erase-before-write). Start Set Address Set Data Enable Write When using the EECON1 register to perform a data EEPROM write, both the EEPGD and CFGS bits must be cleared (EECON1<7:6> = 00). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done prior to initiating a write sequence. The write sequence is initiated by setting the WR bit (EECON1<1> = 1). Start Write Sequence The write begins on the falling edge of the 4th PGC after the WR bit is set. It ends when the WR bit is cleared by hardware. Yes No done? After the programming sequence terminates, PGC must still be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array. FIGURE 3-8: No WR bit clear? Yes Done DATA EEPROM WRITE TIMING P10 1 2 3 4 1 2 1 15 16 2 PGC P5A P5 PGD P11A n 0 0 0 0 4-Bit Command BSF EECON1, WR n 16-Bit Data Payload Poll WR Bit, Repeat until Clear (see below) PGD = Input 1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 PGC P5 P5A P5 P5A Poll WR bit PGD 0 0 0 0 0 0 0 0 4-Bit Command MOVF EECON1, W, 0 PGD = Input 2010 Microchip Technology Inc. 4-Bit Command MOVWF TABLAT Shift Out Data (see Figure 4-4) PGD = Output DS39947B-page 25 PIC18F6XKXX/8XKXX FAMILY TABLE 3-17: PROGRAMMING DATA MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E 7F 9C 7F BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> 62 <AddrH> 63 MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH Step 3: Load the data to be written. 0000 0000 0E <Data> 6E 61 MOVLW <Data> MOVWF EEDATA Step 4: Enable memory writes. 0000 84 7F BSF EECON1, WREN BSF EECON1, WR Step 5: Initiate write. 0000 82 7F Step 6: Poll WR bit, repeat until the bit is clear. 0000 0000 0000 0010 50 7F 6E F5 00 00 <MSB><LSB> MOVF EECON1, W, 0 MOVWF TABLAT NOP Shift out data(1) Step 7: Hold PGC low for time, P10. Step 8: Disable writes. 0000 94 7F BCF EECON1, WREN Repeat steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. DS39947B-page 26 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally even after code protection. Note: The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations. TABLE 3-18: 4-Bit Command Table 3-18 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.2 “Modifying Code Memory”. As with code memory, the ID locations must be erased before being modified. WRITE ID SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 8E 7F 9C 7F BSF BCF EECON1, EEPGD EECON1, CFGS Step 2: Load write buffer with 8 bytes and write. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB><LSB> <MSB><LSB> <MSB><LSB> <MSB><LSB> 00 00 2010 Microchip Technology Inc. MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and post-increment address by 2 bytes and start programming. hold PGC high for time P9 and low for 2. 2. 2. time P10. DS39947B-page 27 PIC18F6XKXX/8XKXX FAMILY 3.5 Boot Block Programming 3.6 The code sequence detailed in Table 3-15 should be used, except that the address used in “Step 2” will be in the range of 000000h to 0007FFh or 000000h to 000FFFh, as defined by the BBSIZ0 bit in the CONFIG4L register (see Table 5-1). Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-19. Note: TABLE 3-19: The address must be explicitly written for each byte programmed. The addresses can not be incremented in this mode. SET ADDRESS POINTER TO CONFIGURATION LOCATION 4-Bit Command Data Payload Core Instruction Step 1: Enable writes and direct access to configuration memory. 0000 0000 8E 7F 8C 7F BSF BSF EECON1, EEPGD EECON1, CFGS Step 2: Set Table Pointer for configuration byte to be written; write even/odd addresses.(1) 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 1111 0000 Note 1: 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 <MSB ignored><LSB> 00 00 0E 01 6E F6 <MSB><LSB ignored> 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9A and low for time P10. Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits. FIGURE 3-9: DS39947B-page 28 CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9A and P10 Time for Write Delay P9A and P10 Time for Write Done Done 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits The 4-bit command is shifted in, LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Code memory is accessed one byte at a time via the 4-bit command, ‘1001’ (table read, post-increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD. TABLE 4-1: This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and Configuration registers. READ CODE MEMORY SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E <Addr[21:16]> F8 <Addr[15:8]> F7 <Addr[7:0]> F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Addr[21:16] TBLPTRU <Addr[15:8]> TBLPTRH <Addr[7:0]> TBLPTRL Step 2: Read memory and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-1: 1 TBLRD *+ TABLE READ, POST-INCREMENT INSTRUCTION TIMING (1001) 2 3 4 1 2 3 4 5 6 7 9 8 1 10 11 12 13 14 15 16 2 3 4 PGC P5 P5A P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input 2010 Microchip Technology Inc. PGD = Output 6 MSb n n n n Fetch Next 4-Bit Command PGD = Input DS39947B-page 29 PIC18F6XKXX/8XKXX FAMILY 4.2 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 4.1 “Read Code Memory, ID Locations and Configuration Bits” for implementation details of reading code memory. FIGURE 4-2: The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the table read 4-bit command may not be used to increment the Table Pointer beyond the code memory space. In a 128-Kbyte device, for example, a post-increment read of address, 1FFFFh, will wrap the Table Pointer back to 000000h, rather than point to unimplemented address, 020000h. VERIFY CODE MEMORY FLOW Start Set TBLPTR = 0 Set TBLPTR = 200000h Read Low Byte with Post-Increment Read Low Byte with Post-Increment Read High Byte with Post-Increment Does Word = Expect data? Yes No All code memory verified? Yes Increment Pointer No Read High Byte with Post-Increment Does Word = Expect data? Failure, Report Error No Failure, Report Error Yes No All ID locations verified? Yes Done DS39947B-page 30 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 4.3 Verify Configuration Bits FIGURE 4-3: READ DATA EEPROM FLOW A configuration address may be read and output on PGD via the 4-bit command, ‘1001’. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer’s memory for verification. Refer to Section 4.1 “Read Code Memory, ID Locations and Configuration Bits” for implementation details of reading configuration data. 4.4 Start Set Address Read Byte Read Data EEPROM Memory Data EEPROM is accessed one byte at a time via an Address Pointer (register pair, EEADRH:EEADR) and a data latch (EEDATA). Data EEPROM is read by loading EEADRH:EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register (Register 3-1). The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command, ‘0010’ (Shift Out Data Holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-4). Move to TABLAT Shift Out Data No Done? Yes Done The command sequence to read a single byte of data is shown in Table 4-2. TABLE 4-2: READ DATA EEPROM MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E 7F 9C 7F BCF BCF EECON1, EEPGD EECON1, CFGS Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E 6E OE 6E <Addr> 62 <AddrH> 63 MOVLW MOVWF MOVLW MOVWF <Addr> EEADR <AddrH> EEADRH BSF EECON1, RD Step 3: Initiate a memory read. 0000 80 7F Step 4: Load data into the Serial Data Holding register. 0000 0000 0000 0010 Note 1: 50 61 6E F5 00 00 <MSB><LSB> MOVF EEDATA, W, 0 MOVWF TABLAT NOP Shift Out Data(1) The <LSB> is undefined; the <MSB> is the data. 2010 Microchip Technology Inc. DS39947B-page 31 PIC18F6XKXX/8XKXX FAMILY FIGURE 4-4: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5A P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 6 MSb 4.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, ‘0000’) and then output on PGD via the 4-bit command, ‘0010’ (TABLAT register). The result may then be immediately compared to the appropriate data in the programmer’s memory for verification. Refer to Section 4.4 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. 4.6 Blank Check The term, “Blank Check”, means to verify that the device has no programmed memory cells. All memories must be verified: code memory, data EEPROM, ID locations and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. PGD = Output FIGURE 4-5: n n n Fetch Next 4-Bit Command Shift Data Out PGD = Input n PGD = Input BLANK CHECK FLOW Start Blank Check Device Is device blank? Yes Continue No Abort A “blank” or “erased” memory cell will read as a ‘1’. So, Blank Checking a device merely means to verify that all bytes read as FFh except the Configuration bits. Unused (reserved) Configuration bits will read ‘0’ (programmed). Refer to Table 5-1 for blank configuration expect data for the various PIC18F6XKXX/8XKXX family devices. Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 “Read Data EEPROM Memory” and Section 4.2 “Verify Code Memory and ID Locations” for implementation details. DS39947B-page 32 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 5.0 CONFIGURATION WORD 5.1 The PIC18F6XKXX/8XKXX family of devices have several Configuration Words. These bits can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting Configuration Words. These bits may be read out normally, even after read or code protection. See Table 5-1 for a list of Configuration bits and device IDs, and Table 5-3 for the Configuration bit descriptions. TABLE 5-1: ID Locations A user may store Identification information (ID) in eight ID locations, mapped in 200000h:200007h. It is recommended that the Most Significant nibble of each ID be Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as a NOP. CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 300000h CONFIG1L — XINST — 300001h CONFIG1H IESO FCMEN — 300002h CONFIG2L — BORPW1 BORPW0 300003h CONFIG2H — WDTPS4 300004h CONFIG3L WAIT(3,4) BW(3,4) 300005h CONFIG3H MCLRE — 300006h CONFIG4L DEBUG 300008h CONFIG5L CP7(1) WDTPS3 Bit 4 Bit 3 SOSCSEL1 SOSCSEL0 PLLCFG FOSC3 Bit 2 Default/ Unprogrammed Value Bit 1 Bit 0 INTOSCSEL — RETEN -1-1 11-1 FOSC2 FOSC1 FOSC0 00-0 1000 -111 1111 BORV1 BORV0 BOREN1 BOREN0 PWRTEN WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111 EASHFT(3,4) — — RTCSOSC 1111 1--1 MSSP7 — ECCPMX(3) CCP2MX 1--- 1-11 ABW1(3,4) ABWO(3,4) — — — — BBSIZ0 — — — STVREN 1--1 ---1 CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 1111 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 1111 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L EBRT7(1) EBRT6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 1111 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx 3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. Unimplemented in PIC18FX5K90/X6K90/X5K22/X6K22 devices. See Register 25-13 in the “PIC18F87K90 Family Data Sheet” for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. Unimplemented in PIC18F6XKXX devices. Unimplemented in PIC18FXXK90 devices. 2010 Microchip Technology Inc. DS39947B-page 33 PIC18F6XKXX/8XKXX FAMILY 5.2 Device ID Word FIGURE 5-1: The Device ID word (DEVID<2:1>) for the PIC18F6XKXX/8XKXX family of devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection. See Table 5-2 for a complete list of Device ID values. READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte with Post-Increment Done TABLE 5-2: DEVICE ID VALUE Device Note: Device ID Value DEVID2 DEVID1 PIC18F65K22 53h 000x xxxx PIC18F65K90 52h 010x xxxx PIC18F66K22 52h 110x xxxx PIC18F66K90 52h 000x xxxx PIC18F67K22 51h 100x xxxx PIC18F67K90 51h 000x xxxx PIC18F85K22 537 011x xxxx PIC18F85K90 52h 101x xxxx PIC18F86K22 53h 001x xxxx PIC18F86K90 52h 011x xxxx PIC18F87K22 51h 110x xxxx PIC18F87K90 51h 010x xxxx The ‘x’s in DEVID1 contain the device revision code. DS39947B-page 34 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-3: Bit Name PIC18F6XKXX/8XKXX FAMILY CONFIGURATION BIT DESCRIPTIONS Configuration Words Description XINST CONFIG1L Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) SOSCSEL<1:0> CONFIG1L SOSC Power Selection and Mode Configuration bits 11 = High-power SOSC circuit selected 10 = Digital (SCLKI) mode 01 = Low-power SOSC circuit selected 00 = Reserved INTOSCSEL CONFIG1L LF-INTOSC Low-Power Enable bit 1 = LF-INTOSC in High-Power mode during Sleep 0 = LF-INTOSC in Low-Power mode during Sleep RETEN CONFIG1L VREG Sleep Enable bit 1 = Regulator power is in Sleep mode, controlled by VREGSLP (WDTCON<7>) 0 = Regulator power is in Sleep mode, controlled by SRETEN (WDTCON<4>). Ultra low-power regulator is enabled. IESO CONFIG1H Internal External Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled PLLCFG CONFIG1H 4 x PLL Enable bit 1 = Oscillator multiplied by 4 0 = Oscillator used directly FOSC<3:0> CONFIG1H Oscillator Selection bits 1101 = EC1, EC oscillator (low power, DC-160 kHz) 1100 = EC1IO, EC oscillator with CLKOUT function on RA6 (low power, DC-160 kHz) 1011 = EC2, EC oscillator (medium power, 160 kHz-4 MHz) 1010 = EC2IO, EC oscillator with CLKOUT function on RA6 (medium power, DC-160 kHz) 1001 = INTIO1, internal RC oscillator with CLKOUT function on RA6 1000 = INTIO2, internal RC oscillator 0111 = RC, external RC oscillator 0110 = RCIO, external RC oscillator with CKLOUT function on RA6 0101 = EC3, EC oscillator (high power, 4 MHz-64 MHz) 0100 = EC3IO, EC oscillator with CLKOUT function on RA6 (high power, 4 MHz-64 MHz) 0011 = HS1, HS oscillator (medium power, 4 MHz-16 MHz) 0010 = HS2, HS oscillator (high power, 16 MHz-25 MHz) 0001 = XT oscillator 0000 = LP oscillator BORPWR<1:0> CONFIG2L BORMV Power Level bits 11 = ZPBORMV instead of BORMV is selected 10 = BORMV is set to high-power level 01 = BORMV is set to medium power level 00 = BORMV is set to low-power level BORV<1:0> CONFIG2L Brown-out Reset Voltage bits 11 = VBOR set to 1.8V 10 = VBOR set to 2.0V 01 = VBOR set to 2.7V 00 = VBOR set to 3.0V Note 1: 2: 3: The BBSIZ0 bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. Available on PIC18F8XKXX devices only. Available on PIC18F8XK22 devices only. 2010 Microchip Technology Inc. DS39947B-page 35 PIC18F6XKXX/8XKXX FAMILY TABLE 5-3: Bit Name PIC18F6XKXX/8XKXX FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description BOREN<1:0> CONFIG2L Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software PWRTEN CONFIG2L Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTPS<4:0> CONFIG2H Watchdog Timer Postscale Select bits 10101-11111: Reserved 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32,768 01110 = 1:16,384 01101 = 1:8,192 01100 = 1:4,096 01011 = 1:2,048 01010 = 1:1,024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 WDTEN<1:0> CONFIG2H Watchdog Timer Enable bits 11 = WDT enabled in hardware; SWDTEN bit disabled 10 = WDT controlled with the SWDTEN bit setting 01 = WDT enabled only while device is active and disabled in Sleep; SWDTEN bit disabled 00 = WDT disabled in hardware; SWDTEN bit disabled WAIT CONFIG3L External Bus Wait Enable bit(3) 1 = Wait states for operations on External Memory Bus disabled 0 = Wait states for operations on External Memory Bus enabled BW CONFIG3L Data Bus Width Select bit(3) 1 = 16-Bit External Bus mode 0 = 8-Bit External Bus mode ABW<1:0> CONFIG3L External Memory Bus Configuration bits(3) 11 = 20-Bit Address mode 10 = 16-Bit Address mode 01 = 12-Bit Address mode 00 = 8-Bit Address mode EASHFT CONFIG3L External Address Shift bit(3) 1 = Address shifting enabled – external address bus is shifted to start at 000000h 0 = Address shifting disabled – external address bus reflects the PC value RTCSOSC CONFIG3L RTCC Reference Clock Select bit 1 = RTCC uses SOSC as the reference clock 0 = RTCC uses LF-INTOSC as the reference clock Note 1: 2: 3: The BBSIZ0 bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. Available on PIC18F8XKXX devices only. Available on PIC18F8XK22 devices only. DS39947B-page 36 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-3: Bit Name PIC18F6XKXX/8XKXX FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description MCLRE CONFIG3H MCLR Pin Enable bit 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled MSSP7 CONFIG3H MSSP V3 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode enable 0 = 5-Bit Address Masking mode enable ECCPMX CONFIG3H ECCP Mux bit(2) 1 = Enhanced CCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3, respectively 0 = Enhanced CCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4, respectively CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode DEBUG CONFIG4L Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug BBSIZ0(1) CONFIG4L Boot Block Size Select bit 1 = 2K word Boot Block size 0 = 1K word Boot Block size STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled CP7 CONFIG5L Code Protection bits (Block 7 code memory area) 1 = Block 7 is not code-protected 0 = Block 7 is code-protected CP6 CONFIG5L Code Protection bits (Block 6 code memory area) 1 = Block 6 is not code-protected 0 = Block 6 is code-protected CP5 CONFIG5L Code Protection bits (Block 5 code memory area) 1 = Block 5 is not code-protected 0 = Block 5 is code-protected CP4 CONFIG5L Code Protection bits (Block 4 code memory area) 1 = Block 4 is not code-protected 0 = Block 4 is code-protected CP3 CONFIG5L Code Protection bits (Block 3 code memory area) 1 = Block 3 is not code-protected 0 = Block 3 is code-protected CP2 CONFIG5L Code Protection bits (Block 2 code memory area) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0 CONFIG5L Code Protection bits (Block 0 code memory area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected CPD CONFIG5H Code Protection bits (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected Note 1: 2: 3: The BBSIZ0 bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. Available on PIC18F8XKXX devices only. Available on PIC18F8XK22 devices only. 2010 Microchip Technology Inc. DS39947B-page 37 PIC18F6XKXX/8XKXX FAMILY TABLE 5-3: Bit Name PIC18F6XKXX/8XKXX FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description CPB CONFIG5H Code Protection bits (Boot Block memory area) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected WRT7 CONFIG6L Write Protection bits (Block 7 code memory area) 1 = Block 7 is not write-protected 0 = Block 7 is write-protected WRT6 CONFIG6L Write Protection bits (Block 6 code memory area) 1 = Block 6 is not write-protected 0 = Block 6 is write-protected WRT5 CONFIG6L Write Protection bits (Block 5 code memory area) 1 = Block 5 is not write-protected 0 = Block 5 is write-protected WRT4 CONFIG6L Write Protection bits (Block 4 code memory area) 1 = Block 4 is not write-protected 0 = Block 4 is write-protected WRT3 CONFIG6L Write Protection bits (Block 3 code memory area) 1 = Block 3 is not write-protected 0 = Block 3 is write-protected WRT2 CONFIG6L Write Protection bits (Block 2 code memory area) 1 = Block 2 is not write-protected 0 = Block 2 is write-protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected WRTD CONFIG6H Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB CONFIG6H Write Protection bit (Boot Block memory area) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected WRTC CONFIG6H Write Protection bit (Configuration registers) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected EBTR7 CONFIG7L Table Read Protection bit (Block 7 code memory area) 1 = Block 7 is not protected from table reads executed in other blocks 0 = Block 7 is protected from table reads executed in other blocks EBTR6 CONFIG7L Table Read Protection bit (Block 6 code memory area) 1 = Block 6 is not protected from table reads executed in other blocks 0 = Block 6 is protected from table reads executed in other blocks EBTR5 CONFIG7L Table Read Protection bit (Block 5 code memory area) 1 = Block 5 is not protected from table reads executed in other blocks 0 = Block 5 is protected from table reads executed in other blocks EBTR4 CONFIG7L Table Read Protection bit (Block 4 code memory area) 1 = Block 4 is not protected from table reads executed in other blocks 0 = Block 4 is protected from table reads executed in other blocks EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area) 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks Note 1: 2: 3: The BBSIZ0 bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. Available on PIC18F8XKXX devices only. Available on PIC18F8XK22 devices only. DS39947B-page 38 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-3: Bit Name PIC18F6XKXX/8XKXX FAMILY CONFIGURATION BIT DESCRIPTIONS (CONTINUED) Configuration Words Description EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area) 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (Boot Block memory area) 1 = Boot Block is not protected from table reads executed in other blocks 0 = Boot Block is protected from table reads executed in other blocks DEV<10:3> DEVID2 Device ID bits These bits are used with the DEV<2:0> bits in the DEVID1 register to identify part number. DEV<2:0> DEVID1 Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. REV<4:0> DEVID1 Revision ID bits These bits are used to indicate the revision of the device. Note 1: 2: 3: The BBSIZ0 bit cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. Available on PIC18F8XKXX devices only. Available on PIC18F8XK22 devices only. 2010 Microchip Technology Inc. DS39947B-page 39 PIC18F6XKXX/8XKXX FAMILY 5.3 Embedding Configuration Word Information in the HEX File To allow portability of code, a PIC18F6XKXX/8XKXX device programmer is required to read the Configuration Word locations from the hex file. If Configuration Word information is not present in the hex file, then a simple warning message should be issued. Similarly, while saving a hex file, all Configuration Word information must be included. An option to not include the Configuration Word information may be provided. When embedding Configuration Word information in the hex file, it should start at address, 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.4 Embedding Data EEPROM Information in the HEX File To allow portability of code, a PIC18F6XKXX/8XKXX device programmer is required to read the data EEPROM information from the hex file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a hex file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. 5.5 Checksum Computation The checksum is calculated by summing the following: • The contents of all code memory locations • The Configuration Word, appropriately masked • ID locations The Least Significant 16 bits of this sum are the checksum. Table 5-4 (pages 41 through 46) describes how to calculate the checksum for each device. Note: The checksum calculation differs depending on the code-protect setting. Since the code memory locations read out differently depending on the code-protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The Configuration Word and ID locations can always be read. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. DS39947B-page 40 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: CHECKSUM COMPUTATION Blank Value 0xAA at 0 and Max Address 0xA40B 0xA361 Boot Block SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0xAC43 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xABEE CodeProtect Device None PIC18F65K90 Boot/ Panel0/ Panel1 Checksum SUM(0000:0FFF) + SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0xD440 (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xD3EB (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0434 0x0434 0xA40B SUM(0000:0FFF) + SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xA361 0xAC43 Boot Block SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F65K22 Boot/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0xD440 Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xABEE 0x0434 0x0434 All None All Legend: Item CFGW SUM[a:b] SUM_ID + & (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) = = = = = 0xD3EB Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. DS39947B-page 41 PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED) Blank Value 0xAA at 0 and Max Address SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x040B 0x0361 Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0C43 0x0BEE CodeProtect Device None PIC18F66K90 Checksum Boot/ Panel0/ Panel1 SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x8440 0x83EB All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0434 0x0434 None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x040B 0x0361 0x0C43 Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F66K22 Boot/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0x8440 Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0BEE All Legend: Item CFGW SUM[a:b] SUM_ID + & DS39947B-page 42 (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) = = = = = 0x0434 0x83EB 0x0434 Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: CHECKSUM COMPUTATION (CONTINUED) Blank Value 0xAA at 0 and Max Address SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x06DB 0x0631 Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 2K words SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + PIC18F67K90 (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0F13 0x0EBE Device CodeProtect None Checksum Boot/ Panel0/ Panel1 SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x8710 0x86BB All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0614 0x0614 SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x06DB SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0631 None Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 2K words SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + PIC18F67K22 (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) Legend: 0x0F13 0x0EBE Boot/ Panel0/ Panel1 SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x8710 0x86BB All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 89) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0614 0x0614 Item CFGW SUM[a:b] SUM_ID + & = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. DS39947B-page 43 PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: Device CHECKSUM COMPUTATION (CONTINUED) CodeProtect Blank Value Checksum 0xAA at 0 and Max Address 0xA40D SUM(0000:0FFF) + SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x8363 Boot Block SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 0xAC45 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F85K90 Boot/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0xD442 Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xABF0 None 0xD3ED All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0436 0x0436 None SUM(0000:0FFF) + SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0xA505 0xA45B 0xAD3D 0xACE8 Boot Block SUM(1000:17FF) + SUM(1800:3FFF) + SUM(4000:5FFF) + SUM(6000:7FFF) + 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F85K22 Boot/ SUM(4000:5FFF) + SUM(6000:7FFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0xD53A 0xD4E5 Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) All Legend: Item CFGW SUM[a:b] SUM_ID + & DS39947B-page 44 (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + 0x052E (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) = = = = = 0x052E Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: Device CHECKSUM COMPUTATION (CONTINUED) CodeProtect None Checksum Blank Value 0xAA at 0 and Max Address SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + 0x040D SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0363 Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x0C45 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F86K90 Boot/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0x8442 Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0BF0 0x83ED All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0436 0x0436 None SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0505 0x045B Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x0D3D 2K words (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) PIC18F86K22 Boot/ SUM(8000:BFFF) + SUM(C000:FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + 0x853A Panel0/ (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + Panel1 (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x0CE8 (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + 0x052E (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & 0F) + (CONFIG5H & C0) + (CONFIG6L & 0F) + (CONFIG6H & E0) + (CONFIG7L & 0F) + (CONFIG7H & 40) + SUM(IDs) 0x052E All Legend: Item CFGW SUM[a:b] SUM_ID + & = = = = = 0x84E5 Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. DS39947B-page 45 PIC18F6XKXX/8XKXX FAMILY TABLE 5-4: Device CHECKSUM COMPUTATION (CONTINUED) CodeProtect None Blank Value Checksum 0xAA at 0 and Max Address 0x06DD SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0633 0x0F15 0x0EC0 Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 2K words SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + PIC18F87K90 (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) Boot/ Panel0/ Panel1 SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x8712 0x86BD All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & 01) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0616 0x0616 0x07D5 SUM(0000:0FFF) + SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x072B Boot Block SUM(1000:3FFF) + SUM(4000:7FFF) + SUM(8000:BFFF) + SUM(C000:FFFF) + 0x100D 2K words SUM(10000:13FFF) + SUM(14000:17FFF) + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + PIC18F87K22 (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x0FB8 None Legend: Boot/ Panel0/ Panel1 SUM(8000:BFFF) + SUM(C000:FFFF) + SUM(10000:13FFF) + SUM(14000:17FFF) 0x880A + SUM(18000:1BFFF) + SUM(1C000:1FFFF) + (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x87B5 All (CONFIG1L & 5D) + (CONFIG1H & DF) + (CONFIG2L & 7F) + (CONFIG2H & 7F) + 0x070E (CONFIG3L & F9) + (CONFIG3H & 8B) + (CONFIG4L & 91) + (CONFIG4H & 00) + (CONFIG5L & FF) + (CONFIG5H & C0) + (CONFIG6L & FF) + (CONFIG6H & E0) + (CONFIG7L & FF) + (CONFIG7H & 40) + SUM(IDs) 0x070E Item CFGW SUM[a:b] SUM_ID + & DS39947B-page 46 = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all customer ID locations Addition Bit-wise AND 2010 Microchip Technology Inc. PIC18F6XKXX/8XKXX FAMILY 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym Characteristic D110 VIHH High-Voltage Programming Voltage on MCLR/VPP/RG5 D111 VDD Supply Voltage during Programming Min Max Units Conditions VDD + 1.5 10 V 2.1 5.50 V Row Erase/Write 2.7 5.50 V Block Erase operations D112 IPP Programming Current on MCLR/VPP/RG5 — 600 A D113 IDDP Supply Current during Programming — 3.0 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage — 0.6 V IOL = 8.5 mA @ 4.5V D090 VOH Output High Voltage VDD – 0.7 — V IOH = -3.0 mA @ 4.5V D012 CIO Capacitive Loading on I/O pin (PGD) — 50 pF To meet AC specifications P1 TR MCLR/VPP/RG5 Rise Time to Enter Program/Verify mode — 1.0 s (Note 1) P2 TPGC Serial Clock (PGC) Period 100 — ns VDD = 5.0V 1 — s VDD = 2.0V P2A TPGCL Serial Clock (PGC) Low Time 40 — ns VDD = 5.0V 400 — ns VDD = 2.0V 40 — ns VDD = 5.0V VDD = 2.0V P2B TPGCH Serial Clock (PGC) High Time 400 — ns P3 TSET1 Input Data Setup Time to Serial Clock 15 — ns P4 THLD1 Input Data Hold Time from PGC 15 — ns P5 TDLY1 Delay between 4-Bit Command and Command Operand 40 — ns P5A TDLY1A Delay between 4-Bit Command Operand and Next 4-bit Command 40 — ns P6 TDLY2 Delay between Last PGC of Command Byte to First PGC of Read of Data Word 20 — ns P9 TDLY5 PGC High Time (minimum programming time) 1 — ms Externally timed P9A TDLY5A PGC High Time 5 — ms Configuration Word programming time P10 TDLY6 PGC Low Time after Programming (high-voltage discharge time) 100 — s P11 TDLY7 Delay to allow Self-Timed Data Write or Block Erase to Occur 5 — ms P11A TDRWT Data Write Polling Time 4 — ms Note 1: Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2010 Microchip Technology Inc. DS39947B-page 47 PIC18F6XKXX/8XKXX FAMILY 6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED) Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym Characteristic Min Max Units P12 THLD2 Input Data Hold Time from MCLR/VPP/RG5 250 — s P13 TSET2 VDD Setup Time to MCLR/VPP/RG5 100 — ns P14 TVALID Data Out Valid from PGC 10 — ns P15 TDLY8 Delay between Last PGC and MCLR/VPP/RG5 0 — s P16 THLD3 MCLR/VPP/RG5 to VDD — 100 ns P17 THLD3 MCLR/VPP/RE3 to VDD — 100 ns Note 1: Conditions Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions to occur. The maximum transition time is: 1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. DS39947B-page 48 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-376-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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