CXB1456R VGA/SVGA/XGA 24-bit Receiver Description CXB1456R is the 1 chip deserializer for VGA/SVGA/ XGA 24-bit color digital RGB, and meet to the Gigabit Video Interface specification. 64 pin LQFP (Plastic) Features • 1 chip receiver for serial transmission of 24-bit color VGA/SVGA/XGA picture • On chip PLL circuit for data and clock recovery • On chip panel mode automatically selectable circuit • TTL compatible I/O • Support 1 pixel/shiftclock mode with 1 chip and 2 pixel/shiftclock mode with 2 chip • +3.3V single power supply • Low power consumption • 64pin plastic LQFP package with body size 10mm × 10mm Absolute Maximum Ratings • Supply voltage Vcc • Storage temperature Tstg • Allowable power dissipation PD 4.2 –65 to +150 650 Recommended Operating Condition • Supply voltage 3.3 ± 0.3 • Operating temperature Topr 0 to +80 Application Gigabit video interface V °C mW V °C REXT PANEL0 PANEL1 LOS TESTDT CE REFRQP SDATAP SDATAN REFRQN TESTEXN VCCA VEES VEEA LPFA Block Digagram & Pin out LPFB Structure Bi-CMOS IC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CNTL 49 32 CLKPOL DE 50 31 R0 30 R1 29 GND VDD 53 28 VDD VEE 54 27 VEE VCC 55 26 VCC HSYNC 56 25 R2 24 R3 23 R4 B6 59 22 R5 GND 60 21 GND VDD 61 20 VDD B5 62 19 R6 B4 63 18 R7 VDD 64 17 GND SFTCLK 51 CDR PLL GND 52 Serial to Parallel Converter VSYNC 57 B7 58 VDD G0 G1 G2 9 10 11 12 13 14 15 16 G3 8 G4 B1 7 G5 B2 6 GND B3 5 VDD 4 G6 3 B0 2 G7 1 GND Decoder Fig. 1. Block Diagram & Pin out Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98Y04C9X-PS CXB1456R Pin List Table 1. Power/Ground Pin number Pin name Descriptions VDD 8, 16, 20, 28, 53, 61, 64 MOS power supply, should be connected to 3.3V ± 0.3V GND 1, 9, 17, 21, 29, 52, 60 MOS ground, connected to 0V VCC 26, 55 ECL power supply, connected to 3.3V ± 0.3V VEE 27, 54 ECL ground, connected to 0V VCCA 44 Analog power supply, connected to 3.3V ± 0.3V VEEA 45 Analog ground, connected to 0V VEES 46 Substrate GND, connected to 0V Table 2. Digital Signals Pin name Pin number Type Descriptions TTL out Shift clock, for the data fetch at falling or rising edge SFTCLK 51 RED (7 to 0) 18, 19, 22, 23, 24, 25, 30, 31 6, 7, 10, TTL out 11, 12, 13, 14, 15 58, 59, 62, 63, 2, 3, 4, 5 Pixel data HSYNC 56 TTL out Hsync data VSYNC 57 TTL out Vsync data CNTL 49 TTL out Control data DE 50 TTL out Display enable data LOS 36 TTL out Los of signal PANEL (1, 0) 35, 34 TTL in Panel mode select switch CLKPOL TTL in Trigger edge select switch GRN (7 to 0) BLU (7 to 0) 32 Equivalent circuit VDD TTL-OUT GND VCCA VDD TTL-IN CE 38 TTL in Chip enable TESTEXN TESTDT 43, 37 TTL in Reversed for TEST under fabrication –2– VEES GND CXB1456R Table 2. Digital Signals (Cont.) Pin name Pin number Type Descriptions Equivalent circuit VCCA SDATAP/N 40, 41 Rx Serial input SDATAP/N REFRQP/N VDD REFRQP/N 39, 42 Rx Refclk request VEEA GND Table 3. Special Pin name Pin number Descriptions Equivalent circuit VCC REXT 33 REXT External Register VDD VEE GND VCCA LPFA LPFB LPFA/B 47, 48 External loop filter VDD VEEA GND –3– CXB1456R Electrical characteristics Table 4. Absolute Maximum Rating Description Symbol Min. Typ. Max. Unit Power supply voltage VCC –0.3 4.2 V TTL DC input voltage VI_T –0.5 4.6 V TTL output current (High) IOH_T –10 0 TTL output current (Low) IOL_T 0 10 mA ' mA Serial input pin voltage Vsdin –0.5 VCC + 0.5 V REFREQ output pin voltage VRQout 0.5 VCC + 0.5 V Storage temperature Tstg –65 150 °C Comments Table 5. Recommended Operating Conditions Description Symbol Min. Typ. Max. Unit 3.3 3.6 V 80 °C Power supply voltage VCC 3.0 Ambient temperature Ta 0 Comments Table 6. DC Characteristics (Under the recommended conditons. See Tab. 5) Description Symbol Min. Typ. Max. Unit Conditions Input HIGH voltage (TTL) VIH_T 2 VCC V Input LOW voltage (TTL) VIL_T 0 0.8 V Input HIGH current (TTL) IIH_T 10 µA VIN = VCC Input LOW current (TTL) IIL_T –10 µA VIN = 0 Output HIGH voltage (TTL) VOH_T 2.4 V IOH = –3mA Output LOW voltage (TTL) VOL_T 0.4 V IOL = 3mA +0.1 mA 0 Output HIGH current (REFREQ) IOH_RQ –0.1 Output LOW current (REFREQ) IOL_RQ 7.8 11 mA Input dynamic range (SDATA) VIM_SD VCC – 0.4 VCC + 0.2 V Common mode voltage Input dynamic range (SDATA) VID_SD –0.5 +0.5 V Differential voltage 138 173 mA 77 104 mA Worst Case Supply current 16 Grayscale ICC –4– See Fig. 3, 4 REXT = 5.6kΩ CL = 8pF, f = 65MHz See Fig. 9, 10 CXB1456R VDD/VCC/VCCA CXB1456R VCC 37 TESTDT 50Ω 50Ω A A REFRQP 39 150Ω 38 CE 43 TESTEXN REFRQN 42 150Ω GND/VEE/VEEA Fig. 3. IOH_RQ and IOL_RQ DC measurement TESTDT CE TESTEXN Fig. 4. IOH_RQ and IOL_RQ DC measurement setting –5– CXB1456R Table 7. AC Characteristics (Under the recommended conditons. See Tab. 5) Description Symbol Minimum SFTCLK frequency Maximum SFTCLK frequency Fsftclk SFTCLK duty factor Dsftclk Pixel/Sync/Cntl/DE setup to SFTCLK Tsetup Min. Typ. Max. Unit 25.0 MHz MHz 65 % Vth = 1.4V, CL = 8pF 17 9 4.5 ns ns ns Vth = 1.4V, CL = 8pF 25MHz 40MHz 65MHz 16 9 4.5 ns ns ns Vth = 1.4V, CL = 8pF 25MHz 40MHz 65MHz 65.0 35 Conditions Pixel/Sync/Cntl/DE hold to SFTCLK Thold SFTCLK rise time Torc 5 ns 0.8V to 2.0V, CL = 8pF SFTCLK fall time Tofc 3 ns 2.0V to 0.8V, CL = 8pF Pixel/Sync/Cntl/DE rise time Tord 5 ns 0.8V to 2.0V, CL = 8pF Pixel/Sync/Cntl/DE fall time Tord 3 ns 2.0V to 0.8V, CL = 8pF CLOCK mode assert time TAclk 0.5 µs CLOCK mode deassert time TDclk 20 µs LOS signal assert time TAlos 0.5 µs LOS signal deassert time TDlos 0.15 µs VDD/VCC/VCCA VCC TTLout Cprobe CXB1456R CL' oscilloscope GND/VEE/VEEA CL' + Cprobe = 8pF Fig. 5. Pixel/Sync/Cntl/DE waveform measurement –6– CXB1456R Timing Chart 1/Fsftclk 2.0V SFTCLK Vth 0.8V Torc Setup/hold time is referred from rising edge in CLKPOL = GND falling edge in CLKPOL = VDD Dsftclk/Fsftclk Tofc Tsetup Thold Tord REDxx GRNxx BLUxx H/Vsync CNTL DE 2.0V 0.8V Tofd Fig. 6. TTL output timing Pixel Sync/Cntl/DE error Indefinite SftClk TAclk REFRQP REFRQN Indefinite TDclk SDATAP SDATAN Fig. 7. Refclk request timing SDATAP SDATAN NRZ data TAlos TDlos LOS Fig. 8. Idle mode timing –7– CXB1456R SFTCLK f RGB <7, 5, 3, 1> f/2 RGB <6, 4, 2, 0> f/2 Fig. 9. Worst case test pattern f SFTCLK RGB <7> f/16 RGB <6> f/8 RGB <5> f/4 RGB <4> f/2 RGB <3> Fix Low RGB <2> Fix Low RGB <1> Fix Low RGB <0> Fix Low Fig. 10. 16 Grayscale test pattern –8– CXB1456R CLKPOL Pin Control The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.) The CLKPOL pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 8. SFTCLK Polarity CLKPOL Receiver operation trigger L Rising edge H Falling edge PANEL1 and 0 Pin Control The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.) For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1 and 0 to High. The PANEL1 and 0 pins are open High-impedance TTL inputs, and they should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 9. Panel Mode PANEL1 PANEL0 L L L Supporting panel size Shift Clock Serial rate VGA (640 × 480) 25MHz 750Mbps H SVGA (800 × 600) 40MHz 1200Mbps H L XGA (1024 × 768) 65MHz 1950Mbps H H VGA to XGA 25MHz to 65MHz 750Mbps to 1950Mbps CE Pin Control The CE pin is used to select the standby mode. (See Table 10.) The CE pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12. Recommended application circuit.) Table 10 CE Operation mode L Standby mode, all TTL outputs fixed to Low (excluding LOS) H Normal mode Test Pin Control The TESTEXN and TESTDT pins are for test only. Select normal mode. (See Table 11.) The TESTEXN and TESTDT pins are open High-impedance TTL inputs, and they should not be left open for use. Table 11. Test mode TESTEXN TESTDT Operation mode L X Test mode H X Normal mode LOS Pin Output The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is disconnected or the transmitter is idle. The LOS pin is TTL output. –9– CXB1456R Applications CXB1456R GVIF receiver is applied to the digital RGB signal transmission for P/C with LCD monitor Video on demand system Monitoring system Graphical controller Projector Digital TV monitor Car navigation system with GVIF transmitter, CXB1455R. 8 8 8 4 Parallel to Serial Converter SHIFTCLOCK Cable Driver PLL STP or Twin axial Serial to Parallel Converter PLL Decoder RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/ DE/CNTL Encoder CXB1455R GVIF Transmitter 8 8 8 RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/ DE/CNTL SHIFTCLOCK CXB1456R GVIF Receiver Fig. 11. Block Diagram of GVIF transceiver chip set – 10 – CXB1456R Application Cicuit Differential cable (1) CHIP RESISTOR (1%) (2) CHIP CAPACITOR (3) FORMED BY THE PRINTED CIRCUIT PATTERN (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm) VCC 0.1 to 0.4n (3) Connector E 0.1 to 0.4n (3) 0.1 to 0.4n (3) 36 35 34 33 PANEL0 REXT 37 LOS REFRQN VEES 50 DE 38 PANEL1 VCCA 45 5.6k (1) CE 43 TESTEXN 46 VEEA 49 CNTL 47 LPFA LPFB 48 47p (2) 40 39 TESTDT 44 47p (2) 42 41 47 (1) 150 (1) 100 (1) SDATAP 330 47 (1) 470p (2) 150 (1) REFRQP 0.1µ (2) SDATAN 33µ 16V 330 VCC 330 32 CLKPOL R0 31 51 SFTCLK 0.1µ (2) VCC 0.1µ (2) E SW1 H: FALLING EDGE TRIGGER L: RISING EDGE TRIGGER R1 30 52 GND GND 29 53 VDD VDD 28 54 VEE VEE 27 55 VCC VCC 26 56 HSYNC VCC E 0.1µ (2) 0.1µ (2) R2 25 CXB1456R 57 VSYNC R3 24 58 B7 R4 23 59 B6 0.1µ (2) R5 22 60 GND GND 21 61 VDD VDD 20 62 B5 R6 19 VCC VCC 63 B4 0.1µ (2) R7 18 B2 B1 B0 G7 G6 VDD GND G5 G4 G3 G2 G1 G0 VDD GND 17 B3 64 VDD GND VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC 0.1µ (2) VCC CNTL SFTCLK HSYNC VSYNC DE 0.1µ (2) 7 6 5 4 3 2 1 0 MSB LSB BLUE DATA 0.1µ (2) 7 6 5 4 3 2 1 0 MSB LSB GREEN DATA 7 6 5 4 3 2 1 0 MSB LSB RED DATA Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Fig. 12. Recommended application circuit – 11 – CXB1456R , ,, , Recommended Printed Circuit Board Structure L1 : Cu plate (18µm) + solder coat l1 : Fiber-glass epoxy core (0.3mm) L2 : Cu plate (36µm) l2 : Fiber-glass epoxy core (0.8mm) L3 : Cu plate (36µm) l3 : Fiber-glass epoxy core (0.3mm) L4 : Cu plate (18µm) + solder coat Fig. 13. Recommended Printed Circuit Board Structure Recommended Printed Circuit Board Pattern POWER and special signal routing example 0.5mm G Through hole to the GND plane (L2) E Through hole to the VCC plane (L3) D Through hole to the VDD plane (L3) Chip capacitor Chip resistor 49 G G REXT 33 PANEL0 PANEL1 LOS TESTDT CE REFRQP SDATAP SDATAN REFRQN VCCA TESTEXN VEEA VEES LPFB 48 LPFA L2 doesn't have plane in this area CNTL CLKPOL DE R0 SFTCLK R1 GND GND VDD VDD VEE VEE VCC VCC 32 G G G E HSYNC R2 VSYNC R3 B7 R4 B6 R5 GND D D D E GND D VDD G VDD G D B5 D D D R6 B4 R7 VDD VDD G0 G1 G2 G3 G4 G5 GND G6 VDD G7 B0 B1 B2 B3 GND GND 64 17 G G 1 16 G Fig. 14. Recommended Printed Circuit Board Pattern – 12 – CXB1456R Micro Strip Line For maximum performance, the impedance between the pins SDDATAP/N of the LSI and the footprint of the connector should be 50Ω using a micro strip line. 50Ω impedance can be reached when using 0.5mm width pattern lines on L1 using this circuit board structure. The length of the lines should be identical and throughhole should not be used. L2 is recommended as the large ground plane. Terminators Terminators (100Ω resistor) should be located as close to the LSI as possible. Filter Devices and Reference Registors Capacitors and resistors which are connected to LPFA/B and REXT are filters and reference resistors. The region of Layer 2 (L2) is under the device and conductive patterns. The ground plane should be taken off in order to reduce parasitic capacitors. Bypass Capacitors Bypass capacitors (0.1µF SMD type) should be located as close to the pins as possible. Refer to the recommendation. – 13 – CXB1456R Recommendation for Cable and Connector Characteristics The GVIF system uses terminators at both ends (transmitter and receiver), a cable equalizer and a small amplitude differential signal. In order to solve the problems of high speed data transmission such as signal reflection, reduce the signal level and EMI. In order to achieve the best solution, note the following: Tx termination 50Ω Tx termination 100Ω Tx LSI Rx LSI Microstrip line (50Ω) Foot print Connector Cable (diff. 100Ω) Connector Foot print Microstrip line (50Ω) It is important to note the following issues for a good data transmission system: • Good impedance matching Differential impedance should be fit to the recommended template on the next page. • Cable loss should be small and the loss curve should be smooth. Maximum loss should be less than 6dB at 1GHz. See the next page. • Skew of POS/NEG (differential signal) should be small Less than 12% of 1-bit time or 160ps@VGA, 100ps@SVGA, 60ps@XGA. • Good EMI performance cable and connectors. In order to satisfy these issues, the recommendations are as follows: • Use the differential cable which provides good controlled impedance, low loss and good skew matching. A shielded twisted pair (STP) cable is recommended. • Use a low reflectance connector. • To minimize interference from other signals, high speed signal lengths should be identical. • Use double shielded cable. – 14 – CXB1456R Recommended Transmission Path : Differential impedance template Zo (Ω) 150 110 106 94 90 75 < 500ps Microstrip line Foot print < 500ps Connector Connector Foot print Microstrip line Recommended Transmission Path : Attennation Characteristics Loss < 6dB 2dB Measured curve Fitting curve Frequency 1GHz – 15 – CXB1456R TTL output waveform with CL = 8pF SFTCLK 65MHz TTL output B0 T 65Mbps TTL output 1.00V/div 1.00V/div 5ns/div SFTCLK Power spectrum ATTEN 10dB RL 0dBm 10dB/ CENTER 65.00MHz D CENTER 65.00MHz RBW 100kHz VBW 100kHz – 16 – SPAN 10.00MHz SWP 50.0ms CXB1456R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 + 0.08 0.18 – 0.03 16 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 17 –