TC1321 10-Bit Digital-to-Analog Converter with Two-Wire Interface Features General Description • • • • The TC1321 is a serially accessible, 10-bit voltage output, digital-to-analog converter (DAC). The DAC produces an output voltage that ranges from ground to an externally supplied reference voltage. It operates from a single power supply that can range from 2.7V to 5.5V, making it ideal for a wide range of applications. Built into the part is a Power-on Reset (POR) function that ensures that the device starts at a known condition. 10-Bit Digital-to-Analog Converter 2.7-5.5V Single Supply Operation Simple SMBus/I2CTM Serial Interface Low Power Operation - Normal Mode: 350 µA - Shutdown Mode: 0.5 µA • Temperature Range: 40°C to +85°C • 8-Pin SOIC and 8-Pin MSOP Packages Communication with the TC1321 is accomplished via a simple 2-wire SMBus/I2C compatible serial port, with the TC1321 acting as a slave only device. The host can enable the SHDN bit in the CONFIG register to activate the Low Power Standby mode. Applications • Programmable Voltage Sources • Digital Controlled Amplifiers/Attenuators • Process Monitoring and Control Package Type 8-Pin MSOP and 8-Pin SOIC (Narrow) V REF 1 8 V SDA 2 7 DAC-OUT 6 NC 5 V SCL 3 VSS TC1321 4 DD OUT Typical Application VIN 8 VDD TC1321 VREF 1 VREF DAC 5 VOUT – + VADJUST Serial Port 3 SCL 2 SDA Microcontroller 2010 Microchip Technology Inc. DS21387C-page 1 TC1321 Functional Block Diagram VDD SDA SCL TC1321 Configuration Register Serial Port Interface Data Register Control Circuit DAC-OUT VREF DS21387C-page 2 V DAC OUT VSS 2010 Microchip Technology Inc. TC1321 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings* Supply Voltage (VDD) ........................................................+6V Voltage on any Pin ....................(VSS – 0.3V) to (VDD + 0.3V) Current on any Pin ......................................................±50 mA Package Thermal Resistance (JA)....................... 330°C C/W Operating Temperature (TA)................................... See Below Storage Temperature (TSTG) .........................-65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C TA +85°C, VREF = 1.2 V unless otherwise noted. Symbol Parameter Min Typ Max Unit Test Conditions Power Supply VDD Supply Voltage 2.7 — 5.5 V IDD Operating Current — 350 500 µA VDD = 5.5V, VREF = 1.2V Serial Port Inactive (Note 1) IDD- Standby Supply Current — 0.1 1 µA VDD = 3.3V Serial Port Inactive (Note 1) Resolution — — 10 Bits Integral Non-Linearity at FS, TA = +25°C — — ±4.0 LSB FSE Full Scale Error — — ±3 %FS DNL Differential Non-Linearity, TA = +25°C -1 — +2 LSB All Codes (Note 2) VOS Offset Error at VOUT — ±0.3 ±8 mV (Note 2) TCVOS Offset Error Tempco at VOUT — 10 — µv/°C PSRR Power Supply Rejection Ratio — 80 — dB VREF Voltage Reference Range 0 — VDD – 1.2 V IREF Reference Input Leakage Current — — ±1.0 µA VSW Voltage Swing 0 — VREF V VREF (VDD – 1.2V) ROUT () STANDBY Static Performance - Analog Section INL ROUT Output Resistance @ VOUT — 5.0 — IOUT Output Current (Source or Sink) — 2 — mA ISC Output Short-Circuit Current VDD = 5.5V — — 30 20 50 50 mA mA (Note 2) VDD at DC Source Sink Dynamic Performance SR Voltage Output Slew Rate — 0.8 — V/µs tSETTLE Output Voltage Full Scale Settling Time — 10 — µs tWU Wake-up Time — 20 — µs Digital Feed Through and Crosstalk — 5 — nV-s SDA = VDD, SCL = 100 kHz Serial Port Interface VIH Logic Input High 2.4 — VDD V VIL Logic Input Low — — 0.6 — VOL SDA Output Low — — — — 0.4 0.6 V V IOL = 3 mA (Sinking Current) IOL = 6 mA Note 1: SDA and SCL must be connected to VDD or VSS. 2: Measured at VOUT 50 mV referred to VSS to avoid output buffer clipping. 2010 Microchip Technology Inc. DS21387C-page 3 TC1321 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VDD = 2.7V to 5.5V, -40°C TA +85°C, VREF = 1.2 V unless otherwise noted. Parameter Min Typ Max Unit CIN Symbol Input Capacitance (SDA and SCL pins) — 5 0.4 pF ILEAK I/O Leakage — — ±1.0 µA Test Conditions Serial Port AC Timing fSMB SMBus Clock Frequency 10 — 100 kHz tIDLE Bus Free Time Prior to New Transition 4.7 — — µs tH(START) START Condition Hold Time 4.0 — — µs tSU(START) START Condition Setup Time 4.7 — — µs tSU(STOP) STOP Condition Setup Time 4.0 — — µs tH-DATA Data In Hold Time 100 — — ns tSU-DATA Data In Setup Time 100 — — ns tLOW Low Clock Period 4.7 — — µs 10% to 10% tHIGH High Clock Period 4 — — µs 90% to 90% tF SMBus Fall Time — — 300 ns 90% to 10% tR SMBus Rise Time — — 1000 ns 10% to 90% tPOR Power-on Reset Delay — 500 — µs VDD VPOR (Rising Edge) 90% SCL to 10% SDA (for Repeated START Condition) Note 1: SDA and SCL must be connected to VDD or VSS. 2: Measured at VOUT 50 mV referred to VSS to avoid output buffer clipping. TEMPERATURE CHARACTERISTICS Electrical Specifications: VDD = 2.7V to 5.5V, -40°C TA +85°C, VREF = 1.2V unless otherwise noted. Parameters Symbol Min Typ Max Units Operating Temperature Range TA -40 — +85 °C Storage Temperature Range TA -65 — 150 °C Thermal Resistance, 8L SOIC JA — 149.5 — °C/W Thermal Resistance, 8L MSOP JA — 211 — °C/W Conditions Temperature Ranges Thermal Package Resistances DS21387C-page 4 2010 Microchip Technology Inc. TC1321 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Pin Number 2.1 PIN FUNCTION TABLE Pin Name Type Description 1 VREF Input Voltage Reference Input Pin 2 SDA Bi-Directional Serial Data Input/Output Pin 3 SCL Input Serial Clock Input Pin 4 VSS Power Ground Reference Pin 5 VOUT Output Buffered Analog Voltage Output Pin 6 NC None No connection 7 DAC-OUT Output Unbuffered Analog Voltage Output Pin 8 VDD Power Positive Power Supply Input Pin External Voltage Reference Input (VREF) Voltage Reference Input can range from 0V to 1.2V below VDD. 2.6 No Connection (NC) There is not a connection at this pin. 2.7 Output (DAC-OUT) Serial data is transferred on the SMBus in both directions using this pin. Unbuffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. This output is unbuffered and care must be taken that the pin is connected only to a high-impedance node. 2.3 2.8 2.2 Bi-Directional Serial Data Input and Output (SDA) Serial Clock Input (SCL) SMBus/I2C serial clock. Clocks data into and out of the TC1321. 2.4 Positive Power Supply Input (VDD) See the Electrical Specifications table. Supply Power Ground (VSS) The ground reference pin. 2.5 Output (VOUT) Buffered DAC output voltage. This voltage is a function of the reference voltage and the contents of the DATA register. 2010 Microchip Technology Inc. DS21387C-page 5 TC1321 NOTES: DS21387C-page 6 2010 Microchip Technology Inc. TC1321 3.0 DETAILED DESCRIPTION 3.2 Output Amplifier The TC1321 is a monolithic 10-bit digital-to-analog converter that is designed to operate from a single supply that can range from 2.7V to 5.5V. The DAC consists of a data register (DATA), a configuration register (CONF), and a current output amplifier. The TC1321 uses an external reference which also determines the maximum output voltage. The TC1321 DAC output is buffered with an internal unity gain rail-to-rail input/output amplifier with a typical slew rate of 0.8V/µs. Maximum full scale transition settling time is 10 µsec to within ±1/2LSB when loaded with 1 k in parallel with 100 pF. The TC1321 uses a current steering DAC based on an array of matched current sources. This current, along with a precision resistor, converts the contents of the DATA Register and VREF into an output voltage, VOUT, that is given by: The TC1321 allows the host to put it into a Low Power (IDD = 0.5 µA, typically) Standby mode. DATA V OUT = VREF ---------------1024 3.1 3.3 In this mode, the D/A conversion is halted. The SMBus port operates normally. Standby mode is enabled by setting the SHDN bit in the CONFIG register. Table 3-1 summarizes this operation. TABLE 3-1: Reference Input The reference pin, VREF, is a buffered high-impedance input. Because of this, the load regulation of the reference source needs only to be able to tolerate leakage levels of current (less than 1 µA). VREF accepts a voltage range from 0 to (VDD – 1.2V). Input capacitance is typically 10 pF. 2010 Microchip Technology Inc. Standby Mode 3.4 STANDBY MODE OPERATION SHDN Bit Operating Mode 0 Normal 1 Standby SMBus Slave Address The TC1321 is internally programmed to have a default SMBus address value of 1001 000b. Seven other addresses are available by custom order (contact Microchip Worldwide Sales and Service). See Figure 3-1 for the location of address bits in SMBus protocol. DS21387C-page 7 TC1321 Write 1-Byte Format S Address R/W 7-Bits 0 Command ACK ACK 8-Bits Slave Address Data ACK P 8-Bits Command Byte: selects which register you are writing to. Data Byte: data goes into the register set by the command byte. Write 2-Byte Format S Address R/W 7-Bits 0 Command ACK ACK 8-Bits Slave Address Data ACK 8-Bits Command Byte: selects which register you are writing to. Data ACK P NACK P 8-Bits Data Byte: data goes into the register set by the command byte. Read 1-Byte Format S Address 7-Bits R/W ACK Command 0 ACK R/W ACK Data Address S 8-Bits 1 7-Bits NACK P 8-Bits Command Byte: selects Slave Address: repeated Data Byte: reads from which register you are due to change in data the register set by the reading from. flow direction. command byte. Slave Address Read 2-Byte Format S Address 7-Bits R/W ACK Command 0 ACK Slave Address R/W ACK Data Address S 8-Bits 1 7-Bits Command Byte: selects which register you are reading from. 8-Bits ACK Data 8-Bits Slave Address: repeated Data Byte: reads from due to change in data the register set by the flow direction. command byte. Receive 1-Byte Format S Address 7-Bits R/W ACK 1 Data NACK P 8-Bits S = START Condition Data Byte: reads data from P = STOP Condition the register commanded by Shaded = Slave Transmission the last read-byte or writebyte transmission. Receive 1-Byte Format S Address 7-Bits R/W ACK 1 Data ACK 8-Bits Data NACK P 8-Bits Data Byte: reads data from S = START Condition the register commanded by P = STOP Condition Shaded = Slave Transmission the last read-byte or writebyte transmission. FIGURE 3-1: DS21387C-page 8 SMBus/I2C Protocols. 2010 Microchip Technology Inc. TC1321 4.0 SERIAL PORT OPERATION 4.1 START Condition (START) The Serial Clock input (SCL) and bi-directional data port (SDA) form a 2-wire bi-directional serial port for programming and interrogating the TC1321. The following conventions are used in this bus architecture. The TC1321 continuously monitors the SDA and SCL lines for a START condition (a HIGH to LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. TABLE 4-1: 4.2 Term TC1321 SERIAL BUS CONVENTIONS Explanation Transmitter The device sending data to the bus. Receiver The device receiving data from the bus. Master The device that controls the bus: initiating transfers (START), generating the clock, and terminating transfers (STOP) Slave The device addressed by the master. START A unique condition signaling the beginning of a transfer, indicated by SDA falling (High Low) while SCL is high. STOP A unique condition signaling the end of a transfer, indicated by SDA rising (Low - High) while SCL is high. Address Byte Immediately following the START condition, the host must transmit the address byte to the TC1321. The 7-bit SMBus address for the TC1321 is 1001000. The 7-bit address transmitted in the serial bit stream must match for the TC1321 to respond with an Acknowledge (indicating the TC1321 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read-Write bit. This bit is a 1 for a read operation or 0 for a write operation. During the first phase of any transfer, this bit will be set = 0 to indicate that the command byte is being written. 4.3 Acknowledge (ACK) ACK A receiver acknowledges the receipt of each byte with this unique condition. The receiver drives SDA low during SCL, high of the ACK clock pulse.The master provides the clock pulse for the ACK cycle. Acknowledge (ACK) provides a positive handshake between the host and the TC1321. The host releases SDA after transmitting eight bits, then generates a ninth clock cycle to allow the TC1321 to pull the SDA line LOW to Acknowledge that it successfully received the previous eight bits of data or address. Busy Communication is not possible because the bus is in use. 4.4 Not Busy When the bus is IDLE, both SDA and SCL will remain high. Data Valid The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. See START and STOP conditions. All transfers take place under control of a host, usually a CPU or microcontroller, acting as the master, which provides the clock signal for all transfers. The TC1321 always operates as a slave. The serial protocol is illustrated in Figure 4-1. All data transfers have two phases; all bytes are transferred MSB first. Accesses are initiated by a START condition (START), followed by a device-address byte and one or more data bytes. The device-address byte includes a Read/Write selection bit. Each access must be terminated by a STOP Condition (STOP). A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for START and STOP conditions). 2010 Microchip Technology Inc. Data Byte After a successful ACK of the address byte, the host must transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TC1321. 4.5 Stop Condition (STOP) Communications must be terminated by a STOP condition (a LOW to HIGH transition of SDA while SCL is HIGH). The STOP condition must be communicated by the transmitter to the TC1321. Refer to Figure 4-1, for serial bus timing. DS21387C-page 9 TC1321 Write Timing Diagram A B ILOW I HIGH C D E F G H K J I SCL SDA tSU(START) tH(START) tSU(STOP) tSU-DATA A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave E = Slave Pulls SDA Line Low F = Acknowledge Bit Clocked into Master G = MSB of Data Clocked into Master H = LSB of Data Clocked into Master tIDLE I = Acknowledge Clock Pulse J = STOP Condition K = New START Condition Read Timing Diagram A B ILOW IHIGH C D E F G H I J K L M SCL SDA tSU(START) tH(START) A = START Condition B = MSB of Address Clocked into Slave C = LSB of Address Clocked into Slave D = R/W Bit Clocked into Slave E = Slave Pulls SDA Line Low FIGURE 4-1: DS21387C-page 10 tSU-DATA tH-DATA F = Acknowledge Bit Clocked into Master G = MSB of Data Clocked into Slave H = LSB of Data Clocked into Slave I = Slave Pulls SDA Line Low tSU(STOP) tIDLE J = Acknowledge Clocked into Master K = Acknowledge Clock Pulse L = STOP Condition, Data Executed by Slave M = New START Condition SMBus/I2CTiming Diagrams. 2010 Microchip Technology Inc. TC1321 4.6 Register Set and Programmer’s Model TABLE 4-2: TC1321 COMMAND SET (READ_BYTE AND WRITE_BYTE) Command Byte Description Command Code RWD 00h Read/Write Data (DATA) RWCR 01h Read/Write Configuration (CONFIG) TABLE 4-3: Function CONFIGURATION REGISTER (CONFIG), 8-BIT, READ/WRITE Configuration Register (CONFIG) Bit Name D[7] D[6] D[5] Bit Function D[4] D[3] D[2] D[1] D[0] Reserved (Note 1) SHDN (Note 2) Note 1: Always returns ‘0’ when reading 2: 1 = Standby (Shut down) mode 0 = Normal mode TABLE 4-4: DATA REGISTER (DATA), 10-BIT, READ/WRITE Data Register (DATA) for 2nd Byte Data Register (DATA) for 1st Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] X X X X X X MSB X X X X X X X X LSB X X X X X X The DAC output voltage is a function of reference voltage and the binary value of the contents of the register DATA. The transfer function is given by the expression: EQUATION 4-1: DATA V OUT = VREF ---------------1024 4.7 Register Set Summary The register set for the TC1321 is summarized in Table 4-5. TABLE 4-5: Name Data Config TC1321 REGISTER SET SUMMARY Description POR State Read Write DATA Register (2-Byte Format) 0000000000b X X CONFIG Register 0000 0000b X X 2010 Microchip Technology Inc. DS21387C-page 11 TC1321 NOTES: DS21387C-page 12 2010 Microchip Technology Inc. TC1321 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN TC1321E e3 OA^^1029 256 8-Lead MSOP Example XXXXXX 1321E YWWNNN 029256 Legend: XX...X Y YY WW NNN e3 * Note: Example Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. DS21387C-page 13 TC1321 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21387C-page 14 2010 Microchip Technology Inc. TC1321 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. DS21387C-page 15 TC1321 !"#$%& ' ! "#$%&"'"" ($) % *++&&&! !+$ DS21387C-page 16 2010 Microchip Technology Inc. TC1321 ( )*+#(& ' ! "#$%&"'"" ($) % *++&&&! !+$ D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 A" !" E!" G#!8 )(" EE;; G G GH J ( H5L N K<?@ N %%($$"" < < < % )) 1 N 1< H5O% ; %%($O% ;1 =?@ H5E =?@ E E E1 11 ?@ K <; Q N Q E%$"" N = E%O% 8 N ' 1 (15"#%7)#!5'8#!#"8 %&% !" "%;1% #%! %)" #" " %)" #" "" 7%1<!!"% = !" % ;>1< ?@* ?"!" 75#" && # " ;* )!" '#"#& # ') ) ! # "" & @111? 2010 Microchip Technology Inc. DS21387C-page 17 TC1321 8-Lead Plastic Micro Small Outline Package (UA) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21387C-page 18 2010 Microchip Technology Inc. TC1321 APPENDIX A: REVISION HISTORY Revision C (November 2010) The following is the list of modifications: 1. 2. 3. 4. Updated the Electrical Specifications table. Updated Section 5.0 “Packaging Information”. Replaced the older package drawings with current drawings from the Microchip Packaging Specification (DS00049BF). Added the Revision History section. Updated the Product Identification System section. Revision B (May 2008) • Undocumented changes. Revision A (November 2007) • Original Release of this Document. 2010 Microchip Technology Inc. DS21387C-page 19 TC1321 NOTES: DS21387C-page 20 2010 Microchip Technology Inc. TC1321 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device TC1321: 10-Bit Digital-to-Analog Converter with Two-Wire Interface Tape and Reel TR = Tape and Reel Temperature Range I = -40C to Package OA UA = = +85C (Industrial) Examples: a) b) TC1321VUA: TC1321VUATR: c) d) TC1321EUA: TC1321EUATR: e) f) TC1321EOA: TC1321EOATR: g) h) TC1321VOA: TC1321VOATR: 8LD MSOP package. Tape and Reel 8LD MSOP package. 8LD MSOP package. Tape and Reel, 8LD MSOP package. 8LD SOIC package. Tape and Reel 8LD SOIC package. 8LD SOIC package. Tape and Reel 8LD SOIC package. Small Outline Package (SOIC), (3,90 mm) 8-lead Micro Small Outline Package (MSOP), 8-lead 2010 Microchip Technology Inc. DS21387C-page 21 TC1321 NOTES: DS21387C-page 22 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-567-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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