Product is End of Life 3/2014 Si9168 Vishay Siliconix Synchronous Buck or Boost Controller for 2-Cell Li+ Battery Operated Portable Communication Devices DESCRIPTION FEATURES The Si9168 is a synchronous buck or boost controller for 2-cell Li+ battery operated portable communication devices. Designed for use with external high-frequency MOSFETs, the Si9168 is ideal for providing power to various power amplifiers such as TDMA, CDMA, GSM, or PCS. For ultrahigh efficiency, converters are designed to operate in synchronous rectified PWM mode under full load, while transforming into externally controlled pulse skipping mode (PSM) under light load conditions. All these features are provided by Si9168 without sacrificing system integration requirements of fitting these circuits into ever demanding smaller space. The Si9168 is capable of switching up to 2 MHz to minimize the size of the output inductor and capacitor, in order to decrease the overall converter footprint. The programmability to design a buck or boost converter with this IC makes it convenient to power either the high voltage (7.2 V) or low voltage (4 V) PAs. • • • • The Si9168 is available in TSSOP-16 pin package and specified to operate over the industrial temperature range of - 25 °C to 85 °C. • • • • • • • • Voltage Mode Control 5 V to 10 V Input Voltage Range for VDD 5 V to 12.6 V Input Voltage Range for VS - Boost Programmable PWM/PSM Control - Up to 2 MHz Switching Frequency in PWM - Synchronous Rectification in PWM - Less than 350 µA IDD in PSM Very High Efficiencies In Buck or Boost Modes Low Dropout Operation at 100 % Duty Cycle In Buck Mode Integrated UVLO and POR Integrated Soft-Start Synchronization Logic Controlled Micropower Shutdown Current < 2 µA Fast Line and Load Transient Response Available in 16-Lead TSSOP Package APPLICATIONS • • • • • • Cellular Telephones Wireless Modems Portable Instruments Notebook and Palmtop Computers PDA’s Battery Operated Devices FUNCTIONAL BLOCK DIAGRAM VIN (5 - 10 V) VIN (5 - 10 V) 1.3 V ~ 10 V SMPS VOUT (5 ~ 12.6 V) VOUT (1.3 ~ 10 V) 5 V ~ 12.6 V SMPS 1.3 V Voltage Reference SD Shutdown Control Buck Mode Document Number: 70899 S11-0975-Rev. B, 16-May-11 VREF (1.3 V) 1.3 V Voltage Reference SD VREF (1.3 V) Shutdown Control Boost Mode www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9168 Product is End of Life 3/2014 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Voltages Referenced to AGND VDD 13.2 VSS - VDD 2 PWM/PSM, SYNC, SD, VREF, ROSC, COMP, FB, Mode V - 0.3 to VDD + 0.3 VO - 0.3 to VS + 0.3 PGND ± 0.3 Voltages Referenced to PGND VS 13.2 DH, DL V - 0.3 to VS + 0.3 Peak Output Current (DH, DL) 1 Storage Temperature A - 65 to 150 Operating Junction Temperature °C 150 Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)b 925 mW Thermal Impedance (ΘJA) 16-Pin TSSOP 135 °C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 7.4 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Limit Unit VDD 5 to 10 V FOSC 200 kHz to 2 MHz ROSC 25 to 300 kΩ PWM/PSM, SYNC, SD, Mode 0 to VDD V 0.1 µF Voltages Referenced to AGND VREF Voltages Referenced to PGND VS Buck 5.0 to 10 Boost 5.0 to 12.6 V SPECIFICATIONS Parameter Symbol Test Conditions Unless Otherwise Specified 5 V ≤ VDD, VS ≤ 10 V Limits - 25 °C to 85 °C Min.a Typ.b Max.a Unit Reference Output Voltage VREF VREF Current IREF Power Supply Rejection PSRR IREF = 0 A 1.268 1.3 1.332 VDD = 7.2, 25 °C 1.280 1.3 1.320 - 500 V µA 60 dB UVLO Under Voltage Lockout (Turn-On) Hysteresis VUVLO/LH 4.3 4.5 VHYS 0.2 tSS 3 4.7 V Soft-Start Time SS Time www.vishay.com 2 ms Document Number: 70899 S11-0975-Rev. B, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix SPECIFICATIONS Parameter Symbol Test Conditions Unless Otherwise Specified 5 V ≤ VDD, VS ≤ 10 V Limits - 25 °C to 85 °C Min.a Typ.b Max.a Unit SD, SYNC, PWM/PSM Logic High VIH Logic Low VIL 2.4 IL - 1.0 Logic High VIH 70 % VDD Logic Low VIL Input Current V 0.8 1.0 µA Mode Input Current V 70 % VDD IL - 1.0 1.0 µA Oscillator Maximum Frequency FMAX Accuracy Maximum Duty Cycle (Buck, Non LDO Mode) DMAX FSW = 2 MHz 75 80 65 71 FSYNC/FOSC 20 1.2 SYNC Low Pulse Width % 1.5 50 SYNC High Pulse Width SYNC tr, tf MHz - 20 ROSC = 130 kΩ, VDD = 5 V, VS = 12.6 V Maximum Duty Cycle (Boost) SYNC Range 2 1 External Resistor 50 ns tr, tf 50 Error Amplifier VFB = 1.4 V Input Bias Current IBIAS Open Loop Voltage Gain AVOL 50 Offset Voltage VOS - 10 Unity Gain BW BW Output Current (Source) Output Current (Sink) Power Supply Rejection IEA -1 1 µA 10 mV 60 dB 2 VFB = 1.05 V VFB = 1.55 V -2 1 PSRR MHz -1 3 60 mA dB PSM Modulator Switch On Time tON Switch Off Blanking Time tOFF 180 VDD = 7.2 V, VOUT = 3.3 V, Buck Mode ns 330 Output Drive (DH and DL) Output High Voltage VOH VS = 7.2, IOUT = - 20 mA Output Low Voltage VOL VS = 7.2, IOUT = 20 mA Peak Output Source ISOURCE Peak Output Sink ISINK Break-Before-Make tBBM VS = 7.2 V, DH = DL = VS/2 VS = VDD = 10 V 7.08 500 7.14 0.06 0.12 - 1000 - 500 1000 40 V mA ns Supply Normal Mode PSM Mode Shutdown Mode IDD VDD = 7.2 V, fOSC = 2 MHz 1100 VDD = 7.2 V 350 VDD = 7.2 V, SD = 0 V 2.0 µA Notes: a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. c. Guaranteed by design and characterization, not subject to production testing. Document Number: 70899 S11-0975-Rev. B, 16-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix 1.310 1.320 1.308 1.316 1.306 1.312 1.304 1.308 1.302 1.304 V REF (V) V REF (V) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.300 1.298 VDD = 7.2 V 1.300 1.296 1.296 1.292 1.294 1.288 1.292 1.284 1.29 4 6 8 10 12 1.28 - 50 14 - 25 VDD - (V) 25 50 75 100 Temperature (°C) VREF vs. VDD VREF vs. Temperature 10000 2.2 VDD = 7.2 V ROSC = 25 kΩ Frequency (kHz) 2.1 Frequency (MHz) 0 2.0 1.9 1000 1.8 1.7 - 50 0 50 100 10 100 100 ROSC (kΩ) Temperature (°C) Frequency vs. Temperature Frequency vs. ROSC 74 98 VIN = 7.2 V VIN = 7.2 V 70 94 66 90 % Max Duty Cycle % Max Duty Cycle 1000 86 82 78 62 58 54 50 74 46 70 400 600 800 1000 1200 1400 1600 1800 2000 2200 Frequency (kHz) Max Duty Cycle vs. Frequency (Buck Mode) www.vishay.com 4 42 400 600 800 1000 1200 1400 1600 1800 2000 2200 Frequency (kHz) Max Duty Cycle vs. Frequency (Boost Mode) Document Number: 70899 S11-0975-Rev. B, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1400 1400 1200 1000 1000 I DD (µA) I DD (µA) FOSC = 1.6 MHz 1200 800 800 600 600 400 400 200 200 4 6 8 10 12 4 14 6 8 10 12 14 VDD - (V) VDD - (V) PWM Supply Current vs. VDD (Buck Mode) PWM Supply Current vs. VDD (Boost Mode) 300 300 250 250 200 200 I DD (µA) I DD (µA) FOSC = 1.6 MHz 150 100 150 100 50 50 4 6 8 10 12 14 4 6 8 VDD - (V) 10 12 14 VDD - (V) PSM Supply Current vs. VDD (Buck Mode) PSM Supply Current vs. VDD (Boost Mode) 100 100 PSM = 5 VIN 90 PWM = 5 VIN 80 PWM = 7.2 VIN PSM = 7.2 VIN PWM = 8.4 VIN 70 Efficiency (%) Efficiency (%) 90 PWM: 5.4 VIN PSM: 5.4 VIN PWM: 6.0 VIN 80 PSM: 6.0 VIN PSM: 7.0 VIN PWM: 7.0 VIN 70 PSM = 8.4 VIN 60 60 50 10 100 1000 10000 50 10 100 1000 10000 Load Current (mA) Load Current (mA) Efficiency - Buck, VOUT = 3.6 V Efficiency - Boost, VOUT = 7.2 V Document Number: 70899 S11-0975-Rev. B, 16-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix PIN CONFIGURATION TSSOP-16 MODE 1 ORDERING INFORMATION 16 VS DL 2 15 N/C PGND 3 14 DH SD 4 13 PWM/PSM VO 5 12 SYNC VDD 6 11 GND ROSC 7 10 VREF COMP 8 9 Si9168BQ Part Number Temperature Range Package Si9168BQ-T1 - 25 °C to 85 °C Tape and Reel Eval Kit Si9168DB Temperature Range Board Type - 25 °C to 85 °C Surface Mount FB Top View PIN DESCRIPTION Pin Number Name 1 MODE 2 DL 3 PGND Function Determines the converter topology. Connect to AGND for buck or VDD for boost. The gate drive output for the low-side N-Channel MOSFET for buck and boost converter Power ground for output drive stage 4 SD Logic low shuts down the IC completely and decreases the current consumption of IC to < 2 µA. 5 VO Direct output voltage sense 6 VDD Input supply voltage for the analog circuit. VDD voltage should be the ac filtered voltage of VSS. Input voltage range is 5 V to 10 V. 7 ROSC External resistor to determine the switching frequency. 8 COMP Error amplifier output for external compensation network. 9 FB 10 VREF 11 GND Low power controller ground SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD, or logic high. 12 13 Output voltage feedback connected to the inverting input of an error amplifier. 1.3 V reference voltage. Connected internally to non-inverting error amplifier input. Decouple with 0.1 µF ceramic capacitor. PWM/PSM Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification drive is disabled. 14 DH The gate drive output for the high-side P-Channel MOSFET for buck and boost converter 15 N/C Not used. 16 VS Supply voltage for the output driver section. Voltage range is 5 V to 10 V (Buck), 5 V to 12.6 V (Boost). www.vishay.com 6 Document Number: 70899 S11-0975-Rev. B, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix BLOCK DIAGRAM VDD SD Positive Supply Reference 1.3 V Soft-Start Timer UVLO Threshold Generator POR Bias Generator System Monitor VREF VO FB COMP VS PWM Modulator 1.0 V Ramp SYNC PWMIN 0.5 V DH PWMIN Oscillator PWM/PFM Select ROSC COSC Drivers PSMIN PSMIN DL PSM Modulator PWM/PSM PGND Negative Return and Substrate MODE GND Figure 1. DETAIL OPERATIONAL DESCRIPTION Start-Up The UVLO circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on VDD pin is less than 4.5 V. With typical UVLO hysteresis of 0.2 V, the controller is continuously powered on until the VDD voltage drops below 4.3 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. After the POR time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging of the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchroDocument Number: 70899 S11-0975-Rev. B, 16-May-11 nous switch is tri-stated until the duty cycle reaches about 10 %. See start-up timing diagram. In tri-state, the high-side P-Channel MOSFET is turned off by pulling up the gate voltage (DH) to VS potential. The low-side N-Channel MOSFET is turned off by pulling down the gate voltage (DL) to PGND potential. Note that Si9168 will always soft starts in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown Si9168 is designed to conserve as much battery life as possible by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low level on the SD pin, current consumption of the Si9168 decreases to less than 2 µA by shutting off most of the circuits. The logic high enables the controller and starts up as described in "Start-Up" section above. www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si9168 Product is End of Life 3/2014 Vishay Siliconix DETAIL OPERATIONAL DESCRIPTION PWM Mode Pulse Skipping Mode With PWM/PSM mode pin in logic high condition, Si9168 operates in constant frequency (PWM) mode. As the load and input voltage vary, switching frequency remain constant. The switching frequency is programmed by the ROSC value as shown by the oscillator curve. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A. In continuous current mode, the transfer function of the converter remain constant providing fast transient response. If the converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be 10 times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltage regulation. Therefore, the PWM/PSM pin is available to dynamically program the controller. If the synchronous rectifier switch is not used, the converter may not operate in PWM mode if the load current is low enough to force the converter into pulse skipping mode. The maximum duty cycle of the Si9168 can reach 100 % in buck mode. The duty cycle will continue to increase as the input voltage decreases until it reaches 100 %. This allows the system designers to extract out the maximum stored energy from the battery. Once the controller delivers 100 % duty cycle, the converter operates like a saturated linear regulator. At 100 % duty cycle, synchronous rectification is completely turned off. At up to 80 % duty cycle at 2 MHz switching frequency, the controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80 % duty cycle, the controller will deliver 100 % duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time and the internal propagation delays. In order to maintain regulation, the controller might fluctuate its duty cycle back and forth from 100 % to something lower than 80 % during this input voltage range. If the input voltage drops further, the controller will remain on for 100 % duty cycle. If the input voltage increases to a point where it’s requiring less than 80 % duty cycle, synchronous rectification is once again activated. The maximum duty cycle under boost mode is internally limited to 75 % to prevent inductor saturation. If the converter is turned on for 100 % duty cycle, the inductor never gets a chance to discharge its energy and eventually saturate. In boost mode, the synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. The controller will deliver 0 % duty cycle, if the input voltage is greater than the programmed output voltage. Because of fixed BBM time, the controller will not transition smoothly from minimum controllable duty cycle to 0 % duty cycle. For example, controller may decrease its duty cycle from 5 % to 0 % abruptly, instead of the gradual decrease seen from 75 % to 5 %. The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter during light load (i.e. < 200 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9168 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 350 µA, instead of 900 µA during the PWM mode. This is accomplished by turning off most of the internal control circuitry and utilizing a simple constant on-time control with the feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on the inductor used (2 µH typical) and the maximum load current. Therefore, with this control method, duty cycles ranging from 0 to 100 % are possible depending on whether the boost or buck mode is chosen. www.vishay.com 8 Reference The reference voltage for the Si9168 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The REF pin requires a 0.1 µF decoupling capacitor. Error Amplifier The error amplifier gain-bandwidth product and slew rate are critical parameters which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, the error amplifier determines the converter response time. In order to minimize the response time, Si9168 is designed with a 2 MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and a 3.5 V/µs slew rate for ultra-fast large signal response. Document Number: 70899 S11-0975-Rev. B, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix DETAIL OPERATIONAL DESCRIPTION Oscillator Break-Before-Make Timing The oscillator is designed to operate up to 2 MHz minimum. The 2 MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with a 2 MHz switching frequency, quiescent current is only 1100 µA (max) with the unique power saving circuit design. The switching frequency is easily programmed by attaching a resistor to the ROSC pin. See oscillator frequency versus Rosc curve to select the proper timing values for the desired operating frequency. The tolerance on the operating frequency is ± 20 % with a 1 % tolerance resistor. A proper BBM time is essential in order to prevent shootthrough current and to maintain high efficiency. The breakbefore-make time is set internally at 20 to 60 ns at VS = 7.2 V. The high- and low-side gate drive voltages are monitored and when the gate-to-source voltage reaches 3.5 V above or below the initial starting voltage, 20 to 60 ns BBM time is set before the other gate drive transitions to its proper state. The maximum and minimum duty cycle is limited by the BBM time. Since the BBM time is fixed, controllable maximum duty cycle will vary depending on the switching frequency. Output Driver Stage Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. The logic high to low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. Document Number: 70899 S11-0975-Rev. B, 16-May-11 The DH pin is designed to drive the main switch MOSFET and DL pin is designed to drive the synchronous rectifier MOSFET. The driver stage is sized to sink and source peak currents up to 1000 mA with VS = 7.2 V. The ringing from the gate drive output trace inductance can produce negative voltage on the DH and DL respect to PGND. The gate drive circuit is capable of withstanding these negative voltages without any functional defects. www.vishay.com 9 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Product is End of Life 3/2014 Si9168 Vishay Siliconix APPLICATIONS VIN 5-10 V 6, 7 Q1B 5 C1 22 µF 16 V R1* 51 Ω Si6803DQ R9* 5.6 Ω 1 2 DL NC 3 PGND DH 4 5 6 VOUT SYNC VDD GND C5 0.1 µF R5 75 kΩ 8.2 k Ω C6 1 nF 4 14 Q1A C2 10 µF 10 V C3 0.1 µF COM 2, 3 Si6803DQ 13 12 R2 200 Ω 11 R3 22 kΩ 10 VREF 8 COMP C9 0.1 µF 15 PWM/PSM SD 7 R OSC R6 16 VS MODE 8 1 D1 MBR0520T1 R8* 5.6 Ω U1 VOUT 3.6 V 1.5 A L1, 4.7 µH IHLP2525 COM 9 FB C8 0.1 µF PWM/PSM to VIN for PWM mode; PWM/PSM to GND for PSM mode. C4 330 pF SD to VIN for converter enable mode; SD to GND for shutdown mode. Si9168BQ C7 56 pF R4 12.4 kΩ * = Optional Figure 2. 1.5 A Buck Regulator Using the Si9168BQ VIN 5-7.2 V C1 10 µF 16 V COM R1* 51 Ω Q2 L1, 4.7 µH IHLP2525 Si3442DV 1, 2, 5, 6 Q1 5, 6, 7, 8 SI9803DY 3 D1 B130LB 4 U1 1 MODE VS DL NC 3 PGND DH 2 4 5 6 SD PWM/PSM VOUT SYNC VDD GND 7 R OSC C5 0.1 µF R5 75 kΩ R6 C6 5.6 nF VREF 8 COMP 4.7 kΩ VOUT 7.2 V 2.5 A 4 FB 1, 2, 3 16 15 14 13 PWM/PSM to VIN for PWM mode; PWM/PSM to GND for PSM mode. 12 SD to VIN for converter enable mode; SD to GND for shutdown mode. 11 * = Optional C2 47 µF 16 V C3 0.1 µF COM 10 9 R2 1 kΩ C8 0.1 µF Si9168 C7 220 pF R3 56.2 kΩ C4 560 pF R4 12.4 kΩ Figure 3. Si9168BQ Boost Regulator Application Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70899. www.vishay.com 10 Document Number: 70899 S11-0975-Rev. B, 16-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TSSOP: 16-LEAD DIMENSIONS IN MILLIMETERS Symbols Min Nom Max A - 1.10 1.20 A1 0.05 0.10 0.15 A2 - 1.00 1.05 0.38 B 0.22 0.28 C - 0.127 - D 4.90 5.00 5.10 E 6.10 6.40 6.70 E1 4.30 4.40 4.50 e - 0.65 - L 0.50 0.60 0.70 L1 0.90 1.00 1.10 y - - 0.10 θ1 0° 3° 6° ECN: S-61920-Rev. D, 23-Oct-06 DWG: 5624 Document Number: 74417 23-Oct-06 www.vishay.com 1 PAD Pattern www.vishay.com Vishay Siliconix RECOMMENDED MINIMUM PAD FOR TSSOP-16 0.193 (4.90) 0.171 0.014 0.026 0.012 (0.35) (0.65) (0.30) (4.35) (7.15) 0.281 0.055 (1.40) Recommended Minimum Pads Dimensions in inches (mm) Revision: 02-Sep-11 1 Document Number: 63550 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000