Si9166 Vishay Siliconix High Frequency Programmable Topology Controller FEATURES D D D D Buck or Boost Configuration Voltage Mode Control 2.7-V to 6-V Input Voltage Range for VDD and VS Programmable PWM/PSM Control − Up to 2-MHz Switching Frequency in PWM − Synchronous Rectification in PWM − Less than 200-mA IDD in PSM D D D D Integrated UVLO and POR Integrated Soft-Start Synchronization Shutdown Current <1 mA DESCRIPTION The Si9166 is a programmable topology controller for today’s continuous changing portable electronic market. Si9166 provides flexibility of utilizing various battery configurations and chemistries such as NiCd, NiMhy, or Li+ with input voltage range of 2.7 V to 6 V. An additional flexibility is provided with topology programmability to power multiple loads such as power amplifiers, microcontrollers, or baseband logic IC’s. The converters can be programmed to be synchronous Buck or Boost topology. For ultra-high efficiency, converters are designed to operate in synchronous rectified PWM mode under full load while transforming into externally controlled pulse skipping mode (PSM) under light load. All these features are provided by the Si9166 without sacrificing system integration requirements of fitting these circuits into ever demanding smaller and smaller space. The Si9166 is capable of switching up to 2 MHz to minimize the output inductor and capacitor size in order to decrease the overall converter size. The Si9166 is available in both standard and lead (Pb)-free TSSOP-16 pin packages and specified to operate over the industrial temperature range of −25_C to 85_C. TYPICAL APPLICATION CIRCUITS VIN Si6803 VOUT Si6803 D D D D S1 S2 S1 S2 S1 S2 S1 S2 G1 G2 VIN VOUT G1 G2 SD SD Si9166 VS N/C PWM/PSM SYNC Si9166 MODE N/C SD DH DL PWM/PSM PGND VS N/C PWM/PSM MODE N/C SD DH DL PWM/PSM PGND SYNC VO SYNC VO GND VDD GND VDD ROSC REF REF FB COMP Buck Configuration Document Number: 70847 S-40701—Rev. C, 19-Apr-04 SYNC FB ROSC COMP Boost Configuration www.vishay.com 1 Si9166 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to GND Peak Output Current (DH, DL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C MODE, PWM/PSM, SYNC, SD, VREF, ROSC COMP, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VS + 0.3 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "0.3 V Voltages Referenced to PGND VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V DH, DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VS + 0.3 V Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (qJA) 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.4 mW/_C above 25_C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Voltages Referenced to AGND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD Voltages Referenced to PGND VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V Fosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 kHz to 2 MHz Rosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 300 kW VREF Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter Symbol Limits 2.7 V v VDD, VS v 6 V Mina Typb Maxa IREF = 0A 1.268 1.3 1.332 IREF = 0, TA = 25°C 1.280 1.3 1.320 Unit Reference Output Voltage Load Regulation Power Supply Rejection VREF DVREF VDD = 3.3 V, −500 µA < IREF <0 PSRR V 3 mV 60 dB UVLO Under Voltage Lockout (turn-on) Hysteresis VUVLOLH VHYS 2.3 VUVLOLH − VUVLOHL 2.4 2.5 0.1 V Soft-Start Tim SS time tss 6 mS Mode Logic High VIH Logic Low VIL Input Current 0.7 VDD 0.3 VDD IL −1.0 Logic High VIH 2.4 Logic Low VIL 1.0 V mA SD, SYNC, PWM/PSM Input Current www.vishay.com 2 IL 0.8 −1.0 1.0 V mA Document Number: 70847 S-40701—Rev. C, 19-Apr-04 Si9166 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter Symbol Limits 2.7 V v VDD, VS v 6 V Mina Typb Nominal 1.60 MHz, ROSC = 30 kW −20 Fsw = 2 MHz (non LDO mode) 75 85 52 65 Maxa Unit Oscillator Maximum Frequency FOSC Accuracy Maximum Duty Cycle—Buck Maximum Duty Cycle—Boost SYNC Range DMAX 2 Fsw = 2 MHz FSYNC/FOSC MHz 20 1.2 SYNC Low Pulse Width 50 SYNC High Pulse Width 50 % 1.5 ns SYNC tr, tf 50 Error Amplifier Input Bias Current IBIAS Open Loop Voltage Gain AVOL FB Threshold VFB Unity Gain BW BW Output Current Power Supply Rejection IEA VFB = 1.4 V TA = 25_C −1 1 50 60 1.270 1.30 1.330 1.258 1.30 1.342 dB 2 Source (VFB = 1.05 V), VCOMP = 0.75 V Sink (VFB = 1.55 V), VCOMP = 0.75 V −3 1 PSRR mA V MHz −1 3 60 mA dB Output Drive (DH and DL) Output High Voltage VOH VS = 3.3 V, IOUT = −20 mA Output Low Voltage VOL VS = 3.3 V, IOUT = 20 mA Peak Output Source ISOURCE Peak Output Sink ISINK Break-Before-Make tBBM VS = 3.3 33V V, DH = DL = VS/2 3.18 500 3.24 0.06 0.12 −750 −500 750 VS = VDD = 3.3 V 30 VDD = 3.3 V, FOSC = 2 MHz 500 750 VDD = 3.3 V 180 250 V mA ns Supply Normal Mode PSM Mode Shutdown Mode IDD VDD = 3.3 V, SD = 0 V mA 1 Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Document Number: 70847 S-40701—Rev. C, 19-Apr-04 www.vishay.com 3 Si9166 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED) VREF vs. VDD 1.310 1.31 V REF (V) 1.305 V REF (V) VREF vs. Temperature 1.32 1.300 1.30 1.29 1.295 1.290 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.28 −50 6.0 50 100 150 Temperature (_C) VDD − (V) Frequency vs. Temperature 2.00 0 Frequency vs. ROSC 10000 1.90 Frequency (kHz) Frequency (MHz) 1.95 ROSC = 25 kW 1.85 1.80 1000 1.75 1.70 −100 100 −50 0 50 100 10 150 100 Temperature (_C) 1000 ROSC (kW) Buck Mode Efficiency, VO = 2.7 V Boost Mode Efficiency, VO = 3.6 V 100 100 PWM−3.3 V PSM−3 V PSM−3.6 V 80 PWM−3.3 V PWM−3 V PWM−3.6 V 70 PSM−3 V 80 PSM−2.7 V PWM−2.7 V PWM−3 V 70 60 60 50 50 1 10 100 Load Current (mA) www.vishay.com 4 PSM−3.3 V 90 PSM−3.3 V Effocoemcu (%) Effocoemcu (%) 90 1000 1 10 100 1000 Load Current (mA) Document Number: 70847 S-40701—Rev. C, 19-Apr-04 Si9166 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED) PWM Supply Current PSM Supply Current 800 250 700 200 I DD (mA) I DD (mA) 600 500 150 400 100 300 200 50 2 3 4 5 6 2 7 3 4 VDD − (V) 5 6 7 VDD − (V) PIN CONFIGURATION TSSOP-16 VS 1 16 MODE N/C 2 15 SD DH 3 14 DL PWM/PSM 4 13 PGND SYNC 5 12 VO GND 6 11 VDD VREF 7 10 ROSC FB 8 9 COMP Top View ORDERING INFORMATION Part Number Temperature Range Package −25 25 to 85_C Tape and Reel Eval Kit Temperature Range Board Type Si9166DB −25 to 85_C Surface Mount Si9166BQ-T1 Si9166BQ-T1—E3 PIN DESCRIPTION Pin Symbol 1 VS Input supply voltage for the output driver section. Input voltage range is 2.7 V to 6V 2 N/C Not Used 3 DH The gate drive output for the high-side p-channel MOSFET. The p-channel MOSFET is the main switch for buck topology and the synchronous rectifier for the boost topology. 4 PWM/PSM 5 SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD, or logic high. 6 GND Low power controller ground 7 VREF 1.3-V reference. Decoupled with 0.1-mF capacitor 8 FB 9 COMP Error amplifier output for external compensation network. 10 ROSC External resistor to determine the switching frequency. 11 VDD Input supply voltage for the analog circuit. Input voltage range is 2.7 V to 6 V. 12 VO Direct output voltage sense 13 PGND 14 DL The gate drive output for the low-side n-channel MOSFET. The n-channel MOSFET is the synchronous rectifier for the buck topology and the main switch for the boost topology. 15 SD Shuts down the IC completely and decreases current consumed by the IC to < 1 mA. 16 MODE Document Number: 70847 S-40701—Rev. C, 19-Apr-04 Description Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled. Output voltage feedback connected to the inverting input of an error amplifier. Power ground for output drive stage Determines the converter topology. Connect to AGND for Buck or VDD for Boost. www.vishay.com 5 Si9166 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD Reference Threshold Generator 1.3 V SD Positive Supply Soft-Start Timer UVLO POR Bias Generator SYSTEM MONITOR VREF FB COMP VS PWM Modulator 1.0 V Ramp SYNC PWMIN PWMEN 0.5 V PWM/PSM Select Oscillator ROSC PSMEN COSC DH Drivers DL PSMIN PSM Modulator PGND VO PWM/PSM MODE Negative Return and Substrate GND DETAIL OPERATIONAL DESCRIPTION Start-Up will always soft start in the PWM mode regardless of the voltage level on the PWM/PSM pin. The UVLO circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on VDD pin is less than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is continuously powered on until the VDD voltage drops below 2.4 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. After the POR time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchronous switch is tri-stated until the duty cycle reaches about 10%. See start-up timing diagram. In tri-state, the high-side p-channel MOSFET is turned off by pulling up the gate voltage (DH) to VS potential. The low-side n-channel MOSFET is turned off by pulling down the gate voltage (DL) to PGND potential. Note that the Si9166 Shutdown www.vishay.com 6 The Si9166 is designed to conserve battery life by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low-level on the SD pin, current consumption of the Si9166 decreases to less than 1 mA by shutting off most of the circuits. The logic high enables the controller and starts up as described in Start-Up section above. MODE Selection The Si9166 can be programmed to operate as Buck or Boost converter. If the MODE pin is connected to AGND, it operates in buck mode. If the MODE pin is connected to VDD, it operates in boost mode. The DH gate drive output is designed to drive high-side p-channel MOSFET, acting as the main switch in buck topology and the synchronous rectifier in boost topology. The DL gate drive output is designed to drive low-side n-channel MOSFET, acting as the synchronous rectifier in buck topology and the main switch in boost topology. Document Number: 70847 S-40701—Rev. C, 19-Apr-04 Si9166 Vishay Siliconix PWM Mode Pulse Skipping Mode With PWM/PSM mode pin in logic high condition, the Si9166 operates in constant frequency (PWM) mode. As the load and line varies, switching frequency remain constant. The switching frequency is programmed by the ROSC value. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A. Therefore, the converter always operates in continuous conduction mode (CCM) if a synchronous switch is used. In CCM, transfer function of the converter remains almost constant, providing fast transient response. If the converter operates in discontinuous conduction mode (DCM), overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc/dc converter to meet the transient voltage regulation. The PWM/PSM pin is available to dynamically program the controller. If the synchronous rectifier switch is not used, the converter will operate in DCM at light load. The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter during light load (i.e. < 10 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9166 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 mA, instead of 500 mA during the PWM mode. This is accomplished by turning off most of internal control circuitry and utilizing a simple constant on-time control with feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on inductor used (1.5-mH typical), MODE pin selection and maximum load current. Therefore, with this control method, duty cycle ranging from 0 to near 100% is possible depending on whether buck or boost is chosen. In pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss and increase overall converter efficiency. The maximum duty cycle of the Si9166 can reach 100% in buck mode. The duty cycle will continue to increase as the input voltage decreases until it reaches 100%. This allows the system designers to extract the maximum stored energy from the battery. Once the controller delivers 100% duty cycle, the converter operates like a saturated linear regulator. At 100% duty cycle, synchronous rectification is completely turned off. Up to 80% maximum duty cycle at 2-MHz switching frequency, the controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80% duty cycle, the controller will deliver 100% duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time, MOSFET delay/rise/fall time, and the internal propagational delays. In order to maintain regulation, controller might fluctuate its duty cycle back and forth from 100% to something lower than 80% while the converter is operating in this input voltage range. If the input voltage drops further, controller will remain on 100%. If the input voltage increases to a point where it’s requiring less than 80% duty cycle, synchronous rectification is once again activated. Reference The reference voltage for the Si9166 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The reference pin requires 0.1-mF decoupling capacitor. Error Amplifier The maximum duty cycle under boost mode is internally limited to 70% to prevent inductor saturation. If the converter is turned on for 100% duty cycle, inductor never gets a chance to discharge its energy and eventually saturate. In boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. The controller will deliver 0% duty cycle, if the input voltage is greater than the programmed output voltage. Because of signal propagation time and MOSFET delay/rise/fall time, controller will not transition smoothly from minimum controllable duty cycle to 0% duty cycle. For example, controller may decrease its duty cycle from 5% to 0% abruptly, instead of gradual decrease you see from 70% to 5%. Document Number: 70847 S-40701—Rev. C, 19-Apr-04 The error amplifier gain-bandwidth product and slew rate are critical parameters which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, error amplifier determines the converter response time. In order to minimize the response time, the Si9166 is designed with 2-MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 V/msec slew rate for ultra-fast large signal response. www.vishay.com 7 Si9166 Vishay Siliconix Oscillator The oscillator is designed to operate up to 2-MHz minimal. The 2-MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with 2-MHz switching frequency, quiescent current is only 500 mA with unique power saving circuit design. The switching frequency is easily programmed by attaching resistor to ROSC pin. See oscillator frequency versus ROSC curve to select the proper timing values for desired operating frequency. The tolerance on the operating frequency is (20% with 1% tolerance resistor). Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. The logic high-to-low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. Break-Before-Make Timing A proper BBM time is essential in order to prevent shoot-through current and to maintain high efficiency. The www.vishay.com 8 break-before-make time is set internally at 20 to 60 ns @ VS = 3.6 V. The high- and low-side gate drive voltages are monitored and when the gate to source voltage reaches 1.75 V above or below the initial starting voltage, 20 to 60 ns BBM time is set before the other gate drive transitions to its proper state. The maximum and minimum duty cycle is limited by the BBM time. Since the BBM time is fixed, controllable maximum duty cycle will vary depending on the switching frequency. Output Driver Stage The DH pin is designed to drive the high-side p-channel MOSFET, independent of topology. The DL pin is designed to drive the low-side n-channel MOSFET, independent of topology. The driver stage is sized to sink and source peak currents up to 450 mA with VS = 3.3 V. The ringing from the gate drive output trace inductance can produce negative voltage on the DH and DL respect to PGND. The gate drive circuit is capable of withstanding these negative voltages without any functional defects. Document Number: 70847 S-40701—Rev. C, 19-Apr-04 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1 Package Information Vishay Siliconix TSSOP: 16-LEAD DIMENSIONS IN MILLIMETERS Symbols Min Nom Max A - 1.10 1.20 A1 0.05 0.10 0.15 A2 - 1.00 1.05 0.38 B 0.22 0.28 C - 0.127 - D 4.90 5.00 5.10 E 6.10 6.40 6.70 E1 4.30 4.40 4.50 e - 0.65 - L 0.50 0.60 0.70 L1 0.90 1.00 1.10 y - - 0.10 θ1 0° 3° 6° ECN: S-61920-Rev. D, 23-Oct-06 DWG: 5624 Document Number: 74417 23-Oct-06 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1