S6J3200 series
32bit Microcontorller
Spansion Traveo Family
Datasheet
Supplementary Information
Note: This sheet shows a change trace of description in datasheet. All the changes between previous and current document edition are described in this sheet.
Following "ID" is a number which is owned by every change. A change which is applied to other documents of same family should have a same ID.
Summary
Error
Error
Page
Original document code: DS708-00003-0v02-E, Previous document code: DS708-00003-0v01-E
Rev. 1.0 December 26, 2014
Pin assignment
22, 23
(Relation on pin assignment)
||Function||PORT ||
||MFS8_CS0||P3_08||
||MFS9_CS0||P3_09||
||MFS9_CS1||P3_10||
||MFS8_CS3||P3_11||
||MFS8_CS1||P3_12||
||MFS8_CS2||P3_13||
Correct
Page
Correct
ID
22, 23
(Relation on pin assignment)
||Function||PORT ||
||MFS8_CS0||P3_12||
||MFS9_CS0||P3_13||
||MFS9_CS1||P3_14||
||MFS8_CS3||P3_15||
||MFS8_CS1||P3_16||
||MFS8_CS2||P3_17||
#150
I2S port name
22,23
I2S1_WS1
I2S1_SCK1
22,23
I2S1_WS
I2S1_SCK
#190
Ethernet port name
22,23
RDX0, RDX1, RDX2, RDX3
22,23
RXD0, RXD1, RXD2, RXD3
#191
Vcc12 power supply
62
Vss12:
1.15(min), 1.3(max)
62
Vss12:
1.15(min), 1.3(max)
1.1(min)*1, 1.3(max)
− *1. The value will be for the product series with revision digit B.
#169
Current consumption
69
ICC12: -(typ), 1900(max)
ICCT5: -(typ), 2620(max)
ICCH5: -(typ), 2620(max)
68
ICC12: 950(typ),1900(max)
ICCT5: 350(typ),700(max)
ICCH5: 150(typ),450(max)
#170
Vcc5 current consumption
69
ICC5 Normal operation 60mA(max)
68
ICC5 Normal operation 45mA(typ), 75mA(max)
#181
Current consumption of FPD link
69
-
68
ILVDS: VCC3_LVDS_Tx,AVCC3_LVDS_PLL:
70mA (FPD-Link)
#204
Source clock error
72
Note:
- ,,,,
- Jitter of source oscillator must be smaller than 300ppm.
71
Note:
- ,,,,
- The error of source oscillator frequency must be smaller than 300ppm.
#178
Publication Number S6J3200_DS708-00003-1v0-E-SI
Revision 1
Issue Date September 30, 2015
Supplementary Information
Summary
Trace clock
Error
Page
74, 75
Error
FCLK_TRC: 50MHz
Correct
Page
73, 74
FCLK_TRC: 100MHz
Correct
ID
#182
Note;
- FCLK_TRC/2 (half frequency of FCLK_TRC) comes out of the trace clock port of
package external pin.
Internal clock frequency
75
Notes;
-,,,
74
Notes;
#180
-,,,
- Even if a combination of clock frequency is able to be configured by software, the
frequency should be configured under maximum frequency described in Table. For
example, 80MHz of CLK_LCP0A seems to be configurable from both divided 240MHz
and 160MHz of CLK_CPU. But each duty ratio of configured 80MHz as an internal signal
is different from one another. In this series, the 80MHz from the 160MHz divided by 2 can
only be assured, but the 240MHz divided by 3 cannot be assured from the internal timing
design point of view.
Power On condition
79
Level detection voltage: 2.25(min) 2.45(typ) 2.65(max)
78
Level detection voltage: 2.15(min) 2.35(typ) 2.55(max)
Reset release voltage: 2.25(min) 2.45(typ) 2.65(max)
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#138
2
Supplementary Information
Summary
Error
Page
Display controller AC specification 101
Error
Display controller0 Timing (TTL mode)
Correct
Page
100
Display controller0 Timing (TTL mode)
tDC0CYC:
12.5ns (min)
Correct
ID
#187
tDC0CYC:
12.5ns (min) *1
20ns(min) *2
|tDC0D|:
- (Remarks)
|tDC0D|:
*3 (Remarks)
tDC0V:
- (Remarks)
tDC0V:
*1, *4 (Remarks)
Notes:
- ,,,,
Notes:
- ,,,,
− For *1, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC3 area.
− For *2, when used with DSP0_DATA* and DSP0_CTRL4-0 in VCC53 area.
− For *3, the value can be configured and adjusted.
− For *4, the value is defined as tDC0CYC - |tDC0D| and depends on adjustment of *3.
Display controller0 Timing (RSDS)
|tRSD|:
- (Remarks)
tSPV:
- (Remarks)
Display controller0 Timing (RSDS)
|tRSD|:
*1 (Remarks)
Notes:
- ,,,,
tSPV:
*2 (Remarks)
Video Capture
104
TCAP0CYC:
11.11ns (min)
103
tCAP0SU:
2ns (min)
Note of NC pins, LVDS pins, and
other no-used pin
105
-
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
Notes:
- ,,,,
− For *1, the value can be configured and adjusted.
− For *2, the value is defined as tDC0CYC - |tDC0D| and depends on adjustment of *1.
TCAP0CYC:
12.5ns (min)
#188
tCAP0SU:
4ns (min)
104
Note:
− All the corresponding ports of products which don't support FPD-Link should be
connected to GND.
AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx, VSS3_LVDS_Tx,
TxDOUTn+/-.
#143
3
Supplementary Information
Summary
FPD-Link timing chart
Error
Page
105
HyperBus AC specification
108-112
Error
-
16-1 (3 items)
CS↓ -> RDS↓ Chip select active to RDS valid (Low):
CS↑-> RDS(Hi-z) Chip select Inactive to RDS High-Z:
CS↑ -> CS↓ Chip select HIGH between operation:
Correct
Page
105, 106 Figure: LVDS AC characteristics
(Timing chart)
Correct
ID
#183
109-112 (Removed)
#173
16-2 (4 items)
CS↑ -> CS↓ Chip select HIGH between transaction:
CS↓ -> CS↑ Chip select maximum LOW time:
Read-Writer recovery time :
CK↓ -> CK↓(4th) Page open time :
16-3 (7 items)
Read Initial Access Time :
CS↑↓ -> CK↑ Chip select active to RDS valid (Low):
CS↑ -> RDS(Hi-Z) Chip select Inactive to RDS High-Z:
CK↑↓ -> DQ (Low Z) Clock to DQs Low Z:
CS↑ -> DQ (Hi-Z) Chip select Inactive to DQs High-Z:
CK↑↓ -> RDS↑↓ CK transition to RDS transition:
CS↑ -> CS↓ Chip select HIGH between Operation:
16-4 (8 items)
CK↓ -> CK↓(4th) Page open time:
CS↑ -> RWDS(Hi-Z) Chip select Inactive to RWDS High-Z:
CK↑↓ -> DQ (Low Z) Clock to DQs Low Z:
CS↑ -> DQ (Hi-Z) Chip select Inactive to DQs High-Z:
CK↑↓ -> RWDS↑↓ CK transition to RWDS transition:
CS↑ -> CS↓ Chip select HIGH between Transition:
CS↓ -> CS↑ Chip select maximum LOW time:
Read-Writer recovery time
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
4
Supplementary Information
Summary
HyperBus AC specification
Error
Page
108, 109 tCKCYC:
12.5ns(min)
Error
Correct
Page
109,110 tCKCYC:
12.5ns(min) (A)
10ns(min) (B)
tCSS:
3ns (min)
109
tCSH:
1.25ns (min)
tIS:
5.25ns (max) (A)
4ns (max) (B)
Notes;
- ,,,,
tCSH:
1ns (min)
tDMV:
0ns (min)
Notes;
- ,,,,
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
ID
#184
tCSS:
3.25ns (max) (A)
2ns (max) (B)
tIS:
1.25ns (min)
HyperBus AC specification
Correct
110
Notes;
- ,,,,
- (A): The value will be targeted by the product series with revision digit A.
- (B): The value will be targeted by the product series with revision digit B.
tDMV:
5.25ns (max) (A)
4ns (max) (B)
#185
Notes;
- ,,,,
- (A): The value will be targeted by the product series with revision digit A.
- (B): The value will be targeted by the product series with revision digit B.
5
Supplementary Information
Summary
HyperBus AC specification
Error
Page
110,111
Error
tRDSCYC:
12.5ns (min)
Correct
Page
111,112 tRDSCYC:
12.5ns (min) (A)
10ns (min) (B)
tDSS:
-0.8ns (min)
0.8ns (max)
15
-
Original document code: DS708-00003-0v03-E, Previous document code: DS708-00003-0v02-E
Rev. 1.0 May 20, 2015
Display output
10
Number of display outputs:
2 outputs simultaneously
Selectable from 2 x DRGB, 1 x RSDS, or 1 x LVDS (FPD-Link)
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#186
tDSH:
-4.2ns (min)
- (max)
Notes;
- ,,,,
Power domain reset
ID
tDSS:
-0.8ns (min)
- (max)
tDSH:
-0.8ns (min)
0.8ns (max)
Original document code: DS708-00003-0v02-E, Previous document code: DS708-00003-0v01-E
Rev. 2.0 May 20, 2015
Note for Basic Option
11
Notes;
- ,,,
Correct
Notes;
- ,,,,
- (A): The value will be targeted by the product series with revision digit A.
- (B): The value will be targeted by the product series with revision digit B.
11
Notes;
- ,,,
− The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic
clock. They are defined at the chapter of Clock Configuration.
#194
15
Power domain (PD):
#175
---See the platform manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), and
PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the
product series, and "0" is always read from the reset factor flags of them.
10
Number of display outputs:
Option
Maximum 2 outputs simultaneously
#210
6
Supplementary Information
Summary
Display output
Error
Page
11
Error
Revision B description
11
Note:
- ,,,
- The function digit A, B, C, and D supports Hyper SRAM. Its 3,
4, 5, and 6 doesn’t support Hyper
SRAM. Hyper Bus interface ch.2 on graphic sub system will be
embedded on product which is
specified with function digit 7and 8 after revision B. Revision A
only has ch.0 and 1 of Hyper Bus
interface.
12
Note:
- ,,,
- HyperBus Interface ch.1 of the function digit 3, 4, 5, and 6 support HyperRAM after
Revision B.
#267
CHIP ID information
12
-
12
Function digit: A, B, C, D
Revision B:
Chip ID: 0x10110000
JTAG ID: 0x100095CF
#140
Clock Supervisor output function
15
-
15
Clock Supervisor: See the platform manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and
internal circuit is implemented.)
#224
CR oscillation stabilization time
15
-
15
Embedded CR oscillation
See the platform manual in detail.
Stabilization time is as followings.
− 5us for 4MHz (Fast clock)
− 20us for 100kHz (Slow clock)
#259
MOST physical channel
19
MediaLB:
--MOST25 (512FS)
3 wires
Maximum 15ch is available. (1ch is occupied by the system)
19
MediaLB:
--MOST25 (512FS)
3 wires
Maximum 15ch is available.
#128
Pin assignment
IO type
23, 25
29
-
24, 27
31
(Figures are added)
(X0 and X1 symbol are added in fugure.)
#141
#253
Notes;
- ,,,,
- ,,,,
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
Correct
Correct
Page
12
Notes;
- ,,,,
- ,,,,
− Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital
RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and
DRGB. Display Output ch.1 is used for DRGB only.
ID
#211
7
Supplementary Information
Summary
Absolute Maximum Rating
8kB Backup RAM Current
Consumption
Error
Page
59,60
68
Error
IOL3,,, When setting is 5 mA*9
IOLAV3,,, When setting is 5 mA*9
ΣIOL2 50mA *7
ΣIOL3 250mA *8
IOH3,,, When setting is 5 mA*9
IOHAV3,,, When setting is 5 mA*9
ΣIOH2 -50mA *7
ΣIOH3 -250mA *8
Correct
Correct
Page
61,62
IOL3,,, When setting is 5 mA*6, *7, *8, *9
IOLAV3,,, When setting is 5 mA*6, *7, *8, *9
ΣIOL2 250mA *7
ΣIOL3 50mA *8
IOH3,,, When setting is 5 mA*6, *7, *8, *9
IOHAV3,,, When setting is 5 mA*6, *7, *8, *9
ΣIOH2 -250mA *7
ΣIOH3 -50mA *8
-
70
ID
#234
ICCT5:
345uA(typ),675uA(max):When shutting down 8kB Backup RAM.
450uA(typ),820uA(max):Power only supplies to Backup RAM and system controllers.
When using 8MHz crystal for main oscillator.
445uA(typ),795uA(max):When shutting down 8kB Backup RAM.
#206
ICCH5:
145uA(typ),425uA(max):When shutting down 8kB Backup RAM.
DC characterization of PSS
68
ICCT5: Timer mode
ICCH5: Stop mode
70
Notes:
- ,,,
Current consumption
68
Oscillator frequency range
71
Icc12 -(typ) 1700mA(max):CPU:160MHz, HPM:80MHz,
GDC:160MHz
Source oscillation clock frequency: X0, X1:
3.6MHz(min), 4.0MHz(max)
Notes:
,,,
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
ICCT5: PSS Timer mode Shutdown (PD6=OFF)
ICCH5: PSS Stop mode Shutdown
#214
Notes:
- ,,,
- The definition of timer mode and stop mode can be seen at the chapter of STATE
transition of S6J3200 hardware manual.
70
Icc12 900(typ) 1700mA(max):CPU:160MHz, HPM:80MHz, GDC:160MHz
#260
73
Source oscillation clock frequency: X0, X1:
3.6MHz(min), 16MHz(max)
#230
Notes:
,,,
− Enough evaluation and adjustment are recommended using oscillator on your system
board.
8
Supplementary Information
Summary
PLL/SSCG maximum frequency
Error
Page
73
Error
-
Correct
Correct
Page
75, 76
FSSCG0:480,800(400),640,640 MHz, SSCG0 output clock
FSSCG1:800(400),800(400), 800(400),800(400) MHz, SSCG1 output clock
FSSCG2:800(400),800(400), 800(400),640 MHz, SSCG2 output clock
FSSCG3:800,800,800,800 MHz, SSCG3 output clock
FPLL0:720,800,800,640 MHz, PLL0 output clock
FPLL1:800,800,800,640 MHz, PLL1 output clock
FPLL2:800(400),800(400),800(400),800 MHz, PLL2 output clock
FPLL3:480,480,480,480 MHz, PLL3 output clock
#208
Notes:
- ,,,,
− The frequency described in () is not maximum value but recommended configuration
value.
Note:
- ,,,
- ,,,
− The configurable minimum frequency of PLLn and SSCGn output is 400MHz.
Minimum PLL/SSCG frequency
74
Note:
- ,,,
- ,,,
76
CAN clock frequency
"Unused" clock configuration
74
74
Notes:
,,,
,,,
76
76
Output short circuit current
AC spec of DDRHSSPI
104
107,108
Output short circuit current IOS:
[SDR mode]
toddata: 6.5ns (max)
tohdata: 3.5ns (min)
todsel: 5.5ns (max)
tohsel: 4.5ns (min)
106
(Removed)
109, 110 [SDR mode]
toddata: tcyc/2 + 2ns (max)
tohdata: 2.0ns (min)
todsel: -12.0ns + (SS2CD+0.5)*tcyc ns (min)
tohsel: 3.5ns (min)
[DDR mode]
toddata: 6.5ns (max)
todsel: 7.0ns (max)
ID
#219
FCLK_CAN 40MHz(Max)
Notes:
,,,
,,,
- "Unused" means a clock source which doesn’t have any supply destinations. Configure
it as disable with performing at the lower clock frequency than the described maximum.
#222
#229
#203
#164
[DDR mode]
toddata: tcyc/4 + 1.5ns (max)
todsel: -15.75ns + (SS2CD+0.5)*tcyc ns (min)
Notes:
− This is target spec.
− SS2CD [1:0] should be configured as 01, 10, or 11.
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
9
Supplementary Information
Summary
SDR/DDR (HSSPI) remark
Error
Page
107,108
ADC trigger input
119
Error
Remark:
tcyc -3.5ns
tcyc -4.5ns
tcyc/2-1.5ns
tcyc -3.0ns
Correct
ID
#232
121
A/D trigger input time:ADTRG
4tCLK_LCP1A ns (min) 4tCLK_LCP1A ≥ 100ns
100 ns (min) 4tCLK_LCP1A < 100ns
#231
ADC resumption time
119
Original document code: DS708-00003-0v04-E, Previous document code: DS708-00003-0v03-E
Rev. 1.0 June 30, 2015
FPD-Link port definition
45
-
121
Resumption time: 1us(max)
#239
60-61
TxCLK-
LVDS clock output pin: Described as TXOUT4M in FPD-Link Converter
TxCLK+
LVDS clock output pin: Described as TXOUT4P in FPD-Link Converter
TxDOUT0-
LVDS data output pin: Described as TXOUT0M in FPD-Link Converter
TxDOUT0+
LVDS data output pin: Described as TXOUT0P in FPD-Link Converter
TxDOUT1-
LVDS data output pin: Described as TXOUT1M in FPD-Link Converter
TxDOUT1+
LVDS data output pin: Described as TXOUT1P in FPD-Link Converter
TxDOUT2-
LVDS data output pin: Described as TXOUT2M in FPD-Link Converter
TxDOUT2+
LVDS data output pin: Described as TXOUT2P in FPD-Link Converter
TxDOUT3-
LVDS data output pin: Described as TXOUT3M in FPD-Link Converter
TxDOUT3+
LVDS data output pin: Described as TXOUT3P in FPD-Link Converter
#146
Non support port
25, 27,
28, 29,
32, 34,
35, 36
(Added the Note for non-supported pin condition on PCB)
92
VCC3_LVDS_TX: 56mA(max)
AVCC3_LVDS_PLL: 7mA(max)
Current consumption of FPD link
21, 23
70
-
Correct
Page
109,110 (Delete)
-
VCC3_LVDS_Tx, AVCC3_LVDS_PLL: 70 mA(max)
#215
AVcc and AVRH description
58
(AVCC0, AVCC1, AVRH0, and AVRH1)
73
(AVCC,AVRH)
TEQFP256 support
11
Pin count N:320
12
Pin count M:256
TEQFP256 support
13, 14
BGA320
15, 16
TEQFP256
Notes:
- ,,,
- BGA is a package option under planning.
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#246
#250
#272
Notes:
- ,,,
- TEQFP-256 is a package option under planning.
#273
10
Supplementary Information
Summary
TEQFP256 support
TEQFP256 support
Error
Page
17
19
Error
A/D Converter:
50 channels of analog input for TEQFP216
,,,
24 channels of them are shared with the SMC for
TEQFP216/208
Correct
Correct
Page
19
A/D Converter:
50 channels of analog input for TEQFP256 and TEQPF216
,,,
24 channels of them are shared with the SMC for TEQFP256/216/208
LCD Controller:
TEQFP216 : 4com x 32seg
TEQFP208 : 4com x 30seg
,,,
21
20, 24
-
23, 38
(TEQFP256 assignment is added.)
Chip ID
12
Revision:B, Chip ID:0x10100010
14
Revision:B, Chip ID:Revision:C and D, Chip ID:0x10100100
64, 65
Operating temperature
TA: -40(min), +105(max)
80, 81
#274
LCD Controller:
TEQFP256 : 4com x 32seg
TEQFP216 : 4com x 32seg
TEQFP208 : 4com x 30seg
,,,
TEQFP256 support
Case Temperature issue
ID
#275
#276
#278
Operating temperature
TA: -40(min), +105(max)
TC: -40(min), +144(max)
Notes:
− Both rating of TA and TC should simultaneously be satisfied as maximum operation
temperature.
− The following condition should be satisfied in order to facilitate heat dissipation.
1. 4 or more layers PCB should be used.
#283
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should
be 1.6 mm or more. (JEDEC standard)
3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with
residual copper rate 90% or more. The layer can be used for system ground.
4. 35~50% of the die stage area which is exposed at back surface of package should be
soldered to a part of 1st layer.
5. The part of 1st layer should be connected to the dedicated heat radiation layer with
more than 10 thermal via holes.
Main clock frequency
Revision description
CPU Clock Maximum
15
11
11
Main and sub oscillator is available.
− A wide range of 3.6 - 4MHz is available for main oscillator
17
-
12
200MHz (CPU Clock of function digit A, B, C, and D)
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
13
Main and sub oscillator is available.
− A wide range of 3.6 - 16MHz is available for main oscillator
#311
(Inside Figure 2-1: Option and Part Number)
C: Support MCAN 3.0.1.
D: Support MCAN 3.2.
#313
160MHz (CPU Clock of function digit A, B, C, and D)
#314
11
Supplementary Information
Summary
Maximum gap between package
and board
Power dissipation and Operation
temperature
Error
Page
24
62
Error
-
-
Correct
Correct
Page
39
Note:
− Same size is specified for MIN, NOM, MAX, then it should be regarded as maximum
size.
77, 78
ID
#315
Power dissipation and Operation temperature Case 1,
PD - 3300 mW,
TA -40 +97 degC, Both should be satisfied.
TC -40 +144 degC,
Power dissipation and Operation temperature Case 2,
PD - 3150 mW,
TA -40 +100 degC, Both should be satisfied.
TC -40 +144 degC,
Power dissipation and Operation temperature Case 3,
PD - 3000 mW
TA -40 +102 degC, Both should be satisfied.
TC -40 +144 degC,
Power dissipation and Operation temperature Case 4,
PD - 2900 mW,
TA -40 +105 degC, Both should be satisfied.
TC -40 +144 degC,
#317
Power dissipation and Operation temperature Case 5,
PD - 2800 mW,
TA -40 +105 degC, Both should be satisfied.
TC -40 +144 degC,
System Thermal Resistance,
Theta j-a - 16 degC/W,
The minimum value depends on the system specification of heat radiation. The described
value is estimated under the condition which is specified at Operation Assurance
Condition.
Package Thermal Resistance,
Theta j-c - 7.5 degC/W,
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
12
Supplementary Information
Summary
HyperBus GPO Remark
Error
Page
18
Error
HyperBus
,,,
Correct
Correct
Page
21
HyperBus
,,,
GPO signal can only be used for "Internal Control example by GPO" in this product, that
is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System.
ID
#345
Chip Select Output
11
-
13
(Part Number is added to show Chip Select Output of MFS)
Revision B description
12
Notes:
,,,
- SCL4, 10, 12 and SDA4, 10, 12 of I2C is not supported yet,
and will be enhanced after Revision B.
13
Notes:
,,,
- Multi-function serial interface of the function digit 3, 4, 5, 6, 7, and 8 support SCL4, 10,
12 and SDA4, 10, 12 of I2C after Revision D.
#349
-
18
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,
- Lock: 0x112ABB56
- Unlock: 0xACCABB56
#351
MPU lock and unlock value
Flash Access Speed
Oscillator error
16
17
73
1-wait-cycle with 80-160MHz.
2-wait-cycle with 160-240MHz.
− The error of source oscillator frequency must be smaller than
300ppm.
19
97
#346
0-wait-cycle: 80MHz or less.
1-wait-cycle: 160MHz or less.
2-wait-cycle: more than 160MHz.
The maximum frequency should be referred in datasheet.
#357
− The error of source oscillator frequency must be smaller than 3000ppm.
#360
Input leakage current,Pull-up
resistor,Pull-down resistor and
Input capacitance for P4_25 to
P4_31
69
Input leakage current:IIL:P2_16, 17, 19, 22, 24 to 31, P3_00 to 89
31, P4_00 to 12, P6_02 to 31
Input capacitance:CIN1:P0_00 to 31, P1_00 to 09, P2_16, 17,
19, 22, 24 to 31, P3_00 to 20, P5_21, 22, 27 to 31, P6_00 to 08,
17 to 26
Input leakage current:IIL:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to
31, P5_00 to 20, P6_02 to 31
Input capacitance:P0_00 to 31, P1_00 to 09, P2_16, 17, 19, 22, 24 to 31, P3_00 to 20,
#363
P4_25 to 31, P5_00 to 20, P5_21, 22, 27 to 31, P6_00 to 08, 17 to 26
CLK_HPM Frequency
16
1 wait cycle is necessary to read at over 180MHz (target).
See the platform manual in detail.
1 wait cycle is necessary for RAM read at over 160MHz.
No need to insert wait cycles for RAM write.
nSRST description
Hardware flow control
15
18
18
− INITX
- SRSTX
- nSTRST
17
Multi-functional Serial (MFS):,,,
20
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#366
− INITX
− SRSTX (and nSRST pin)
#367
Multi-functional Serial (MFS):CTS/RTS is not mounted (hardware flow control is not
supported for this series.)
#373
13
Supplementary Information
Summary
Error
Page
Pin assignment and pin list should 20
be separately instead of the red
characters
DDR-HSSPI DDR Mode
Oscillator Error Issue
Input Pulse Width
TYPO in 216 pin assign
CHIP ID
110
76
120
21,22
12
Error
-
Correct
Correct
Page
24-37
(The figure of pin assignment are added)
ID
#374
Note:
,,,
- SS2CD [1:0] should be configured as 01, 10, or 10.
140
Notes:
− *1: Target maximum clock frequencies when CPU clock =
240MHz
- ,,,
100
Port Noise Filter:
Width for input removal: All GPIO: 25ns(max)
*: Input pulse width less than at least 25nm is removed when
Port noise filter is enabled.
151
P0_26 0
P0_27 0
P0_28 0
24-30
-
14
-
#376
Notes:
− *1: Target maximum clock frequencies when CPU clock = 240MHz
- 232MHz or less is available for SSCG Down Spread.
- 240MHz or less is available for PLL.
- ,,,
#380
Port Noise Filter:
Width for input removal: All GPIO: 67ns(max)
*: Input pulse width less than at least Typ 25ns to Max 67ns is removed when Port noise
filter is enabled.
*: Input pulse width 100ns or more is recommended to be effective.
#382
("0"s are removed)
P0_26
P0_27
P0_28
#384
Function Digit: 3,4,5,6,7,8
E and F:
Chip ID: 0x10100101, JTAG ID: 0x1000C5CF
--Function Digit: A,B,C,D
E and F:
Chip ID: 0x10110001, JTAG ID: 0x100095CF
#409
RVD Detection/Release Voltage
99
DDH-HSSPI AC Specification
109, 110 (Old value)
138, 140 (New values are added in the table)
HyperBus AC Specification
111-114
(Old value)
142-145 (New values are added in the table)
Power Supply Current
72
-
92-96
(New table is added, and the value of Icc12, Icc5, Icct5, and Icch5 are improved.)
Unsupport Partial Wakeup
15
Power Domain (PD): ,,,
17
Power Domain (PD): ,,,This series doesn't support partial wakeup for PD6.
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
124
Notes:
,,,
- SS2CD [1:0] should be configured as 01, 10, or 11.
(LVDL0 spec is added.)
#410
#411
#412
#413
#416
14
Supplementary Information
Summary
Vcc12 power supply limit
Error
Page
64
Error
VSS12:
1.15
1.1*1
Correct
Page
80
VSS12:
1.15*1
1.1*1
Correct
ID
#417
Notes:
− *1. The value will be for the product series with revision digit B.
- ,,,
FPD-Link DC Spec
106
VOD:
270, 300, 340 mV
310, 350, 400 mV
360, 400, 450 mV
Notes:
- *1. The value is only applied to the product series with revision digit A.
- ,,,
135
VCM:
1.120, 1.150, 1.175 V
1.170, 1.200, 1.225 V
1.220, 1.250, 1.280 V
Land Pattern for Thermal Via
65
Power On Sequence
Recommendation
64
Internal Clock Timing for
FSSCG0-3 and FPLL0-3
75, 76
-
FSSCG0 480 800(400) 640 640
FSSCG1 800(400) 800(400) 800(400) 800(400)
FSSCG2 800(400) 800(400) 800(400) 640
FSSCG3 800 800 800 800
FPLL0 720 800 800 640
FPLL1 800 800 800 640
FPLL2 800(400) 800(400) 800(400) 800
FPLL3 480 480 480 480
Notes:
,,,
− The frequency described in () is not maximum value but
recommended configuration value.
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
VOD:
210, 300, 390 mV
250, 350, 450 mV
295, 400, 505 mV
#418
VCM:
1.075, 1.200, 1.325 V
1.125, 1.250, 1.375 V
81-84
(Land pattern of thermal via hole is added.)
80
Notes:
-,,,
− Power supply sequence is recommended as VCC5 -> [DVCC or AVCC5 or VCC3 or
AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL or VCC3_LVDS_TX]
99, 100
#429
#431
FSSCG0 232(480) 200(800) 160(640) 160(640)
FSSCG1 200(800) 200(800) 200(800) 200(800)
FSSCG2 200(800) 200(800) 200(800) 160(640)
FSSCG3 200(800) 200(800) 200(800) 200(800)
FPLL0 240(720) 200(800) 200(800) 160(640)
FPLL1 400(800) 400(800) 400(800) 320(640)
FPLL2 200(800) 200(800) 200(800) 200(800)
FPLL3 240(480) 240(480) 240(480) 240(480)
#432
Notes:
,,,
− The frequency described in () is maximum output frequency of SSCG PLL / PLL
multiplier circuit.
15
Supplementary Information
Summary
VIH spec(TTL level) for JTAGpins
VIH of Media LB port
Error
Page
65
Error
VIH9: 2.0(Min)
Correct
Page
85
VIH9: 2.3(Min)
Correct
ID
#437
65
VIH12: 1.7(V)
85
VIH12: 1.8(V)
Original document code: DS708-00003-1v0-E, Previous document code: DS708-00003-0v04-E
Rev. 1.0 September 30, 2015
Resource clock frequency
9
Resource clock frequency : 40MHz (Max)
8
Resource clock frequency : Option : See AC specification on the datasheet
#465
Description for up/down counter
10, 20
Up/Down Counter
9, 19
Quad Position & Revolution Counter
(Up/Down Counter)
#530
Display output
13
Notes:
,,,
- Display Output ch.0 is used for RSDS and FPD-LINK (LVDS)
as well as DRGB (Digital RGB). The
ch.0 of the product which doesn’t support FPD-LINK is used for
RSDS and DRGB. Display Output
ch.1 is used for DRGB only.
12
Notes:
#452
,,,
- Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital
RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and
DRGB.
- Display Output ch.1 is used for FPD-LINK (LVDS) and DRGB (Digital RGB). The ch.1 of
the product which doesn't support FPD-LINK is used for DRGB only.
Relationship SYSC0_SYSIDR
and ChipID
14
ID is specified for each function digit and revision which is
defined at Figure 2-1.
13
ID is specified for each function digit and revision which is defined at Figure 2-1. Chip ID
can be read from SYSC0_SYSIDR.
For SYSC0_SYSIDR, see the TraveoTM Platform
hardware manual.
#471
Typo in trace buffer size
17
4kB Embedded Trace Buffer
16
4k Word Embedded Trace Buffer
#528
WUCR function
20
MFS:
,,,
19
MFS:
,,,
WUCR function is not supported for this product.
#284
CS port availability
20
MFS:Chip select function of CSIO is not supported yet and will
be enhanced with next revision.
19
MFS:The availability of chip select function can be seen at Function Digit Table.
#448
Not support CS input
20
-
19
Chip Select Input is not supported.
#467
Usage for I2S ch1
20
− I2S0 only supports the output of sound sources.
− I2S1 supports both the input and the output.
− ,,,
19
- I2S0 can output sound sources which are processed by Sound System.
- I2S1 can input sound sources which are processed by Sound System.
− ,,,
See the "Sound System Configuration" of S6J3200 hardware
manual in detail.
#529
Imporvement of descritption for
I2C
20
Note all pins do not necessarily support I2C, but the pins which
have the dedicated I/O characteristics only support it.
19
Note - Not all pins support I2C. Only pins which have the I2C I/O characteristics support
it.
#531
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#438
16
Supplementary Information
Summary
Reference for DDR High Speed
SPI & CAN-FD
Error
Page
20
Error
-
Correct
Correct
Page
19, 20
(Added "See the platform manual in detail" for CAN-FD & DDR High Speed SPI)
ID
#532
Reference information for GPO
21
GPO signal can only be used for "Internal Control example by
GPO" in this product, that is, it can select
using HyperBus of PF or using HyperBus of Graphic Sub
System.
20
GPO signal can only be used for "Internal Control example by GPO" in this product, that
is, it can select
using HyperBus of PF or using HyperBus of Graphic Sub System. See the "HyperBus
Interface Port Configuration" of S6J3200 hardware manual in detail.
#533
Delete unnecessary description
for Graphic subsystem
21
Order replacement of RGB pins.
20
(Deleted)
#534
Delete Ethernet restriction for
product
22
(Delete)
#516
Improvement of description for
Pin Assignment
23
Direct Memory Access Interface, MAC Filtering Block -VLAN tag, 21
IEEE 1588 and IEEE 802.1AS Support, MAC PFC Priority Based
Pause Frame Support, and 802.1Qav Support – Credit Based
Shaping
Alphabets with pin numbers are signs specify I/O circuit type.
22
The characters next to the pin number in the pin assignment drawing specify the I/O
circuit type.
(figure added)
#535
Regarding "red" character in Pin
Assignment
23-38
The pins which are described in "red" character are not
supported, and will be enhanced with next revision
products.
23-35
The pins which are described in "red" character are not supported product with revision A #524
and C.
Note for Input voltage and Max
clamp current
76
Maximum clamp current:*A (Remarks)
Total maximum clamp current:*A (Remarks)
75
Maximum clamp current:*12, *A (Remarks)
Total maximum clamp current:*12, *A (Remarks)
#503
TYPO in Absolute Maximum
Rating
76
Input voltage:VI2:VCC5+0.3(Max)
,,,
Input voltage:VIE:VCC5+0.3(Max)
75
Input voltage:VI2:DVCC+0.3(Max)
,,,
Input voltage:VIE:VCC53+0.3(Max)
#518
Note for Input voltage and Max
clamp current
78
-
77
*12: VI or VO should never exceed the specified ratings. However, if the maximum
current to/from an input is limited by a suitable external resistor, the ICLAMP rating
supersedes the VI rating.
#470
Power supply sequence
80
Power supply sequence is recommended as VCC5 -> [DVCC or 79
AVCC5 or VCC3 or AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL
or VCC3_LVDS_TX]
Power supply sequence is recommended as VCC5 -> [DVCC or AVCC5 or VCC3 or
AVCC3] -> VCC12 -> [AVCC3_LVDS_PLL or VCC3_LVDS_TX].
Note that power supplies inside "[]" can be turned on in arbitrary order.
#474
VIH/VIL characteristics for I/O of
DVCC
85, 86
-
84, 85
(Added the "*1" for note of some characteristics and the description)
#439
DS 8.3.1 Port Function
Characteristics
86
VIL10(Max) 0.3xVcc5
85
VIL10(Max) 0.3xVcc3
#453
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
17
Supplementary Information
Summary
Error
Page
87
VOH16:VCC3-0.5(Min)
Correct
Page
86
VOH16:2.0(Min)
VOH/L4, VOH/L5, VOH/L6
characteristics for I/O of VCC5
and DVCC
87, 88
-
86, 87
(Added the "*1" for note of some characteristics and the description)
#442
VOL4, VOL5 characteristics
88
VOL4:0.55(Max)
VOL5:0.55(Max)
87
VOL4:0.4(Max)
VOL5:0.4(Max)
#443
Pull-up/Pull-down resistor for
5V/3V pins (P4_25 to 31, P5_00
to 20)
89
PUP2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12,
88
P6_02 to 31:Pull-up registor selected
,,,
Pdown2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12,
P6_02 to 31:Pull-down registor selected
PUP2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to 20,
P6_02 to 31:Pull-up registor selected Vcc53 = 4.5V to 5.5V
,,,
Pdown2:P2_16, 17, 19, 22, 24 to 31, P3_00 to 31, P4_00 to 12, P4_25 to 31, P5_00 to
20, P6_02 to 31:Pull-down registor selected Vcc53 = 4.5V to 5.5V
#430
Typo in condition of IIL
characterisistics for 3V I/O
89
VCC3=3.3 V
VSS < VI < VCC3
88
VCC3=3.6 V
VSS < VI < VCC3
#444
Typo in symbol for input
capacitance
89
CIN1:P3_21 to 31, P4_00 to 12, P6_09 to 16
88
CIN2:P3_21 to 31, P4_00 to 12, P6_09 to 16
#445
Pull-up/Pull-down resistor for
5V/3V pins
89
-
88
Pull-up resistor:RUP2:P4_25 to 31, P5_00 to 20:Pull-up resistor
#501
Selected Vcc53 = 3.0V to 3.6V:40(Min):100(Typ):200(Max):kΩ:5V/3V pins
,,,
Pull-down resistor:Rdown1:P4_25 to 31,P5_00 to 20:Pull-down resistor Selected Vcc53 =
3.0V to 3.6V:40(Min):100(Typ):200(Max):kΩ:5V/3V pins
FPD-Link DC Spec
92
-
91
Note: - ,,, - The current consumption at Vcc3_LVDS_Tx is specified under RL=100ohm,
CL=5pF, f=50MHz, and 0/1 alternation pattern output.
#433
DS 8.3.2.1 Run Mode
93
(Icc5 is only defined)
92
(Current values related CPU operation should be specified as Icc12)
#454
Maximu clock frequency of
SSCG3
99
FSSCG3:200(800), 200(800), 200(800), 200(800)
98
FSSCG3:400(800), 400(800), 400(800), 400(800)
#458
VOH characteristic for I/O of
MediaLB
Error
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
Correct
ID
#441
18
Supplementary Information
Summary
Delete "Taget spec"
Error
Page
99, 100, 131-134,
138,
140,142150, 159
Error
Correct
Page
98, 99, (Deleted explanation for target spec)
100,
131-134,
138,
140,
142-150,
159
Correct
ID
#504
SSCG Max Frequency
100
Notes:
− *1: Target maximum clock frequencies when CPU clock =
240MHz
- 232MHz or less is available for SSCG Down Spread.
- 240MHz or less is available for PLL.
99
Notes:
− *1: Target maximum clock frequencies when CPU clock = 240MHz
- 232MHz or less is available for SSCG Down Spered on/off.
- 240MHz or less is available for PLL.
Internal Clock Timing
100
Notes:
,,,
- *3: Target maximum clock frequencies when CPU clock =
160MHz
- From *1 to *3, they are not applied to the product series with
function digit A, B, C, and D.
- *4: Target maximum clock frequencies when CPU clock =
160MHz for the product series with the
function digit A, B, C, and D.
100
Notes:
#406
,,,
- *3: Target maximum clock frequencies when CPU clock = 160MHz. This is also a
combination of maximum clock frequencies for TC FLASH Programming or Erasing.
- From *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, and
8.
- *4: Target maximum clock frequencies when CPU clock = 160MHz for the product
series with the function digit A, B, C, and D. This is also a combination of maximum clock
frequencies for TC FLASH Programming or Erasing.
Level detection hysteresis width
105
Level detection hysteresis width
104
(Delete)
#457
Default Value of LVDL1
126
LVDL1V=01(Default),,,
LVDL1V=10
125
LVDL1V=01,,,
LVDL1V=10(Default)
#502
Display AC specification
131
-
131
( - Updated the min/max value in |tDC0D| and tDC0V. - Added the new definition for
#347
DSP0_CTRL11-0 of tDC0V. - Update the note for *2 and delete the note for *4. - Updated
figure for definition of tDC0V.)
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
#487
19
Supplementary Information
Summary
Display AC specification
Error
Page
132
Error
-
Display AC specification
133
-
133
( - Updated the min/max value for tDC1D, tDC1V and delete the remarks for tDC1V. Updated figure for definition of tDC1V.)
#505
FPD-Link Output Clock
Frequency
Add "TxCLK+/-" in case of don't
support FPD-Link
135
Output clock frequency: 1MHz(min),50MHz(max)
135
Output clock frequency: - (min),50MHz(max)
#522
135
Note: − All the corresponding ports of products which don't
support FPD-Link should be connected to GND.
AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx,
VSS3_LVDS_Tx, TxDOUTn+/-.
135
Note: − All the corresponding ports of products which don't support FPD-Link should be
connected to GND. AVCC3_LVDS_PLL, AVSS3_LVDS_PLL, VCC3_LVDS_Tx,
VSS3_LVDS_Tx, TxDOUTn+/-, TxCLK+/-.
#525
DDRHSSPI (SDR) clock cycle for 138
Quad Page Program
-
138
HSSPI clock cycle:20(Min):when Quad Page Program
#484
HyperBus AC specification
144
RDS↑↓> DQ (valid) Setup time ,,,
RDS↑↓> DQ (invalid)Hold time
144
RDS↑↓> DQ Setup time ,,,
RDS↑↓> DQ Hold time
#519
ADC Software Trimming
153
-
153
8.5.4 Calibration Condition
Calibration Condition A/D Converter should be calibrated under the following condition.
AVCC=5.0V
AVRH=5.0V
Ta=25℃
system clock frequency (CLK_LCP1A)= 10MHz
See A/D Converter Calibration on the S6J3200 hardware manual.
#358
September 30, 2015, S6J3200_DS708-00003-1v0-E-SI1
Correct
Correct
Page
132
( - Updated the min/max value for |tRSD|, tRSV, tSPD, tSPV. - Delete the note for *2. Updated figure for definition of tSPV and tRSV.)
ID
#506
20