S6J3200 series
32bit Microcontorller
Spansion Traveo Family
Hardware Manual
Supplementary Information
Note: This sheet shows a change trace of description in hardware manual. All the changes between previous and current document edition are described in this sheet.
Following "ID" is a number which is owned by every change. A change which is applied to other documents of same family should have a same ID.
Summary
Rev. 1.0 October 14, 2014
Error
Page
Error
Correct
Page
Correct
ID
Initial release
Original document code: MN708-00005-2v0-E, Previous document code: MN708-00005-1v0-E
Rev. 2.0 May 20, 2015
Display output
25
Number of display outputs:
2 outputs simultaneously
Selectable from 2 x DRGB, 1 x RSDS, or 1 x LVDS (FPD-Link)
29
Number of display outputs:
Option
Maximum 2 outputs simultaneously
#210
Display output
27
Notes;
- ,,,,
- ,,,,
32
Notes;
- ,,,,
- ,,,,
− Display Output ch.0 is used for RSDS and FPD-LINK (LVDS) as well as DRGB (Digital
RGB). The ch.0 of the product which doesn’t support FPD-LINK is used for RSDS and
DRGB. Display Output ch.1 is used for DRGB only.
#211
Revision B description
27
Note:
32
- ,,,
- The function digit A, B, C, and D supports Hyper SRAM. Its 3,
4, 5, and 6 doesn’t support Hyper SRAM. Hyper Bus interface
ch.2 on graphic sub system will be embedded on product which
is specified with function digit 7and 8 after revision B. Revision A
only has ch.0 and 1 of Hyper Bus interface.
Note:
- ,,,
- HyperBus Interface ch.1 of the function digit 3, 4, 5, and 6 support HyperRAM after
Revision B.
#267
TEQFP256 support
27
Pin count N:320
31
Pin count M:256
#272
Revision description
27
-
31
(Inside Figure 2-1: Option and Part Number)
C: Support MCAN 3.0.1.
D: Support MCAN 3.2.
#313
Chip Select Output
27
-
32
(Part Number is added to show Chip Select Output of MFS)
#346
Revision B description
27
Notes:
,,,
- SCL4, 10, 12 and SDA4, 10, 12 of I2C is not supported yet,
and will be enhanced after Revision B.
32
Notes:
,,,
- Multi-function serial interface of the function digit 3, 4, 5, 6, 7, and 8 support SCL4, 10,
12 and SDA4, 10, 12 of I2C after Revision D.
#349
Publication Number S6J3200_MN708-00005-3v0-E-SI
Revision 1
Issue Date June 30, 2015
Supplementary Information
Summary
Note for Basic Option
Error
Page
27
CHIP ID information
Error
Notes;
- ,,,
Correct
Correct
Page
32
Notes;
- ,,,
− The CLK_CPU is assigned for CPU clock. The CLK_CD3A0 is assigned for Graphic
clock. They are defined at the chapter of Clock Configuration.
ID
28
-
33
Function digit: A, B, C, D
Revision B:
Chip ID: 0x10110000
JTAG ID: 0x100095CF
#140
Chip ID
28
Revision:B, Chip ID:0x10100010
33
Revision:B, Chip ID:Revision:C and D, Chip ID:0x10100100
#278
TEQFP256 support
30
Notes:
- ,,,
35
TEQFP256
#273
#194
Notes:
- ,,,
- TEQFP-256 is a package option under planning.
CR oscillation stabilization time
33
-
39
Embedded CR oscillation
See the platform manual in detail.
Stabilization time is as followings.
− 5us for 4MHz (Fast clock)
− 20us for 100kHz (Slow clock)
#259
Main clock frequency
33
Main and sub oscillator is available.
- A wide range of 3.6 - 4MHz is available for main oscillator
39
Main and sub oscillator is available.
− A wide range of 3.6 - 16MHz is available for main oscillator
#311
Power domain reset
33
-
39
Power domain (PD):
#175
---See the platform manual and chapter STATE TRANSITION in detail.
The product series supports the power off control of PD1, PD2 (including PD3 and 5), and
PD6.
The power domain resets of PD3 and PD5 included in PD2 are not supported in the
product series, and "0" is always read from the reset factor flags of them.
Clock Supervisor output function
33
-
39
Clock Supervisor: See the platform manual in detail.
This product series doesn’t support clock supervisor output port. (Related register and
internal circuit is implemented.)
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
#224
2
Supplementary Information
Summary
Watchdog Counter Monitor
Error
Page
33
Error
Hardware watchdog:
Hardware watchdog function stops during PSS mode.
,,,
Correct
Correct
Page
39
Hardware watchdog:
,,,
Hardware watchdog function stops during PSS mode. In the related register of
HWDG_CFG, the bit ALLOWSTOPCLK is always read as 1
(HWDG_CFG.ALLOWSTOPCLK=1).
The product series doesn’t support Watchdog Counter Monitor Output port. (Related
register and internal circuit is implemented.)
ID
#225
Software watchdog:
See the platform manual in detail.
The product series doesn’t support Watchdog Counter Monitor Output port. (Related
register and internal circuit is implemented.)
MPU lock and unlock value
34
-
40
To configure Lock or Unlock for both MPUXn_UNLOCK and MPUHn_UNLOCK,
- Lock: 0x112ABB56
- Unlock: 0xACCABB56
#351
TEQFP256 support
35
A/D Converter:
50 channels of analog input for TEQFP216
,,,
24 channels of them are shared with the SMC for
TEQFP216/208
41
A/D Converter:
50 channels of analog input for TEQFP256 and TEQPF216
,,,
24 channels of them are shared with the SMC for TEQFP256/216/208
#274
TEQFP256 support
37
TEQFP216 : 4com x 32seg
TEQFP208 : 4com x 30seg
,,,
43
TEQFP256 : 4com x 32seg
TEQFP216 : 4com x 32seg
TEQFP208 : 4com x 30seg
,,,
#275
HyperBus GPO Remark
37
HyperBus
,,,
42
HyperBus
,,,
GPO signal can only be used for "Internal Control example by GPO" in this product, that
is, it can select using HyperBus of PF or using HyperBus of Graphic Sub System.
#345
MOST physical channel
37
MediaLB:
--MOST25 (512FS)
3 wires
Maximum 15ch is available. (1ch is occupied by the system)
43
MediaLB:
--MOST25 (512FS)
3 wires
Maximum 15ch is available.
#128
The restriction for Ethernet
38
-
43, 44
2.1. Ethernet
#340
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
3
Supplementary Information
Summary
Error
Page
40
-
PD5 register configuration
40
-
48
SYSC0_RUNPDCFGR.PD5_xEN
SYSC0_PLLPDCFGR.PD5_xEN
SYSC0_APPPDCFGR.PD5_xEN
SYSC0_STSPDCFGR.PD5_xEN
--------------------------Configure them as same as PD2 registers because PD5 is a sub power domain of PD2.
#177
Register initial value
40
-
46, 47
3.3.
Register initial value
(And its content)
#168
Blockdiagram
42
-
50
(HyperBus, DDRHSSIP and line is added.)
#131
CLK configuration
47
Audio DAC:
CLK_CD4:PLL2:
See TraveoTM Platform hardware manual.
55
Audio DAC:
CLK_CD4:PLL2:
See TraveoTM Platform hardware manual.
It is described as "CLKDACI" in the chapter or Audio DAC.
#127
DDRHSSPIn_PCC03:SS2CD[1:0] needs limitation for
Amber-P/Amber-P2/Amethyst
Error
Correct
Correct
Page
48
3.4. Restriction
(Table)
DDRHSSPI
DDRHSSPI Peripheral Communication Configuration Registers
(DDRHSSPIn_PCC0-3):
SS2CD[1:0] = 00 cannot be used. Configure delay as 01. 10, or 11.
ID
#147
CLK_CD5B0:PLL3:
See TraveoTM Platform hardware manual.
It is described as "CLKPI" in the chapter or Audio DAC.
Sound system clock
47
-
57
Notes:
- The configuration of the maximum clock frequency above should satisfy the values
specified in Datasheet.
- The frequency of CLK_CD5 and CLK_CD5A0 should satisfy the following conditions.
- CLK_CD5 = 240MHz or 120MHz.
- CLK_CD5A0 = 120MHz.
#135
Clock configuration
47
-
55
Registers of INDICATOR PWM and LCDE: CLK_SYSC0P: SSCG0
Registers of LCDC: CLK_LCP1A: PPL0 or SSCG0
#159
PLL/SSCG maximum frequency
47
-
56
Note:
− The frequency of PLLout (output of PLL/SSCG PLL multiplier circuit) should be
800MHz or less.
#165
Source clock list
47
-
56
(Source Clock - Local Clock List is added.)
#312
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
4
Supplementary Information
Summary
Area of SWDT (Traveo PF)
Error
Page
58
Base address map
58
Error
B030_8000 B03F_FFFF || SYSC2 || SWDT
Correct
Correct
Page
68
B030_8000 B03F_FFFF || SYSC1 || SWDT
ID
#161
-
68
#199
An address of a certain register can be specified as below.
− Base address
Look for the base address X of the function from the base address map below.
− Offset address
Look for the offset address Y of the register from the offset address list which is
described in the chapter of the function. Each function chapter has offset address list or
its information.
− Specify
The register address can be specified as X + Y.
PPU number
63
PPU No.
,,,
SMIX (Sound System): 301
Audio DAC (Sound System): PCM-PWM (Sound System): I2S0 (Sound System): ,,,
73, 74
PPU No.
,,,
SMIX (Sound System): 301
Audio DAC (Sound System): 301
PCM-PWM (Sound System): 301
I2S0 (Sound System): 301
#354
Notes:
- ,,,
- PPU number 301 is same for SMIX, Audio-DAC, PCM-PWM, and I2S0.
IRQ map
66
8: TCFLASH Single Bit Error
10: Work FLASH Single Bit Error
20: Work FLASH Write Completion
78
8: TCFLASH RDY, Hang up, Single Bit Error
10: Work FLASH Hang up
20: Work FLASH RDY, Write Enable Release, Single Bit Error
#308
IRQ map
66, 77
17 to 18: Reserved
429 to 430: Reserved
78, 84
17 to 19: Reserved
429 to 431: Reserved
#205
GDC interrupt
77
426
CAEI
427
BEI
84
426
BEI
427
CAEI
#189
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
5
Supplementary Information
Summary
NMI table revise
Error
Page
79
Error
14: DMAC MPU #1 protection violation IRC0_NMIPL3 :
NMIPL14 IRC0_NMIVA14
20: 2D Graphics Core_NMI[0] IRC0_NMIPL5 : NMIPL20
IRC0_NMIVA20
21: 2D Graphics Core_NMI[1] IRC0_NMIPL5 : NMIPL21
IRC0_NMIVA21
FPD-Link port definition
99
Correct
Correct
Page
86
14: Reserved, -, 20: Graphics subsystem Memory Protection
21: Graphics subsystem (VRAM) ECC Single Bit Error Detection
ID
#233
-
105, 106 TxCLK- LVDS clock output pin: Described as TXOUT4M in FPD-Link Converter
TxCLK+ LVDS clock output pin: Described as TXOUT4P in FPD-Link Converter
TxDOUT0- LVDS data output pin: Described as TXOUT0M in FPD-Link Converter
TxDOUT0+ LVDS data output pin: Described as TXOUT0P in FPD-Link Converter
TxDOUT1- LVDS data output pin: Described as TXOUT1M in FPD-Link Converter
TxDOUT1+ LVDS data output pin: Described as TXOUT1P in FPD-Link Converter
TxDOUT2- LVDS data output pin: Described as TXOUT2M in FPD-Link Converter
TxDOUT2+ LVDS data output pin: Described as TXOUT2P in FPD-Link Converter
TxDOUT3- LVDS data output pin: Described as TXOUT3M in FPD-Link Converter
TxDOUT3+ LVDS data output pin: Described as TXOUT3P in FPD-Link Converter
#146
Multiplexed I/O Port Configuration 111
-
117
(Block Diagram added)
#339
Port Configuration
112
The resource input configuration module (RIC) is a function to
select input from an external or output from another internal
resource as resource input.
118
The resource input configuration module (RIC) is a function to select input from an
external or output from another internal resource as resource input.
A resource which supports either a port input relocation or a resource inputs from the
other resource has its RIC_RESIN register to configure resource input configuration.
#261
POF/RIC definition
112, 203, MFSx_SCL, MFSx_SDA
204
118,
SCLx, SDAx
210, 211
External interrupt during port
disconnection
196
-
203
Note:
#223
− When both GPIO_PORTEN.GPORTEN and PPC_PCFGR.PIE are configured as 0, the
input signal is disconnected and external interrupt cannot be detected. During
disconnecting, I/O internally outputs "low" to internal logic, and if ELVR is configured as
low-level-detection, falling-edge-detection, or both-edge-detection it will be detected as
external interrupt with EIRR=1.
− "Set 0" (Set 1) means that "0" ("1") is inputted.
− OCUx_MODn is described as MODn pin in Traveo Platform manual.
The port output function configuration (POF) is a function to
select a function to output to a port.
204
The port output function configuration (POF) is a function to select a function to output to #262
a port.
A resource which supports a port output relocation has its PPC_PCFGR.POF to configure
resource output.
Port Output function Configuration 197
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
#160
6
Supplementary Information
Summary
SCLK port name
Error
Page
198
Error
PPC_PCFGR030(0x003C): G_SCLK
Correct
Page
205
PPC_PCFGR030(0x003C): G_SCLK0
P2-19 (Input only)
199
PPC_PCFGR219(0x00A6) :P2_19: GPIO_PODR2:POD[18]
206
Chip Select Output
201, 202, 203, 204
208,
(CS functions are added in POF table)
209,
210, 211
#348
POF configuration
207
Notes:
− The hyphen indicates that setting is prohibited.
214
#148
RSDS port definition
208
-
216, 217 3.2.3 PIE (Port Input Enable) configuration
3.2.4 RSDS port definition
#154
Output Drive Capacity
213-215
PORT NO. Remarks
P0_26
P0_27
P4_10
P4_11 *2-2
P5_10
P5_11 *2-2
P5_18
P5_19
P4_30
P4_31
222-224 PORT NO. Remarks
P0_26 *2-2
P0_27 *2-2
P4_10 *2-2 only for Revision D
P4_11 *2-2 only for Revision D
P5_10 *2-2 only for Revision D
P5_11 *2-2 only for Revision D
P5_18 *2-2 only for Revision D
P5_19 *2-2 only for Revision D
P4_30 *2-2
P4_31 *2-2
#266
Multiple assign with POF
215
-
227
#163
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
Correct
ID
#221
PPC_PCFGR219(0x00A6) :P2_19: GPIO_PODR2:POD[19]
#201
Notes:
− The hyphen indicates that setting is prohibited. If setting the port will be operated as
input independent on the register value of the GPIO_DDR.
3.7 Function Port Group
7
Supplementary Information
Summary
Note on I2C port configuration
(No-spec change)
Error
Page
215
Error
− *1 When the PPC_PCFGR:POF[2:0] value setting is "2"(the
RSDS function setting),
If setting to "0" the value of the PPC_PCFGR:ODR[0], the drive
capacity will be 2mA.
If setting to "1" the value of PPC_PCFGR:ODR[0], The drive
capacity will be 4mA.
− *2-1 When the PPC_PCFGR:POF[2:0] value setting is
"4"(SDA or SCL function setting), regardless of the value of the
PPC_PCGR:ODR[1:0], the drive capacity will be "I2C".Then, the
port status is to be Pseudo Open Drain, and IOL is to be 3mA.
− *2-2 When the PPC_PCFGR:POF[2:0] value setting is
"4"(SDA or SCL function setting), the port status is to be Pseudo
Open Drain, and IOL is to be the configured value for ODR.
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
Correct
Correct
ID
Page
225
- *1 If PPC_PCFGR:POF[2:0] = "2"(the RSDS function setting) and PPC_PCFGR:ODR[0] #174
= "0", the drive capacity will be 2mA.
If PPC_PCFGR:POF[2:0] = "2"(the RSDS function setting) and PPC_PCFGR:ODR[0]
= "1", the drive capacity will be 4mA.
− *2-1 If the PPC_PCFGR:POF[2:0] is configured as SDA or SCL function, the pin is set
to "Pseudo Open Drain" and IOL is set to 3mA ("I2C" function) - independent of the
corresponding PPC_PCGR:ODR[1:0] setting.
− *2-2 If the PPC_PCFGR:POF[2:0] is configured as SDA or SCL function, the pin is set
to "Pseudo Open Drain". IOL is configured by the corresponding PPC_PCGR:ODR[1:0]
register.
8
Supplementary Information
Summary
Port status explanation
Error
Page
215
Error
-
Correct
Page
Port Status
226
Correct
ID
#226
Hi-z control
TraveoTM platform manual has description of System Special Setting Register
(SYSC0_SPECFGR).
The [bit23] PSSPADCTRL: PSS-time port configuring bit should be configured as below.
− 0: Do not perform Hi-z control.
− 1: Perform Hi-z control.
Notes:
− At RUN mode, if configured as Hi-z control, it doesn’t affect the port status immediately, but after
executing WFI instruction to update the profile registers, then it turns out Hi-z status during PSS
mode.
− As opposite control from PSS to RUN, the port status of Hi-z will automatically be released
without reconfiguration of SYSC0_SPECFGR.PSSPADCTRL = 0.
Port status hold during PSS mode
All of the GPIO except ports in VCC3 area can be kept the port status during PSS mode by System
Special Setting Register (SYSC0_SPECFGR).
The [bit31] to [bit24] HOLDIO_PDx: HOLD data latch bit should be configured as below.
− 0: Do not retain control.
− 1: Retain control.
Notes:
− During MCU RUN mode, I/O port status will be latched immediately after
SYSC0_SPECFGR.HOLDIO_PDx= 1 (Retain control) configured.
− After SYSC0_SPECFGR.HOLDIO_PDx= 1,the status of followings will be latched. Please note
that PID is not included, that is, input data cannot be latched.
− PPC_PCFGRijj POD, POE, PIL, PUE, PDE, ODR, NFE, and POF. (excluding PID: Input data
cannot be latched)
− RIC_RESINx.PORTSEL and RESSEL
− At turning from MCU PSS mode to RUN, the latched status will not be released automatically.
Configuration SYSC0_SPECFGR.HOLDIO_PDx = 0 should be necessary for releasing the status.
Port Configuration Procedure
216
-
230
5. Configuration Procedure
#247
Low voltage detection
229
Notes:
- ,,,
- ,,,
251
Notes:
- ,,,
- ,,,
− Internal Low-voltage detection works with generating Power On reset.
#242
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
9
Supplementary Information
Summary
Low voltage detection
configuration
Error
Page
230
Error
[Bit18:17] LVDL2V Extended internal low-voltage detection
voltage setting bits
Correct
Correct
Page
253
[Bit18:17] LVDL2V Extended internal low-voltage detection voltage setting bits
Note:
− Greater than 0x0 should be written because initial configuration of 0.77V is not
supported.
ID
#197
Low voltage detection
configuration
230-231
Note;
- ,,,,
252-254 Note:
- ,,,,
- LVDL/HnV will be initial value with reset. If LVDL/HnV is changed from initial vale,
LVDL/HnS should be configured as interrupt.
Low voltage detection
configuration
232
[Bit6] LVDH2S Extended external low-voltage detection voltage
operation selection bit
,,,
254
Low voltage detection
configuration
232
[Bit4:1] LVDH2V Extended external low-voltage detection
voltage setting bits
:
:
0011 3.60
0100 3.80
0101 4.00
0110 4.20
0111 4.40
1000 4.65
1001 4.65
1010 4.65
1011 4.65
1100 4.65
1101 4.65
1110 4.65
1111 4.65
254, 255 [Bit4:1] LVDH2V Extended external low-voltage detection voltage setting bits
:
:
0011 Not supported
0100 Not supported
0101 Not supported
0110 Not supported
0111 Not supported
1000 Not supported
1001 Not supported
1010 Not supported
1011 Not supported
1100 Not supported
1101 Not supported
1110 Not supported
1111 Not supported
#198
Serial Programming
237
P2_22/SOT0
261
P2_25/SOT0
#241
Polarity of RSTX is wrong
238
-
262
(RSTX pin level in figure is changed)
#353
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
#195
[Bit6] LVDH2S Extended external low-voltage detection voltage operation selection bit
#196
,,,
Note:
− LVDH2S should be used as Interrupt. If LVDH2S is configured as Reset, the reset itself
will be released immediately because LVDH2 is initially disabled.
10
Supplementary Information
Summary
PSC pin state during serial writer
mode
Error
Page
243
Error
-
Correct
Correct
ID
Page
267
6.1. PSC port state
#153
PSC port which is expected to control switching of external power supply devises will
output "low" during external reset ("low" is inputted to RSTX) in SERIAL PROGRAMMING
MODE. After reset ("high" is inputted to RSTX), PSC port will output "high".
If 1.2V power supply is supervised and RSTX is controlled with its low voltage state, PSC
cannot output "high", that is, external power supply devises would not start power
supplying, and MCU cannot go to a power-on sequence before a serial programming
operation.
Add the section "3.Operation" and 556
"4.Registers"
-
581
3. Operation of the Ethernet MAC
4. Registers
#342
PCMPWM DOUBLE bit
730
[bit13] DOUBLE : Double Mode Enable
This bit enables operation in mono or stereo mode.
982
[bit13] DOUBLE : Double Mode Enable
This bit enables operation in single or double mode.
#171
FPD-Link internal signal
861
Notes:
− ,,,
- ,,,
1113
Notes:
#341
− ,,,
- ,,,
− DLYDn (n=0, 1, 2, 3, and 4), FRSEL, RSEL, and VRM are internal signal names which
cannot be configured by software.
Error in desctiption for UNLOCK
register
865
Writing any value other than LOCK results in LOCK.
1118
Writing any value other than UNLOCK code results in LOCK.
#279
FPD-Link port status
868
[bit16] PWD12
0:Operation
1:Power Down(default) Differential 0 output
,,,
[bit0] RST
0:Release operation
1:Reset(default)
1121
[bit16] PWD12
0:Operation
1:Power Down(default) Differential Hi-Z output
,,,
[bit0] RST
0:Release operation
1:Reset(default) Differential 0 output
#344
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
11
Supplementary Information
Summary
FPD-Link internal signal
Error
Error
Correct
Page
Page
869,870, 30:RSEL2:R/W,29:RSEL1:R/W,28:RSEL0:R/W,24:VRM:R/W,9: 1122,
1123
871
DLY4-1:R/W,8:DLY4-0:R/W,7:DLY3-1:R/W,6:DLY30:R/W,5:DLY2-1:R/W,4:DLY2-0:R/W,3:DLY1-1:R/W,2:DLY10:R/W,1:DLY0-1:R/W,0:DLY0-0:R/W
[bit31] Reserved
Always write "0" to this bit. The read value is "0".
[bit30:28] RSEL
[bit27:25] Reserved
Always write "0" to this bit. The read value is "0".
[bit24] VRM
,,,
[bit15:10] Reserved
Always write "0" to this bit. The read value is "0".
[bit9:8] DLY4[1:0] : Delay for TX4 ch
[bit7:6] DLY3[1:0] : Delay for TX3 ch
[bit5:4] DLY2[1:0] : Delay for TX2 ch
[bit3:2] DLY1[1:0] : Delay for TX1 ch
[bit1:0] DLY0[1:0] : Delay for TX0 ch
Correct
ID
30:Reserved:R0,W0,29:Reserved:R0,W0,28:Reserved:R0,W0,24:Reserved:R0,W0,9:Re #343
served:R0,W0,8:Reserved:R0,W0,7:Reserved:R0,W0,6:Reserved:R0,W0,5:Reserved:R
0,W0,4:Reserved:R0,W0,3:Reserved:R0,W0,2:Reserved:R0,W0,1:Reserved:R0,W0,0:R
eserved:R0,W0
[bit31:28] Reserved
Always write "0" to this bit. The read value is "0".
[bit27:24] Reserved
Always write "0" to this bit. The read value is "0".
,,,
[bit15:0] Reserved
Always write "0" to this bit. The read value is "0".
The restriction for the accesses
by the 2D / 3D Graphics Cores
944
-
1194
3.2.4 The restriction for the accesses by the 2D / 3D Graphics Cores
#337
Port definition of base timer
1030
-
1281
(New chapter Base time port definition is added.)
#149
Port state under reset and PSS
1030
-
1287
(Appendix Pin Status in Each CPU State is added)
#162
Original document code: MN708-00005-3v0-E, Previous document code: MN708-00005-2v0-E
Rev. 3.0 June 30, 2015
Software watchdog location
50
(Software Watchdog in PD1)
50
(Delete)
#220
MCU Configuration Clock
55
MCU Configuration: SSCG0
55
MCU Configuration: SSCG0/PLL0
#356
Description for "Source Clock Local Clock List"
Link error
56
-
56
#398
56, 57
(Unnecessary link exists in the column of clock name)
56
The relation between source clock and local clock in product-specific functions is as
follows.
(Delete the link from column of clock name)
SSCG Restriction
57
Note:
−The frequency of PLLout (output of PLL/SSCG PLL multiplier
circuit) should be 800MHz or less.
56
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
#386
Note:
#361
−The frequency of PLLout (output of PLL/SSCG PLL multiplier circuit) should be 800MHz
or less.
−The frequency of CLK_CPU should be 232MHz or less if its source clock is SSCG.
12
Supplementary Information
Summary
Clock Quit
Error
Page
57
DMA Flag Clear
88
-
88-90
(The row of Remark is added.)
#407
DMA channel activation factors
88,89
N: Base Timer ch.m - 1
N+1: Base Timer ch.m+1 - 0
88,89
N: Base Timer ch.m+1 - 0
N+1: Base Timer ch.m - 1
#371
213
Notes: − The description of 3.2.2 is also described in 3.2.3 and 3.2.4.
#368
227
("3.8 Key Code Register" is added)
#359
Link information for headline 3.2.3 215
Error
Notes:
- ,,,
Correct
Correct
ID
Page
57
Notes:
- ,,,
- Read/Write access from CPU or DMA may bring about dead-lock when the clock source
#434
is not supplied to the accessed clock domain because "handshake" for AXI transaction
cannot be done. If you want to quit a clock generation for some clock domain, you also
need to configure an access protection for the domain using MPU.
Kyecode register
228
Notes: − The description of 3.2.2 is also described in 0 and
3.2.4.
-
Note on Port Output
230
-
229
Notes:
− Glitch at output port may sometime be observed when the following case.
1. from input to output
2. from output to input
3. from input to input
4. from output to output
#414
LVD description
249
-
250
(Clarify the definition of LVDL0/1/2 and LVDH0/1/2)
#399
Block Diagram of Ethernet MAC
580
(APB Slave Interface)
580
(AHB Slave Interface)
#365
(bit29:tsu_timer_comparison interrup)
(bit27:receive_lpi_idication_status_bit_change)
639
(bit29:tsu_timer_comparison_interrup)
(bit27:receive_lpi_indication_status_bit_change)
#420
TYPO in bit name of ETHERNET 639
register
TYPO in bit name of ETHERNET 647, 650 (bit25:disable_ptp_pdelay_reso_frame_transmitted)
register
(bit25:ptp_pdelay_reso_frame_transmitted)
647, 650 (bit25:disable_ptp_pdelay_resp_frame_transmitted)
(bit25:ptp_pdelay_resp_frame_transmitted_mask)
#422
Ethernet Description
(4.33 IEEE 1588 Timer Comparison Value Seconds Bottom
Register (ETHERNETn_tsu_sec_cmp)
-
(Delete)
#426
TYPO in bit name of ETHERNET 759
register
(bit27:20:rx_buffer_length)
758
(bit27:20:rx_buffer_length_def)
#427
TYPO in bit name of ETHERNET 772
register
[bit5] retry_limit_exceeded: Retry limit exceeded
771
[bit5] retry_limit_exceeded_or_late_collision
: Retry limit exceeded
#419
680
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
13
Supplementary Information
Summary
Error
Page
TYPO in bit name of ETHERNET 792
register
Error
[bit28] dstc_match_enable: DS/TC match enable
[bit27:12] udp_port_match_enable: UDP port match enable
[bit11:4] dstc_match_enable: DS/TC match enable
Correct
Correct
Page
791
[bit28] dstc_enable: DS/TC enable
[bit27:12] udp_port_match: UDP port match
[bit11:4] dstc_match: DS/TC match
ID
#424
TYPO in bit name of ETHERNET 795, 797, register
799
794,
(bit0:reserved)
796, 798
#425
TYPO in offset address of
ETHERNET register
799
(OFFSET:(0x6E0 + (i*0x4) + ((i-1)*0x4)))
798
(OFFSET:(0x640 + ((i-1)*0x4)))
#428
Link information for headline 6.8
1042
See 0, 6.9
1040
See 6.8, 6.9
#369
Indicator interrupt via Wakeup
Controller
1093
-
1091
3.5.3 Return from PSS Mode
Enhancement of Graphic
subsystem
1177
-
Register address for Graphic
Subsystem
11961267
(offset address information is decimal number)
June 30, 2015, S6J3200_MN708-00005-3v0-E-SI1
An interrupt of indicator PWM can be applied to a trigger of returning from PSS mode.
Then the bus clock CLK_SYSC0P should be supplied during the PSS mode.
#435
1175
(Add another HyperBus interface)
#405
11951279
(offset address information is hexadecimal number)
#362
14