CY2081WAF Three-PLL General Purpose EPROM Programmable Clock Generator Die Features Benefits • Three integrated phase-locked loops Provides all necessary system clocks in a single package • EPROM programmability Easy customization and fast turnaround time • Low-skew, low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • Power management options (Shutdown, OE, Suspend) Supports low power applications • Frequency select option Enables design flexibility and margin testing • Smooth slewing on SELCLK Allows downstream PLLs to stay locked on SELCLK output • 3.3V or 5V operation Enables application compatibility Part Number Outputs CY2081WAF 6 Input Frequency Range Output Frequency Range 10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V) 76.923 kHz–80 MHz (3.3V) Specifics Commercial Temperature Logic Block Diagram XTALIN OSC. XTALOUT XBUF PLL1 (8 BIT) /1,2,4 SELCLK S0 CLKA S1 S2/SUSPEND PLL3 (8 BIT) /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 CLKC CLKD CONFIG EPROM SHUTDOWN/ OE Overview The CY2081WAF is a standard CY2081 EPROM Programmable clock in die form. The die is intended to be used as a clock generator integrated with a crystal in a single package. This integration can dramatically lower the WIP and Lead Time for Oscillator manufacturing. Cypress Semiconductor Corporation CLKB /1,2,4,8 MUX PLL2 (10 BIT) • All Performance Specifications are based on a CY2081 in a 16-pin SOIC package per Cypress Specification. When the CY2081WAF is placed in packages as commonly used in the oscillator market performance will usually meet or exceed the specifications given in this datasheet. However, Cypress cannot guarantee performance in these packages. Each company that uses Cypress die should test and characterize the performance of their final product. 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 5, 2000 CY2081WAF PAD Configurations CY2081WAF 1 16 15 2A 2B DIE SIZE w/Scribe 79.3 mils x 82.3 mils 2015.0 µm x 2091 µm 14 # of Transistors 9271 3A 3B 13 4 12 5 6 7 8 9 DIE Substrate Attach: Float or GND DIE Thickness 20 mils Standard Backlap to 14 mils 10 11 Pin Summary Name PAD Number Function Programming Function CLKC 1 Configurable clock output C Serial Data Out VDD 2A, 2B Voltage supply Vpp, High Voltage Pin GND 3A, 3B Ground Ground 4 Reference crystal input Testmode Control XTALOUT 5 Reference crystal feedback NC XBUF 6 Buffered reference clock output Serial Data Out CLKD 7 Configurable clock output D NC SELCLK 8 SELCLK frequency clock output NC CLKB 9 Configurable clock output B NC CLKA 10 Configurable clock output A NC GND 11 Ground NC S0 12 SELCLK select input, bit 0; On Die 50K Pull Up Resistor Serial Data In S1 13 SELCLK select input, bit 1; On Die 50K Pull Up Resistor Shift Enable Vdd 14 Core Vdd Supply Vdd Supply S2/SUSPEND 15 SELCLK select input, bit 2. Optionally enables suspend feature when LOW [2] On Die 50K Pull Up Resistor Program Enable SHUTDOWN/OE 16 Places outputs in three-state[3] condition Serial Data Clock and shuts down chip when LOW. Optionally, only places outputs in three-state[3] condition and does not shut down chip when LOW. On Die 50K Pull Up Resistor [1] XTALIN [1] [4] Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF. 2. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information. 3. The CY2081WAF has weak pull-downs on all outputs. Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW. 4. SELCLK is shown as CPUCLK on the original CY2292 data sheet and programming guide. 2 CY2081WAF Operation Power Saving Features The CY2081WAF is a third-generation family of clock generators. The part can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10-MHz to 25-MHz crystals, providing additional flexibility. No external components are required with this crystal. The SHUTDOWN/OE input three-states the outputs when pulled LOW. If system shutdown is enabled (the default), a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins will be less than 50 µA and is typically 10 µA. After leaving shutdown mode, the PLLs will have to re-lock. All outputs have a weak pull-down so that the outputs do not float when three-stated.[3] Output Configuration The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs can be shut off in nearly any combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[2] The CY2081WAF has four independent frequency sources on chip. These are the reference oscillator and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The PLL3 offers the most output frequency divider options. PLL1 is controlled by the select inputs (S0–S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. PLL2 provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. PLL1 can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V; 80 MHz at 3.3V). All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note “Understanding the CY2291, CY2292 and CY2295” for information on configuring the part. 3 CY2081WAF Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ..........................260°C Supply Voltage ............................................... –0.5V to +7.0V Package Power Dissipation ...................................... 750 mW DC Input Voltage............................................ –0.5V to +7.0V Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Junction Temperature ...................................................150°C Storage Temperature ................................. –65°C to +150°C Operating Conditions[5] Min. Max. Unit VDD Parameter Supply Voltage, 5.0V (3.3V) operation Description All Part Numbers 4.5 (3.0) 5.5 (3.6) V TA Operating Temperature, Ambient All 0 +70 °C CLOAD Max. Load Capacitance 5.0V (3.3V) Operation All 18 25 (15) pF fREF Reference Frequency All 10.0 25.0 MHz Max. Unit Electrical Characteristics Parameter Description Conditions VOH[6] HIGH-Level Output Voltage IOH = 4.0 mA VOL[6] LOW-Level Output Voltage IOL = 4.0 mA VIH [7] HIGH-Level Input Voltage [7] Except crystal pins LOW-Level Input Voltage Except crystal pins Input HIGH Current IIL Input LOW Current VIN = VDD–0.5V VIN = +0.5V IOZ Output Leakage Current VDD Supply Current IDDS VDD Power Supply Current in Shutdown Mode[8] V 0.4 IIH IDD Typ. 2.4 VIL [8] Min. 2.0 V 0.8 V <1 10 µA <1 10 µA 250 µA 75(50) 100(65) mA 10 50 µA Three-state outputs VDD = VDD max., 5V (3.3V) operation Shutdown active V Notes: 5. Electrical parameters are guaranteed with these operating conditions. 6. All outputs swing rail to rail 7. Xtal Inputs have CMOS thresholds 8. Load = Max., VIN = 0V or VDD, Typical (–104) configuration, SELCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06•(FPLL1+FPLL2+2•FPLL3)+0.27•(FSELCLK+FCLKB+FCLKC+FCLKD+FCLKA+FXBUF ). 4 CY2081WAF Switching Characteristics[9] Parameter Name Description Min. Typ. Max. Unit t1 Output Period Clock output range, 5V operation All 10 (100 MHz) 13000 (76.923 kHz) ns t1 Output Period Clock output range, 3.3V operation All 12.5 (80 MHz) 13000 (76.923 kHz) ns Output Duty Cycle[10] Duty cycle for outputs, defined as t2 ÷ t1[11] fOUT > 66 MHZ 40% 50% 60% Duty cycle for outputs, defined as t2 ÷ t1[11] fOUT < 66 MHZ 45% 50% 55% t3 Rise Time Output clock rise time[12] 3 5 ns t4 Fall Time Output clock fall time[12] 2.5 4 ns t5 Output Disable Time Time for output to enter three-state mode after SHUTDOWN/OE goes LOW 10 15 ns t6 Output Enable Time Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH 10 15 ns t7 Skew Skew delay between any identical or related outputs[2, 11] < 0.25 0.5 ns t8 PLL1 Slew Frequency transition rate 20.0 MHz/ ms t9A Clock Jitter[13] Peak-to-peak period jitter (t9A max. – t9A min.), % of clock period (fOUT < 4 MHz) <0.5 1 % t9B Clock Jitter[13] Peak-to-peak period jitter (t9B max. – t9B min.) (4 MHz < fOUT < 16 MHz) <0.7 1 ns t9C Clock Jitter[13] Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) <400 500 ps t9D Clock Jitter[13] Peak-to-peak period jitter (fOUT > 50 MHz) <250 350 ps t10A Lock Time for PLL1 Lock Time from Power-up <25 50 ms t10B Lock Time for PLL2 and PLL3 Lock Time from Power-up <0.25 1 ms Slew Limits PLL1 Slew Limits 100 (5V) 80 (3.3V) MHz 1.0 All 8 Notes: 9. Guaranteed by design and characterization, not 100% tested in production. 10. XBUF duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. 12. Measured between 0.4V and 2.4V. 13. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: “Jitter in PLL-Based Systems. 5 CY2081WAF Switching Waveforms All Outputs, Duty Cycle and Rise/Fall Time t1 t2 OUTPUT t3 t4 CY2081WAF-7 Output Three-State Timing[3] OE t6 t5 ALL THREE-STATE OUTPUTS CY2081WAF-8 CLK Outputs Jitter and Skew t9A CLK OUTPUT t7 RELATED CLK CY2081WAF-9 SELCLK Frequency Change SELECT OLD SELECT Fold NEW SELECT STABLE t8 & t10 Fnew SELCLK CY2081WAF-10 6 CY2081WAF Test Circuit VDD CLK out 0.1 µF OUTPUTS CLOAD VDD 0.1 µF GND CY2081WAF The CY2081 wafer yields approximately 3000 die. Therefore, the CY2081WAF must be purchased in multiples of 3000. After Ordering Information Ordering Code CY2081WAF Operating Range Commercial Operating Voltage 3.3 or 5.0V sorting the wafer, a certain number of die will be inked mark as bad. The wafer will then be backlapped and shipped. Only the good die will be billed. Assume 3000 good die per wafer for inventory control purposes. Document #: 38-00959-** © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.