Release Notes
SAM4C Device Support Pack
Introduction
The “SAM4C device support pack” contains updates required for supporting
the Atmel® SAM4C series in Atmel Studio. This document contains a short
description on how to get started with developing and debugging the two cores
of a SAM4C device simultaneously.
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Table of Contents
Introduction .................................................................................... 1
1. Developing for two cores ........................................................ 3
1.1.
1.2.
1.3.
1.4.
Prerequisites ........................................................................
Project Setup .......................................................................
Configure core1 ....................................................................
Debugging two cores .............................................................
3
3
4
4
2. References .............................................................................. 7
3. Document revision history ....................................................... 8
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1.
Developing for two cores
1.1
Prerequisites
Make sure that Atmel Studio 6.1 SP2 is installed. Then install the SAM4C part pack.
1.2
Project Setup
The best way of setting up your projects on a multi-core device (considering debugging at a later stage),
is to create two separate projects in two separate instances of Atmel Studio, one for each core. Select
ATSAM4C16C_0 as device for the first project, and ATSAM4C16C_1 for the other.
ASF projects demonstrating interaction between the two cores may consist of two projects in one Atmel Studio
solution.
A simple example with two projects is shown in the program listings below. The program running in core0 writes
a value to shared memory, and the program in core1 reads the location.
Example 1-1. Program for core0
/*
* SAM4C_core0_counter.c
*/
#include "sam.h"
static volatile unsigned int *gpSharedCounter = (unsigned int *)0x20100000;
// Enable the parts of subsystem 1 used by this example. Doing this before
// main is called (e.g. from the reset handler in startup_sam4c.c) ensures
// that access done by the debugger (watch/memory windows) after reset can
// take place without risking buss stalls.
void enable_subsystem_1()
{
// Disable watchdog
WDT->WDT_MR |= WDT_MR_WDDIS;
// Subsystem 1 bus master clock enable, enable clocks
PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
// Subsystem 1 clock source = main, clock prescaler = 1
PMC->PMC_MCKR |= PMC_MCKR_CPCSS_MAIN_CLK;
while ( (PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
PMC->PMC_MCKR |= PMC_MCKR_CPPRES(1);
while ( (PMC->PMC_SR & PMC_SR_MCKRDY) == 0);
// Subsystem 1 SRAM clock enable
PMC->PMC_PCER1 = PMC_PCER1_PID42;
}
// Release co-processor peripheral reset
RSTC->RSTC_CPMR |= (RSTC_CPMR_CPKEY(0x5Au) | RSTC_CPMR_CPEREN);
// Application entry point.
int main(void)
{
// Initialize the SAM system
SystemInit();
}
*gpSharedCounter = 0;
while (1) {
(*gpSharedCounter)++;
}
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Example 1-2. Program for core1
/*
* SAM4C_core1_monitor.c
*/
#include "sam.h"
static volatile unsigned int *gpSharedCounter = (unsigned int *)0x20100000;
// Place a breakpoint here
void trap()
{
}
// Application entry point
int main(void)
{
// Initialize the SAM system
SystemInit();
}
1.3
while (1)
{
if ((*gpSharedCounter) > 1000)
trap();
}
Configure core1
The code project for core1 must be configured to place program code in the designated SRAM.
1.4
1.
Right-click the project in Solutions Explorer, and select Properties... and the Project Settings dialog will
open.
2.
In the tree menu, select ARM/GNU Linker → Miscellaneous.
3.
In the Linker Flags text box, set the flag -Tsam4c16c_1_sram.ld.
Debugging two cores
Debug the two projects using the two separate Atmel Studio instances and one common Atmel SAM-ICE™:
1.
In the first Atmel Studio instance, open the project made for core0.
2.
Select Debug → Start Debugging and Break, and the program will be loaded into core0 and run to main.
3.
In the second Atmel Studio instance, open the project made for core1.
4.
Select Debug → Start Debugging and Break, and the program will be loaded into core1 and run to main.
At this point the program pointer for core0 should point to a location in Flash, while the program pointer for
core1 should point to a location in SRAM1.
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Figure 1-1. Debugging both cores
5.
Place a breakpoint on the trap() function in core1
6.
In core0 step past the initialization of gpSharedCounter
7.
Start core1 and then start core0 and observe that the breakpoint in core1 will be hit.
Figure 1-2. Core1 in breakpoint
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Note
●
The two cores can be debugged independently. The SAM-ICE will enable and initialize the
core1 sub-system as described in the boot strategies section of the SAM4C datasheet.
●
A system reset, such as an WDT reset, will reset the core1 sub-system to it's initial state. This
will destroy any ongoing debug session for core1.
●
Attempting to access peripherals in the core1 sub-system from core0 or a debugger
connected to core0, without enabling the core1 sub-system first will lead to a bus stall,
effectively making the device unresponsive. To recover from this situation perform a chip
erase using the designated erase pin as described in the datasheet.
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2.
References
1
●
For more information about device boot strategies, see the device datasheet .
●
Atmel Software Framework contains more examples for SAM4C.
1
2
2
http://www.atmel.com/devices/SAM4C16.aspx
http://asf.atmel.com/docs/latest/search.html?device=sam4c
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3.
Document revision history
Document
revision
Date
Comment
42210A
31/10/2013
First release
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