Per Pin Parametric Measurement Unit/Source Measure Unit AD5520 FEATURES Force/Measure Functions Force Voltage/Current, Measure Current/Voltage Force Current/Voltage, Measure Current/Voltage Force/Measure Voltage Range 11 V 4 Programmable Force/Measure Current Ranges 4 A, 40 A, 400 A, 4 mA Extended Current Ranges 40 mA and 160 mA with External Driver Clamp Circuitry and Window Comparators On Board Guard Amplifier 64-Lead LQFP Package GENERAL DESCRIPTION The AD5520 is a single channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. The part is also suited for use as a source measurement unit for instrumentation applications. It contains programmable modes to force a pin voltage and measure the corresponding current or force a current and measure the voltage. The AD5520 can force/measure over a ± 11 V range or currents up to ± 4 mA with its on-board force amplifier. An external amplifier is required for wider current ranges. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. The AD5520 is available in a 64-lead LQFP package. APPLICATIONS Automatic Test Equipment Per Pin PMU, Shared Pin PMU, Device Power Supply Instrumentation Source Measure, Parametric Measurement, Precision Measurement COMPOUT2 COMPOUT1 COMPOUT0 COMPIN2 AD5520 COMPIN1 COMPIN0 FUNCTIONAL BLOCK DIAGRAM AVEE AVCC FOH BW SELECT FOH3 FOH2 FIN FOH1 FOH0 MEASI5H CLAMP DETECT MEASI4H MEASI3H MEASI2H CLH MEASI1H CLL MEASI0H REFGND G = 16 MEASIOUT MEASIL ISENSE INST AMP VSENSE INST AMP MEASOUT GUARDIN G=1 MEASVH G=1 MEASVOUT COMPARATOR CPH MEASVL AGND QM5 DGND QM4 AC0 AC1 CLLDETECT CLHDETECT MOE AM0 AM1 AM2 MSEL FSEL CPSEL CPCK STB CPL STANDBY LOGICS CS DVDD CPOH CPOH GUARD REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 5%, AV = –15 V 5%, DV = 5 V 10%, AGND = 0 V, REFGND = 0 V, 0C to 70C, unless otherwise noted.) AD5520–SPECIFICATIONS (AVDGND==+150 V.VAllspecifications CC Parameter VOLTAGE FORCE MODE Force Control Output Voltage Range FOH Output Impedance FOH0 FOH1 FOH2 FOH3 Input Offset Error Gain Error Clamp Voltage Error2 Min Typ1 70 2.5 3 500 60 ⫾1 ⫾1 50 ⫾0.1 30 ⫾4 95 Gain Error Gain Error Temperature Coefficient4 MEASIOUT Output Load Current CMRR CURRENT FORCE MODE Input Offset Error Gain Error Clamp Current Error2 AMPLIFIER SETTLING TIME4, 5 VSENSE Amp ISENSE Amp LOOP SETTLING4, 5 COMPIN2 = 100 pF COMPIN1 = 1000 pF COMPIN0 = 3000 pF Unit Test Conditions/Comments RLOAD = 10 kΩ, CLOAD = 50 pF ⫾5 1 ⫾1 V Ω kΩ kΩ Ω Ω mV % % FS ±4 ± 40 ± 400 ±4 CURRENT MEASURE MODE High Sense Input Range, VMEASIxH Linearity3 Input Bias Current Input Bias Current Drift1 Output Offset Error µA µA µA mA ⫾11 ⫾0.01 ⫾3 ⫾100 ⫾100 ⫾100 ⫾100 ⫾0.35 V % FSR nA pA/°C mV mV mV mV % µV/°C mA dB ⫾10 1 ⫾1 mV % % FS +0.005 ⫾10 V mV % FSR mV ⫾11 ⫾100 ⫾5 DD Max ⫾11 CURRENT MEASURE/FORCE FOH0 FOH1 FOH2 FOH3 VOLTAGE MEASURE MODE Differential Input Range Low Sense Input Voltage Range Linearity3 Input Offset Error Input Offset Error Temperature Coefficient1 Gain Error Gain Error Temperature Coefficient4 Input Bias Current Input Bias Current Drift4 MEASVOUT Output Load Current CMRR4 EE of FIN Set with external sense resistors MODE0, RS = 125 kΩ MODE1, RS = 12.5 kΩ MODE2, RS = 12.5 kΩ MODE3, RS = 125 Ω +11 V > VFOL > –11 V MODE0 MODE1 MODE2 MODE3 Gain of 16 @ DC With MODE0, MODE1, MODE2, MODE3 of FIN MEASVL +11 V > VMEASVH to VMEASVL > –11 V FIN = 0 V, Measured @ MEASVOUT ⫾15 ⫾0.03 ⫾0.15 2 ⫾1 ⫾3 50 ⫾4 73 mV/°C % mV/°C nA pA/°C mA dB 20 12 µs µs To 0.2% To 0.2% µs µs µs ms ms ms Settling to within 0.024% of 8 V step MODE0 MODE1 MODE2, MODE3 MODE0 MODE1, MODE2, MODE3 MODE0, MODE1, MODE2, MODE3 450 285 170 2 1.8 5.75 600 390 240 2.5 2.4 8.7 –2– Gain of 1 @ DC REV. A AD5520 Parameter Min 4, 5 SLEW RATE COMPARATOR CPH, CPL Input Range Input Offset GUARD DRIVER Output Voltage Output Impedance Output Offset Voltage Load Current4 Output Settling Time4 ANALOG REFERENCE INPUTS Force Control Input Range Force Control Input Impedance Clamp Control Input Range Clamp Control Input Impedance Comparator Threshold Input Range Comparator Threshold Input Impedance Input Capacitance4 LOGIC OUTPUTS Output Low Voltage, VOL4 Output High Voltage, VOH4 POWER REQUIREMENTS AVCC AVEE Power Supply Rejection Ratio, PSRR1 FOH MEASOUT DC PSR DVDD IAVCC IAVEE IDVDD Unit Test Conditions/Comments 50 4.3 1.28 mV/µs mV/µs mV/µs COMPIN2 = 100 pF COMPIN1 = 1000 pF COMPIN0 = 3000 pF ⫾7 V mV VCPH > VCPL 2 V Ω mV mA µs ⫾11 ⫾11 130 400 ⫾4 0.5 ⫾11 1 3 V MΩ V MΩ V MΩ pF 2 3 1 Ω Ω kΩ 8 pF 1 ⫾11 1 ⫾11 ANALOG MEASUREMENT OUTPUTS Voltage Measure Output Impedance Current Measure Output Impedance Multiplexed Sense Output Impedance Input Capacitance MEASIxH, MEASVH, FOHx LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VIHL Input Capacitance4 Typ1 Max All digital inputs together 0.4 V V ISINK = 2 mA ISOURCE = 2 mA +15.75 +15.75 V V For specific performance6 100 kHz 500 kHz 1 MHz 100 kHz 500 kHz 12 12 0.5 dB dB dB dB dB dB V mA mA mA 2.4 –25 –16 –15 –55 –10 90 5 NOTES 1 Typical values are at 25°C and nominal supply, unless otherwise noted. 2 Full-scale = 11 V. 3 Full-scale range = 22 V. 4 Guaranteed by design and characterization but not subject to production test. 5 Force control amplifier dominates slew rate and settling time. 6 Operational with ± 12 V supplies, force/measure range is reduced to ± 8.5 V. Specifications subject to change without notice. REV. A VCLH > VCLL µA V V pF 3 +15 –15 100 pF Capacitive Load ⫾1 0.8 2.0 +14.25 –14.25 Capacitive Load Only –3– Digital inputs at supply rails AD5520 TIMING CHARACTERISTICS1, 2 (AVCC = +15 V 5%, AVEE = –15 V 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0C to 70C, unless otherwise noted.) Parameter DVDD 5 V 10% 3.3 V Unit Conditions/Comments t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 30 40 0 550 320 450 150 100 240 150 100 320 0 200 70 40 560 320 500 800 440 240 500 440 320 ns min ns min ns min ns min ns min ns min ns min ns min ns min µs min ns min ns min ns min CS Falling Edge to STB Falling Edge Setup Time STB Pulse Width STB Rising Edge to CS Rising Edge Setup Time Data Setup Time CS Falling Edge to CPCK Rising Edge Setup Time CPCK Pulse Width CPCK to STB Falling Edge Setup Time STB Rising Edge to QMx, CLxDETECT Valid STB Rising Edge to CPOH, CPOL Valid Comparator Setup Time, MODE2, MODE3 settling Comparator Hold Time Comparator Output Delay Time Comparator Strobe Pulse Width NOTES 1 See Figure 1. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. Specifications subject to change without notice. CS t1 t2 t3 STB t4 AMx, ACx, FSEL, MSEL, CPSEL t5 t6 t7 CPCK t8 t9 QM4, QM5, CLHDETECT, CLLDETECT CPOL, CPOH Figure 1. Timing Diagram t 11 MEASVOUT OR MEASIOUT CPCK CPOH, CPOL t 10 t 13 t 12 Figure 2. Comparator Timing –4– REV. A AD5520 Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature, (TJ max) . . . . . . . . . 150°C Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/JA Thermal Impedance JA . . . . . . . . . . . . . . . . . . . . . . 47.8°C/W Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) AVCC to AVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V AVCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V AVEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVDD + 0.3 V Analog Inputs to AGND . . . . . AVCC + 0.3 V to AVEE – 0.3 V CLH to CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V CPH to CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V REFGND, DGND . . . . . . . . . AVCC + 0.3 V to AVEE – 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD5520JST AD5520JST-REEL EVAL-AD5520EB 0°C to 70°C 0°C to 70°C 64-Lead LQFP 64-Lead LQFP Evaluation Board and Software ST-64-2 ST-64-2 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5520 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –5– AD5520 PIN CONFIGURATION MEASOUT REFGND COMPIN2 COMPIN1 COMPIN0 50 FOH REFGND AVCC_B MEASIOUT COMPOUT0 MEASVOUT COMPOUT1 FIN COMPOUT2 CLH 51 49 MEASI4H 45 FOH3 44 MEASI3H 43 FOH2 42 MEASI2H 41 FOH1 40 MEASI1H 39 FOH0 38 MEASI0H 37 MEASIL 36 MEASVH 35 GUARD(NC) 15 34 MEASVL 16 33 AVCC_G 3 4 5 6 AD5520 (Not to Scale) 9 10 11 12 13 22 23 24 25 26 27 28 29 30 31 32 GUARDIN 21 NC 20 GUARD 19 AVEE_G 18 AGND 17 AVCC 14 DGND AC1 52 MEASI5H AVEE AC0 53 46 CPSEL STB 54 MSEL CS 55 2 CLHDETECT MOE 56 AVEE_B 8 QM5 57 47 7 QM4 58 48 DGND CLLDETECT 59 FSEL CPCK 60 STANDBY CPOL 61 AM0 CPOH 62 AM1 DVDD 63 AM2 CPL 64 1 DVDD CPH CLL 64-Lead LQFP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3, 18 4 5 6 7, 17 8 9 10 Mnemonic CPH CPL DVDD CPOH CPOL CPCK DGND CLHDETECT CLLDETECT QM4 11 QM5 12 13 MOE CS 14 STB 15 AC0 16 AC1 Description Upper Comparator Threshold Voltage Input, CPH > CPL. Lower Comparator Threshold Voltage Input, CPL < CPH. Digital Supply Voltage. Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH. Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL. Logic Input. Used to initiate comparator sampling and update CPOH and CPOL. Digital Ground. Logic Output. When high, indicates upper clamp active. For details, see the Clamp Function section. Logic Output. When high, indicates lower clamp active. For details, see the Clamp Function section. Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or switch. For details, see the High Current Ranges section. Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or switch. For details, see the High Current Ranges section. Active Low MEASOUT Enable. Active Low Logic Input. The device is selected when this pin is low. For details, see the Interface section. Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different configurations. Rising edge of STB triggers sequence inputs. For details, see the Interface section. Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors. For details, see the Force Control Amplifier section. Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors. For details, see the Force Control Amplifier section. –6– REV. A AD5520 PIN FUNCTION DESCRIPTIONS (continued) Pin No. 19 Mnemonic AM2 20 AM1 21 AM0 22 STANDBY 23 FSEL 24 MSEL 25 CPSEL 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57, 59 58 60 61 62 63 64 AVEE AVCC AGND AVEE_G GUARD NC GUARDIN AVCC_G MEASVL GUARD(NC) MEASVH MEASIL MEASI0H FOH0 MEASI1H FOH1 MEASI2H FOH2 MEASI3H FOH3 MEASI4H MEASI5H AVEE_B FOH AVCC_B COMPOUT0 COMPOUT1 COMPOUT2 COMPIN0 COMPIN1 COMPIN2 REFGND MEASOUT MEASIOUT MEASVOUT FIN CLH CLL REV. A Description Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable standby mode. For details, see the Current Ranges section. Logic Input. When high, device is in standby mode of operation. For details, see the Standby Mode section. Logic Input. Force mode select. Used to select between current or voltage force operation. For details, see the Force Voltage or Force Current section. Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT when low. Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when high. For details, see the Comparator Function and Strobing section. Most Negative Supply Voltage. Most Positive Supply Voltage. MEASx Input Ground. Most Negative Supply Voltage. Guard Output. No Connect. Guard Input. Most Positive Supply Voltage. DUT Voltage Sense Inputs (Low Sense). No Connect. DUT Voltage Sense Inputs (High Sense). DUT Current Sense Inputs (Low Sense). DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). Force Control Voltage Output. DUT Current Sense Inputs (High Sense). DUT Current Sense Inputs (High Sense). Most Negative Supply Voltage. External Force Driver Control Voltage Output. Most Positive Supply Voltage. Compensation Capacitor 0 Output. Compensation Capacitor 1 Output. Compensation Capacitor 2 Output. Compensation Capacitor 0 Input. Compensation Capacitor 1 Input. Compensation Capacitor 2 Input. Analog Input/Output Reference Ground. Multiplexed DUT Voltage/Current Sense Output. For details, see the Measured Parameter section. DUT Current Sense Output. DUT Voltage Sense Output. Force Control Voltage Input. Upper Clamp Voltage Input CLH > CLL. Lower Clamp Voltage CLL < CLH. –7– AD5520–Typical Performance Characteristics 0.0030 0.0030 VDD = +15V VSS = –15V MODE 3 0.0025 0.0020 IM LINEARITY (%) VM LINEARITY (%) 0.0025 0.0015 0.0010 0.0005 0.0020 0.0015 0.0010 0.0005 0 0 0 10 20 30 40 TEMPERATURE (C) 50 60 70 0 TPC 1. Voltage Sense Amplifier Linearity vs. Temperature 140 VDD = +15V VSS = –15V TA = 25C 70 20 30 40 TEMPERATURE (C) VDD = +15V VSS = –15V TA = 25C 120 60 50 60 70 ISENSE CMRR 100 50 CMRR (dB) AMPLITUDE (dB) 10 TPC 4. Current Sense Linearity vs. Temperature 80 40 30 80 60 40 20 20 10 0 VDD = +15V VSS = –15V MODE 3 1 10 100 1k 10k FREQUENCY (Hz) 100k 0 1M TPC 2. Voltage Sense Amplifier CMRR vs. Frequency 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M TPC 5. Current Sense Amplifier CMRR vs. Frequency 10 5 0 CCOMP = 0.1nF 0 –5 AMPLITUDE (dB) AMPLITUDE (dB) –10 –20 CCOMP = 1.0nF –30 CCOMP = 0.1nF –10 –15 CCOMP = 1.0nF –20 –25 –40 –30 CCOMP = 3.3nF –50 –60 100 VDD = +15V VSS = –15V TA = 25C –35 1k 10k FREQUENCY (Hz) –40 100 100k TPC 3. Force Amplifier Bandwidth–MODE 0 (4 A) CCOMP = 3.3nF VDD = +15V VSS = –15V TA = 25C 1k 10k FREQUENCY (Hz) 100k TPC 6. Force Amplifier Bandwidth–MODE 1 (40 A) –8– REV. A AD5520 0 0 VDD = +15V VSS = –15V TA = 25C –5 –15 –20 CCOMP = 1.0nF –25 –30 CCOMP = 3.3nF –35 –15 –20 CCOMP = 1.0nF –25 –30 CCOMP = 3.3nF –35 –40 –40 –45 100 1k 10k FREQUENCY (Hz) –45 100 100k TPC 7. Force Amplifier Bandwidth–MODE 2 (400 A) 1k 10k FREQUENCY (Hz) 100k TPC 10. Force Amplifier Bandwidth–MODE 3 (4 mA) 5 30 VDD = +15V VSS = –15V TA = 25C 0 20 –5 AMPLITUDE (dB) AMPLITUDE (dB) CCOMP = 0.1nF –10 CCOMP = 0.1nF AMPLITUDE (dB) AMPLITUDE (dB) –10 –10 –15 –20 –25 VDD = +15V VSS = –15V TA = 25C –5 10 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M VDD = +15V VSS = –15V TA = 25C –30 100 100M TPC 8. Guard Amplifier Bandwidth 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 11. Voltage Sense and Current Sense Amplifier Bandwidths 20 10 VSENSE –10 –20 1 ISENSE 0 VDD = +15V VSS = –15V TA = 25C –5 VDD = +15V VSS = –15V TA = 25C AMPLITUDE (dB) AMPLITUDE (dB) 0 –10 –20 –30 –10 –15 –20 –40 –25 –50 –60 100k 1M FREQUENCY (Hz) –30 100k 10M TPC 9. Current Sense Amplifier AC PSRR REV. A 1M FREQUENCY (Hz) 10M TPC 12. Force Amplifier AC PSRR–MODE 3, CCOMP = 100 pF –9– AD5520 16 20 10 VDD = +15V VSS = –15V TA = 25C 14 10 –10 VOLTAGE (V) AMPLITUDE (dB) VCC 12 0 –20 –30 8 6 4 –40 2 –50 VDUT 0 –2 –60 100k 1M FREQUENCY (Hz) 10M 0 5 TPC 13. Voltage Sense Amplifier AC PSRR 10 15 20 25 TIME (ms) 30 35 40 45 TPC 15. Power Up 700 9 COMPIN2 = 100pF 8 600 COMPIN1 = 1000pF GUARD 7 6 VOLTAGE (V) nV/ Hz 500 400 300 VSENSE 5 COMPIN2 = 3000pF 4 3 2 200 FOH 1 100 0 0 10 ISENSE 100 –1 1k FREQUENCY (Hz) 10k 100k 0 TPC 14. Noise Spectral Density 0.001 0.002 0.003 0.004 0.005 TIME (s) 0.006 0.007 0.008 TPC 16. Settling Time, Mode 2 –10– REV. A AD5520 THEORY OF OPERATION The AD5520 is a single channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), and force voltage measure voltage (FVMV). The PPMU can force or measure a voltage from –11 V to +11 V. It can force or measure a current over four ranges: 4 µA, 40 µA, 400 µA, and 4 mA. The addition of an external driver allows two extended ranges. DAC FOHx G = 16 MEASIOUT MEASVOUT G=1 FSEL is an input that determines whether the PPMU forces a voltage or current. Table II. FSEL Function FSEL Function Low Voltage Force and Current Clamp with MEASIOUT Voltage Current Force and Voltage Clamp with MEASVOUT Voltage High The AD5520 PPMU is controlled via a number of digital inputs, which are discussed in detail in the following sections. All inputs are TTL compatible. CS is used to select the device while STB (active low input) latches data available on the other digital inputs and updates any required digital outputs. The rising edge of STB triggers sequence inputs. The remaining digital inputs control the function of the PMU—which measure mode it is in, which compensation capacitor is used, and the selected current range. Measured Parameter MEASOUT is a muxed output that tracks the sensed parameter, MSEL connects it to the output of either the current sense amplifier or the voltage sense amplifier, depending on which is the measured parameter of interest. The MEASOUT pin will be connected back to an ADC to allow the measured value to be converted to a digital code. The AD5520 may be placed into standby mode via the standby logic input. In this mode, the force amplifier is disconnected from the force input (FIN), the switch in series with the force output pins, FOHx, is opened, and the current measure amplifier is disconnected from the sense resistors. The voltage measure amplifier is still connected across the DUT, so DUT voltage measurements may still be made while in standby mode. Figure 3 shows the configuration of the PMU while in standby mode. Function Low High Normal Force Mode Standby Mode DUT Force Voltage or Force Current INTERFACE STANDBY MEASVH Figure 3. PMU in Standby Mode On chip is clamp circuitry that clamps the output of the force amplifier if the voltage at MEASIOUT and MEASVOUT exceeds CLL and CLH. Table I. Standby Mode RS MEASVL The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. Also provided on the chip is clamp circuitry that will flag via CLHDETECT and CLLDETECT if the voltage applied to FIN or across the DUT has exceeded the voltage applied to CLL and CLH. Standby Mode MEASIHx MEASIL The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. REV. A FIN Table III. MEASOUT Connected to Voltage or Current MSEL Function Low High MEASOUT = DUT Voltage MEASOUT = DUT Current The MEASOUT pin may also be made high impedance through the MOEB logic input. Table IV. MOEB Allows MEASOUT to Go High Impedance –11– MOEB Function Low High Enable MEASOUT Output Hi-Z MEASOUT Output AD5520 Current Ranges A number of current ranges are possible with the AD5520. The AM0, AM1, and AM2 pins are digital inputs used to establish full-scale current range of the PMU. Table V. Selection of Current Range AM0 AM1 AM2 Function Low High Low High Low Low Low High High Low High Low Low High High High Low Current Range MODE0 (up to 4 µA) Low Current Range MODE1 (up to 40 µA) Low Current Range MODE2 (up to 400 µA) Low Current Range MODE3 (up to 4 mA) High Current Range MODE4 (External Buffer Mode) High Current Range MODE5 (External Buffer Mode) High Standby (same as STANDBY = High) High Standby (same as STANDBY = High) RS Selection The AD5520 is designed so that the voltage drop across each of the RS resistors will be less than ±500 mV when maximum current is flowing through them. To support other current ranges, these sense resistor values may be changed. A force amplifier can drive a maximum of 6 mA. It is not recommended to increase the maximum current above the nominal range. The two external current ranges use an external buffer to drive the required current. Our example uses 40 mA and 160 mA ranges. These ranges can be changed to suit user requirements for a high current range. Force Control Amplifier The force control amplifier requires external capacitors connected between the COMPOUTx and COMPINx pins. For stability with large capacitance at the DUT, the largest capacitance value (3000 pF) should be selected. The force control amplifier should always contribute the dominant pole in the control loop. Settling times will increase with larger capacitances. ACx inputs select which external compensation capacitor is used. After CPSEL has selected which amplifier output is of interest, logic input CPCK is used to initiate comparator sampling and update the logic outputs CPOH and CPOL, indicating if the voltages at MEASIOUT or MEASVOUT have exceeded voltages set at CPL or CPH (thus providing DUT too high or DUT too low information). A rising edge on STB is required to clock the CPOH and CPOL data out. Table VIII. CPCK Synchronous Logic Outputs AC1 Low Low High Low Low High Comparator Function and Strobing The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high. CPSEL is the digital input that controls this function, selecting whether it should compare to the voltage sense or the current sense amplifier. Function Low High Compare CPL, CPH to MEASVOUT Compare CPL, CPH to MEASIOUT MEASVOUT or MEASIOUT < CPH MEASVOUT or MEASIOUT > CPH CPOL Function Low High MEASVOUT or MEASIOUT > CPL MEASVOUT or MEASIOUT < CPL The digital output flags, which indicate a clamp limit has been hit, are CLHDETECT for the upper clamp and CLLDETECT output for the lower clamp. Table IX. Clamp Detect Outputs CLHDETECT Function Low High Upper Clamp Inactive Upper Clamp Active CLLDETECT Function Low High Lower Clamp Inactive Lower Clamp Active High Current Ranges With the use of an external high current amplifier, two high current ranges are possible. The current range values can be selected as required in the application through appropriate selection of the sense resistors connected between MEASI5H, MEASI4H, and MEASIL. When one of these high current ranges (MODE 4 or MODE 5) is selected via the AMx control lines, the appropriate QM4 or QM5 output will be enabled. These outputs can thus be used to control relays connected in series with the high current amplifier as shown in Figure 8. Table VII. Comparator Function Select CPSEL Low High Clamp circuitry is also included on chip, allowing the output of the force amplifier to be clamped in the event of the voltage at MEASIOUT and MEASVOUT exceeding CLL and CLH. The clamp circuitry play their role in the event of a short or open circuit. When in force current range, the voltage clamps protect the DUT in the event of an open circuit. Likewise, when forcing a voltage and a short circuit occurs, the current clamps will protect the DUT in this case. The clamps also function to protect the DUT in the event of a transient voltage or current spike that may occur when changing to a different operating mode or when programming the device to a different current range. Function Select External Compensation Capacitor 0 Select External Compensation Capacitor 1 Select External Compensation Capacitor 2 Function Clamp Function Table VI. AC0, AC1 Compensation Capacitor Selection AC0 CPOH Table X. High Current Range Logic Outputs QM4 QM5 Function High Low Low High Current Range MODE 4 Enable Output Current Range MODE 5 Enable Output –12– REV. A AD5520 the CLL and CLH levels to ensure the clamp voltages have not been exceeded. Strobing CPCK and STB will provide information about the voltage level with respect to the comparator levels, CPH and CPL. CIRCUIT OPERATION Force Voltage Most PMU measurements are performed while in force voltage and measure current modes, for example, when the device is used as a device power supply, or in continuity or leakage testing. In the force voltage mode, the voltage at analog input FIN is mapped directly to the voltage forced at the DUT. FIN When in force voltage and measure current modes, the maximum voltage applied to the input corresponds to the maximum current outputs. Figure 4 shows the transfer function when forcing a voltage. FOHx MEASIHx VFIN G = 16 CLH MEASIL MEASVH CLL VCLL REFGNDI/V VCLH RDUT RS 16 V V VFIN VCLL RDUT G=1 RDUT MEASIOUT VCLH MEASVOUT VDUT RS MEASVL VMEASVOUT VMEASIOUT CONDITION VCLH > IDUT RS 16 VCLL < IDUT RS 16 VCLH < IDUT RS 16 VCLL < IDUT RS 16 VCLH > IDUT RS 16 VCLL > IDUT RS 16 OUTPUT VDUT = VFIN VDUT = VCLH VDUT = VCLL RS 16 Figure 5. Voltage Force, Measure Current Mode Force Current In the force current mode, the voltage at FIN is now converted to a current through the following relationship: Force Current = VFIN /RSENSE IDUT Figure 6 shows a simplified diagram of the PMU when in force current mode. The control loop consists of the force amplifier with the current sense amplifier making up the feedback path. In this case, voltage at the DUT is sensed across the voltage measure amplifier (Gain = 1) and presented at the MEASVOUT output. VCLH RS 16 VCLH VCLH VFIN FIN VCLL FOHx RS 16 MEASIHx VFIN G = 16 CLH MEASIL MEASVH VCLL Measure Current REFGNDI/V Figure 5 shows a simplified diagram of the PMU when in force voltage mode. The control loop consists of the force amplifier with the voltage sense amplifier making up the feedback path. Current flowing through the DUT is measured by sensing the current flowing through a selectable sense resistor, which is in series with the DUT. The current sense amplifier (Gain = 16) generates a voltage at its output, which is proportional to the current flowing through the DUT. This voltage is compared to V V CONDITION OUTPUT RDUT G=1 MEASIOUT VCLH MEASVOUT CLL Figure 4. Voltage Force Transfer Function MEASVL VMEASVOUT VMEASIOUT VCLH > VDUT VCLL < VDUT IDUT = VFIN RS VCLH < VDUT VCLL < VDUT IDUT = VCLH RS VCLH > VDUT VCLL > VDUT IDUT = VCLL RS Figure 6. Current Force, Voltage Measure Mode REV. A –13– RS AD5520 Figure 7 illustrates the transfer function of the current force mode. external compensation capacitors are added. As mentioned, making an accurate measurement in the fastest time while avoiding overshoots and ringing is the key requirement in any ATE system. This in itself provides challenges. The external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and, while one compensation capacitor value may suit one range, it may not suit other ranges. To optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account. IDUT VCLH RDUT VFIN When selecting a faster settling time, there is a trade-off between the faster settling, overshoots, and ringing. A small compensation value will result in faster settling but may incur penalties in overshoots or ringing at the DUT. Compensation capacitor selection should be optimized to ensure minimum overshoots while still giving good settling time performance. VCLL RDUT While careful selection of the compensation capacitor is required to minimize the settling time, another factor can greatly contribute to the overall settling of the loop if the feedback loop is broken in some manner and the force control amplifier goes to either the positive or negative rails. There is a finite amount of time required for the amplifier to recover from this condition, typically 85 µs, which adds to the settling of the loop. Ensuring that the force control amplifier never goes into saturation is the best solution. This solution can be helped by putting the device into standby mode at any time the operating mode or range selection is changed. In addition, ensure that the selected output range can supply the required current needed by the DUT. VDUT VCLH VCLH VCLH VFIN VCLH PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration to the power supply and the ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5520 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the PMU is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. Figure 7. Current Force Transfer Function Measure Voltage A DUT voltage is tested via the voltage measure amplifier by a window comparator to ensure that CPH and CPL levels are not exceeded. In addition, the DUT voltage is automatically tested against the voltage levels at the clamp, and clamp flags are enabled if the DUT voltage exceeds either of the levels. Short Circuit Protection The AD5520 is designed to withstand a direct short circuit on any of the amplifier outputs. SETTLING TIME CONSIDERATIONS Fast throughput is a key requirement in automatic test equipment because it relates directly to the cost of manufacturing the DUT, thus reducing the time required to make a DAC measurement is of upmost importance. When taking measurements using a PMU, the limiting factor is usually the time it takes the output to settle to the required accuracy so a measurement can be taken. DUT capacitance, measurement accuracy, and the design of the PMU are the major contributors to this time. Figure 8 shows a simplified block diagram of the AD5520 PMU. In brief, the device consists of a force control amplifier, access to a number of selectable sense resistors, a voltage measure instrumentation amplifier, and a current measure instrumentation amplifier. To optimize the performance of the device, there are also nodes provided where This PMU should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF, tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. –14– REV. A AD5520 It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. required, an external amplifier must be used with relays to switch in the different current ranges to the DUT. Other components are also required to make the PMU function. The PMU requires a number of discrete voltage levels: five DAC levels for each PMU used in the system, two levels each for the comparator and clamps, and one voltage level for the AD5520 force input voltage. To utilize the information gathered from the DUT, an ADC (such as the AD7665 16-Bit ADC) must be connected to the MEASOUT pin to convert the measured current or voltage to the digital world for analysis. TYPICAL CONNECTION CIRCUIT FOR THE AD5520 Figure 8 shows the AD5520 connected as it would be in a typical application. The external components required are three compensation capacitors and six sense resistors, depending on how many ranges are required. If high current ranges > 6 mA are 3000pF 1000pF 100pF COMPOUT2 COMPOUT1 COMPOUT0 COMPIN2 COMPIN1 AD5520 COMPIN0 +15V –15V AVEE AVCC AD815 FOH BW SELECT RELAY FOH3 FOH2 FIN FOH1 FOH0 FORCE AMPLIFIER <ⴞ11.5V MEASI5H CLAMP DETECT MEASI4H 3.126⍀ MEASI3H 12.5⍀ MEASI2H CLH 125⍀ MEASI1H CLL 1.25k⍀ MEASI0H REFGND 12.5k⍀ 125k⍀ G = 16 MEASIOUT MEASIL ISENSE INST AMP MEASOUT GUARDIN VSENSE INST AMP G=1 MEASVH G=1 MEASVOUT COMPARATOR CPH GUARD AGND LOGICS DGND CS DVDD QM4 AC0 AC1 CLLDETECT CLHDETECT MOE AM0 AM1 AM2 MSEL FSEL CPSEL STANDBY STB <ⴞ100mV QM5 CPOH CPCK DUT MEASVL CPOH CPL ⱕⴞ11V Figure 8. Typical Configuration of the AD5520 as Used in an ATE Circuit REV. A –15– AD5520 TYPICAL APPLICATION CIRCUIT Figure 9 shows the AD5520 as it would be used in an ATE system. This device could be used as a per pin parametric unit in order to speed up the rate at which testing could be done. It could also be used as a DUT power supply, as shown in the application circuit. The central PMU shown in the block diagram is usually a highly accurate PMU and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices, such as the AD5379, offer a highly integrated solution for a number of these levels. The AD5379 is a dense 40-channel DAC designed with high channel requirements, like ATE in mind. The flexible function of the AD5520 also makes it suited for use in instrumentation applications such as source measure units. Source measure units are programmable instruments capable of sourcing and measuring voltage or current simultaneously. The AD5520 provides a more integrated solution in such equipment. centronics connector to a PC. PC-based software to control the AD5520 is provided as part of the evaluation kit. The evaluation board schematic is shown in Figure 10. Note that VDD and VSS must provide sufficient headroom for the force and measure voltage range. In addition to the supply voltages for the evaluation board, it is also necessary to provide the following voltage levels for the clamp, comparator, and the force input pin—CLL, CLH, CPL, CPH, and FIN. SMB connections are provided for these voltage inputs. To use the evaluation board, it will also be necessary to provide a DUT connected via the gold pins. Both AGND and DGND inputs are provided on the board. The AGND and DGND planes are connected at one location close to the AD5520. It is recommended not to connect AGND and DGND elsewhere in the system to avoid ground loop problems. REFGND is routed back to AGND at the power block to maintain a clean ground reference for accurate measurements. Each supply is decoupled to the relevant ground plane with 10 F and 0.1 F capacitors. The device supply pin is again decoupled with a 10 F and 0.1 F capacitor pair to the relevant ground plane. EVALUATION BOARD FOR THE AD5520 PMU A full featured evaluation kit is available for the AD5520. It consists of an evaluation board with direct hookup via a 36-way Care should be taken when replacing devices to ensure that the pins line up correctly with the PCB pads. CENTRAL PMU DAC GUARD AMP ADC DAC DAC VCH ADC VTERM DAC TIMING DATA MEMORY PPMU VH DAC DEVICE UNDER TEST (DUT) RELAYS TIMING GENERATOR DLL, LOGIC FORMATTER DE-SKEW 50 COAX DRIVER VL DAC VCL DAC DAC COMPARE MEMORY DEVICE POWER SUPPLIES VTH FORMATTER DE-SKEW GUARD AMP GND SENSE DAC COMP VTL ADC DAC ACTIVE LOAD IOL DAC VCOM DAC DAC IOH Figure 9. Typical Application ATE Circuit –16– REV. A C26 0.1F C27 0.1F Figure 10. Evaluation Board Schematic –17– J1–2 J1–3 J1–4 J1–5 J1–6 J1–7 J1–8 J1–9 J1–36 J1–31 J1–1 J1–14 D[0:7] D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 19 18 17 16 15 14 13 12 11 C 1 OE 8 D6 9 D7 D0 D1 D2 D3 D4 D5 74HCT573 U4 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 J1–19 J1–20 J1–21 J1–22 J1–23 J1–24 J1–25 J1–26 J1–27 J1–28 J1–29 J1–30 19 18 17 16 15 14 13 12 U3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 74HCT573 11 C 1 OE 2 3 4 5 6 7 8 9 U2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 J10–2 J10–1 C20 0.1F 20V C21 10F C6 10F C5 0.1F C9, 3.3nF C8, 1nF C7, 100pF 20V C4 10F C3 0.1F +15V COMPIN0 COMPOUT0 COMPIN1 COMPOUT1 COMPIN2 COMPOUT2 CPOH CPOL CHL-DET CLL-DET QM4 QM5 AM0 AM1 AM2 FSEL CPSEL MSEL AC0 AC1 STANDBY STB CPCK MOEB CSB AVCC AVCC_G AVCC_B 20V +5VD J11–3 J11–2 J11–1 3 C24 0.1F C22 0.1F AGND 28 MEASVH NC MEASVL GAURDIN NC GUARD MEASI5H MEASI4H FOH3 MEASI3H FOH2 MEASI2H FOH1 MEASI1H FOH0 MEASIOH MEASIL FOH T12 J2 T4 C25 10F C23 10F 36 35 34 32 31 30 47 46 45 44 43 42 41 40 39 38 37 49 59 REFGND 57 REFGND 58 60 61 62 63 64 1 2 20V C1 0.1F MEASOUT MEASIOUT MEASVOUT FIN CLH CLL CPH CPL DVDD DGND DGND 7 17 26 AVEE 29 AVEE_G 48 AVEE_B 54 51 55 52 56 53 4 5 8 9 10 11 21 20 19 23 25 24 15 16 22 14 6 12 13 27 33 50 DVDD 18 +5VD T5 J3 C14 R12 5k T6 J4 +15V –15V 20V 20V LK1 R1, 124k 74HCT573 11 C 1 OE 2 3 4 5 6 7 8 9 T8 J6 T9 J7 R11 5k AD815ARB U5–A T7 J5 C18 C17 R2, 12.4k D0 D1 D2 D3 D4 D5 D6 D7 R10 R4, 124 C28 0.1F R3, 1.24k +5VD T10 J8 RELAY–G6H 8 9 T11 J9 C19 7 R6 C2 10F R5, 12.4 REV. A R7 U2, U3, U4 BYPASS CAPACITORS 4 2 B RL1 C15 10pF –15V E Q1 C 10 1 20V C11 0.1F C10 10F 7 8 9 QM4 R8 10k D1 RELAY–G6H +15V 20V C13 10F 12 AD815ARB–24 U5–C –VS +VS C12 13 0.1F 3 +5VD 4 3 2 T2 16 15 T1 E Q1 C 10 1 B RL2 14 T3 QM5 R9 10k D2 AD815ARB–24 U5–B C16 10pF +5VD AD5520 AD5520 OUTLINE DIMENSIONS 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters 0.75 0.60 0.45 12.00 BSC SQ 1.60 MAX 64 49 1 48 SEATING PLANE PIN 1 10.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 10ⴗ 6ⴗ 2ⴗ SEATING PLANE 0.20 0.09 VIEW A 7ⴗ 3.5ⴗ 0ⴗ 0.08 MAX COPLANARITY 16 33 32 17 0.50 BSC VIEW A ROTATED 90ⴗ CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BCD –18– REV. A AD5520 Revision History Location Page 10/03—Data Sheet changed from REV. 0 to REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 REV. A –19– –20– C03701–0–10/03(A)