AT91SAM7S256 and AT91SAMS128 Errata Update ® Subject: AT91SAM7S256 and AT91SAMS128 Errata Update Date: November 13th, 2006 Device Part Numbers Affected (all Date Codes) AT91SAM7S256-AU-001 AT91SAM7S128-AU-001 AT91SAM7S256-AU-999 AT91SAM7S128-AU-999 AT91SAM7S256-MU AT91SAM7S128-MU AT91SAM7S256-MU-999 AT91SAM7S128-MU-999 Watchdog Timer (WDT) Under certain rare circumstances, if the Watchdog Timer is used with the Watchdog Reset enabled (WDRSTEN set at 1), the watchdog timer may lock the device in a reset state when the user restarts the watchdog (WDDRSTT). The only way to recover from this state is a power-on reset. The issue depends on the values of WDD and WDV in register WDT_MR. Workaround: Two workarounds are possible. 1) Either do not use the Watchdog Timer with the Watchdog Reset enabled (WDRSTEN set at 1), 2) or set WDD to 0xFFF and in addition use only one of the following values for WDV: 0xFFF, 0xDFF, 0xBFF, 0x9FF, 0x7FF, 0x77F,0x6FF, 0x67F,0x5FF, 0x57F,0x4FF,0x47F,0x3FF,0x37F, 0x2FF, 0x27F, 0x1FF, 0x1BF, 0x17F, 0x13F, 0x0FF, 0x0DF, 0x0BF, 0x09F, 0x07F, 0x06F, 0x05F, 0x04F, 0x03F, 0x037, 0x02f, 0x027, 0x01F, 0x01B, 0x017, 0x013 and 0x00F. Real-time Timer (RTT) Under certain rare circumstances, the Real-time Timer Value (RTT_VR) may be corrupted. Workaround Use RTTINC as an increment for a software counter. Slow clock selected in PMC and a Transition occurs on PA1 Under certain rare circumstances, when CSS=00 in PMC_MCKR, and PA1 is set as an input, and a transition occurs on PA1, device malfunction might occur. Workaround Do not transition PA1 as an input when CSS=00 in PMC_MCKR. IMPORTANT/CONFIDENTIAL: This message is intended only for the use of the individual or entity to which it is addressed. This message contains information from Atmel which may be privileged, confidential, and exempt from disclosure under applicable law. If you have received this communication in error, please notify us immediately. We will be happy to arrange for the return of this message at no cost to you. Atmel Rousset Zone Industrielle 13106 Rousset Cedex France Tel.: (+33) 4 42 53 60 00 Fax.: (+33) 4 42 53 60 01 www.atmel.com Page 1 of 2 AT91SAM7S256 and AT91SAMS128 Errata Update ® Subject: AT91SAM7S256 and AT91SAMS128 Errata Update (cont) Date: November 13th, 2006 Programming CSS in PMC_MCKR register. Under certain rare circumstances , reprogramming the CSS value in the PMC_MCKR register (i.e switching the main clock source) might generate malfunction of the device if the following 2 actions occur simultaneously. 1) Switching from: • PLL Clock to Slow Clock or • PLL Clock to Main Clock or • Main Clock to PLL Clock or • Main Clock to Slow Clock AND 2) Program code is being executed out of flash, OR a transition is occurring on PA1, either as an input or output. Note this issue does not occur when transitioning from slow clock to main clock or from slow clock to PLL clock. Workaround When changing CSS in the PMC_MCKR to switch from • PLL Clock to Slow Clock or • PLL Clock to Main Clock or • Main Clock to PLL Clock or • Main Clock to Slow Clock Ensure that the processor is executing out of SRAM, AND ensure no transition occurs on PA1 either as an input or output, starting from writing to the PMC_MCKR register until MCKRDY=1. IMPORTANT/CONFIDENTIAL: This message is intended only for the use of the individual or entity to which it is addressed. This message contains information from Atmel which may be privileged, confidential, and exempt from disclosure under applicable law. If you have received this communication in error, please notify us immediately. We will be happy to arrange for the return of this message at no cost to you. Atmel Rousset Zone Industrielle 13106 Rousset Cedex France Tel.: (+33) 4 42 53 60 00 Fax.: (+33) 4 42 53 60 01 www.atmel.com Page 2 of 2