4-Channel, 24 GHz, Receiver Downconverter ADF5904 Data Sheet FEATURES GENERAL DESCRIPTION Integrated baluns for single-ended receiver (Rx) inputs and local oscillator (LO) input Rx channel gain: 22 dB Noise figure (NF): 10 dB P1dB: −10 dBm LO input range: −8 dBm to +5 dBm Rx to IF isolation: 30 dB RF signal bandwidth: 250 MHz Rx output impedance: 900 Ω differential LO input buffer: 24 GHz RF and LO S11 at 50 Ω: −5 dB Temperature sensor with analog output: ±5° Electrostatic discharge (ESD) performance Human body model (HBM): 2000 V Charged device model (CDM): 500 V Qualified for automotive applications The ADF5904 is a 4-channel, 24 GHz, receiver downconverter. Each channel contains a single-ended RF input with an on-chip balun followed by a differential low noise amplifier (LNA) and a downconverter mixer with differential output buffers. The RF LO path also has an on-chip balun. Control of the on-chip registers is through a simple 3-wire interface. The ADF5904 comes in a compact 32-lead, 5 mm × 5 mm LFCSP package. APPLICATIONS Automotive radars Industrial radars Microwave (µW) radar sensors FUNCTIONAL BLOCK DIAGRAM ATEST CE AVDD RX1_RF RX2_RF RX3_RF RX4_RF TEMP SENSOR BALUN BALUN BALUN BALUN LNA LNA LNA LNA CLK DATA LE 32-BIT DATA REGISTER DOUT LO_IN BALUN 12885-001 RX4_O RX4_OB RX3_O RX3_OB RX2_O RX2_OB RX1_O GND RX1_OB ADF5904 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF5904 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .......................................................................9 Applications ....................................................................................... 1 Program Modes .............................................................................9 General Description ......................................................................... 1 Register Map ................................................................................... 10 Functional Block Diagram .............................................................. 1 Register 0 ..................................................................................... 11 Revision History ............................................................................... 2 Register 1 ..................................................................................... 12 Specifications..................................................................................... 3 Register 2 ..................................................................................... 12 Timing Characteristics ................................................................ 4 Initialization Sequence .............................................................. 13 Absolute Maximum Ratings............................................................ 5 Temperature Sensor ................................................................... 13 ESD Caution .................................................................................. 5 Application Information ................................................................ 14 Pin Configuration and Function Descriptions ............................. 6 Application of the ADF5904 in FMCW Radar ...................... 14 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 15 Theory of Operation ........................................................................ 9 Ordering Guide .......................................................................... 15 RF Path ........................................................................................... 9 Automotive Products ................................................................. 15 LO Path .......................................................................................... 9 REVISION HISTORY 2/16—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Change to Parameter HBM, Table 3 .............................................. 5 Change to Temperature Sensor Section....................................... 13 Changes to Ordering Guide .......................................................... 15 3/15—Revision 0: Initial Version Rev. A | Page 2 of 15 Data Sheet ADF5904 SPECIFICATIONS AVDD = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −40°C to +105°C. Table 1. Parameter OPERATING CONDITIONS LO and RF Frequency Range LO INPUT Input Return Loss (S11) LO Input Level BASEBAND OUTPUTS Voltage Conversion Gain Demodulation Bandwidth Output DC Offset (Differential) Output Common Mode Output Swing Channel to Channel Phase Mismatch over Temperature DYNAMIC PERFORMANCE, RF = 24.125 GHz Conversion Gain Input P1dB RF Input Return Loss Second-Order Input Intercept Third-Order Input Intercept LO to RF Isolation RF to IF Isolation Noise Figure Noise Figure Under Blocking Conditions LOGIC INPUTS Input Voltage High Low Input Current Input Capacitance LOGIC OUTPUTS Output Voltage High Low Output Current High Low TEMPERATURE SENSOR Analog Accuracy Sensitivity POWER SUPPLIES AVDD Power-Down Current Symbol Min Typ 24 −8 IIP2 IIP3 VIH VIL IINH, IINL CIN 1.4 VOH VDD − 0.4 −5 −5 Max Unit 24.25 GHz +5 dB dBm 22 10 ±20 AVDD − 1.0 2 ±5 dB MHz mV V V peak Degrees 22 −10 −5 20 0 30 30 10 15 dB dBm dB dBm dBm dB dB dB dB 0.6 ±1 10 Measured differentially Maximum capacitance = 10 pF Differential 900 Ω load Terminated in 50 Ω Double sideband (DSB) at 100 kHz With a −30 dBm input interferer at 5 MHz offset from carrier (DSB) V V µA pF V VOL 0.4 V IOH IOL 500 500 µA µA ±5 4.243 °C mV/°C 170 100 mA µA Rev. A | Page 3 of 15 Test Conditions/Comments VDD selected from the DOUT VSEL bit (Bit DB8, Register 0) Following one-point calibration ADF5904 Data Sheet TIMING CHARACTERISTICS AVDD = 3.3 V ± 5%, GND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Operating temperature range is −40°C to +105°C. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN to TMAX 20 10 10 25 25 10 20 10 15 Unit ns min ns min ns min ns min ns min ns min ns min ns max ns max Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width LE setup time to DOUT CLK setup time to DOUT Timing Diagrams t4 t5 CLK t2 DATA t3 DB30 DB31 (MSB) DB1 (CONTROL BIT C2) DB2 (CONTROL BIT C3) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 DB31 (MSB) DOUT DB30 DB0 DB1 12885-002 t8 t9 Figure 2. Timing Diagram 500µA VDD/2 CL 10pF 500µA IOH 12885-003 TO DOUT PIN IOL Figure 3. Load Circuit for DOUT Timing, CL = 10 pF Rev. A | Page 4 of 15 Data Sheet ADF5904 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND RXx_RF, LO_IN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature θJA Thermal Impedance1 (Pad Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar ESD CDM HBM 1 Rating –0.3 V to +3.9 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –40°C to +105°C –65°C to +125°C 150°C 40.83°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 260°C 40 sec 65,100 2280 500 V 2000 V Two signal planes (that is, on the top and the bottom surfaces of the board), two buried planes, and nine vias. Rev. A | Page 5 of 15 ADF5904 Data Sheet 32 31 30 29 28 27 26 25 RX1_O RX1_OB GND LO_IN GND AVDD RX3_OB RX3_O PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADF5904 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND RX3_RF GND AVDD GND RX4_RF GND RX4_O NOTES 1. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE CONNECTED TO GND. 12885-004 RX2_OB LE CLK DATA CE DOUT ATEST RX4_OB 9 10 11 12 13 14 15 16 GND RX1_RF GND AVDD GND RX2_RF GND RX2_O Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 3, 5, 7, 18, 20, 22, 24, 28, 30 2 4, 21, 27 Mnemonic GND Description Ground Pins. RX1_RF AVDD 6 8 9 10 RX2_RF RX2_O RX2_OB LE 11 CLK 12 DATA 13 14 15 16 17 19 23 25 26 29 31 32 CE DOUT ATEST RX4_OB RX4_O RX4_RF RX3_RF RX3_O RX3_OB LO_IN RX1_OB RX1_O EPAD Channel 1 RF Input. Analog Power Supply. The supply range is 3.3 V ± 5%. Place decoupling capacitors (0.1 µF, 1 nF, and 10 pF) to the ground plane as close as possible to this pin. Channel 2 RF Input. Channel 2 Baseband Output. Channel 2 Complementary Baseband Output. Load Enable, CMOS Input. When LE goes high, data stored in the shift registers is loaded into one of the four latches; the control bits select the latch. Serial Clock Input. This serial clock clocks in the serial data to the registers. Data latches into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data loads MSB first and the two LSBs are the control bits. This input is a high impedance CMOS input. Chip Enable. A logic low on this pin powers down the device. Serial Data Output. Analog Test Output Channel 4 Complementary Baseband Output. Channel 4 Baseband Output. Channel 4 RF Input. Channel 3 RF Input. Channel 3 Baseband Output. Channel 3 Complementary Baseband Output. Local Oscillator Input. Channel 1 Complementary Baseband Output. Channel 1 Baseband Output. Exposed Pad. The LFCSP has an exposed pad that must connect to GND. Rev. A | Page 6 of 15 Data Sheet ADF5904 TYPICAL PERFORMANCE CHARACTERISTICS 30 10 CHANNEL GAIN (dB) 0.1 –40 –35 –30 –25 –20 –15 –10 –5 0 0 23.90 23.95 24.00 24.05 24.10 24.15 24.20 24.25 24.30 24.35 RF FREQUENCY (Hz) Figure 8. Channel Gain vs. RF Frequency, Rx Input = −50 dBm, LO Power = −5 dBm, and IF Frequency = 100 kHz 30 25 25 CHANNEL GAIN (dB) 30 20 15 10 –40°C +25°C +105°C 0 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 15 10 0 RF INPUT POWER (dBm) 0 –20 20 15 18 10 16 5 14 NOISE FIGURE (dB) 20 0 –5 –10 –15 –20 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 RF INPUT POWER (dBm) Figure 7. IF Output Power vs. RF Input Power, LO Frequency = 24 GHz at −5 dBm, and IF Frequency = 100 kHz 0 5 12 10 8 6 –40°C +25°C +105°C 2 0 10k 12885-007 –35 –50 –10 –5 LO INPUT POWER (dB) 4 –40°C +25°C +105°C –30 –15 Figure 9. Channel Gain vs. LO Input Power, Rx Input = −50 dBm, LO Frequency = 24 GHz, and IF Frequency = 100 kHz Figure 6. Conversion Gain vs. RF Input Power, LO Frequency = 24 GHz at −5 dBm, and IF Frequency = 100 kHz –25 –40°C +25°C +105°C 5 12885-006 5 20 12885-009 –45 –40°C +25°C +105°C 5 RF INPUT POWER (dBm) CONVERSION GAIN (dB) 10 –40°C +25°C +105°C Figure 5. IF Output Power vs. RF Input Power, LO Frequency = 24 GHz at −5 dBm and IF Frequency = 100 kHz IF OUTPUT POWER (dBm) 15 100k 1M IF FREQUENCY (Hz) 10M 12885-010 0.01 –50 20 12885-008 1 12885-005 IF OUTPUT POWER (V p-p) 25 Figure 10. Noise Figure vs. IF Frequency, LO Frequency = 24.125 GHz at −5 dBm Rev. A | Page 7 of 15 ADF5904 Data Sheet 30 20 OP1dB 15 25 20 –40°C +25°C +105°C 5 GAIN (dB) 0 10 5 –10 1k 10k 100k 1M 0 100 12885-011 –15 10M IF FREQUENCY (Hz) 1M 100k 10M Figure 13. Gain vs. IF Frequency, Rx Power = −50 dBm and LO Frequency = 24 GHz at −5 dBm 1.8 50 40 IIP3 5dBm 1.7 30 1.6 20 10 1.5 0 –10 VATEST (V) OUTPUT POWER (dBm) 10k 1k IF FREQUENCY (Hz) Figure 11. P1dB vs. IF Frequency, LO Frequency = 24 GHz at −5 dBm –20 –30 –40 –50 1.4 1.3 1.2 1.1 –60 1.0 –70 –80 0.9 –90 –35 –30 –25 –20 –15 –10 INPUT POWER (dBm) –5 0 5 10 0.8 12885-012 –100 –40 –40°C +25°C +105°C 12855-013 IP1dB –5 15 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 12. Output Power vs. Input Power, IIP3 LO Frequency = 24.125 GHz at −5 dBm, Rx Frequency = LO + 100 kHz and LO + 200 kHz Rev. A | Page 8 of 15 Figure 14. Temperature Sensor Voltage on ATEST 120 12885-014 P1dB (dBm) 10 Data Sheet ADF5904 THEORY OF OPERATION RF PATH INPUT SHIFT REGISTER The ADF5904 contains four identical 24 GHz downconverter channels. Each channel contains a balun that converts the single-ended input into a differential signal for the rest of the downconverter path (see Figure 15). This balun is followed by a LNA that feeds the downconverter mixer. The ADF5904 digital section includes power-down bits and test modes to read back registers. Data is clocked into the 32-bit input shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the input shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the input shift register. These are the two LSBs (DB1 and DB0, respectively), as shown in Table 5. The truth table for these bits is shown in Table 5. Figure 18 to Figure 20 show a summary of how the latches are programmed. AVDD GND PROGRAM MODES AVDD Table 5 and Figure 18 through Figure 20 show how to set up the program modes in the ADF5904. RXx_RF BALUN Table 5. C2 and C1 Truth Table Control Bits AVDD 2kΩ C2 (DB1) 0 0 1 1 2kΩ 12885-015 GND Figure 15. RF Input Stage LO PATH The four downconverter channels share the same LO path. The LO path contains a balun that converts the single-ended input to a differential signal to drive the mixer (see Figure 16). AVDD GND AVDD 20Ω 20Ω 400Ω 400Ω LO_IN BALUN AVDD 12885-016 GND Figure 16. LO Input Stage Rev. A | Page 9 of 15 C1 (DB0) 0 1 0 1 Register R0 R1 R2 R3 ADF5904 Data Sheet REGISTER MAP DOUT VSEL LO PIN BIAS PUP LO PUP CH1 PUP CH2 RESERVED PUP CH3 PUP CH4 REGISTER 0 (R0) CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC4 PC3 PC2 PC1 PLO LPB DIO 1 0 1 0 0 DB2 0 DB1 DB0 C2(0) C1(0) REGISTER 1 (R1) CHANNEL SELECT CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 CS2 CS1 CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 DB2 0 DB1 DB0 C2(0) C1(1) REGISTER 2 (R2) 5-BIT CHANNEL TEST SELECT RESERVED CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 DB2 1 DB1 DB0 C2(1) C1(0) REGISTER 3 (R3) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17. Latch Summary Rev. A | Page 10 of 15 0 0 0 0 0 0 0 0 0 0 DB2 0 DB1 DB0 C2(1) C1(1) 12885-017 CONTROL BITS RESERVED Data Sheet ADF5904 DOUT VSEL LO_IN PIN BIAS PUP LO PUP CH1 PUP CH3 PUP CH4 RESERVED PUP CH2 REGISTER 0 (R0) CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC4 0 1 0 0 PC4 PC3 PC2 PC1 PLO LPB DIO 1 0 1 0 0 DB2 0 DB1 DB0 C2(0) C1(0) PUP CH4 POWER DOWN POWER UP PC3 0 1 PUP CH3 POWER DOWN POWER UP PC2 0 1 PUP CH2 POWER DOWN POWER UP PC1 PUP CH1 0 1 POWER DOWN POWER UP PLO 0 1 DIO PUP LO 0 1 POWER DOWN POWER UP LPB 0 1 DOUT VSEL 3.3V 1.8V LO_IN PIN BIAS NO DC BIAS 1.5V DC BIAS 12885-018 1 Figure 18. Register 0 REGISTER 0 PUP CH1 Register 0 Control Bits With Bits[C2:C1] set to 00, Register R0 is programmed. Figure 18 shows the input data format for programming this register. DB11 provides the power-up bit for RF Receiver Channel 1. Setting this bit to 0 performs a power-down of Channel 1 blocks. Setting this bit to 1 returns Channel 1 blocks to normal operation. DOUT VSEL PUP CH2 DB8 controls the DOUT logic levels. Set this bit to 0 to set the DOUT logic level to 3.3 V, and set this bit to 1 to sets the DOUT logic level to 1.8 V. DB12 provides the power-up bit for RF Receiver Channel 2. Set this bit to 0 to power down the Channel 2 blocks, and set this bit to 1 to return the Channel 2 blocks to normal operation. LO_IN Pin Bias PUP CH3 DB9 controls the dc bias voltage on the LO_IN pin (Pin 29). Set this bit to 0 to set no dc bias on the LO_IN pin, and set this bit to 1 to set the dc bias to 1.5 V. AC couple the LO signal to the LO_IN pin. DB13 provides the power-up bit for RF Receiver Channel 3. Set this bit to 0 to power down the Channel 3 blocks, and set this bit to 1 to return the Channel 3 blocks to normal operation. PUP LO DB14 provides the power-up bit for RF Receiver Channel 4. Set this bit to 0 to power down the Channel 4 blocks, and set this bit to 1 to return the Channel 4 blocks to normal operation. DB10 provides the power-up bit for the LO block. Set this bit to 0 to power down the LO block, and set this bit to 1 to return the LO block to normal operation. PUP CH4 Rev. A | Page 11 of 15 ADF5904 Data Sheet REGISTER 1 (R1) CHANNEL SELECT CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 CS1 CS0 CS2 CS1 CS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 DB1 DB0 C2(0) C1(1) CHANNE L SELECT NONE CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 LO RESERVED RESERVED 12885-019 CS2 DB2 Figure 19. Register 1 REGISTER 2 (R2) 5-BIT CHANNEL TEST SELECT CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 TC4 TC3 TC2 TC1 TC0 0 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 0 1 0 1 x 0 0 0 0 0 0 DB2 1 DB1 DB0 C2(1) C1(0) CHANNEL TEST SELECT NONE SELECTED TEMPERATURE SENSOR TO ATEST RESERVED RESERVED RESERVED REGISTER 0 READBACK REGISTER 1 CHANNEL 1 READBACK REGISTER 1 CHANNEL 2 READBACK REGISTER 1 CHANNEL 3 READBACK REGISTER 1 CHANNEL 4 READBACK REGISTER 1 LO READBACK REGISTER 2 READBACK RESERVED RESERVED 12855-020 RESERVED Figure 20. Register 2 REGISTER 2 REGISTER 1 Register 1 Control Bits Register 2 Control Bits With Bits[C2:C1] set to 01, Register R1 is programmed. Register 1 contains the internal controls for the four RF channels and the LO path. During the initialization sequence, the default conditions are loaded. See Step 3 to Step 7 in Table 6. With Bits[C2:C1] set to 10, Register R2 is programmed. Figure 20 shows the input data format for programming this register. 5-Bit Channel Test Select Bits[DB14:DB10] control the ADF5904 test modes. These bits allow access to the temperature sensor on the ATEST pin and the register readback on the DOUT pin. See Figure 20 for the truth table. Rev. A | Page 12 of 15 Data Sheet ADF5904 INITIALIZATION SEQUENCE TEMPERATURE SENSOR After powering up the device, administer the initialization sequence in Table 6 to set the register with the code to configure the device. The on-chip temperature sensor of the ADF5904 is accessed on the ATEST pin. The temperature sensor operates over the full operating temperature range of −40°C to +105°C. To improve accuracy, conduct a one-point calibration at room temperature and store the result in the external memory. Convert the ATEST voltage to temperature by using the following equation: Table 6. Initialization Sequence Step 1 2 3 4 5 6 7 8 Register R3 R2 R1 R1 R1 R1 R1 R0 Hex Code 0x00000003 0x00020406 0x20001499 0x40001499 0x60001499 0x80001499 0xA0000019 0x80007CA0 Description Reserved Temperature sensor to ATEST Configure Channel 1 Configure Channel 2 Configure Channel 3 Configure Channel 4 Configure LO Power up Temperature (°C) = (VATEST − VOFF)/VGAIN where: VATEST is the voltage on the ATEST pin. VOFF is the offset voltage and it is 1.212 V. VGAIN is the voltage gain and it is 4.072e−3. Rev. A | Page 13 of 15 ADF5904 Data Sheet APPLICATION INFORMATION APPLICATION OF THE ADF5904 IN FMCW RADAR Figure 21 shows the application of the ADF5904 in a frequency modulated continuous wave (FMCW) radar system. In the FMCW radar system, the ADF4159 generates the sawtooth or triangle ramps necessary for this type of radar to operate. The ADF4159 controls the VTUNE pin on the transceiver (Tx) monolithic microwave integrated circuit (MMIC) and thus the frequency of the voltage controlled oscillator (VCO) and the Tx output signal on TXOUT1 or TXOUT2. The LO signal from the Tx MMIC is fed to the LO input on the ADF5904. The ADF5904 downconverts the signal from the four receiver antennas to baseband with the LO signal from the Tx MMIC. The downconverted baseband signals from the four receiver channels on the ADF5904 are fed to the ADAR7251 4-channel, continuous time (CT), sigma-delta (Σ-Δ) analog-to-digital converter (ADC). A digital signal processor (DSP) follows the ADC to handle the target information processing. LOOP FILTER CP ADF4159 VTUNE RFINA AUX RFINB AUX TX_MMIC TXOUT1 TXOUT2 LO_OUT DSP ADAR7251 RX BASEBAND ADF5904 RX1_RF RX2_RF RX3_RF RX4_RF Figure 21. FMCW Radar with ADF5904 Rev. A | Page 14 of 15 12885-021 LO_IN Data Sheet ADF5904 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 3.60 SQ 3.55 EXPOSED PAD 17 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADF5904WCCPZ ADF5904WCCPZ-RL7 ADF5904ACPZ ADF5904ACPZ-RL7 EV-ADF5904SD2Z 1 2 Temperature Range –40°C to + 105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADF5904W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12885-0-2/16(A) Rev. A | Page 15 of 15