Fractional-N / Integer-N PLL Synthesizer ADF4150 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer-N synthesizer Programmable divide-by-1/2/4/8 or 16 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast-lock mode Cycle slip reduction The ADF4150 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external Voltage Controlled Oscillator (VCO), loop filter and external reference frequency. The ADF4150 is for use with external VCO parts and is software compatible with the ADF4350. The VCO frequency can be divided-by 1/2/4/8 or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation the RF output stage can be muted. The mute function is both pin and software controllable. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless infrastructure (WCDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock Generation The ADF4150 is available in a 4mm x 4mm package. FUNCTIONAL BLOCK DIAGRAM SDV DD AV DD DVDD VP RSET A D F4150 REFIN ×2 DOUBLER 10-BIT R COUNTER MUXOUT MULTIPLEXER ÷2 DIVIDER FLO SWITCH LOCK DETECT CLK DATA SW LD DATA REGISTER FUNCTION LATCH LE CHARGE PUMP CPOUT PHASE COMPARATOR INTEGER REG FRACTION REG DIVIDE BY 1/2/4/8/16 MODULUS REG OUTPUT STAGE RFOUT+ RFOUT– PDBRF THIRD-ORDER FRACTIONAL INTERPOLATOR RF INPUT M U L T IP L E X E R RFIN+ RFIN– N COUNTER CE AGND DGND CPGND SDGND Figure 1. Rev. PrI Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Preliminary Technical Data ADF4150 TABLE OF CONTENTS Features .............................................................................................. 1 Register 2 ..................................................................................... 16 Applications....................................................................................... 1 Register 3 ..................................................................................... 17 General Description ......................................................................... 1 Register 4 ..................................................................................... 18 Functional Block Diagram .............................................................. 1 Register 5 ..................................................................................... 18 Specifications..................................................................................... 3 Initialization Sequence .............................................................. 18 Timing Characteristics..................................................................... 5 RF Synthesizer— A Worked Example ..................................... 19 Absolute Maximum Ratings............................................................ 6 Modulus....................................................................................... 19 Transistor Count........................................................................... 6 Reference Doubler and Reference Divider ............................. 19 ESD Caution.................................................................................. 6 12-Bit Programmable Modulus................................................ 19 Pin Configuration and Function Descriptions............................. 7 Cycle Slip Reduction for Faster Lock Times........................... 20 Typical Performance Characteristics ............................................. 9 Spurious Optimization and Fast lock ...................................... 20 Circuit Description......................................................................... 10 Fast-Lock Timer and Register Sequences ............................... 20 Reference Input Section............................................................. 10 Fast Lock—An Example ............................................................ 20 RF N Divider............................................................................... 10 Fast Lock—Loop Filter Topology............................................. 20 INT, FRAC, MOD and R Counter Relationship .................... 10 Spur Mechanisms ....................................................................... 21 INT N MODE ............................................................................. 10 Spur Consistency and Fractional Spur Optimization ........... 21 R Counter .................................................................................... 10 PHASE Resync............................................................................ 21 Phase Frequency Detector (PFD) and Charge Pump............ 10 Applications Information .............................................................. 23 MUXOUT and LOCK Detect................................................... 11 Direct Conversion Modulator .................................................. 23 Input Shift Registers................................................................... 11 Interfacing ................................................................................... 24 Program Modes .......................................................................... 11 PCB Design Guidelines for Chip Scale Package .................... 24 Output Stage................................................................................ 11 Output Matching ........................................................................ 25 Register Maps .................................................................................. 12 Outline Dimensions ....................................................................... 26 Register 0 ..................................................................................... 16 Ordering Guide .......................................................................... 26 Register 1 ..................................................................................... 16 Rev. PrI | Page 2 of 27 ADF4150 Preliminary Technical Data SPECIFICATIONS AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 1. Parameter REFIN CHARACTERISTICS Input Frequency Input Sensitivity Input Capacitance Input Current RF INPUT CHARACTERISTICS RF Input Frequency (RFIN) PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source High Value Low Value RSET Range Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output High Current, IOH Output Low Voltage, VO POWER SUPPLIES AVDD DVDD, SDVDD, VP DIDD + AIDD3 Output Dividers IRFOUT3 Low Power Sleep Mode RF OUTPUT CHARACTERISTICS Minimum output frequency using RF output dividers Maximum RFIN frequency using RF output dividers Harmonic Content (Second) Harmonic Content (Third) Harmonic Content (Second) Harmonic Content (Third) Output Power 4 Output Power Variation B Version Unit Conditions/Comments 10 to 250 0.7 to AVDD 5.0 ±60 MHz min to MHz max V p-p min to V p-p max pF max µA max For f < 10 MHz ensure slew rate > 21 V/µs Biased at AVDD/21 0.5/4.0 4.0/6.0 GHz min/max GHz min/max −10 dBm/0 dBm minimum/maximum −5 dBm/0 dBm minimum/maximum For lower frequencies, ensure slew rate > 400 V/µs 32 MHz max 5 0.312 2.7 to 10 2 1.5 2 mA typ mA typ kΩ min to kΩ max % typ % typ % typ 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD − 0.4 500 0.4 V min µA max V max 3.0 to 3.6 AVDD AVDD/5.5 25 6-24 32 7 V min to V max V min/V max mA typ mA typ mA typ µA typ 31.25 MHz 3500 MHz −19 - 13 −20 - 10 −4 to +5 ±1 dBc typ dBc typ dBc typ dBc typ dBm typ min to dBm typ max dB typ With RSET = 5.1 kΩ 0.5 V ≤ VCP ≤ VP - 0.5 V 0.5 V ≤ VCP ≤ VP - 0.5 V VCP = 2.0 V CMOS output chosen IOL = 500 µA Each output divide by two consumes 6 mA RF output stage is programmable 500 MHz VCO input and divide by 16 selected Rev. PrI | Page 3 of 27 Fundamental VCO output Fundamental VCO output Divided VCO output Divided VCO output Programmable in 3 dB steps Preliminary Technical Data Parameter NOISE CHARACTERISTICS Normalized In-Band Phase Noise Floor5 Normalized In-Band Phase Noise Floor6 Spurious Signals Due to PFD Frequency Level of Signal With RF Mute Enabled ADF4150 B Version Unit Conditions/Comments −219 dBc/Hz typ Anti-backlash pulse width set to 6 ns. −222 dBc/Hz typ Anti-backlash pulse width set to 3 ns. −70 dBc typ −40 dBm typ 1 AC coupling ensures AVDD/2 bias. Guaranteed by design. Sample tested to ensure compliance. TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 2.5 GHz. 4 Using 50 Ω resistors to VVCO, into a 50 Ω load. 5 This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 + 10log(fPFD) + 20 logN . The value given is the lowest noise mode. fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 50 kHz; VCO frequency = 1850.1 MHz. N = 74; loop BW = 500 kHz, ICP = 2.5 mA; low noise mode. The noise was measured with an EVAL-ADF4150EB1Z and the Agilent E5052A signal source analyzer. 6 This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output use the following formula: −213 + 10log(fPFD) + 20 logN . The value given is the lowest noise mode. fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 50 kHz; VCO frequency = 1850 MHz. N = 74; loop BW = 500 kHz, ICP = 2.5 mA; low noise mode. The noise was measured with an EVAL-ADF4150EB1Z and the Agilent E5052A signal source analyzer. 2 3 Rev. PrI | Page 4 of 27 ADF4150 Preliminary Technical Data TIMING CHARACTERISTICS AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width t5 CLOCK t2 DATA DB31 (MSB) t3 DB30 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 07325-002 t6 LE Figure 2. Timing Diagram Rev. PrI | Page 5 of 27 ADF4150 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance (Paddle-Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 27.3°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TRANSISTOR COUNT 23380 (CMOS) and 809 (bipolar) ESD CAUTION 260°C 40 sec GND = AGND = DGND = 0 V Rev. PrI | Page 6 of 27 Preliminary Technical Data ADF4150 24 23 22 21 20 19 RSET SDGND SDVDD MUXOUT LD REFIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADF4150 TOP VIEW 18 17 16 15 14 13 DVDD PDBRF AVDD2 RFOUT+ RFOUT− AGND CP 7 CPGND 8 AVDD1 9 RFIN+ 10 RFIN− 11 AGND 12 CLK DATA LE CE SW VP Figure 3. Pin Configuration, 24 lead 4mm x 4 mm Table 4. Pin Function Descriptions Pin No. 1 Mnemonic CLK 2 DATA 3 LE 4 CE 5 6 SW VP 7 CP 8 9 CPGND AVDD1 10 11 RFIN+ RFIN− 12,13 14 AGND RFOUT− 15 RFOUT+ 16 AVDD2 17 18 PDBRF DVDD 19 REFIN 20 LD 21 MUXOUT Function Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the three LSBs. Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. Taking the pin high powers up the device depending on the status of the power-down bits. Fastlock Switch. A connection should be made from the loop filter to this pin when using the fastlock mode. Charge Pump Power Supply. This should be greater than or equal to AVDD. In systems where AVDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the external VCO. Charge Pump Ground. This is the ground return pin for CPOUT. Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. AVDD must have the same value as DVDD. Input to the RF Input. This small signal input is ac-coupled to the external VCO. Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Analog Ground. This is a ground return pin for AVDD1 and AVDD2. Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided down version is available. RF Output. The output level is programmable. The VCO fundamental output or a divided down version is available. Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. AVDD2 must have the same value as DVDD. RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable. Digital Power Supply. Should be the same voltage as AVDD. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Lock Detect output pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock. Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Rev. PrI | Page 7 of 27 ADF4150 Pin No. 22 Mnemonic SDVDD 23 24 SDGND RSET Preliminary Technical Data Function Power Supply Pin for the Digital Σ-∆ Modulator. Should be the same voltage as AVDD. Decoupling capacitors to the ground plane are to be placed as close as possible to this pin. Digital Σ-∆ Modulator Ground. Ground return path for the Σ-∆ Modulator. Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is I CP = 25.5 R SET where RSET = 5.1 kΩ, ICP = 5 mA. Rev. PrI | Page 8 of 27 Preliminary Technical Data ADF4150 TYPICAL PERFORMANCE CHARACTERISTICS –0000 –0000 –0000 –0000 ALL CAPS (Initial cap) ALL CAPS (Initial cap) –0000 TBD –0000 TBD –0000 –0000 –000 –000 –000 ALL CAPS (Initial cap) –000 –0000 –000 00000-0-000 00000-0-000 –0000 –000 –0000 –0000 ALL CAPS (Initial cap) –0000 TBD –0000 TBD –000 ALL CAPS (Initial cap) –000 –0000 –000 00000-0-000 00000-0-000 –000 –000 –000 Figure 6. –000 ALL CAPS (Initial cap) –000 –000 Figure 7. –0000 –0000 –0000 ALL CAPS (Initial cap) –0000 –0000 –000 –0000 –0000 –0000 –000 –000 Figure 5. –0000 TBD –0000 TBD –0000 –0000 –000 –000 –000 ALL CAPS (Initial cap) –000 –000 Figure 8. –0000 –000 00000-0-000 –0000 00000-0-000 ALL CAPS (Initial cap) ALL CAPS (Initial cap) Figure 4 –0000 –000 ALL CAPS (Initial cap) –000 –000 –000 ALL CAPS (Initial cap) Figure 9. Rev. PrI | Page 9 of 27 –000 –000 ADF4150 Preliminary Technical Data CIRCUIT DESCRIPTION REFERENCE INPUT SECTION RF N DIVIDER The reference input stage is shown in Figure 5. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. TO PFD N COUNTER THIRD ORDER FRACTIONAL INTERPOLATOR POWER-DOWN CONTROL MOD REG FRAC VALUE 07325-006 INT REG 100kΩ SW2 TO R COUNTER REFIN NC Figure 11. RF INT Divider BUFFER SW1 INT N MODE 07325-005 SW3 NO If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the synthesizer operates in integer-N mode. The DB8 in Register 2 (LDF) should be set to 1 to get integer-N digital lock detect. Figure 10. Reference Input Stage RF N DIVIDER The RF N divider allows a division ratio in the PLL feedback path. Division ratio is determined INT, FRAC and MOD values, which build up this divider. INT, FRAC, MOD AND R COUNTER RELATIONSHIP The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. See the RF Synthesizer—A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = fPFD × (INT + (FRAC/MOD)) (1) where RFOUT is the output frequency of external voltage controlled oscillator (VCO). fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2) where REFIN is the reference input frequency. D is the REFIN doubler bit. T is the REFIN divide-by-2 bit (0 or 1). R is the preset divide ratio of the binary 10–bit programmable reference counter (1 to 1023). INT is the preset divide ratio of the binary 16–bit counter (23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler). MOD is the preset fractional modulus (2 to 4095). FRAC is the numerator of the fractional division (0 to MOD − 1). R COUNTER The 10–bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 1023 are allowed. PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The Phase Frequency Detector (PFD) takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 12 is a simplified schematic of the phase frequency detector. The PFD includes a programmable delay element that sets the width of the anti-backlash pulse, which can be either 6 ns (default) or 3 ns (for integer-N mode). This pulse ensures there is no dead zone in the PFD transfer function, and gives a consistent reference spur level. HI D1 Q1 UP U1 +IN CLR1 DELAY HI U3 CHARGE PUMP CLR2 DOWN D2 Q2 U2 –IN Figure 12. PFD Simplified Schematic Rev. PrI | Page 10 of 27 CP 07325-007 NC N = INT + FRAC/MOD FROM VCO OUTPUT/ OUTPUT DIVIDERS Preliminary Technical Data ADF4150 MUXOUT AND LOCK DETECT Table 5. C3, C2 and C1 Truth Table The output multiplexer on the ADF4150 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 18). Figure 13 shows the MUXOUT section in block diagram form. C3 0 0 0 0 1 1 DVDD THREE-STATE-OUTPUT C1 0 1 0 1 0 1 Register Register 0 (R0) Register 1 (R1) Register 2 (R2) Register 3 (R3) Register 4 (R4) Register 5 (R5) OUTPUT STAGE DVDD DGND R COUNTER OUTPUT Control Bits C2 0 0 1 1 0 0 MUX CONTROL MUXOUT N COUNTER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT DGND 07325-008 RESERVED Figure 13. MUXOUT Schematic INPUT SHIFT REGISTERS The ADF4150 digital section includes a 10–bit RF R counter, a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit modulus counter. Data is clocked into the 32–bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of six latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2 and C1) in the shift register. These are the 3 LSBs, DB2, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Figure 19 shows a summary of how the latches are programmed. The RFOUT+ and RFOUT- pins of the ADF4150 family are connected to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 14. To allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may be set. These levels give output power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to VDD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see Output Matching Section)If the outputs are used individually, the optimum output stage consists of a shunt inductor to VDD. Another feature of the ADF4150 family is that the supply current to the RF output stage can be shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in Register 4 (R4). RFOUT+ RFOUT- PROGRAM MODES A number of settings in the ADF4150 are double buffered. These include the modulus value, phase value, R counter value, reference doubler, reference divide-by-2, and current setting. This means that two events have to occur before the part uses a new value of any of the double buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0. For example, any time the modulus value is updated, Register 0 (R0) must be written to, to ensure the modulus value is loaded correctly. Divider select in Register 4 (R4) is also double buffered, but only if DB13 of Register 2 (R2) is high. Rev. PrI | Page 11 of 27 MUX BUFFER/ DIVIDE-BY 1/2/4/8/16 07325-010 Table 5 and Figure 11 through Figure 21 show how the program modes are to be set up in the ADF4150. Figure 14. Output Stage ADF4150 Preliminary Technical Data REGISTER MAPS RESERVED REGISTER 0 16-BIT INTEGER VALUE (INT) CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) PRESCALER REGISTER 1 RESERVED DBR1 12-BIT PHASE VALUE (PHASE) CONTROL BITS DBR 1 12-BIT MODULUS VALUE (MOD) P1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 DB2 DB1 DB0 M3 M2 M1 C3(0) C2(0) C1(1) COUNTER RESET 0 CP THREESTATE 0 PD 0 LDP 0 PD POLARITY DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 CONTROL BITS DBR1 CURRENT SETTING LDF DBR 1 10-BIT R COUNTER DOUBLE BUFF MUXOUT NOISE MODE RDIV2 REFERENCE DOUBLER DBR 1 RESERVED REGISTER 2 DBR 1 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 DB2 DB1 DB0 C3(0) C2(1) C1(0) RESERVED RESERVED RESERVED CSR ABP CHARGE CANCEL REGISTER 3 CLK DIV MODE CONTROL BITS 12-BIT CLOCK DIVIDER VALUE 0 0 0 0 0 0 0 0 0 F3 F2 V2 V1 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 RF OUTPUT ENABLE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 D1 OUTPUT POWER DB2 DB1 DB0 C3(0) C2(1) C1(1) FEEDBACK SELECT REGISTER 4 DBB 2 DIVIDER SELECT MTLD RESERVED RESERVED RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 D13 D12 D11 D10 0 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 CONTROL BITS DB2 DB1 DB0 C3(1) C2(0) C1(0) LD PIN MODE RESERVED RESERVED CONTROL BITS DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 1DBR 2DBB 0 0 0 0 0 0 0 D15 D14 0 1 1 0 0 0 0 0 0 0 0 0 0 = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0. = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH. Figure 15. Register Summary Rev. PrI | Page 12 of 27 0 0 0 0 0 0 DB2 DB1 DB0 C3(1) C2(0) C1(1) 07325-011 RESERVED RESERVED REGISTER 5 RESERVED Preliminary Technical Data ADF4150 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 DB7 DB6 DB5 DB4 F5 F4 F3 F2 DB3 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) N16 N15 ... N5 N4 N3 N2 N1 INTEGER VALUE (INT) F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC) 0 0 ... 0 0 0 0 0 NOT ALLOWED 0 0 .......... 0 0 0 0 0 ... 0 0 0 0 1 NOT ALLOWED 0 0 .......... 0 1 1 0 0 ... 0 0 0 1 0 NOT ALLOWED 0 0 .......... 1 0 2 . . ... . . . . . ... 0 0 .......... 1 1 3 0 0 ... 1 0 1 1 0 NOT ALLOWED . . .......... . . . 0 0 ... 1 0 1 1 1 23 . . .......... . . . 0 0 ... 1 1 0 0 0 24 . . .......... . . . . . ... . . . . . ... 1 1 .......... 0 0 4092 1 1 ... 1 1 1 0 1 65533 1 1 .......... 0 1 4093 1 1 ... 1 1 1 1 0 65534 1 1 .......... 1 0 4094 1 1 ... 1 1 1 1 1 65535 1 1 ......... 1 1 4095 07325-012 0 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) INTmin = 75 with prescaler = 8/9 PRESCALER Figure 16. Register 0 (R0) RESERVED 12-BIT PHASE VALUE (PHASE) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 P1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 DB7 DB6 DB5 DB4 M5 M4 P1 PRESCALER P12 P11 .......... P2 P1 PHASE VALUE (PHASE) M12 M11 .......... M2 M1 0 4/5 0 0 .......... 0 0 0 0 0 .......... 1 0 1 8/9 0 0 .......... 0 1 1 (RECOMMENDED) 0 0 .......... 1 1 3 0 0 .......... 1 0 2 . . .......... . . . 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 . . .......... . . . 1 1 .......... 0 1 4093 . . .......... . . . 1 1 .......... 1 0 4094 1 1 .......... 0 0 4092 1 1 .......... 1 1 4095 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 M3 M2 DB3 M1 DB2 DB1 DB0 C3(0) C2(0) C1(1) INTERPOLATOR MODULUS (MOD) 2 07325-013 0 CONTROL BITS 12-BIT MODULUS VALUE (MOD) Figure 17. Register 1 (R1) Rev. PrI | Page 13 of 27 COUNTER RESET CP THREESTATE PD CURRENT SETTING PD POLARITY LDF 10-BIT R COUNTER LDP MUXOUT RDIV2 NOISE MODE DOUBLE BUFF Preliminary Technical Data REFERENCE DOUBLER RESERVED ADF4150 DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 L2 L1 M3 M2 M1 RD2 RD1 R10 L1 L2 NOISE MODE RD2 REFERENCE DOUBLER 0 0 LOW NOISE MODE 0 DISABLED 0 1 RESERVED 1 ENABLED 1 0 RESERVED 1 1 LOW SPUR MODE R10 R9 R8 R7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.31 0.63 0.94 1.25 1.56 1.88 2.19 2.50 2.81 3.13 3.44 3.75 4.06 4.38 4.69 5.00 0 1 1 0 2 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 1020 1 1 .......... 0 1 1021 1 1 .......... 1 0 1022 1 1 .......... 1 1 1023 DVDD 1 0 DGND 0 1 1 R DIVIDER OUTPUT 1 0 0 N DIVIDER OUTPUT 1 0 1 ANALOG LOCK DETECT 1 1 0 DIGITAL LOCK DETECT 1 1 1 RESERVED 1 OUTPUT U3 U2 U1 DB2 DB1 DB0 C3(0) C2(1) C1(0) COUNTER RESET 0 DISABLED INT-N 1 ENABLED 1 CP1 U4 U1 ENABLED 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 U5 LDF DISABLED CP2 U6 FRAC-N 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CP1 U6 0 CP3 R DIVIDER (R) CP2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 .......... 0 DOUBLEBUFFER R4 DB22-20 CP4 .......... 1 CP3 ENABLED 0 0 CP4 DISABLED 0 M1 D1 1 0 M2 R1 0 0 0 R2 ICP (mA) 5.1kΩ R1 0 R3 REFERENCE DIVIDE BY 2 R2 0 R4 RD1 .......... 0 R5 D1 R9 M3 R6 CONTROL BITS U5 LDP U2 CP THREE-STATE 0 10ns 0 DISABLED 1 6ns 1 ENABLED U4 PD POLARITY U3 POWER DOWN 0 NEGATIVE 0 DISABLED 1 POSITIVE 1 ENABLED 07325-014 THREE-STATE OUTPUT CLK DIV MODE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 F3 F2 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 DB7 DB6 D5 .......... D2 D1 CLOCK DIVIDER VALUE 0 .......... 0 0 0 0 DISABLED 0 0 .......... 0 1 1 1 ENABLED 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 0 0 CLOCK DIVIDER OFF 1 1 .......... 0 0 4092 0 1 FASTLOCK ENABLE 1 1 .......... 0 1 4093 1 0 RESYNC ENABLE 1 1 .......... 1 0 4094 1 1 RESERVED 1 1 .......... 1 1 4095 F2 CHARGE CANCELLATION 0 DISABLED 1 ENABLED 6 ns (FRAC-N) 3 ns (INT_N) D1 D11 CLOCK DIVIDER MODE 1 D2 0 C1 0 D3 DB3 D12 C2 ANTI-BACKLASH PULSE WIDTH D4 DB5 DB4 CYCLE SLIP REDUCTION F1 F3 CONTROL BITS 12-BIT CLOCK DIVIDER VALUE Figure 19. Register 3 (R3) Rev. PrI | Page 14 of 27 DB2 DB1 DB0 C3(0) C2(1) C1(1) 07325-015 RESERVED CSR RESERVED RESERVED CHARGE CANCEL ABP Figure 18. Register 2 (R2) OUTPUT DIVIDER SELECT RESERVED RF OUTPUT ENABLE RESERVED ADF4150 MTLD FEEDBACK SELECT Preliminary Technical Data RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 0 0 0 0 0 0 0 D13 D12 D11 D10 0 0 0 0 0 0 0 0 0 D8 0 0 0 0 D3 FEEDBACK D13 SELECT 0 DIVIDED FUNDAMENTAL D12 D11 D10 RF DIVIDER SELECT 0 0 0 /1 0 0 1 /2 0 1 0 /4 0 1 1 /8 1 0 0 /16 D8 MUTE TILL LOCK DETECT 0 MUTE DISABLED 1 MUTE ENABLED D3 RF OUT 0 DISABLED 1 ENABLED D2 D1 DB2 DB1 DB0 C3(1) C2(0) C1(0) D2 D1 OUTPUT POWER 0 0 -4 0 1 -1 1 0 +2 1 1 +5 07325-016 1 CONTROL BITS OUTPUT POWER LD PIN MODE RESERVED RESERVED Figure 20. Register 4 (R4) CONTROL BITS RESERVED RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 D15 D14 0 1 D1 5 D1 4 LOCK DETECT PIN OPERATION 0 0 LOW 0 1 DIGITAL LOCK DETECT 1 0 LOW 1 1 HIGH 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB2 DB1 DB0 C3(1) C2(0) C1(1) 07325-017 0 DB3 Figure 21. Register 5 (R5) Rev. PrI | Page 15 of 27 ADF4150 Preliminary Technical Data REGISTER 0 12-Bit PHASE Value Control Bits These bits control what is loaded as the PHASE word. The word must be less than the MOD value programmed in Register 1. The word is used to program the RF output phase from 0° to 360° with a resolution of 360°/MOD. See the PHASE Resync section for more information. In most applications, the phase relationship between the RF signal and the reference is not important. In such applications, the PHASE value can be used to optimize the fractional and subfractional spur levels. See the Spur Consistency and Fractional Spur Optimization section for more information. With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed. Figure 16 shows the input data format for programming this register. 16-Bit INT Value These sixteen bits set the INT value, which determines the integer part of the feedback division factor. It is used in Equation 1 (see the INT, FRAC, MOD and R Counter Relationship section). All integer values from 23 to 65,535 are allowed for 4/5 prescaler. For 8/9 prescaler, the minimum integer value is 75. 12-Bit FRAC Value The 12 FRAC bits set the numerator of the fraction that is input to the Σ-Δ modulator. This, along with INT, specifies the new frequency channel that the synthesizer locks to, as shown in the RF Synthesizer—A Worked Example section. FRAC values from 0 to MOD − 1 cover channels over a frequency range equal to the PFD reference frequency. This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. Please refer to the RF Synthesizer—A Worked Example section for more information. Control Bits Control bits With Bits [C3:C1] set to 0, 0, 1, Register 1 is programmed. Figure 17 shows the input data format for programming this register. Prescaler Value The dual modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the VCO output to the PFD input. Operating at CML levels, it takes the clock from the VCO output and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4150 above 3 GHz, this must be set to 8/9. The prescaler limits the INT value, where: In the ADF4150 P1 in Register 1 sets the prescaler values. 12-Bit Interpolator MOD Value REGISTER 2 REGISTER 1 P = 4/5, NMIN = 23 P = 8/9, NMIN = 75 If neither the PHASE resync nor the spurious optimization functions are being used, it is recommended the PHASE word be set to 1. With Bits [C3:C1] set to 0, 1, 0, Register 2 is programmed. Figure 18 shows the input data format for programming this register. Noise and Spur Modes The noise modes on the ADF4150 are controlled by DB30 and DB29 in Register 2 (see Figure 18). The noise modes allow the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so it resembles white noise rather than spurious noise. As a result, the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. (Wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES)). A wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. For best noise performance, use the lowest noise setting option. As well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings. Rev. PrI | Page 16 of 27 Preliminary Technical Data ADF4150 MUXOUT Lock Detect Precision (LDP) The on-chip multiplexer is controlled by Bits [DB28:DB26](see Figure 18). When DB7 is set to 0, 40 consecutive PFD cycles of 10 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 6 ns must occur before digital lock detect is set. When DB8 is set to 0, the fractional-N digital lock detect is activated. When DB8 is set to 1, the integer–N digital lock detect is activated. In this case, setting DB7 to 0 causes three consecutive cycles of 15 ns to occur before digital lock detect is set. When this bit is set to 1, five consecutive cycles of 15 ns must occur. Reference Doubler Setting DB25 to 0 feeds the REFIN signal directly to the 10–bit R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 10–bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled. The maximum allowable REFIN frequency when the doubler is enabled is 30 MHz. RDIV2 Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop between the R counter and PFD, which extends the maximum REFIN input rate. This function allows a 50% duty cycle signal to appear at the PFD input, which is necessary for cycle slip reduction. 10–Bit R Counter The 10–bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 1023 are allowed. Double Buffer DB13 enables or disables double buffering of Bits [DB22:DB20] in Register 4. The Divider Select section explains how double buffering works. Charge Pump Current Setting Bits [DB12:DB09] set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Figure 18). Phase Detector Polarity DB6 sets the phase detector polarity. When a passive loop filter, or non-inverting active loop filter us used, this should be set to 1. If an active filter with an inverting characteristic is used, it should be set to 0. Power-Down DB5 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. When in software power-down mode, the part retains all information in its registers. Only if the supply voltages are removed are the register contents lost. When a power-down is activated, the following events occur: • • • • • The synthesizer counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFOUT buffers are disabled. The input register remains active and capable of loading and latching data. Charge Pump Three-State DB4 puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. Counter Reset DB3 is the R counter and N counter reset bit for the ADF4150. When this is 1, the RF synthesizer N counter and R counter are held in reset. For normal operation, this bit should be set to 0. REGISTER 3 Control Bits LDF Setting DB8 to 1 enables integer–N digital lock detect, when FRAC part of the divider is zero; setting DB8 to 0 enables fractional–N digital lock detect. With Bits [C3:C1] set to 0, 1, 1, Register 3 is programmed. Figure 19 shows the input data format for programming this register. Rev. PrI | Page 17 of 27 ADF4150 Preliminary Technical Data Anti-backlash pulse width Mute-till-Lock Detect Setting DB22 bit to 0 sets the PFD anti-backlash pulse width to 6 ns. This is the recommended mode for fractional-N use. Setting this bit to 1, the 3 ns pulse-width is used and will result in a phase noise and spur improvement in integer-N operation. For fractional-N mode it is not recommended to use this smaller setting. If DB10 is set to 1, the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. Charge cancellation mode pulse width Setting this bit to 1 enables charge pump charge cancellation. This has the effect of reducing PFD spurs in Integer-N mode. In fractional-N mode this should not be used and the relevant result in a phase noise and spur improvement. For fractional-N mode it is not recommended to use this smaller setting. CSR Enable Setting this bit to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the phase frequency detector (PFD) must have a 50% duty cycle for cycle slip reduction to work. The charge pump current setting must also be set to a minimum. See the Cycle Slip Reduction for Faster Lock Time section for more information. RF Output Enable DB5 enables or disables primary RF output, depending on the chosen value. Output Power DB4 and DB3 set the value of the primary RF output power level (see Figure 20). REGISTER 5 Control Bits With Bits [C3:C1] set to 1, 0, 1, Register 5 is programmed. Figure 21 shows the input data form for programming this register. Lock Detect PIN Operation Bits [DB32:DB22] set the operation of the lock detect PIN (see Figure 21). Clock Divider Mode INITIALIZATION SEQUENCE Bits [DB16:DB15] must be set to 1, 0 to activate PHASE resync or 0, 1 to activate fast lock. Setting Bits [DB16:DB15] to 0, 0 disables the clock divider. See Figure 19. The following sequence of registers is the correct sequence for initial power up of the ADF4150 after the correct application of voltages to the supply pins: 12-Bit Clock Divider Value The 12-bit clock divider value sets the timeout counter for activation of PHASE resync. See the PHASE Resync section for more information. It also sets the timeout counter for fast lock. See the Fast-Lock Timer and Register Sequences section for more information. • • • • • • REGISTER 4 Control Bits With Bits [C3: C1] set to 1, 0, 0, Register 4 is programmed. Figure 20 shows the input data format for programming this register. Feedback Select DB23 selects the feedback from VCO output to the N-counter. When set to 1, the signal is taken from the VCO directly. When set to 0, it is taken from the output of the Output dividers. The dividers enable covering of the wide frequency band (137.5 MHz – 4.4 GHz). When the divider is enabled and the feedback signal is taken from the output, the RF output signals of two separately configured PLLs are in phase. This is useful in some applications where the positive interference of signals is required to increase the power. Divider Select Bits [DB22:DB20] select the value of the output divider (see Figure 20). Rev. PrI | Page 18 of 27 Register 5 Register 4 Register 3 Register 2 Register 1 Register 0 Preliminary Technical Data ADF4150 RF SYNTHESIZER— A WORKED EXAMPLE 200 kHz (13 MHz/65) necessary for GSM. With dither off, the fractional spur interval depends on the modulus values chosen (see Table 6). The following is an example how to program the ADF4150 synthesizer: RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RFDivider (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. RF Divider is the output divider that divides down the VCO frequency. fPFD = REFIN × [(1 + D)/(R × (1+T))] (4) where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. T is the reference divide-by-2 bit (0 or 1). R is the RF reference division factor. It is also important where the loop is closed. In this example the loop is closed as depicted in Figure 18 (from Out Divider). ÷2 RFOUT The reference divide-by-2 divides the reference signal by 2, resulting in a 50% duty cycle PFD frequency. This is necessary for the correct operation of the cycle slip reduction (CSR) function. See the Cycle Slip Reduction for Faster Lock Times section for more information. N DIVIDER Unlike most other fractional-N PLLs, the ADF4150 allows the user to program the modulus over a 12–bit range. This means the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 10–bit R counter. For example, consider an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD programming the modulus to divide by 130. This also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. 07325-027 fPFD VCO The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. It is important to note that the PFD cannot operate above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N-divider. 12-BIT PROGRAMMABLE MODULUS For example, in a UMTS system, where 2112.6 MHz RF frequency output (RFOUT) is required, a 10 MHz reference frequency input (REFIN) is available, and a 200 kHz channel resolution (fRESOUT) is required, on the RF output. A 2.1 GHz VCO would be suitable, but a 4.2 GHz VCO would be suitable also. In the second case, the RF divider of 2 should be used (VCO frequency = 4225.2 MHz, RFOUT = VCO frequency/RF Divider = 4225.2 MHz/2 = 2112.6 MHz). PFD REFERENCE DOUBLER AND REFERENCE DIVIDER Figure 22. Loop closed before output divider 200 kHz channel resolution (fRESOUT) is required at the output of the RF divider. Therefore, channel resolution at the output of the VCO (fRES) is to be twice the fRESOUT, that is 400kHz. MOD = REFIN/fRES MOD = 10 MHz/400 kHz = 25 From Equation 4 fPFD = [10 MHz × (1 + 0)/1] = 10 MHz (5) 2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 (6) where: INT = 422 FRAC = 13 MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN sets the modulus to 65. This means the RF output resolution (fRES) is the The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal can be fed directly to the PFD, and the modulus can be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus needs to be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remain constant (13 MHz). This allows the user to design one loop filter for both setups without running into stability issues. It is important to remember that the ratio of the RF frequency to the PFD frequency principally affects the loop filter design, not the actual channel spacing. Rev. PrI | Page 19 of 27 ADF4150 Preliminary Technical Data CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES FAST-LOCK TIMER AND REGISTER SEQUENCES As outlined in the Noise and Spur Mode section, the ADF4150 contains a number of features that allow optimization for noise performance. However, in fast locking applications, the loop bandwidth generally needs to be wide, and therefore, the filter does not provide much attenuation of the spurs. If the cycle slip reduction feature is enabled, the narrow loop bandwidth is maintained for spur attenuation but faster lock times are still possible. If the fast-lock mode is used, a timer value is to be loaded into the PLL to determine the duration of the wide bandwidth mode. Cycle Slips Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared to the PFD frequency. The phase error at the PFD inputs accumulates too fast for the PLL to correct, and the charge pump temporarily pumps in the wrong direction. This slows down the lock time dramatically. The ADF4150 contains a cycle slip reduction feature that extends the linear range of the PFD, allowing faster lock times without modifications to the loop filter circuitry. When the circuitry detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Loop stability is maintained because the current is constant and is not a pulsed current. If the phase error increases again to a point where another cycle slip is likely, the ADF4150 turns on another charge pump cell. This continues until the ADF4150 detects the VCO frequency has gone past the desired frequency. The extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth. Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. Setting Bit DB18 in the Register 3 to 1 enables cycle slip reduction. Note that the PFD requires a 45% to 55% duty cycle for CSR to operate correctly. When Bits [DB16:DB15] in Register 3 are set to 0, 1 (fast lock enable), the timer value is loaded by the 12–bit clock divider value. The following sequence must be programmed to use fast lock: 1) Initialization sequence (see the Initialization Sequence section); occurs only once after powering up the part. 2) Load Register 3 by setting Bits [DB16:DB15] to 0, 1 and the chosen fast-lock timer value [DB14:DB3]. Note that the duration the PLL remains in wide bandwidth is equal to the fast-lock timer/fPFD. FAST LOCK—AN EXAMPLE If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz and a required lock time of 50 µs, the PLL is set to wide bandwidth for 40 µs. This example assumes a modulus of 65 for channel spacing of 200 kHz. If the time period set for the wide bandwidth is 40 µs, then Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD /MOD Fast-Lock Timer Value = 40 µs × 13 MHz / 65 = 8 Therefore, 8 must be loaded into the clock divider value in Register 3 in Step 1 of the sequence described in the Fast-Lock Timer and Register Sequences section. FAST LOCK—LOOP FILTER TOPOLOGY In order to use fast-lock mode, the damping resistor in the loop filter is reduced to ¼ of its value while in wide bandwidth mode. To achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16, and to maintain loop stability the damping resistor must be reduced a factor of ¼. To enable fast lock, the SW pin is shorted to the GND pin by settings Bits [DB16:DB15] in Register 3 to 0, 1. The following two topologies are available: • The damping resistor (R1) is divided into two values (R1 and R1A) that have a ratio of 1:3 (see Figure 23). • An extra resistor (R1A) is connected directly from SW, as shown in Figure 24. The extra resistor is calculated such that the parallel combination of an extra resistor and the damping resistor (R1) is reduced to ¼ of the original value of R1 (see Figure 24). SPURIOUS OPTIMIZATION AND FAST LOCK Narrow loop bandwidths can filter unwanted spurious signals, but these usually have a long lock time. A wider loop bandwidth will achieve faster lock times, but a wider loop bandwidth may lead to increased spurious signals inside the loop bandwidth. The fast lock feature can achieve the same fast lock time as the wider bandwidth, but with the advantage of a narrow final loop bandwidth to keep spurs low. Rev. PrI | Page 20 of 27 Preliminary Technical Data ADF4150 ADF4150 Integer Boundary Spurs R2 CP VCO C1 C2 Another mechanism for fractional spur creation is the interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (the point of a fractional-N synthesizer) spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, hence the name integer boundary spurs. C3 R1 SW 07325-018 R1A Figure 23. Fast-Lock Loop Filter Topology—Topology 1 ADF4150 R2 CP VCO C1 C2 R1A R1 C3 Reference Spurs 07325-019 SW Figure 24. Fast-Lock Loop Filter Topology—Topology 2 SPUR MECHANISMS This section describes the three different spur mechanisms that arise with a fractional-N synthesizer and how to minimize them in the ADF4150. Fractional Spurs The fractional interpolator in the ADF4150 is a third order Σ-Δ modulator (SDM) with a modulus (MOD) that is programmable to any integer value from 2 to 4095. In low spur mode (dither enabled) the minimum allowable value of MOD is 50. The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/MOD. In low noise mode (dither off), the quantization noise from the Σ-Δ modulator appears as fractional spurs. The interval between spurs is fPFD/L, where L is the repeat length of the code sequence in the digital Σ-Δ modulator. For the third-order modulator used in the ADF4150, the repeat length depends on the value of MOD, as listed in Table 6. Table 6. Fractional Spurs with Dither Off Condition (Dither Off) If MOD is divisible by 2, but not 3 If MOD is divisible by 3, but not 2 If MOD is divisible by 6 Otherwise Repeat Length 2 × MOD 3 × MOD 6 × MOD MOD Spur Interval Channel step/2 Channel step/3 Channel step/6 Channel step In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum look like broadband noise. This may degrade the in-band phase noise at the PLL output by as much as 10 dB. For lowest noise, dither off is a better choice, particularly when the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feed-through mechanism that bypasses the loop may cause a problem. Feed through of low levels of on-chip reference switching noise, through the RFIN pin back to the VCO, can result in reference spur levels as high as –90 dBc. PCB layout needs to ensure adequate isolation between VCO traces and the input reference to avoid a possible feed through path on the board. SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION With dither off, the fractional spur pattern due to the quantization noise of the SDM also depends on the particular PHASE word with which the modulator is seeded. The PHASE word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. Thus, a look-up table of PHASE values corresponding to each frequency can be constructed for use when programming the ADF4150. If a look-up table is not used, keep the PHASE word at a constant value to ensure consistent spur levels on any particular frequency. PHASE RESYNC The output of a fractional-N PLL can settle to any one of the MOD phase offsets with respect to the input reference, where MOD is the fractional modulus. The PHASE resync feature in the ADF4150 produces a consistent output phase offset with respect to the input reference. This is necessary in applications where the output phase and frequency are important, such as digital beam forming. See the PHASE Programmability section for how to program a specific RF output phase when using PHASE resync. PHASE resync is enabled by setting Bits [DB16:DB15] in Register 3 to 1, 0. When PHASE resync is enabled, an internal timer generates sync signals at intervals of tSYNC given by the following formula: tSYNC = CLK_DIV_VALUE × MOD × tPFD where: tPFD is the PFD reference period. Rev. PrI | Page 21 of 27 ADF4150 Preliminary Technical Data CLK_DIV_VALUE is the decimal value programmed in Bits [DB14:DB3] of Register 3, and can be any integer in the range of 1 to 4095. MOD is the modulus value programmed in Bits [DB14:DB3] of Register 1 (R1). SYNC (Internal) tSYNC LAST CYCLE SLIP FREQUENCY PLL SETTLES TO INCORRECT PHASE PLL SETTLES TO CORRECT PHASE AFTER RESYNC PHASE 07325-020 When a new frequency is programmed, the second sync pulse after the LE rising edge is used to resynchronize the output phase to the reference. The tSYNC time is to be programmed to a value that is as least as long as the worst-case lock time. This guarantees the PHASE resync occurs after the last cycle slip in the PLL settling transient. LE In the example shown in Figure 25, the PFD reference is 25 MHz and MOD = 125 for a 200 kHz channel spacing. tSYNC is set to 400 µs by programming CLK_DIV_VALUE = 80. –100 0 100 200 300 400 500 600 TIME (µs) 700 800 900 1000 Figure 25. PHASE Resync Example PHASE Programmability The PHASE word in Register 1 controls the RF output phase,. As this word is swept from 0 to MOD, the RF output phase sweeps over a 360o range in steps of 360o/MOD. Rev. PrI | Page 22 of 27 Preliminary Technical Data ADF4150 APPLICATIONS INFORMATION DIRECT CONVERSION MODULATOR The LO ports of the AD5375 can be driven differentially from the complementary RFOUTA and RFOUTB outputs of the ADF4150. This gives better performance than a single-ended LO driver and eliminates the use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the AD5375. The typical rms phase noise (100 Hz to 5 MHz) of the LO in this configuration is 0.61° rms. Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 26 shows how Analog Devices, Inc. parts can be used to implement such a system. The circuit block diagram shows the AD9788 TxDAC® being used with the ADL5375. The use of dual integrated DACs, such as the AD9788 with its specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The ADL5375 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4150, which allows levels from −4 dBm to +5 dBm from each output. The local oscillator(LO) is implemented using the ADF4150. The low-pass filter was designed using ADIsimPLL for a channel spacing of 200 kHz and a closed-loop bandwidth of 35 kHz. 51Ω REFIO 51Ω IOUTA MODULATED DIGITAL DATA LOW-PASS FILTER IOUTB AD9788 The RF output is designed to drive a 50 Ωload but must be ac-coupled, as shown in Figure 26. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power from the modulator is approximately 2 dBm. TxDAC QOUTA LOW-PASS FILTER QOUTB FSADJ 51Ω 51Ω 2kΩ IBBP LOCK DETECT VDD ADL5375 VVCO 9 AV DD 18 16 DV DD AVDD 17 4 6 22 CE PDB RF VP SDV DD 21 20 MUXOUT LD 3.9nH IBBN 3.9nH 1nF 1nF 1nF FREF IN LOIN RFOUT– 14 1 CLK VVCO QUADRATURE PHASE SPLITTER RFOUT 1nF 2 DATA DSOP 3 LE SPI COMPATIBLE SERIAL BUS LOIP RFOUT+ 15 19 REF IN 51Ω VCC ADF4150 24 RSET RF IN+ 10 RF IN– 11 4.7kΩ VCO 100pF VCOOUT 100pF QBBP VTUNE 680Ω CP 7 39nF 2700pF 1200pF 360Ω SW CP GND 8 AGND AGND SDGND 12 13 23 QBBN 5 Figure 26 Direct Conversion Modulator Rev. PrI | Page 23 of 27 ADF4150 Preliminary Technical Data INTERFACING SCLOCK MOSI TFS ADSP-21xx CLK SDATA LE ADF4150 CE I/O PORTS MUXOUT (Lock Detect) ADuC812 Interface Figure 27 shows the interface between the ADF4150 family and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4150 family needs a 32-bit word, which is accomplished by writing four 8-bit bytes from the MicroConverter to the device. When the fourth byte has been written, the LE input should be brought high to complete the transfer. MOSI ADuC812 CLK SDATA LE I/O PORTS ADF4150 CE MUXOUT (Lock Detect) 07325-022 SCLOCK Figure 27. ADuC812 to ADF4150 Interface I/O port lines on the ADuC812 are also used to control powerdown (CE input) and detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the described mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 125 kHz. 07325-023 The ADF4150 family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 32 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the register address table. Figure 28. ADSP-21xx to ADF4150 Interface Set up the word length for 8 bits and use four memory locations for each 32-bit word. To program each 32-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-24-3) are rectangular. The PCB pad for these is to be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land is to be centered on the pad. This ensures the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the PCB is to be at least as large as the exposed pad. On the PCB, there is to be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the PCB thermal pad to improve the thermal performance of the package. If vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter is to be between 0.3 mm and 0.33 mm, and the via barrel is to be plated with one ounce copper to plug the via. ADSP-21xx Interface Figure 28 shows the interface between the ADF4150 family and the ADSP-21xx digital signal processor. The ADF4150 family needs a 32-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Rev. PrI | Page 24 of 27 Preliminary Technical Data ADF4150 OUTPUT MATCHING There are a number of ways to match the output of the ADF4150 for optimum operation; the most basic is to use a 50 Ω resistor to AVDD. A dc bypass capacitor of 100 pF is connected in series as shown in Figure 29. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in this circuit into a 50 Ω load typically gives values chosen by Bit D2 and Bit D1 in Register 4 (R4). AVDD 50Ω 50Ω 07325-021 100pF RFOUT Figure 29. Simple ADF4150 Output Stage A better solution is to use a shunt inductor (acting as an RF choke) to AVDD. This gives a better match and, therefore, more output power. Experiments have shown the circuit shown in Figure 30 provides an excellent match to 50 Ω for the WCDMA UMTS Band 1 (2110 – 2170 MHz). The maximum output power in that case is about 7 dBm. Both single-ended architectures can be examined using the EVAL-ADF4150EB1Z evaluation board. AVDD 3.9nH 50Ω 07325-025 1nF RFOUT Figure 30.Optimum ADF4150 Output Stage If differential outputs are not needed, the unused output can be terminated or combined with both outputs using a balun. Rev. PrI | Page 25 of 27 ADF4150 Preliminary Technical Data OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 24 19 18 1 2.65 2.50 SQ 2.45 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 112108-A 0.20 REF Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Dimensions shown in millimeters(Package drawing subject to change). ORDERING GUIDE Model ADF4150BCPZ1 ADF4150BCPZ-RL71 EVAL-ADF4150EB1Z1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. PrI | Page 26 of 27 Package Option CP-24-7 CP-24-7 Preliminary Technical Data ADF4150 NOTES Rev. PrI | Page 27 of 27 PR08226-0-4/09(PrI)