Evaluation Board User Guide UG-600 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADAU1977/ADAU1978/ADAU1979 FEATURES GENERAL DESCRIPTION For the evaluation of the ADAU1977/ADAU1978/ADAU1979 quad ADCs Total harmonic distortion (THD) plus noise (N): −95 dB at −1 dBFS Signal to noise ratio (SNR): 109 dB, A weighting filter Built-in diagnostics for microphone inputs The EVAL-ADAU1977Z/EVAL-ADAU1978Z/EVALADAU1979Z is used for quick evaluation of the ADAU1977/ADAU1978/ADAU1979 quad ADCs. The evaluation board can output up to four channels of digital output. The evaluation board requires a power supply of +5 V for the ADAU1978 and the ADAU1979 and a power supply of +5 V and ±20 V (optional) for testing the diagnostic features of the ADAU1977. APPLICATIONS Automotive 11751-001 EVALUATION BOARD CONNECTION DIAGRAM Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 27 UG-600 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Board Setup Instructions ..........................................6 Applications ....................................................................................... 1 Jumper Settings ..............................................................................6 General Description ......................................................................... 1 USBi and Standalone GUI Setup.................................................7 Evaluation Board Connection Diagram ........................................ 1 ADAU1977 Power-On ..................................................................7 Revision History ............................................................................... 2 Standalone GUI I2C Control ........................................................7 Evaluation Board Hardware ............................................................ 3 Microphone Diagnostics ..............................................................8 Power Supply Connectors ........................................................... 3 Standalone GUI SPI Control .......................................................9 Input Connectors.......................................................................... 3 Standalone Mode ...........................................................................9 Output Connectors ...................................................................... 3 Evaluation Board Schematics and Artwork ................................ 10 I C/SPI Control Connector ......................................................... 3 Board Layout ............................................................................... 16 Jumpers .......................................................................................... 3 Ordering Information .................................................................... 23 Setup of the Evaluation Board Connections ................................. 5 Bill of Materials ........................................................................... 23 2 REVISION HISTORY 8/14—Revision 0: Initial Version Rev. 0 | Page 2 of 27 Evaluation Board User Guide UG-600 EVALUATION BOARD HARDWARE The EVAL-ADAU1977Z board is common for the ADAU1977, ADAU1978, and ADAU1979. The evaluation board is designed as a 4-layer printed circuit board (PCB). The top and bottom layers are for signals, whereas Layer 2 and Layer 3 are used as ground and a power plane, respectively. The PCB layout is important to achieve good audio performance. The following sections offer useful guidelines for operation of the board. POWER SUPPLY CONNECTORS The EVAL-ADAU1977Z board requires +5 V for the ADAU1978 and ADAU1979 and may need an additional ±20 V for testing the 10 V rms inputs of the ADAU1977. Connect the 5 V power supply at J5 and J4. Connect the ±20 V power supply at either TP3 (+20 V) or TP1 (−20 V). The +5 V power supply must be capable of providing a 1 A current rating, and the ±20 V power supply must be capable of providing at least a 100 mA current rating. When the diagnostics feature is not used, the ±20 V supply is not required. OUTPUT CONNECTORS The ADC digital output is available at J25 (unbuffered) and J26 (buffered). In addition, ADC digital output is available as a 2-channel Sony Philips digital interface format (SPDIF). J25 and J26 are used for I2S or time division multiplex (TDM), serial digital output. The U16 provides the SPDIF optical output, and J35 provides the SPDIF coaxial output. I2C/SPI CONTROL CONNECTOR The J8 (10-way header) can be used for I2C/SPI serial port communication for controlling the board. The supplied USB interface board can be used for setting the device. The graphic user interface (GUI) software is used along with the USB interface board. JUMPERS The EVAL-ADAU1977Z board provides jumpers for setting this board into various operating modes. INPUT CONNECTORS The EVAL-ADAU1977Z has five 3.5 mm audio jack connectors for analog inputs: J9, J17, J28, J38, and J47. The J9 connector is used for generating line level inputs capable of 10 V rms, with a common-mode level of 7 V for the ADAU1977. The J17, J28, J38, and J47 connectors are used as Channel 1, Channel 2, Channel 3, and Channel 4 line level inputs to the ADC, respectively. All five inputs are differential. Table 1. Jumper Descriptions Component No. J1 J2 J4 J5 J8 J9 J10 J11 J12 J13 J14 J15/J20 J16 J17 J19 J21 J22 J24 J25 J26 J27/J30 J28 J29 Mnemonic MICBIAS SELECT AUX IN CM SELECT AUX IN GND +5V USBi AUX IN IOVDD IOVDD Ext/Int VBAT Ext/Int 3.3 V Ext/Int AVDD Ext/Int Input 1 Select AVDD Current CH1 Input Input Short Boost Current MICBIAS-CH1 Boost Switch ADC Output ADC Output Buffered Input 2 Select CH2 Input Input Short Description This jumper allows selecting either internal or external micbias for auxiliary input. Used for setting the common mode level for auxiliary input. Ground or 0 V connection for the power supply. +5 V connection for the power supply. Connector for USBi board. Connector for auxiliary input. Selects the IOVDD 1.8 V or 3.3 V. Selects the internal or external supply for IOVDD. Selects the internal or external supply for VBAT. Selects the internal or external 3.3 V supply. Selects the internal or external AVDD supply for the ADAU1977. Selects the input source for Channel 1. This jumper is used to measure the AVDD current. Connector for Channel 1 input. This jumper is used to short the ± Channel 1 input. This jumper is used to measure the boost converter current. Selects the internal or external micbias for Channel 1. This jumper is used to measure the boost switch current. Header for connection to ADC digital pins. Header for ADC digital output. Selects the input source for Channel 2. Connector for Channel 2 input. This jumper is used to short the ± Channel 2 input. Rev. 0 | Page 3 of 27 UG-600 Evaluation Board User Guide Component No. J31 J33 J34 J35 J36/J40 J28 J39 J41 J42 J43 J44 J45 J46/J49 J48 J50 Mnemonic MICBIAS-CH1 IOVDD Current 128fs Mode Coaxial Output Input 3 Select CH3 Input Input Short MICBIAS-CH1 DVDD MCLKIN PLL Filter PLL Filter Input 4 Select Input Short MCLKIN J51 J52 J53 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 MICBIAS-CH1 MCLK Input FREQ Select AUX IN CH1 IN CH2 IN Reset SPDIF Tx CH3 IN SA Mode CH4 IN RESET MCLKIN Reserved Oscillator Enable Description Selects the internal or external micbias for Channel 2. Connector for measuring IOVDD current. Selects the 96 k sample rate for the SPDIF transmitter. Connector for SPDIF coaxial output. Selects the input source for Channel 3 Connector for Channel 3 input. This jumper is used to short the ± Channel 3 input. Selects the internal or external micbias Channel 3. External DVDD current measurement. Selects the external master clock input to the ADAU1977. Selects the PLL filter for LRCLK mode. Selects the PLL filter for MCLK mode. Selects the input source for Channel 4. This jumper is used to short the ± Channel 4 Input. Selects the source for MCLKIN between oscillator, header, and Subminiature Version A, SMA. Selects the internal or external micbias Channel 4. SMA connector for external master clock input. Selects the switching frequency for the 3.3 V regulator. Header for external auxiliary input Header for external Channel 1 input. Header for external Channel 2 input. SPDIF Tx reset. Header for external Channel 3 input. This jumper is used for standalone mode. Header for external Channel 4 input. Header for the ADAU1977 reset. Header for master clock input. Reserved for internal use. Enables the oscillator. Rev. 0 | Page 4 of 27 Evaluation Board User Guide UG-600 SETUP OF THE EVALUATION BOARD CONNECTIONS CONTROL FOR AVDD SWITCHER NORMAL PWDN 1.2MHz +17V TO +22V REQUIRED ONLY FOR GENERATING VBAT AND 10V RMS SIGNAL AT 7V CM 0V GND 1/3 MICBIAS VBAT/2 GND 2/3 MIC BIAS VBAT/2 CM OPTIONS 600kHz DO NOT CONNECT POWER SUPPLY INTERNAL USE ONLY –17V TO –22V BUFFER TO BE USED FOR GENERATING 10V RMS SIGNAL AT VARIOUS CM LEVEL FAULT INPUT +INPUTS 0V FAULT INPUT –INPUTS CONNECT VOLTAGE SOURCE TO INTRODUCE THE FAULT ON INPUT 0V TO 18V MAX DO NOT CONNECT POWER SUPPLY INTERNAL USE ONLY CONNECT 5V SUPPLY EXT AVDD 0V +5V EXT DVDD EXT IOVDD AARDVARK/USBi AUX ANALOG INPUT 10V RMS ADDRESS SETTING FOR 0x71 7 BIT DEVICE ADDRESS ON SLOTS 5 – 8 TDM8 SLAVE TDM 96K 384*fs OFF ANALOG INPUT1 MAX 10V RMS ADDR1 ADDR0 SLOTS 1 – 4 TDM4 MASTER I2S 48K 256*fs SLIDE SWITCH SETTINGS STAND ALONE MODE SPI MODE I2CMODE CHIP ADDRESS 0x11 ON ON CHIP ADDRESS 0x31 ON OFF CHIP ADDRESS 0x51 OFF ON CHIP ADDRESS 0x71 OFF OFF SERIAL DATA OUTPUT SLAVE MASTER ANALOG INPUT2 MAX 10V RMS SDATA TO I2S HDR LRCLK BCLK SDATA2 SDATA1 SDATA TO SPDIF OUT BCLK BCLK LRCLK LRCLK ANALOG INPUT3 MAX 10V RMS SDATA2 SDATA2 SDATA2 SDATA1 SDATA1 SDATA1 MCLK OFF ON 500Ω 300Ω MICBIAS RESISTOR SELECT PSIA MCLKIN PLL FILTER SELECT INSTALL FOR SA MODE MCLKADAU197x SELECT MCLK SELECT Figure 2. Evaluation Board Jumper Settings Rev. 0 | Page 5 of 27 11751-002 MICBIAS SELECT GENERATE FAULT ON INPUTS EXT MCLK IN POWER DOWN OSCILLATOR DIRECT EXT LEVEL SHIFT INT PSIA OSC SMA –INx OFF ON +INx +BUFF DIRECT COUPLE INPUTS ADC INPUT SELECT LRCK MCLK –BUFF NORMAL MICBIAS NORMAL FAULTx GND ANALOG INPUT4 MAX 10V RMS UG-600 Evaluation Board User Guide EVALUATION BOARD SETUP INSTRUCTIONS To setup the EVAL-ADAU1977Z, the user needs a 5 V power supply, differential analog input source, and a PC with a USB port. Use a single 5 V, 1 A current rating for the power supply. For full evaluation of the ADAU1977, a ±20 V supply is required. This power supply facilitates the generation of a 10 V rms signal as well as a VBAT supply for microphone diagnostics. by installing Jumper J44 in the MCLK position. If the LRCLK mode is required, set J44 in the LRCLK position. In the I2S output section, take the following steps: 1. For I2S/LJ/RJ/TDM format, take the following steps: JUMPER SETTINGS See Figure 2 for the setup of the evaluation board connections. Connect the positive power supply lead to J5 and the 0 V lead to J4 of the evaluation board. Do not turn the power supply on at this time. 1. 2. 3. In the power supply section, take the following steps: 1. 2. 3. 4. 5. Set Jumpers J13 and J14 to the INT position. Set Switch S1 to the ON position. Set Jumper J10 to the desired IOVDD supply, 3.3 V, or 1.8 V. Set Jumper J11 to the INT position for the internal IOVDD. Set Switch S2 to the ON position to turn on the 1.8 V regulator. 4. Install Jumpers J16, J21, J24, and J33. The J16 jumper provides the AVDD. Jumpers J21 and J24 provide the 3.3 V power supply to the boost converter. The J33 jumper provides the IOVDD to the ADAU1977/ADAU1978/ADAU1979. In the PLL and MCLK section, take the following steps: 1. 2. 3. 4. 5. 6. Set LK3 and LK5 to the I2S position. Set LK1 and LK2 to the I2S position. Set Switch S13 to the MASTER position if the ADAU1977/ADAU1978/ADAU1979 is used as a master for the serial audio port. Alternatively, it can be set to the SLAVE position; however, in this case, both the LRCLK (frame clock) and the BCLK (bit clock) must be provided from an external source. The buffered serial output is available on the J26 (4-way dual row, 0.1” pitch) header. Alternatively, the direct (unbuffered) ADAU1977 serial outputs are available on the J25 (8-way dual row, 0.1” pitch) header. For SPDIF format, take the following steps: In the daughter board section, take the following steps: 1. Determine the serial data format used for the ADC output. Either I2S/left justified (LJ)/right justified (RJ)/TDM format or SPDIF format are available. Select the master clock source. The evaluation board provides three options for providing the master clock to the ADC. The three options include the following: the onboard 12.288 MHz oscillator, the external source at JP9, and the SMA Connector J52. To use the on-board oscillator, install Jumper JP11. To shut down the oscillator, remove Jumper JP11. Set Jumper J50 in the OSC center position. Alternatively, if the external master clock is available, it can either be connected at J52 as a coaxial 50 Ω SMA connector, or at JP9 as a 2-way header (0.1” pitch). If using JP9 as the source, install J50 in the PSIA position. If using J52 as the source, install J50 in the SMA position. The MCLK is level shifted to the required IOVDD. By default, the level shifted master clock is used. Set Jumper J43 to the IOVDD position. Alternatively, if direct MCLK pin access is needed, set J43 to the 3V3 position. In this case, ensure that the master clock supplied to the ADAU1977 is at the correct IOVDD level. Two options are provided for the PLL filter, MCLK mode or LRCLK mode. By default, the MCLK mode is selected 1. 2. 3. 4. 5. Ensure LK3 and LK5 are set to the SPDIF position. Ensure LK1 and LK2 are set to the SPDIF position. Ensure LK4 is set to the desired serial data pair. Either Pair 1 (Ch1 and Ch2) or Pair 2 (Ch3 and Ch4) can be selected because only 2-channel SPDIF output is available on the evaluation board. Ensure LK6 is set to the SPDIF position which provides the MCLK to the SPDIF transmitter. The SPDIF output is available on U16 as an optical form or on J35 as a coaxial form. For the I2C/SPI control section, take the following steps: 1. Slide Switches S3, S4, and S5 are used to set the control communication protocol for the ADAU1977. For I2C protocol, take the following steps: 1. 2. 3. 4. 5. Rev. 0 | Page 6 of 27 Set Switches S3, S4, and S5 to the I2C position. Ensure JP6 is not installed. The device address for the ADAU1977 is set using Switch S9. The possible 7-bit device addresses are 0x11, 0x31, 0x51, or 0x71. The EVAL-ADAU1977Z evaluation board is set for the 0x71 address. The 20-way (10-pin, dual row, 0.1” pitch), Shrouded Connector J8 is used to connect the supplied USBi. Alternatively, any other I2C master controller can be connected at J8 to control the ADAU1977. The Analog Devices, Inc., USBi is the quickest way to set the EVAL-ADAU1977Z board using the supplied standalone GUI or SigmaStudio™ software. Evaluation Board User Guide UG-600 For the ADAU1977 line input application, take the following steps: USBi AND STANDALONE GUI SETUP 1. 1. 2. 3. 4. 5. 6. 7. J9 is used to level shift the input source to the VBAT/2 level. For the ADAU1977, connect the analog audio source to the J9 auxiliary input connector. J2 has two jumpers that must be set to the VBAT and VBAT2 positions. Check the dc voltage at J2 (Pin 2). This voltage should be approximately 7 V. If not, set J2 using the preset R5. Set the S10, S16, S21, and S26 switches to the ON position for dc-coupled inputs. Set Jumpers J15, J20, J27, J30, J36, J40, J46, and J49 to the BUFF position. Alternatively, the signal source can be connected directly to J17, J28, J38, and J47 by setting Jumpers J15, J20, J27, J30, J36, J40, J46, and J49 to the –IN or +IN position. Note that in this setting, the input source must be level shifted appropriately. For the ADAU1978/ADAU1979 line input applications, take the following steps: 1. 2. 3. 4. 5. Ensure Jumper J15 and Jumper J20 are set to the –IN and +IN position for Ch1. Ensure Jumper J27 and Jumper J30 are set to the –IN and +IN position for Ch2. Ensure Jumper J36 and Jumper J40 are set to the –IN and +IN position for Ch3. Ensure Jumper J46 and Jumper J49 are set to the –IN and +IN position for Ch4. Ensure Switches S10, S16, S21, and S26 are set to the OFF position for the ADAU1978 and the ADAU1979, which sets the inputs as ac-coupled mode. For the ADAU1977 microphone input application, take the following steps: 1. 2. 3. 4. 5. 6. Ensure Switches S7, S12, S15, S18, S20, S23, S25, and S29 are set to the ON position for using the ADAU1977 inputs as microphone. These switches are used to set the microphone bias resistors for the microphone inputs. Either 300 Ω or 500 Ω can be selected when switches are set to the ON position for the respective inputs. Ensure Jumpers J22, J31, J41, and J51 are set to the INT position (the internal micbias is used). These jumpers allow the microphone bias to be selected either from the ADAU1977, or externally, if desired. Jumpers J17, J28, J38, and J47 are used for the microphone input connection. Ensure Jumpers J15, J20, J27, J30, J36, J40, J46, and J49 are set to the IN position. Ensure Switches S10, S16, S21, and S26 are set to the ON position for direct-coupled mode. To set up the USBi and standalone GUI, take the following steps: 2. If using the standalone GUI, click the appropriate x86 or x64 folder setup.exe to install the GUI. The software is installed on your desktop with the ADAU1977 Rev C icon. ADAU1977 POWER-ON To power-on the EVAL-ADAU1977Z, take the following steps: 1. Turn on the 5 V supply. Typical 40 mA current is drawn from the 5 V supply in standby condition. STANDALONE GUI I2C CONTROL The EVAL-ADAU1977Z board can be controlled via the I2C using the standalone GUI and USBi. Take the following steps: 1. Connect the provided USBi board to J8 and to the USB port on the PC. 2. Double-click the ADAU1977 Rev C icon on your desktop to invoke the GUI. 3. A new window, as is shown in Figure 3, will appear. 4. The USBi - Connected message will appear at the top of the window (see Figure 3). 5. Click Power Up. The Communication Established message will appear at the top of the window (see Figure 3). 6. Click Read all to read the PLL status. The PLL status should be green and locked. 7. When using the ADAU1977, and the boost converter is turned on, the Boost Good indicator should be green. For the ADAU1978 and the ADAU1979, this function is not applicable and will stay red. 8. Go to the ADC Control tab (see Figure 4) and click Master/Slave for the ADC master mode. When green, the ADC is in master mode and it will output the bit clock and frame clock, together with the serial data at the J25. 9. Connect the input source at the desired input to AIN1, AIN2, AIN3, and AIN4 or AUXIN using 3.5 mm audio jacks. Alternatively, the 2-pin (0.1” pitch) header can be used to feed the inputs to the EVAL-ADAU1977Z evaluation board. Note that the input level requirements for the ADAU1977, the ADAU1978, and the ADAU1979 are different, and the appropriate level input signal must be applied. The full-scale inputs for the ADAU1977 is 10 V rms, for the ADAU1978 is 2 V rms, and for the ADAU1979 is 4.5 V rms. 10. The ADC output is available at the J26 header or the SPDIF output depending on the selected option. Rev. 0 | Page 7 of 27 Evaluation Board User Guide 11751-005 11751-003 UG-600 Figure 3. Register Control for the ADAU1977 GUI Page 1 Figure 5. Register Control for the ADAU1977 GUI Page 3 MICROPHONE DIAGNOSTICS Microphone diagnostics are applicable for the ADAU1977 only, used with the microphone input application circuit, as described in the ADAU1977 data sheet. 1. 2. 3. 11751-004 4. Figure 4. Register Control for the ADAU1977 GUI Page 2 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Rev. 0 | Page 8 of 27 Connect the microphone to the desired input connector: J17, J28, J38, or J47. Ensure that the inputs are dc-coupled by setting Switches S10, S16, S21, and S26 to On. Select the appropriate bias resistors using Switches S7 and S12 for Channel 1, Switches S15 and S18 for Channel 2, Switches S20 and S23 for Channel 3, Switches S25 and S29 for Channel 4. The resistor options are 300 Ω or 500 Ω. Select the internal microphone bias by setting Jumpers J22, J31, J41, J51 to the INT position. Ensure that the Boost Good indicator is green on the GUI Power Up tab. Ensure Boost is On. By default, the 48 k sample rate is selected, and the boost switching frequency is 1.5 MHz. In the MIC BIAS CONTROL section, select the desired microphone bias output voltage (see Figure 3). By default, it is 8.5 V. Ensure Mic Bias is Enabled (see Figure 3). Check the microphone bias voltage output on the EVALADAU1977Z board at the test point (TP). Go to the Diagnostics tab on the GUI (see Figure 5). With the microphone connected, the typical voltage at the positive (+) input is 2/3 of microphone bias, and at the negative (−) input is 1/3 of microphone bias. Click Read in the Diagnostics tab on the GUI (see Figure 5). With proper connections and normal working conditions, all of the channel status indicators will be blue for each respective channel connected with the microphone. To check the diagnostics functionality, create a fault situation at the microphone input. This fault situation is done by Evaluation Board User Guide 16. 17. 18. 19. 20. 21. UG-600 either using the microphone itself or by using the dummy 300 Ω or 500 Ω resistor connected across the positive and negative input terminals of the evaluation board. The faults are reported in the channel status indicators for each channel for which Diag Control is Enabled (see Figure 5). The GUI shown in Figure 5 provides access to all the diagnostics registers. The DIAG TRIP POINT ADJUST1 section provides control for adjusting the trip thresholds (see Figure 5). The DIAG_ADJUST2 section provides the fault timeout adjustment controls (see Figure 5). The DIAG IRQ1 section is used to generate the IRQ using the FAULT pin. The Fault Pin Drive section is used to report the fault in the system (see Figure 5). Use the previous controls, as well as the ADAU1977 diagnostics registers in this data sheet, to suit the needs of the system using the intended microphone. STANDALONE GUI SPI CONTROL 1. 2. 3. 4. Change Slide Switches S3, S4, and S5 to SPI mode. Ensure JP6 is not installed. In the GUI, go to Options/Comm Protocol and select SPI mode. (The default is I2C mode). The evaluation board is now configured for the SPI protocol, and the GUI functions similarly to the GUI functions in I2C mode. STANDALONE MODE The evaluation board (EVAL-ADAU1977Z) also has a standalone mode that does not require any I2C or SPI control. In standalone mode, the ADAU1977/ADAU1978/ADAU1979 are set internally for a specific operation; no register access is provided because the I2C and SPI ports are disabled. To invoke the standalone mode (SA mode), insert Jumper JP6 and set Slide Switches S3, S4, and S5 to the standalone position. In SA mode, limited options are available that can be set using the dual inline package (DIP) Switch S8. See Table 2 for the S8 switch settings. The EVAL-ADAU1977Z can also be configured for SPI control instead of for I2C control. To use in SPI control mode, take the following steps: Table 2. Settings in SA Mode ADAU1977 Pin No., Mnemonic Pin 17, SDA/COUT Pin 18, SCL/CCLK Pin 19, ADDR0/CLATCH Pin 20, ADDR1/CIN Pin 14, SDATAOUT2 Pin 8, FAULT Switch S8 S8-6 S8-5 S8-4 S8-3 S8-2 S8-1 Function MCLK 256 fs to 384 fs select Full-scale (FS) 48 k/96 k select I2S/TDM select Master/slave select TDM 4 to TDM 8 select TDM 8 slot assignments, Slot 1 to Slot 4 or Slot 5 to Slot 8 Rev. 0 | Page 9 of 27 OFF IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD 384 fs 96 k TDM Slave TDM 8 Slot 5 to Slot 8 ON GND GND GND GND GND GND 256 fs 48 k I2 S Master TDM 4 Slot 1 to Slot 4 J52 C106 0.10µF 1 2 R92 0Ω R90 10.0kΩ Y1 C105 10pF 3 OUTPUT IOVDD R89 OPEN OPEN R91 +3.3V GND 2 OE VDD 1 [2,6] [2,6] [2,6] [2,6] [2,6] [2,6] [2,6] [2,6] R87 49.9Ω AIN1N AIN1P AIN2N AIN2P AIN3N AIN3P AIN4N AIN4P 49.9Ω R86 R84 JP11 L5 OSC_AP3S-12.288MHZ_SMD 4 10.0kΩ AVDD 0Ω JP8 S27 RESET ADAU1977 2 +3.3V C101 C108 0.10µF R83 MCLK_3.3V J16 R85 49.9Ω 0.10µF 6 7 B2 B1 U20 A2 TP63 1 3 5 7 9 11 13 15 17 19 J23 AVDD_ADC 39nF C97 + MICBIAS C45 10µF C67 0.10µF C95 390pF R80 4K87 0.10µF C61 C98 5.6nF R81 1k00 VBAT [2,4] C66 0.10µF 10µF EPAD AVDD3 AIN1N AIN1P AIN2N AIN2P AIN3N AIN3P AIN4N AIN4P AVDD1 C70 VREF 41 31 32 33 34 35 36 37 38 39 40 C49 1.0nF MCLKIN_1977 [1,3] AVDD_ADC AVDD_ADC SELECT J44 OR J45 C94 J43 AVDD_ADC PLL FILTER SELECTION 2 4 6 8 10 12 14 16 18 20 2.2nF NP0 [1] 2x10 PD/RST_1977 TP28 TP29 TP40 TP42 TP54 TP55 TP71 TP74 TP72 AVDD_ADC C53 0.10µF R82 10.0kΩ R78 49.9Ω DAUGHTER BOARD HEADERS 5 3 2 0.10µF C46 A1 DIR SN74LVC2T45DCTR AIN1N AIN1P AIN2N AIN2P AIN3N AIN3P AIN4N AIN4P AVDD 2-JUMPER 8 VCCB TP73 2 4 6 1 VCCA 1 GND 4 1 A B 3 C104 10pF J50 J44 AP 1 OSC 3 SMA 5 2 1 MICBIAS_1977 VBOOST_IN IOVDD PLL-LRCK OPEN 2 R41 J45 2x10 J37 U12 PLL-MCLK MICBIAS_1977 [2] TP25 TP34 ADAU1977 AVDD_ADC +3.3V 2 1 VBAT TP23 GND VREF JP9 1 2 2 IDVDD L3 DVDD_IN 10µF 0.10µF J42 C71 C68 20 19 18 17 16 15 14 13 12 11 1 J33 C112 C65 0.10µF 1 1 J54 FAULT-PULLUP 1 2 10.0kΩ R134 J21 IOVDD C42 0.10µF 2 AVDD_DC_DC 2 2 DC-DC CURRENT MEASUREMENT NORMALLY OPEN INSTALL IF USING EXT DVDD 1 R132 C111 ADDR1/CIN/MS_SEL ADDR0/CLATCH/FMT_SEL SCL/CCLK/FS_SEL SDA/COUT/MCLK_SEL BCLK LRCLK SDATAOUT2/TDM_SEL SDATAOUT1 IOVDD DGND C50 10µF 25V R111 OPEN J24 CURRENT MEASUREMENT R131 19 17 15 13 11 9 7 5 3 1 VREF OPEN J18 2x10 OPEN 20 18 16 14 12 10 8 6 4 2 0Ω R130 30 29 28 27 26 25 24 23 22 21 VBAT AGND3 MB_GND MICBIAS VBOOST_IN VBOOST_OUT SW SW PGND PGND AGND1 VREF PLL_FILT AVDD2 AGND2 /PD/RST MCLKIN FAULT/TBD_SEL SA_MODE DVDD 1 2 3 4 5 6 7 8 9 10 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 TP57 TP61 TP62 TP27 TP45 TP65 TP66 TP67 TP68 TP69 AVDD_1977 GND PD/RST_1977 MCLKIN_1977 FAULT/TBD_SEL SA_MODE DVDD Rev. 0 | Page 10 of 27 [5] SA_MODE Figure 6. EVAL-ADAU1977Z Schematic, Page 1 of 6 [1] PD/RST_1977 [1,3] MCLKIN_1977 20 18 16 14 12 10 8 6 4 2 J32 2x10 C39 10µF 25V AVDD TP35 TP36 TP38 TP41 TP43 TP44 TP46 TP47 TP50 TP24 IOVDD_1977 GND SCAN TEST HEADER ADDR1/CIN/MS_SEL ADDR0/CLATCH/FMT_SEL SCL/CCLK/FS_SEL SDA/COUT/MCLK_SEL BCLK 49.9Ω LRCLK 49.9Ω SDATAOUT2/TDM_SEL 49.9Ω SDATAOUT1 49.9Ω [1,5] ADDR1/CIN/MS_SEL [1,5] ADDR0/CLATCH/FMT_SEL BCLK LRCLK [5] SDATAOUT2/TDM_SEL SDATAOUT1 [1,3] MCLKIN_1977 [1] PD/RST_1977 19 17 15 13 11 9 7 5 3 1 1 3 5 7 9 11 13 15 R47 R50 R53 R56 J43: Use for selecting the direct external MCLK for the DUT J50: Use for selecting the level shifted MCLK for the DUT J45: PLL filter selection is using MCLK as PLL input J44: PLL filter selection is using LRCLK as PLL input J16: Use for Measuring DUT AVDD Current J33: Use for measuring DUT IOVDD current J24: Use for Measuring Current into DC-DC at SW node J21: Use for Measuring Current into DC-DC pre inductor NOTES ON JUMPER SELECTION 2x8 J25 2 4 6 8 10 12 14 16 ADDR1/CIN/MS_SEL [1,5] ADDR0/CLATCH/FMT_SEL [1,5] SCL/CCLK/FS_SEL [5] SDA/COUT/MCLK_SEL [5] BCLK_X [3] LRCLK_X [3] SDATAOUT2/TDM_SEL_X [3] SDATAOUT1_X [3] UG-600 Evaluation Board User Guide EVALUATION BOARD SCHEMATICS AND ARTWORK 11751-006 Evaluation Board User Guide UG-600 INPUT BUFFER FOR LEVEL SHIFTING INPUT 10.0kΩ HVDD 10.0Ω R6 [2] CM_IN– U1-A 10µF C10 U1-B 10.0kΩ HVSS MICBIAS_EXT TP4 HVSS 5 7 O 10µF C5 3 R4 R3 R2 10.0kΩ 10.0kΩ 10.0kΩ MICBIAS – –OUT_BUFFER [2] C13 0.10µF 10.0kΩ C6 TP58 22pF MICBIAS_CH1 MICBIAS_EXT TP32 TP30 TP33 R122 + 2 S10 AC COUPLING CAP BYPASS +OUT_BUFFER [2] TP26 TIP R123 10µF S6 C1 C2 1 OPEN 2 3 4 5 1 OPEN 2 3 4 5 R108 MICBIAS_CH1 [2] FAULT_IN+ VBAT [2,6] [1,2,4] R107 R106 FAULT_IN– [2,6] R105 499Ω MIC BIAS SELECT P 4 3 S12 S7 499Ω 301Ω 1 2 AIN1N [1,6] MICBIAS_CH2 MICBIAS_EXT TP49 TP51 + 2 J29 3 4 S16 AC COUPLING CAP BYPASS 1 +OUT_BUFFER [2] TP39 SHORT P&N 2 1 3 1.0nF S17 2 C78 C1 C2 S14 C1 C2 TIP J28 1 OPEN 2 3 4 5 TP59 TP56 MICBIAS_EXT 2 J39 1 SHORT P&N 1 OPEN 2 3 4 5 R117 499Ω MICBIAS_CH1 [2] [2] FAULT_IN+ VBAT [2,6] R116 [1,2,4] 301Ω TP77 FAULT_IN– [2,6] 4 3 S23 1 301Ω MIC BIAS SELECT N TP76 MICBIAS_EXT R129 3 –OUT_BUFFER [2] 3 2 J48 SHORT P&N 1 S24 C1 C2 1 OPEN 2 3 4 5 R121 499Ω [2] R120 4 3 301Ω R119 R118 C93 MIC BIAS SELECT P 499Ω 301Ω AIN4P [1,6] 1 2 S29 S25 1 2 4 3 MIC BIAS SELECT N FAULT GEN SELECT N AIN4N [1,6] 2 C92 1.0nF 3 4 1 OPEN 2 3 4 5 + 10µF 0Ω C91 OPEN HDR-3WAY J46 B A 1 RING S28 C1 C2 S26 AC COUPLING CAP BYPASS MICBIAS_1977 J51 A B 2 FAULT GEN SELECT P C100 + TP70 TIP 4 3 AIN3N [1,6] MICBIAS_CH4 2 1 +OUT_BUFFER [2] SLEEVE S20 2 R114 AIN3P [1,6] 1 2 499Ω R115 C86 2 HDR-3WAY J49 B A 1 C103 1.0nF 3 FAULT GEN SELECT N 10µF 3 C102 OPEN MICBIAS_1977 J41 A B 2 MIC BIAS SELECT P 1 0Ω TP75 MIC BIAS SELECT N –OUT_BUFFER [2] AIN_CH4+ AIN_CH4– 4 3 + HDR-3WAY J36 B A 1 2 S19 C1 C2 1 OPEN 2 3 4 5 3 C85 1.0nF R128 INPUT CH4 1 2 + + 2 HDR-3WAY J40 B A 1 TP64 TP53 10µF 0Ω 3 4 S21 AC COUPLING CAP BYPASS R127 C84 OPEN S22 2 1 +OUT_BUFFER [2] RING J47 S18 S15 499Ω FAULT GEN SELECT P C90 C1 C2 3 C89 1.0nF INPUT CH3 JP7 301Ω 301Ω AIN2P [1,6] 1 2 AIN2N [1,6] MICBIAS_CH3 10µF 0Ω C88 OPEN TIP 1 2 R109 4 3 1 SLEEVE J38 FAULT_IN– [2,6] MIC BIAS SELECT P –OUT_BUFFER [2] AIN_CH3+ AIN_CH3– JP5 R110 499Ω FAULT GEN SELECT N R126 1 2 MICBIAS_CH1 [2] R113 FAULT_IN+ VBAT [2,6] R112 [1,2,4] C57 3 C60 1.0nF 1 OPEN 2 3 4 5 2 R125 0Ω C56 OPEN HDR-3WAY J27 B A 1 10µF RING INPUT CH2 3 FAULT GEN SELECT P C74 10µF HDR-3WAY J30 B A 1 TP60 R124 0Ω C77 OPEN SLEEVE MICBIAS_1977 J31 A B 2 1 AIN_CH2+ AIN_CH2– JP3 4 3 MIC BIAS SELECT N FAULT GEN SELECT N [2] –OUT_BUFFER 1 2 AIN1P [1,6] 1 2 301Ω C38 3 C37 1.0nF C1 C2 + 0Ω C36 OPEN 3 2 HDR-3WAY J15 B A 1 RING INPUT CH1 3 4 J19 2 1 SLEEVE J17 SHORT P&N C43 1.0nF S11 1 0Ω C40 OPEN 2 HDR-3WAY J20 B A 1 AIN_CH1+ AIN_CH1– JP2 MICBIAS_1977 J22 A B 2 1 FAULT GEN SELECT P C41 10µF 3 1 2 J1 A B 10.0kΩ R7 R9 ANALOG INPUTS 1 J2 HEADER_12WAY_UNSHROUD 1 2 CM_IN+ [2] 3 4 5 6 7 8 CM_IN– [2] 9 10 1/3MICBIAS 11 12 1/2VBAT 2/3MICBIAS MICBIAS_1977 2 + 6 + -IN_BUFFER [1,2,4] VBAT +OUT_BUFFER [2] NOTES ON JUMPER SELECTION J2: USE FOR SELECTING THE CM LEVEL FOR THE EXTERNAL INPUT J1, J22, J31, J41, J51: USE FOR SELECTING INTERNAL OR EXTERNAL MICBIAS FOR INPUTS S12, S18, S23, S29: USE FOR SELECTING THE MICBIAS RESISTOR +INPUTS S5, S15, S20, S25: USE FOR SELECTING THE MICBIAS RESISTOR -INPUTS J20, J15, J30, J27, J40, J36, J49, J46: USE FOR SELECTING THE DIRECT OR BUFFERED INPUT J19, J29, J39, J48: USE FOR SHORTING THE +/- INPUT PINS FOR DIAGNOSTICS TEST S11, S6, S17, S14, S22, S19, S28, S24: USE FOR GENERATING FAULT ON INPUT PINS FOR DIAGNOSTICS TESTING Figure 7. EVAL-ADAU1977Z Schematic, Page 2 of 6 Rev. 0 | Page 11 of 27 11751-007 JP1 R8 100kΩ TP5 TIP RING C19 10µF 3 + R13 R12 10.0Ω [2] CM_IN+ 1 2 ADJUST FOR DESIRED CM LEVEL R5 R1 1 O + 4 V– 1 V+ 8 – 2 2 R16 10.0kΩ 3 100kΩ TP52 SLEEVE C12 0.10µF CW 10µF C18 TP16 +IN_BUFFER J9 CM INPUT SELECT HVDD 22pF C16 R17 UG-600 Evaluation Board User Guide 47.5kΩ 3 R71 47.5kΩ 16 R61 47.5kΩ 1 VCCA VCCY 5 Y B A LK1 GND A 3 U9 FXLP34P5X 28 47.5kΩ 4 R62 47.5kΩ 5 R66 47.5kΩ 18 10.0kΩ R58 0.10µF C75 +3.3V 600Ω @ 100MHz 0.10µF 23 HWCK1 ORIG GND 1 2 20 R76 47.5kΩ 27 SFMT0 SFMT1 R74 47.5kΩ 2 NC2 RST 15 TCBL 47.5kΩ V 1 C79 10nF SPDIF COAX OUTPUT 243Ω NC1 U INPUT +3.3V J34 9 R72 IOVDD R63 47.5kΩ U16 3 TOTX147L(FT) COPY/C NC3 0.10µF C26 BCLK_IO 7 2 U19 CTP-021A-S-YEL 1 5 4 8 6 HI J35 8 17 R67 47.5kΩ 110Ω LO C87 22pF Y A LK6 B A 3 JP4 VCCA 5 VCCY 2 22 SC937-02_AES_TRANSFORMER 1 [1] MCLKIN_1977 GND [1] BCLK_X 4 47.5kΩ R59 47.5kΩ 47.5kΩ 10 11 HWCK0 R77 R73 R64 19 TCBLD 0.10µF C69 0.10µF C24 B A LK2 +3.3V R65 10.0kΩ U17 CS8406_HARDWARE CEN U14 FXLP34P5X 2 APMS EMPH 47.5kΩ R69 0.10µF C48 R60 R75 24 OMCK AUDIO 2 DVDD 25 R68 VCCA VCCY B A LK3 H/S C73 0.10µF 26 ISCLK 21 4 Y IOVDD LRCLK_IO SDATA2_OUT 5 A 1 TXP TXN ILRCLK 128*Fs SDIN 12 +3.3V GND 0.10µF C17 B A LK5 +3.3V 1 +3.3V L4 INSTALL FOR 96KHz Fs GND U15 FXLP34P5X IOVDD 2 SPDIF OPTICAL OUTPUT VL 6 14 VD VCCA VCCY Y 3 [1] LRCLK_X SDATA1_OUT 4 13 [1] SDATAOUT2/TDM_SEL_X C107 GND B A LK4 [1] SDATAOUT1_X +3.3V C81 +3.3V 5 A 3 0.10µF C99 0.10µF C63 1 2 +3.3V 0.10µF I2S TO SPDIF +3.3V IOVDD RESET_SPDIF 4 U18 FXLP34P5X NC 24.9Ω R48 49.9Ω R46 24.9Ω R44 24.9Ω R43 24.9Ω R39 24.9Ω R40 24.9Ω 1k00 1k00 R52 R57 100pF 100pF C64 1k00 OE4 1 A1 Y1 1 3 5 7 J26 3 SN74LVC125ADR IOVDD SLAVE_SEL C59 U11-A 2 6 R42 R70 10pF C82 R54 R37 10pF 10pF C54 C44 R51 10pF C58 4 2 4 6 8 OE2 A2 Y2 11 Y4 OE1 U11-B 5 MASTER_SEL [3] IOVDD A4 13 49.9Ω 49.9Ω 49.9Ω 49.9Ω 12 R45 U11-D LRCLK_IO SDATA1 SDATA2 BCLK LRCLK 1k00 R49 100pF BCLK_IO 49.9Ω 100pF SDATA2_OUT R55 C52 A3 U11-C 8 Y3 C47 SDATA1_OUT I2S/TDM OUTPUT OE3 10 9 [3] 5 U13 NC7SZ125 2 A GND 2 C96 0.10µF IOVDD 3 MASTER_SEL [3] SPST_1SEC_SMD IOVDD U8 2 4 NC7SZ04M5 MASTER / SLAVE SELECT C80 0.10µF SLAVE_SEL [3] 5 U10 NC7SZ125 4 7 GND S13 1 VCCY Y OE 14 VCC 1 4 R38 10.0kΩ 1 Y OE VCCY A GND 2 U11-E SN74LVC125ADR C72 0.10µF 3 I2S OUTPUT 11751-008 NOTES ON JUMPER SELECTION LK3, LK5: USE FOR ROUTING THE SDATA TO SPDIF OR I2S HEADER LK2: USE FOR ROUTING THE LRCLK TO SPDIF OR I2S HEADER LK2: USE FOR ROUTING THE BCLK TO SPDIF OR I2S HEADER LK2: USE FOR ROUTING THE MCLK TO SPDIF S13: USE FOR SELECTING THE I2S BUFFER AS MASTER OR SLAVE Figure 8. EVAL-ADAU1977Z Schematic, Page 3 of 6 Rev. 0 | Page 12 of 27 Figure 9. EVAL-ADAU1977Z Schematic, Page 4 of 6 2 1 2 1 TP48 J4 BINDING_POST_571_BLK +5VDC J5 BINDING_POST_571_RED +5V INPUT HVSS HVDD +5V_EXT TP6 TP1 TP9 TP3 –22VDC MAX GND +22VDC MAX C1 47µF C2 47µF D2 L1 100Ω @ 100MHz + C3 0.10µF + C4 0.10µF 3 IN D4 4 +5V C11 + 0.10µF C109 1µF C35 0.10µF + +5V C29 15µF 1.8V REG SELECT 1 B A J12 2 TP19 EXT_VBAT VBAT 3 D3 R26 475R Red Diffused C15 47µF C22 0.10µF TP8 ADJ OUT1 U2 LM317BD2T 1 +15V_REG 243Ω 2.67kΩ D1 DL4001_50V_1A_DL41 R23 R24 TP20 2 S2 1 SPST_1SEC_SMD C30 1.0µF C34 0.10µF J53 1 A2 B 3 2.21kΩ R14 S1 FB TRK FREQ SYNC/MODE 2 3 BYP EN GND 2 U4 4 ADP1711AUJZ-1.8-R7 1 5 OUT IN R18 10.0kΩ 4 3 2 1 R11 10.0kΩ 17 EPAD 16 PGOOD 15 1 6 GND 5 EN PGND 14 VIN PGND 7 C33 10nF SW SW SW PVIN R10 10Ω 13 PVIN PGND 8 3.3V REG SELECT 10k0 R25 Rev. 0 | Page 13 of 27 C31 1.0µF + 1.8V ADP2118 9 10 11 12 U3 L2 2 C14 100µF C32 10µF 1 +5V C110 0.10µF IOVDD SELECT 1.8V +3.3V 1 C28 100µF +3.3V_REG TP17 A B J13 2 +3.3V HDR-3WAY J10 3 B 2A 1 HV INPUT TP22 3 C8 OPEN C7 NF AVDD_EXT J3 BINDING_POST_571_RED 2 1 25V 1 1 DVDD_IN TP7 DVDD_IN TP15 TP13 IOVDD_EXT J7 BINDING_POST_571_RED C9 OPEN 2 1 2 1 TP21 J6 BINDING_POST_571_RED IOVDD_INT +3.3V_EXT TP18 TP31 TP37 2 3 A B J14 AVDD 2 3 A B J11 +3.3V IOVDD IOVDD_INT TP2 Evaluation Board User Guide UG-600 11751-009 UG-600 Evaluation Board User Guide IOVDD I2C LEVEL SHIFT & DUT ADDRESS I2C, SPI or STAND-ALONE MODE SELECT +3.3V IOVDD R33 10.0kΩ IOVDD ADDRESS S9 4 3 C55 0.10µF 0.10µF TP11TP10 C25 LEVEL SHIFT 8 VCCA 7 VCCB SCLA 6 SCLB SDAB U6 SDAA 5 EN GND USBI_SCL[5,6] USBI_SDA[5,6] R20 2k00 1 2 3 4 R34 10.0kΩ 1 2 R19 2k00 I2C-SPI OR SA MODE SELECT I2C COMMUNICATION PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8 8 7 B1 6 A1 B2 U5 A2 GND USBI_CLATCH [5] VCCA USBI_CIN_MOSI [5] VCCB C83 0.10µF 1 +3.3V IOVDD SPI LEVEL SHIFT DIR 2 +3.3V 2 MS_SEL 4 ADDR0 5 CLATCH_IOVDD 6 FMT_SEL 8 S4-A 3 ADDR1/CIN/MS_SEL [1] 7 ADDR0/CLATCH/FMT_SEL [1] 3 SCL/CCLK/FS_SEL [1] 7 SDA/COUT/MCLK_SEL [1] 3 SDATAOUT2/TDM_SEL [1] 7 FAULT/TBD_SEL [1] S4-B 3 SCL_IOVDD 1 5 CCLK_IOVDD 2 FS_SEL 4 SDA_IOVDD 5 COUT_IOVDD 6 MCLK_SEL 8 VCCA IOVDD +3.3V 3 S5-A 5 Y A 3 S5-B 4 FXLP34P5X U23 USBI_COUT_MISO [5] C114 0.10µF 4 5 4 6 JP6 IOVDD U24 FXLP34P5X TBD_SEL SA_MODE SA_MODE [1] 8 S3-B R79 10.0kΩ R32 R31 R30 R29 R28 R27 S8 S3-A 2 TDM_SEL STAND ALONE MODE 12 11 10 9 1 C51 0.10µF 10.0kΩ 10.0kΩ 10.0kΩ 10.0kΩ 10.0kΩ 10.0kΩ 2 USBI_CCLK [5] IOVDD IOVDD VCCY 1 GND C27 0.10µF VCCA R133 10.0kΩ +3.3V GND 5 2 A Y VCCY 1 C113 0.10µF 1 4 SN74LVC2T45DCTR C62 0.10µF ADDR1 CIN_IOVDD 1 2 3 4 R36 1k00 8 5 R35 1k00 7 6 USBi OR AARDVARK I2C INTERFACE +3.3V USBI_CLK USBI_5V00 USBI_CIN_MOSI [5] 2 4 6 8 10 J8 R21 2.43kΩ 1 3 5 7 9 NOTES FOR JUMPERS AND SWITCHES S3, S4, S5 ARE 3 WAY SWITCHES TO BE USED IN TANDEM FOR I2C, SPI OR SA MODE SET ALL THREE SWITCHES TO EITHER LEFT, CENTER OR RIGHT S8 IS USED FOR SETTING THE PIN FUNCTIONS IN SA MODE J8: USE FOR CONNECTING THE AARDVARK I2C/SPI CONTROL ADAPTER OR USBI R15 10.0kΩ USBI_SCL [5,6] USBI_SDA [5,6] USBI_COUT_MISO [5] USBI_CCLK [5] USBI_CLATCH [5] 11751-010 R22 2.43kΩ MR LINE COMES FROM USBi BOARD RESET Figure 10. EVAL-ADAU1977Z Schematic, Page 5 of 6 Rev. 0 | Page 14 of 27 C21 0.10µF C20 0.10µF 5 8 2 + Q5 4 +3.3V 5 8 2 + Q7 4 K6 D10 D12 + Q6 K8 5 8 + Q8 4 FAULT_IN– TO AIN2N 5 8 4 K1 D6 + Q1 4 K2 5 8 + Q2 4 FAULT_IN+ TO AIN2P 5 8 2 FAULT_IN+ [2,6] +3.3V D5 U22 MAX7310-QSOP16 16 1 SCL VDD 15 2 SDA 3 AD0 RESET 14 IO7 13 4 AD1 IO6 5 AD2 IO5 12 6 IO0 IO4 11 7 IO1 IO3 10 8 GND IO2 9 C23 0.10µF FAULT_IN+ TO AIN1P 2 FAULT_IN+ [2,6] +3.3V USBI_SCL [5,6] USBI_SDA [5,6] FAULT_IN– TO AIN1N 2 FAULT_IN– [2,6] +3.3V FAULT GENERATION FOR AUTOMATED TESTING FAULT_AIN2P_AIN2N [6] FAULT_AIN2N [6] FAULT_AIN2P [6] D11 A K K7 SHORT AIN2P TO AIN2N FAULT_AIN1P_AIN1N [6] FAULT_AIN1N [6] FAULT_AIN1P [6] D9 +3.3V A K K5 OUT 3 OUT 3 2 FAULT_IN– [2,6] +3.3V FAULT_IN– [2,6] FAULT_IN+ [2,6] SHORT AIN1P TO AIN1N TP14 TP12 1 1 OUT 3 OUT 3 IN IN 1 1 GND 2 GND 2 OPEN OPEN OPEN R97 R103 R96 10.0kΩ 10.0kΩ 10.0kΩ R101 R104 R100 IN IN A K A K A K A K GND 2 GND 2 1 +3.3V AIN2N [1,2] INPUT CH2 AIN2P [1,2] AIN1N [1,2] 10.0kΩ +3.3V DISABLE_FAULT_LOGIC USBI_SCL [1,2] USBI_SDA [1,2] D13 +3.3V + Q9 4 FAULT_AIN4P_AIN4N [6] FAULT_AIN4N [6] FAULT_AIN4P [6] D15 +3.3V 5 8 2 K11 + Q11 4 SHORT AIN4P TO AIN4N 5 8 2 K9 SHORT AIN3P TO AIN3N D16 + Q10 4 K12 5 8 + Q12 4 FAULT_IN– TO AIN4N 5 8 2 FAULT_IN– [2,6] +3.3V D14 2 FAULT_IN– [2,6] +3.3V K10 FAULT_IN– TO AIN3N U21 MAX7310-QSOP16 16 1 SCL 2 SDA VDD 15 3 AD0 RESET 14 IO7 13 4 AD1 IO6 5 AD2 IO5 12 6 IO0 IO4 11 7 IO1 IO3 10 8 GND IO2 9 D8 + Q3 4 K4 5 8 + Q4 4 FAULT_IN+ TO AIN4P 5 8 2 FAULT_IN+ [2,6] +3.3V D7 2 FAULT_IN+ [2,6] +3.3V K3 FAULT_IN+ TO AIN3P FAULT_AIN4P [6] FAULT_AIN1P_AIN1N [6] FAULT_AIN2P_AIN2N [6] FAULT_AIN4P_AIN4N [6] FAULT_AIN3P_AIN3N [6] +3.3V I2C ADDRESS 0x19Hex FAULT GENERATION LOGIC CONTROL2 DISABLE FAULT LOGIC FAULT_AIN3P_AIN3N [6] FAULT_AIN3N [6] FAULT_AIN3P [6] R88 FAULT_AIN4N [6] FAULT_AIN1N [6] FAULT_AIN1P [6] FAULT_AIN2N [6] FAULT_AIN2P [6] FAULT_AIN3N [6] FAULT_AIN3P [6] AIN1P [1,2] INPUT CH1 +3.3V I2C ADDRESS 0x18Hex JP10 A K A K OUT 3 OUT 3 OPEN OPEN 10.0KΩ R99 R102 R94 10.0kΩ 10.0kΩ OPEN R95 R98 R93 OUT 3 OUT 3 FAULT GENERATION LOGIC CONTROL1 1 IN 1 IN GND 2 GND 2 GND 2 GND 2 1 IN IN OUT 3 OUT 3 GND 2 C76 0.10µF 1 A K A K A K A K GND 2 GND 2 OUT 3 OUT 3 1 IN IN 1 IN 1 Rev. 0 | Page 15 of 27 IN Figure 11. EVAL-ADAU1977Z Schematic, Page 6 of 6 GND 2 +3.3V INPUT CH4 INPUT CH3 AIN4N[1,2] AIN4P[1,2] AIN3N[1,2] AIN3P[1,2] Evaluation Board User Guide UG-600 11751-011 UG-600 Evaluation Board User Guide 11751-012 BOARD LAYOUT Figure 12. EVAL-ADAU1977Z/EVAL-ADAU1978Z/EVAL-ADAU1979Z Top Assembly Rev. 0 | Page 16 of 27 UG-600 11751-013 Evaluation Board User Guide Figure 13. EVAL-ADAU1977Z Top Layer Rev. 0 | Page 17 of 27 Evaluation Board User Guide 11751-014 UG-600 Figure 14. EVAL-ADAU1977Z Layer 2 Rev. 0 | Page 18 of 27 UG-600 11751-015 Evaluation Board User Guide Figure 15. EVAL-ADAU1977Z Layer 3 Rev. 0 | Page 19 of 27 Evaluation Board User Guide 11751-016 UG-600 Figure 16. EVAL-ADAU1977Z Bottom Layer Rev. 0 | Page 20 of 27 UG-600 11751-017 Evaluation Board User Guide Figure 17. EVAL-ADAU1977Z/EVAL-ADAU1978Z/EVAL-ADAU1979Z Top Silkscreen Rev. 0 | Page 21 of 27 Evaluation Board User Guide 11751-018 UG-600 Figure 18. EVAL-ADAU1977Z Fabrication Drawing Rev. 0 | Page 22 of 27 Evaluation Board User Guide UG-600 ORDERING INFORMATION BILL OF MATERIALS Table 3. Qty 1 2 Component Number C10, C19 NF C107, C108 1 C109 34 NF C11, C17, C23 to C27, C42, C46, C48, C51, C53, C55, C61 to C63, C65 to C69, C72, C75, C76, C80, C81, C83, C96, C99, C101, C106, C110, C113, C114 C111, C112 3 C1, C2, C15 2 C14, C28 NF C20, C21 1 C29 2 C30, C31 1 C32 2 C33, C79 8 C3, C4, C12, C13, C22, C34, C35, C73 C36, C40, C56, C77, C84, C88, C91, C102 C37, C43, C49, C60, C78, C85, C89, C92, C103 C38, C41, C57, C74, C86, C90, C93, C100 NF 9 8 1 C39, C50 6 C44, C54, C58, C82, C104, C105 NF C45 4 C47, C52, C59, C64 2 C5, C18 Description Ceramic capacitor, 10 µF, 50 V, X7R, 20%, 2220 Multilayer ceramic, 16 V, X7R (0402) Multilayer ceramic capacitors (MLCC), 50 V, X7R (1206) Ceramic capacitor, 0.1 µF, 16 V, 10%, X7R, 0402 Manufacturer Digi-Key Part Number 445-1454-1-ND Digi-Key PCC13490CT-ND Digi-Key 490-4795-6-ND Digi-Key 490-3261-1-ND Digi-Key 490-1494-1-ND Digi-Key PCE4008CT-ND Digi-Key 490-3390-1-ND Digi-Key PCC2398CT-ND Digi-Key 511-1448-1-ND Digi-Key 490-3900-1-ND Digi-Key 511-1447-1-ND Digi-Key 445-2664-1-ND Digi-Key 490-1519-1-ND Digi-Key P14254CT-ND Ceramic capacitor, 1000 pF, 50 V, 10%, X7R, 0603 Aluminium electrolytic capacitor frequency converter (FC,) 105°, surfacemount device B (SMD_B) Digi-Key 490-1494-1-ND Digi-Key PCE3995CT-ND Multilayer ceramic, 25 V, X7R (1210), AECQ200 Multilayer ceramic, 50 V, NP0 (0402) Aluminium electrolytic capacitor frequency converter (FC), 10 µF, 50 V, 105°, radial Multilayer ceramic, 50 V, NP0 (0402) Aluminium electrolytic capacitor frequency converter (FC), 10 µF, 50 V, 105°, radial Digi-Key 490-4798-1-ND Digi-Key 399-1011-1-ND Digi-Key PCE4012CT-ND Digi-Key 490-4756-1-ND Digi-Key PCE4012CT-ND Ceramic capacitor, 1000 pF, 50 V, 10%, X7R, 0603 Aluminium electrolytic capacitor frequency converter (FC), 105°, surfacemount device E (SMD_E) Multilayer ceramic, 6.3 V, X5R (1210 ) Multilayer ceramic, 50 V, X7R (0603) Surface-mount device (SMD), tantalum capacitor, 0805, 6.3 V Ceramic capacitor, 1 µF, 16 V, 10%, X7R, 0603 SMD, tantalum capacitor, 0805, 6.3 V Multilayer ceramic, 25 V, NP0 (0603) Ceramic capacitor, 0.1 µF, 50 V, 10%, X7R, 0603 Multilayer varistor, 65 V, 0603 Rev. 0 | Page 23 of 27 UG-600 Qty 1 3 Component Number C6, C16, C87 NF C7 2 C70, C71 NF C8, C9 1 C94 1 C95 1 C97 1 C98 2 D1, D4 1 D2 1 D3 NF D5, D16 20 J1, J10 to J15, J20, J22, J27, J30, J31, J36, J40, J41, J43, J4, J6, J49, J51, J53 J16, J19, J21, J24, J29, J33, J34, J39, J42, J44, J45, J48, J54 13 NF 1 1 1 J18, J23, J32, J37 J2 J25 J26 NF J3, J6, J7 1 J35 1 J4 1 J5 1 1 J50 J52 1 J8 5 J9, J17, J28, J38, J47 NF JP10 Evaluation Board User Guide Description Multilayer ceramic, 50 V, NP0 (0402) Multilayer ceramic, 25 V, X7R (1210), AECQ200 Multilayer ceramic, 10 V, X7R (0805) Multilayer ceramic, 10 V, X7R (0805) Multilayer ceramic, 25 V, NP0 (0402) Multilayer ceramic, 50 V, NP0 (0402) Multilayer ceramic, 25 V, NP0 (1206) Multilayer ceramic, 25 V, NP0 (0603) Passivated rectifier 1 A, 50 V, metal oxide leadless face (MELF) Transient voltage suppressor (TVS) Zener, 15 V, 600 W, surface-mount board (SMB) Red diffused, 6.0 millicandela, 635 nm, 1206 Passivated rectifier 1 A, 50 V, metal oxide leadless face (MELF) 3-position, single inline package (SIP) header 2-pin header, unshrouded jumper 0.10"; use shunt Tyco 881545-2 20-way, unshrouded 12-way, unshrouded 16-way, unshrouded 8-way, unshrouded header, dual row Binding post, mini, right angle, red, uninsulated base, through hole (TH) RCA jack, PCB through hole (TH) mount, right angle, yellow Binding post, mini, right angle, black, uninsulated base through hole (TH) Binding post, mini, right angle, red, uninsulated base, through hole (TH) 6-way, unshrouded header SMA, receptacle straight, (PCB) mount 10-way, shroud, polarized header Stereo mini jack, surfacemounted (SMT) 2-pin header, unshrouded Manufacturer Digi-Key Part Number 490-1283-1-ND Digi-Key 490-4798-1-ND Digi-Key 490-3905-1-ND Digi-Key 490-3905-1-ND Mouser 77-VJ0402Y222JXXCBC Digi-Key 490-1296-1-ND Digi-Key 490-3361-1-ND Digi-Key 445-2666-1-ND Digi-Key DL4001-TPMSCT-ND Digi-Key 1SMB15AT3GOSCT-ND Digi-Key 67-1003-1-ND Digi-Key DL4001-TPMSCT-ND Digi-Key S1011E-03-ND Digi-Key S1011E-02-ND Digi-Key Digi-Key Digi-Key Digi-Key S2011E-10-ND S2011E-06-ND S2011E-08-ND S2011E-04-ND; or cut S2011E-36-ND Mouser 164-6220 Connect-Tech Products CTP-021A-S-YEL Mouser 164-6218 Mouser 164-6219 Digi-Key Digi-Key S2011E-03-ND ARFX1231-ND Digi-Key MHC10K-ND Digi-Key CP-3523SJCT-ND Digi-Key S1011E-02-ND Rev. 0 | Page 24 of 27 Evaluation Board User Guide Qty 1 Component Number 10 JP1 to J9, JP11 NF K1 to K12 1 L1 1 L2 1 L3 1 L4 1 L5 6 LK1 to LK6 NF Q1 to Q12 8 3 R105, R107, R109, R112, R114, R116, R118, R120 R106, R108, R110, R113, R115, R117, R119, R121 R11, R18, R25 NF R111 NF R131 to R132 1 R14 24 2 R1 to R4, R7, R9, R15 to R17, R27 to R34, R58, R79, R82, R84, R92, R133, R134 R19, R20 2 R21, R22 1 R23 1 R24 1 R26 7 2 R35, R36, R42, R45, R52, R57, R81 R37, R47, R48, R50, R51, R53 to R56, R70, R78, R85 to R87 R38, R65 6 R39, R40, R43, R44, R46, R49 NF R41 8 14 UG-600 Description jumper, 0.10"; use shunt Tyco 881545-2 2-pin header, unshrouded jumper, 0.10"; use shunt Tyco 881545-2 Relay Telecom, single-pole single throw (SPST),1 A, 3 V dc SMA Chip ferrite bead, 100 Ω at 100 MHz Inductor, 2.2 µH, 1.7 A, SM1515 Inductor, 4.7 µH, 2.4 A, surface-mount device Chip ferrite bead, 600 Ω at 100 MHz Chip ferrite bead, 600 Ω at 100 MHz 3-position, single inline package (SIP) header Negative-positive-negative (NPN), general-purpose, transistor with bias DDTC114EKA-7-F Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 0.1%, 100 mW, thin film, 0603 Chip resistor, 0.1%, 1 W, thick film, 0805 Chip resistor, 1%, 250 mW, thick film, 1206 Chip resistor, 0.1%, 100 mW thin film, 0603 Chip resistor ,1%, 63 mW, thick film, 0402 Chip resistor,1%, 63 mW, thick film, 0402 Chip resistor ,1%, 63 mW, thick film, 0402 Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 1%, 63 mW, thick film, 0402 Chip resistor, 1%, 63 mW, thick film, 0402 Chip resistor,1%, 63 mW, thick film, 0402 Chip resistor, 1%, 125 mW, thick film, 0603 Chip resistor, 1%, 63 mW, thick film, 0402 Chip resistor, 5%, 125 mW, thick film, 0805 Manufacturer Part Number Digi-Key S1011E-02-ND Digi-Key. Z1230-ND Digi-Key 587-1929-1-ND Digi-Key 490-5326-1-ND Digi-Key 732-1039-1-ND Digi-Key 445-2205-1-ND Digi-Key 445-2162-1-ND Digi-Key S1011E-03-ND Digi-Key DDTC114EKA-7-FDICT-ND Digi-Key P301CCT-ND Digi-Key P499CCT-ND Digi-Key TNP10.0KAACT-ND Digi-Key Y1487-.01-ND Digi-Key P10.0FCT-ND Digi-Key TNP2.21KAACT-ND Digi-Key P10.0KLCT-ND Digi-Key P2.00KLCT-ND Digi-Key P2.43KLCT-ND Digi-Key P243CCT-ND Digi-Key P2.67KCCT-ND Digi-Key P475LCT-ND Digi-Key P1.00KLCT-ND Digi-Key P49.9LCT-ND Digi-Key P10.0KHCT-ND Digi-Key P24.9LCT-ND Digi-Key P1.0ACT-ND Rev. 0 | Page 25 of 27 UG-600 Qty1 1 Component Number R5 15 R59 to R64, R66, R67, R71 to R77 3 R6, R10, R12 1 R68 1 R69 2 R8, R13 1 R80 11 R83, R90, R122 to R130 NF NF R88, R93, R95, R98, R100, R101, R104 R89, R91 NF 3 R94, R96, R97, R99, R102, R103 S1 to S2, S13 1 3 S27 S3 to S5 NF S6, S11, S14, S17, S19, S22, S24, S28 S7, S9, S10, S12, S15, S16, S18, S20 to S21, S23, S25, S26, S29 13 1 S8 75 TP1 to TP11, TP15 to TP77 NF TP12 to TP14 1 U1 2 U10, U13 1 U11 1 U12 1 U16 1 U17 1 U19 Evaluation Board User Guide Description Trim potentiometer, 10 k Ω linear, 3 mm, single turn, surface-mount device (SMD) top adjust Chip resistor,1%, 63 mW, thick film, 0402 Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 1%, 125 mW, thick film, 0805 Chip resistor, 1%, 100 mW, thick film, 0603 Chip resistor, 1%, 125 mW, thick film, 0603 Chip resistor, 1%, 63 mW, thick film, 0402 Chip resistor, 5%, 63 mW, thick film, 0402 Chip resistor, 1%, 63 mW, thick film, 0402 Chip resistor, 1%, 100 mW, thick film, 0603 Do not stuff 1 section, single-pole single throw, (SPST), surface-mount device (SMD) Tact switch, 6 mm gull wing Switch glide, DP3T PC, mount L = 4 mm Switch rotary, 1P5T, top adjust through hole 2 section, single-pole single throw, surface-mount device, switch raised act 6 section, single-pole single throw, surface-mount device, switch raised act Mini test point, white, 1" outer diameter Mini test point, white, 1" outer diameter Dual bipolar/junction, field effect transistor (JFET), audio operational amplifier. IC, buffer tristate, noninverting, SC70-5 Quad buffer, tristate, 14-lead SOIC IC, 4-channel ADC with diagnostics, ADAU1977 40lead LFCSP Fiber optic transmit module, 15 Mbs with shutter 192 kHz, Sony Philips digital interface format (SPDIF) transmitter 110 Ω audio, Engineering Society/European Broadcaster Union (AES/EBU) Manufacturer Digi-Key Part Number 490-2644-1-ND Digi-Key P47.5KLCT-ND Digi-Key P10.0CCT-ND Digi-Key P110CCT-ND Digi-Key P243HCT-ND Digi-Key P100KHCT-ND Digi-Key P4.87KLCT-ND Digi-Key P0.0JCT-ND Digi-Key RHM10.0KLCT-ND Digi-Key P100HCT-ND OPEN Digi-Key OPEN 563-1003-1-ND Digi-Key Digi-Key 450-1133-ND EG1920-ND Digi-Key 563-1078-ND Digi-Key CT2192LPST-ND Digi-Key CT2196LPST-ND Digi-Key 5002K-ND Digi-Key 5002K-ND Analog Devices Inc. OP275GSZ Digi-Key NC7SZ125P5XCT-ND Digi-Key 296-8453-1-ND Analog Devices, Inc. ADAU1977WBCPZ Digi-Key TOTX147L-ND Newark In One 88H6508 Scientific Conversion Inc. SC937-02 Rev. 0 | Page 26 of 27 Evaluation Board User Guide Qty1 Component Number 1 U2 NF U21, U22 1 U3 1 U4 2 U5, U20 1 U6 1 U8 6 U9, U14, U15, U18, U23, U24 1 Y1 1 UG-600 Description transformer Integrated circuit, positive voltage regulator LM317, adjust, D2PAK Integrated circuit, I2C, 8-bit, input/output expander Step down, dc to dc, voltage regulator, ADP2118 Adjustable, low dropout, voltage regulator Integrated circuit, 2-bit, dual bus TXRX, 8-lead shrink small outline package (SSOP) Integrated circuit, I2C bus repeater, 8-lead thin shrink small outline package (TSSOP) Integrated circuit, tiny logic inverter, NC7SZ04 Translator, 1-bit, unidirect, SC70-5 12.288 fixed, surface-mount device (SMD) oscillator, 1.8 V to 3.3 V voltage direct current (VDC) Manufacturer Part Number Digi-Key LM317BD2TR4GOSCT-ND Digi-Key MAX7310AEE+-ND Digi-Key ADP2118ACPZ-R7CT-ND Analog Devices ADP1711AUJZ-1.8-R7 Digi-Key 296-16845-1-ND Digi-Key 568-1829-2-ND Digi-Key NC7SZ04M5CT-ND Digi-Key FXLP34P5XCT-ND Digi-Key AP3S-12.288MHz-F-J-B NF: not fitted or do not populate; ALT: alternate or equivalent. ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11751-0-8/14(0) Rev. 0 | Page 27 of 27