Evaluation Board User Guide UG-564 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the ADAU1962A/ADAU1966A High Performance, Low Power Multibit Sigma-Delta DAC PACKAGE CONTENTS evaluation board must be connected to an external 12 V dc power supply and ground. On-board regulators derive 5 V and 3.3 V supplies for the ADAU196xA and peripherals. ADAU1962A/ADAU1966A evaluation board (EVAL-ADAU1962AZ/EVAL-ADAU1966AZ) USBi control interface board USB cable 12 V desktop supply The ADAU196xA can be controlled through either an I2C or SPI interface. A small, external interface board, EVALADUSB2EBZ, also called USBi, connects to a PC USB port and provides either I2C or SPI access to the evaluation board through a ribbon cable. OTHER SUPPORTING DOCUMENTATION ADAU1962A data sheet ADAU1966A data sheet A graphical user interface (GUI) program, the Automated Register Window Builder, is provided for easy programming of the chip in a Windows® PC environment. The evaluation board allows demonstration and performance testing of most ADAU196xA features, including high performance DAC operation. EVALUATION BOARD OVERVIEW This user guide describes the design and setup of the evaluation board for the ADAU1962A or the ADAU1966A. This document uses ADAU196xA to refer to either the ADAU1962A or the ADAU1966A. Since the ADAU1962A is a 12-channel part and the ADAU1966A is a 16-channel part, DAC outputs 13 through 16 do not function on the ADAU1962A evaluation board. The The board has an S/PDIF receiver with RCA and optical connectors, as well as a discrete serial audio interface. Analog outputs are accessible via eight stereo TRS mini jacks. FUNCTIONAL BLOCK DIAGRAM S/PDIF INTERFACE SDP INTERFACE POWER SUPPLY CLOCK ADAU196xA AND DATA ROUTING DAC 1 TO DAC 16 11588-001 CONTROL INTERFACE Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 32 UG-564 Evaluation Board User Guide TABLE OF CONTENTS Package Contents .............................................................................. 1 Powering the Board.......................................................................5 Other Supporting Documentation ................................................. 1 Resetting the Evaluation Board ...................................................5 Evaluation Board Overview ............................................................ 1 Setting Up the Master Clock (MCLK)........................................6 Functional Block Diagram .............................................................. 1 Selecting PLL .................................................................................6 Revision History ............................................................................... 2 Routing Digital Audio Connections ...........................................7 Setting Up the Evaluation Board .................................................... 3 Connecting Analog Audio Cables ..............................................8 Standalone Mode .......................................................................... 3 Modification for Differential Output .........................................8 I C and SPI Control ...................................................................... 3 Modification to Use the N Output ..............................................8 Automated Register Window Builder Software Installation .. 4 Schematics and Artwork ..................................................................9 Hardware Setup—USBi ............................................................... 4 Bill of Material ................................................................................ 25 2 REVISION HISTORY 7/13—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Evaluation Board User Guide UG-564 SETTING UP THE EVALUATION BOARD STANDALONE MODE The ADAU196xA has a standalone mode, which allows the user to choose between a limited number of operation modes without the need for a control interface. Applying a jumper across JP21, as shown in Figure 2, pulls SA_MODE (Pin 46) high enabling standalone mode in the ADAU196xA. The SA_MODE selections are listed in Table 1. Table 1. Standalone Modes Pin Pin 42 Pin 43 Pin 44 Pin 45 Pin 32 to Pin 31 Setting 0 1 0 1 0 0 1 00 01 10 11 Description Master serial audio interface Slave serial audio interface 256 × fS 384 × fS Reserved, set to 0 I2S mode TDM mode TDM4, pulse TDM8, pulse TDM16, pulse TDM8, 50% duty The EVAL-ADAU196xAZ arrives configured for S/PDIF input. The S/PDIF receiver operates as a clock master, putting out an I2S stream at 256 × fS. For quick startup, the ADAU196xA is in standalone mode with the settings shown in Figure 2. Pin 42 is pulled high (1) and Pin 43 to Pin 45 are pulled low (0). According to Table 1, this puts the ADAU196xA in slave mode, running at 256 × fS, and the audio serial port in I2S mode. Looking at Figure 2, notice that the jumper for Pin 42 is beneath the label for 1 and the other pins are assigned to 0. PIN 31 PIN 32 11588-003 On the EVAL-ADAU196xAZ, each of the four control port pins of the ADAU196xA are brought out to a block of jumpers, allowing the user to assign each pin to either the I2C or SPI ports. In standalone mode, these jumpers can connect the individual pins to high (IOVDD) or low (GND) to put the ADAU196xA in the desired mode. Figure 3. SA_MODE—Master, 384 × fS, TDM Figure 3 shows the other options for each SA_MODE configuration pin; master mode, running at 384 × fS, and the audio serial port in TDM mode. In the case where the ADAU196xA is put in TDM mode, Pin 31 and Pin 32 can be pulled high (IOVDD) or low (GND) to achieve the modes listed in Table 1. The correct pins are located in the top left corner of Figure 3. I2C AND SPI CONTROL 11588-002 The evaluation board can be configured for live control over the registers in the ADAU196xA. When the Automated Register Window Builder software is installed and the USBi control interface is plugged into the board, the software can control the ADAU196xA. For this configuration, the ADAU196xA must be assigned to I2C mode using Address 00. See Figure 4 for the correct jumper positions. Figure 2. SA_MODE—Slave, 256 × fS, I2S Rev. 0 | Page 3 of 32 UG-564 Evaluation Board User Guide AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical interface for direct, live control of the ADAU196xA registers. The GUI content for a specific part is defined in a part-specific .xml file; these files are included in the software installation. To install the Automated Register Window Builder software, follow these steps: 1. 2. 11588-004 3. 4. Figure 4. ADAU196xA I2C Control, Address 00 The Automated Register Window Builder controls the ADAU196xA and is available for download at www.analog.com/ADAU1962A or www.analog.com/ ADAU1966A. Go to www.analog.com/ADAU1962A or www.analog.com/ADAU1966A and download the ARWBvXX.zip file from the product page. Open the downloaded ARWBvXX.zip file and extract the files to an empty folder on your PC. Install the Automated Register Window Builder by doubleclicking setup.exe and following the prompts. A computer restart is not required. Copy the .xml file for the ADAU196xA from the extraction folder into the folder C:\ProgramFiles\Analog Devices Inc\AutomatedRegWin, if it is not already installed. HARDWARE SETUP—USBi The ADAU196xA can also be put in SPI mode for control by other means. See Figure 5 for the correct jumper positions. To set up the USBi hardware, follow these steps: 1. 2. 3. Plug the USBi ribbon cable into the J12 I2C/SPI port. Connect the USB cable to your computer and to the USBi. When prompted for drivers, a. Choose Install from a list or a specific location. b. Choose Search for the best driver in these locations. c. Check the box for Include this location in the search. d. Find the USBi driver C:\Program Files\Analog Devices Inc\AutomatedRegWin\USB drivers. e. Click Next. f. If prompted to choose a driver, select CyUSB.sys. g. If the PC is running Windows® XP and a message appears stating that the software has not passed Windows logo testing, click Continue Anyway. 11588-005 You can now open the Automated Register Window Builder application and load the .xml file for the part on your evaluation board. Plug the 10-way ribbon cable on the USBi into the I2C/SPI port (J12) on the evaluation board. Figure 5. ADAU196xA SPI Control Rev. 0 | Page 4 of 32 Evaluation Board User Guide UG-564 POWERING THE BOARD The EVAL-ADAU196xAZ evaluation board requires a power supply input of +12 V dc and ground to the power jack; +12 V draws ~150 mA at higher sample rates with all channels running. AVDD and IOVDD are connected on the board using 0R00 Ω 0805 package resistors. Should a need arise to insert a different power source, or measure current draw of the entire board, it can be accomplished using these 0 Ω jumpers. REGULATOR OUTPUT REGULATOR SIDE 11588-006 LOAD SIDE Figure 6. AVDD and IOVDD Jumper Resistors Figure 8. ADAU196xA Power Links RESETTING THE EVALUATION BOARD The EVAL-ADAU196xAZ has provisions for resetting and powering down the ADAU196xA. S2 on the evaluation board, shown in Figure 9, is a momentary reset switch that pulls the master reset (MR) line low; this line controls the reset generator U10. MR is also connected to the USBi and the SDP interface connectors through steering diodes and protection resistors so that outside devices can control the reset state of the evaluation board as shown in Figure 25. The power-down jumper JP5 allows the MR line to be tied low. The output of the reset generator drives the PU/RST line. The PU/RST line is directly connected to two devices: the S/PDIF receiver and the ADAU196xA. The line is held low by a pull-down resistor until the reset generator U10 asserts the line high as shown in Figure 25. The PU/RST line is also connected to a pin on the SDP interface through a steering diode and protection resistor allowing external reset control. 11588-007 The ADAU196xA has an internal voltage regulator that allows the user to derive DVDD and PLLVDD from the AVDD voltage source. The external PNP transistor Q1 and and the passives, C36, C40, and R56, make the regulator circuit shown in Figure 7. Both JP9 and JP11 must be shorted to activate the circuit; JP9 supplies the emitter of the PNP and JP11 powers VSUPPLY (Pin 25) on the ADAU196xA. 11588-008 The on-board regulators provide 5 V and 3.3 V rails. The 5 V rail is derived from +12 V by a switching regulator; it supplies 5 V for the 3.3 V power supply and other peripherals via the SDP interface optional resistors R133 and R156. The 3.3 V rail is derived from the 5 V supply by an LDO linear regulator; it provides voltage to AVDD and IOVDD as well as other active peripherals. Links are provided along each ADAU196xA power rail to provide access for current measurement of only the ADAU196xA (see Figure 8). These links also allow the user to directly supply voltage from an outside source. The square pins and the test points are the load side. All four links must be connected for proper operation. Rev. 0 | Page 5 of 32 11588-009 Figure 7. ADAU196xA Internal Regulator Jumpers Figure 9. Reset Switch and Power-Down Jumper UG-564 Evaluation Board User Guide SETTING UP THE MASTER CLOCK (MCLK) SELECTING PLL The MCLK routing on the evaluation board is handled by a block of jumpers, J5, allowing any one of four sources to be selected—S/PDIF, the SMA connector, active OSC, and the INTF connector. The board arrives with S/PDIF selected as shown in Figure 10. The PLL in the ADAU196xA is very flexible, allowing the part to run from a wide range of either MCLK or LRCLK frequencies. 11588-010 11588-013 It is also possible to shut the PLL off altogether and use the part in direct lock mode; functionality with no PLL is limited to 256 × fS. Figure 13. MCLK Selection for PLL Loop Filter By default, the ADAU196xA runs from the PLL using MCLK as the clock source. The MCLK loop filter must be selected using JP2 as shown in Figure 13. Figure 10. SPDIF Selected as MCLK Source 11588-014 The evaluation board has a 12.288 MHz active oscillator that can be selected by shorting the OSC_EN jumper JP8 and selecting OSC on J5 as shown in Figure 11. 11588-011 Figure 14. LRCLK Selection for PLL Loop Filter Figure 11. Active OSC Enabled and Selected as MCLK 11588-012 The evaluation board can be set to receive MCLK from the SDP interface connectors. To do so, select the INTF setting on J5 and enable the MCLK buffer by shorting jumper J6, MCLK_SEL, as shown in Figure 12. DLRCLK can be selected as the PLL clock source using the PLL and Clock Control 0 Register [7:6]. In this case, the LRCLK loop filter must be selected as shown in Figure 14. If DLRCLK is selected as the PLL clock, there is no need for an MCLK. Figure 12. INTF Input Enabled and Selected Rev. 0 | Page 6 of 32 Evaluation Board User Guide UG-564 ROUTING DIGITAL AUDIO CONNECTIONS The ADAU196xA evaluation board has two separate inputs for digital audio signals: the S/PDIF and the SDP interface. 11588-015 11588-017 The S/PDIF receiver can handle either of two options: S/PDIF uses the RCA jack, J1, and optical uses the Toslink jack, U1. The input is selected using S1 as shown in Figure 15. Figure 15. S/PDIF Input Selector Switch SW1 Figure 17. S/PDIF Data and Clock Routing The system development platform (SDP) interfaces, J6 and J8, make up a standard interconnect within Analog Devices, Inc. They provide for the transfer of digital audio clocks and control between boards. See the pinout included in the schematic in Figure 27. A series of resistors have been provided to set the functional mode of the S/PDIF receiver as shown in Figure 16. By default, the S/PDIF receiver runs in master mode, 256 × fS, I2S format. Consult the data sheet for the S/PDIF receiver to make the required changes to the hardware mode. 11588-016 Figure 18 shows the jumper configuration for using the SDP interface connector as the digital audio source. JP22 is set so that the DSDATA1 source from the SDP interface is driving the buffer, and this buffer is connected to all eight DSDATA inputs of the ADAU196xA. JP10 and JP12 are set for the ADAU196xA to run in slave mode from clocks supplied by the SDP interface. Figure 16. S/PDIF Mode Selection Resistors The pins in the middle column of these jumpers are connected to the DSDATAx pins of the ADAU196xA through the appropriate line termination. DBCLK and DLRCLK selections are made with JP10 and JP12 where the middle pins are connected to the DBCLK and DLRCLK pins of the ADAU196xA. Rev. 0 | Page 7 of 32 11588-018 The jumpers shown in Figure 17 are set for the S/PDIF receiver to drive the DBCLK and DLRCLK clock ports and the eight DSDATAx lines of the ADAU1962A/ADAU1966A. JP22 selects the input to a buffer; the output of this buffer shows up on the right-hand column of JP13 to JP20. Figure 18. SDP Interface DSDATA1 Distribution UG-564 Evaluation Board User Guide CONNECTING ANALOG AUDIO CABLES R5 OPEN 10µF DACN C3 OUTP OPEN + R2 OPEN R6 0Ω OUTN R3 49.9kΩ R4 OPEN Figure 19. Typical Evaluation Board Filter MODIFICATION TO USE THE N OUTPUT To evaluate the differential outputs, one can modify the board to accomplish this with a little soldering and a few parts. MODIFICATION FOR DIFFERENTIAL OUTPUT The ADAU196xA evaluation board can be modified to be used differentially. See Figure 19 for the schematic of the standard filter. To modify for balanced operation, perform the following steps for each channel: Remove R6 (0 Ω jumper). Change R1 from 470 Ω to 237 Ω (0402). Add R2 (237 Ω, 0402). Add C3 (10 µf). Add R4 (49.9 kΩ, 0402). C2 C1 2.7nF The single-ended outputs of the ADAU196xA drive the connectors directly, through a simple 1-pole RC filter with appropriate ac coupling. 1. 2. 3. 4. 5. R1 470Ω 11588-019 The board comes standard with the single-ended outputs appearing on through-hole test points as well as on the TRS mini connectors. DACP + There are two forms of the analog outputs of the ADAU196xA evaluation board: differential and single ended. The ADAU196xA evaluation board can be modified to use the DACN output instead of the DACP output. Should you need to invert all the channels, it is recommended to do so in the software using the DAC CONTROL 2 Register or by inverting the I2S data stream. See Figure 19 for the schematic of the standard filter. To modify to use the N output, perform the following steps for each channel: 1. 2. 3. 4. 5. Move R6 over to R5 (0 Ω jumper). Move R1 over to R2 (470 Ω). Move C2 over to C3 (10 µF). Move R3 over to R4 (49.9 kΩ). Install a jumper between the N and P output test points. Note that if new parts are to be used for R2, R4, R5, and C3, then R1, R3, R6, and C2 must be removed. Rev. 0 | Page 8 of 32 Evaluation Board User Guide UG-564 SCHEMATICS AND ARTWORK 12V DC INPUT POWER SUPPLY REGULATORS 5V = SWITCHING SUPPLY DESKTOP SUPPLY 24V DC INPUT MAX! MCLK SOURCES S/PDIF ACTIVE OSC CRYSTAL DSP INTF EXT IN 3.3V = LINEAR SUPPLY DERIVED FROM 5V 0Ω JUMPERS FOR EACH SUPPLY FOR CURRENT MEASUREMENT IOVDD = 3.3V BUFFERED MCLKO AVDD = 3.3V 3.3V FOR S/PDIF CORE IOVDD COMES FROM DUT IOVDD INT REG XISTOR PLLVDD DVDD S/PDIF RECEIVER OPTICAL AND COAX INPUTS, HARDWARE MODE CONTROL JUMPERS DAC DIFF OUTPUT 9 TO 16 PASSIVE RC 1 POLE SINGLE-ENDED OUTPUTS ON TRS MINI JACKS 3.3V/2.5V ADAU196xA BCLK, LRCLK, SDATA JUMPERS WITH BUFFER ALLOWS FOR DIRECT CONNECT TO DUT CLKs AND DATA DAC DIFF OUTPUT 1 TO 8 PASSIVE RC 1 POLE SINGLE-ENDED OUTPUTS ON TRS MINI JACKS DSP/FPGA INTERFACE CLKs Figure 20. Schematic, Page 1—EVAL-ADAU196xAZ Block Diagram Rev. 0 | Page 9 of 32 CM OUTPUT ON TP 11588-020 USBi CONTROL PORT, PD JUMPERS, SA_MODE JUMPERS, COM PORT JUMPERS, RESET SWITCH JP9 + C40 Q1 TP53 ADAU1966 Voltage Regulator 1k50 R56 E ZX5T953GTA [2] VSUPPLY B [6,7] USBI_CLATCH_A [6,7] USBI_CCLK [6,7] USBI_SCL [6,7] USBI_COUT USBI_SDA [6,7] [6,7] USBI_CDATA GND IOVDD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 HEADER_28WAY_UNSHROUD J11 TDM4, Pulse TDM8, Pulse TDM16, Pulse TDM8, 50% Duty Cycle 0 I2S 1 TDM Pin 45 00 01 10 11 0 No Func tion, can be set to 0 or 1 1 No Funct ion Pin 44 Pins 32:3 1 0 256x fs, PLL 1 384x fs, PLL Pin 43 VSENSE [2] 0 Master SAI 1 Slave SAI VDRIVE [2] C36 TP50 Pin 42 Standalone Modes C126 10uF TP57 C C JP11 LF C17 390pF TP26 1966_CLATCH/ADDR0 [2] 1966_CCLK/SCL [2] 1966_COUT/SDA [2] 1966_CDATA/ADDR1 [2] C20 5.6nF R27 562R MCLK JP2 A B PLLVDD C21 39nF R25 3k32 JP7 35 JP23 36 [5] 1966_DSDATA3 [5] 1966_DSDATA4 [6,9] PU_RST IOVDD JP21 SA_MODE Figure 21. Schematic, Page 2—ADAU196xA, PLL Loop Filter (LF) Selection and Internal Regulator R138 10k0 [2] 1966_CLATCH/ADDR0 [2] 1966_CCLK/SCL [2] 1966_COUT/SDA [2] 1966_CDATA/ADDR1 [5] 1966_DSDATA8 [5] 1966_DSDATA7 [5] 1966_DSDATA6 47 46 45 44 43 42 31 32 33 34 37 [5] 1966_DSDATA2 [5] 1966_DSDATA5 38 19 18 17 14 15 16 PLLVDD C67 [5] 1966_DSDATA1 TP21 C125 10uF + 28 C41 C71 27 JP4 C44 C47 CM [2] U6 PU/RST SA_MODE CLATCH/ADDR0 CCLK/SCL COUT/SDA CDATA/ADDR1 DSDATA8 DSDATA7 DSDATA6 DSDATA5 DSDATA4 DSDATA3 DSDATA2 DSDATA1 DLRCLK DBCLK MCLKO XTALO MCLKI/XTALI PLLGND LF C127 10uF + 1966_IOVDD PLLVDD TP44 [5] 1966_DBCLK VSENSE [2] C53 IOVDD JP1 [5] 1966_DLRCLK [6] MCLKO [6] XTALO [6] MCLKI/XTALI C18 2.2nF NP0 LRCLK VSENSE [2] 1966_DVDD VDRIVE [2] Enable AVDD See pages 5&6 for jumper s VSUPPLY [2] 25 VSUPPLY VSENSE [2] 23 VSENSE 24 VDRIVE TP25 22 39 ADAU1966AWBSTZ IOVDD IOVDD 20 29 41 DVDD DVDD DVDD DGND DGND DGND DGND 21 26 30 40 49 58 3 12 DAC16P DAC16N DAC15P DAC15N DAC14P DAC14N DAC13P DAC13N DAC12P DAC12N DAC11P DAC11N DAC10P DAC10N DAC9P DAC9N DAC8P DAC8N DAC7P DAC7N DAC6P DAC6N DAC5P DAC5N DAC4P DAC4N DAC3P DAC3N DAC2P DAC2N DAC1P DAC1N TS_REF CM C42 DAC10P DAC10N DAC11P DAC11N DAC12P DAC12N DAC13P DAC13N 74 75 76 77 78 79 4 5 0.10uF C68 63 62 59 60 1 2 10 11 8 9 0.10uF DAC9P DAC9N 72 73 C134 10uF DAC8P DAC8N 70 71 + C130 10uF C45 0.47uF C133 10uF + TS_REF [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [3] [3] [3] [3] TP63 DAC16P DAC16N DAC15P DAC15N DAC14P DAC14N DAC7P DAC7N 68 69 6 7 DAC6P DAC6N [3] [3] [3] [3] DAC5P DAC5N [3] [3] 66 67 C65 [3] [3] [3] [3] 64 65 + DAC1P DAC1N DAC2P DAC2N DAC4P [3] DAC4N [3] C75 TP27 C131 10uF + DAC3P DAC3N CM [2] C77 C128 10uF + 56 57 TP66 C37 C129 10uF + 54 55 52 53 50 51 AVDD JP3 DAC_BIAS1 DAC_BIAS2 DAC_BIAS3 DAC_BIAS4 AVDD1 AVDD2 AVDD3 AVDD4 AGND1 AGND2 AGND3 AGND4 48 61 80 13 Rev. 0 | Page 10 of 32 TP45 TP71 0.47uF C72 0.47uF C43 1966_AVDD 1966_AVDD [2] C76 0.47uF 11588-021 UG-564 Evaluation Board User Guide Figure 22. Schematic, Page 3—ADAU196xA DAC Output 1 to Output 8 DAC4N [2] DAC4P [2] DAC3N [2] DAC3P [2] DAC2N [2] DAC2P [2] DAC1N [2] TP85 TP84 TP83 TP82 TP81 TP80 TP79 C87 OPEN R98 2.7nF 475 R R97 OPEN R96 2.7nF C86 475 R R95 OPEN R94 2.7nF C85 475 R R93 OPEN R92 2.7nF C84 0 R0 0 0 R0 0 475 R R17 0 R17 1 DAC1P [2] R17 2 + + OPEN C90 C91 C88 OPEN C89 10 uF OPEN R16 5 + + R16 4 OPEN C92 OPEN C93 10 uF R16 3 10 uF + + C94 OPEN OPEN + + C95 10 uF R16 2 OPEN R99 OPEN 49 k9 OPEN 49 k9 R10 0 R10 1 OPEN 49 k9 R10 2 R10 3 OPEN R10 5 R10 4 49 k9 R10 6 TP91 TP90 TP97 TP93 TP99 TP98 TP10 1 TP10 0 OUT4N OUT4P [3] OUT3N OUT3P [3] OUT2N OUT2P [3] OUT1N OUT1P [3] DAC8N [2] DAC8P [2] DAC7N [2] DAC7P [2] DAC6N [2] DAC6P [2] DAC5N [2] DAC5P [2] TP61 TP62 TP64 TP67 TP69 TP72 TP74 TP76 C82 OPEN R68 2.7nF C61 475 R R70 OPEN R74 2.7nF C73 475 R R76 OPEN R80 2.7nF C79 475 R R82 OPEN R86 2.7nF 475 R R88 R17 4 R91 0 R0 0 0 R0 0 R17 3 0 R0 0 0 R0 0 R17 6 R17 5 0 R0 0 0 R0 0 R17 7 Rev. 0 | Page 11 of 32 C81 OPEN C83 10 uF C78 OPEN C80 + + + + C59 OPEN C62 10 uF R16 9 OPEN C69 OPEN C74 10 uF R16 8 OPEN + + 10 uF R16 7 OPEN + + OPEN R16 6 R69 OPEN R71 49 k9 R75 OPEN R77 OPEN 49 k9 R81 R83 OPEN R87 49 k9 49 k9 R89 TP68 TP65 TP73 TP70 TP77 TP75 TP89 TP87 OUT8N OUT8P [3] OUT7N OUT7P [3] OUT6N OUT6P [3] OUT5N OUT5P [3] [3] OUT8P [3] OUT7P [3] OUT6P [3] OUT5P [3] OUT4P [3] OUT3P [3] OUT2P [3] OUT1P RING TIP SLEE VE RING TIP SLEE VE RING TIP SLEE VE RING TIP SLEE VE J9 J3 J14 J10 11588-022 TP78 Evaluation Board User Guide UG-564 DAC12N [2] DAC12P [2] DAC11N [2] DAC11P [2] DAC10N [2] DAC10P [2] DAC9N [2] DAC9P [2] TP39 TP41 TP46 TP48 TP51 TP54 TP58 OPEN R40 C31 2.7nF 475R R44 OPEN R47 C38 2.7nF 475R R51 OPEN R54 C48 2.7nF 475R R57 OPEN R60 C54 2.7nF 475R R64 R118 TP59 R107 R117 R119 + + + + C46 OPEN C49 10uF R109 OPEN C51 OPEN C55 10uF C30 OPEN C32 10uF R112 OPEN C35 OPEN C39 10uF R110 OPEN + + + + OPEN R108 R41 OPEN 49k9 OPEN 49k9 R45 R48 OPEN R52 49k9 R55 OPEN 49k9 R58 R61 R65 TP37 TP24 TP42 TP40 TP49 TP47 TP55 TP52 OUT12N OUT12P [4] OUT11N OUT11P [4] OUT10N OUT10P [4] OUT9N OUT9P [4] DAC16N [2] DAC16P [2] DAC15N [2] DAC15P [2] DAC14N [2] DAC14P [2] DAC13N [2] DAC13P [2] TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 OPEN R30 C23 2.7nF 475R R31 OPEN R32 C24 2.7nF 475R R33 OPEN R34 C25 2.7nF 475R R35 OPEN R36 C26 2.7nF 475R R37 R159 R160 0R00 0R00 0R00 0R00 R158 R161 + + + + 0R00 + + 0R00 + + 0R00 Rev. 0 | Page 12 of 32 0R00 Figure 23. Schematic, Page 4—ADAU196xA DAC Output 9 to Output 12 OPEN C8 OPEN C9 10uF R116 OPEN C13 OPEN C14 10uF R115 OPEN C15 OPEN C16 10uF R114 OPEN C19 OPEN C22 10uF R113 R7 OPEN 49k9 OPEN 49k9 R8 R19 R22 R23 OPEN 49k9 OPEN R28 R26 49k9 R29 TP10 TP7 TP12 TP11 TP18 TP16 TP22 TP19 OUT16N OUT16P [4] OUT15N OUT15P [4] OUT14N OUT14P [4] OUT13N OUT13P [4] [4] OUT16P [4] OUT15P [4] OUT14P [4] OUT13P [4] OUT12P [4] OUT11P [4] OUT10P [4] OUT9P RING TIP SLEEVE RING TI P SLEEVE RING TI P SLEEVE RING TI P SLEEVE J18 J17 J16 J15 11588-023 UG-564 Evaluation Board User Guide [7] 8416_SDATA INTF_DSDATA1 [9] B C7 JP22 IOVDD 2 A 1 Y OE U18 4 SN74LVC1G125DRLR [7] INTF_DSDATA2 [7] INTF_DSDATA3 [7] INTF_DSDATA4 [7] INTF_DSDATA5 [7] INTF_DSDATA6 [7] INTF_DSDATA7 [7] INTF_DSDATA8 [9] 8416_LRCLK [7]INTF_DLRCLK [9] 8416_BCLK R141 DSDATA8 DSDATA1 C141 2.2pF 33R2 DSDATA2 DSDATA3 DSDATA4 DSDATA5 DSDATA6 DLRCLK DSDATA7 DBCLK JP10 A B JP12 A B JP13 A B JP14 A B JP15 A B JP16 A B JP17 A B JP18 A B JP19 A B JP20 A B Rev. 0 | Page 13 of 32 A Figure 24. Schematic, Page 5—BCLK, LRCLK, and SDATA Jumpers and Routing 68R1 68R1 68R1 68R1 68R1 68R1 68R1 68R1 33R2 33R2 R90 R85 R84 R79 R78 R73 R72 R67 R66 R62 4.7pF C70 4.7pF C66 4.7pF C64 4.7pF C63 4.7pF C60 4.7pF C58 4.7pF C57 4.7pF C56 2.2pF C52 2.2pF C50 33R2 33R2 R63 R59 1966_DSDATA1 [2] 1966_DSDATA2 [2] 1966_DSDATA3 [2] 1966_DSDATA4 [2] 1966_DSDATA5 [2] 1966_DSDATA6 [2] 1966_DSDATA7 [2] 1966_DSDATA8 [2] 1966_DLRCLK [2] 1966_DBCLK [2] 11588-024 [7] INTF_DBCLK Evaluation Board User Guide UG-564 IOVDD [2,7] J4 R46 10k0 USBI_SCL [2,7] USBI_SDA [2,7] USBI_COUT [2,7] USBI_CCLK [2,7] USBI_CLATCH_A C33 1 GND OE VDD Rev. 0 | Page 14 of 32 R129 49R9 OUTPUT R42 49R9 C28 10pF R38 49R9 C124 10pF R43 R132 49R9 OMCK_FEED [9] 8416_MCLKI [9] 0R00 Figure 25. Schematic, Page 6—MCLK Selection, USBi Interface, CLKOUT Feed, and Reset Generator R155 3k01 1 3 5 7 9 J5 1 3 5 7 MCLK Source 2 4 6 8 Y1 22pF C34 2 4 6 8 10 USBI_5V00 [7] D10 R39 R49 0R00 150R XTALO [2] R50 1M00 MCLKI/XTALI [2] USBI_CDATA [2,7] MBR0530T1G MR [6,8] MCLK sources 22pF 12.288MHz C29 TP38 MR line comes from USBi Board Reset J12 HEADER_10WAY_POL USBi Interface R111 3k01 IOVDD USBi or Aardvark 3 R157 10k0 2 U5 4 OSC_CPPFXC7-12.288MHZ_7MMX5MM_SMD JP8 L7 EI3_MCLKI [7] C27 IOVDD IOVDD U10 GND RESET MR ADM811R VCC Reset 1 4 TP20 C111 CLKOUT Feed MCLKO [2] 49R9 R53 2 3 A U4 1 R126 100k 2 OE Y 49R9 R24 S2 PU_RST [2,9] 1 3 4 2 SN74LVC1G125DRLR 4 J2 Power down [6,8] MR EI3_MCLKO [7] UG-564 Evaluation Board User Guide 11588-025 JP5 C137 C138 MCLK_SEL [7] EI3_MCLK [7,8] 2 A 1 R137 EI3_IOVDD R130 10k0 EI3_IOVDD [8] EI3_CCLK [8] EI3_CLATCH_C [8] EI3_CLATCH_B [8] EI3_CDATA [8] EI3_CLATCH_A 4 R139 10k0 Y U14 SN74LVC1G125DRLR OE EI3_DSDATA1 EI3_DSDATA2 EI3_DSDATA3 EI3_DSDATA4 EI3_DSDATA5 EI3_DSDATA6 EI3_DSDATA7 EI3_DSDATA8 24 VCCA VCCB 23 DIR VCCB 22 OE A1 21 B1 A2 20 B2 A3 19 U13 B3 A4 18 B4 A5 17 B5 A6 16 B6 A7 15 B7 A8 14 GND B8 13 GND GND MCLK_SEL [7] EI3_IOVDD R147 IOVDD 10k0 R134 EI3_IOVD D SN74LVCH8T245DBR_8BITLVLSHFT 1 24 VCCA VCCB 23 2 DIR VCCB 22 3 OE A1 21 4 B1 A2 20 5 A3 B2 19 6 U16 B3 A4 18 7 B4 A5 8 17 B5 A6 9 16 A7 B6 10 15 A8 B7 11 14 B8 GND 12 13 GND GND SN74LVCH8T245DBR_8BITLVLSHFT 1 2 3 4 5 6 7 8 9 10 11 12 C136 [8] [8] [8] [8] [8] [8] [8] [8] 1 2 3 4 5 6 7 8 R135 33R0 16 15 14 13 12 11 10 9 49R9 49R9 49R9 49R9 R151 R148 R152 EI3_SPI_EN TP96 USBI_CDATA[2,6] 4 Y OE U12 A USBI_5V00[6] [7] MCLK_SEL SN74LVC1G126DRLR 1 [7,8] EI3_MCLK [2,6] USBI_CLATCH_A 1k50 R146 R145 3k32 USBI_CLATCH_B USBI_CLATCH_C TP95 USBI_CCLK[2,6] R150 49R9 EI3_MCLKI [6] INTF_DSDATA1[5] INTF_DSDATA2[5] INTF_DSDATA3[5] INTF_DSDATA4[5] INTF_DSDATA5[5] INTF_DSDATA6[5] INTF_DSDATA7[5] INTF_DSDATA8[5] 2 C140 EI3_SCL EI3_SDA [8] EI3_COUT [8] [8] 49R9 EI3_IOVDD [8] EI3_DBCLK0 [8] EI3_DBCLK1 [8] EI3_DBCLK2 [8] EI3_DBCLK3 [8] EI3_DLRCLK0 [8] EI3_DLRCLK1 [8] EI3_DLRCLK2 [8] EI3_DLRCLK3 R136 1 2 3 4 5 6 7 8 33R0 R140 10k0 16 15 14 13 12 11 10 9 EI3_IOVDD R127 10k0 R128 5 3 2 DIR A2 A1 VCCA SCLA SDAA U15 GND EI3_IOVDD 1 2 3 4 8 VCCB 7 SCLB 6 SDAB 5 EN U11 B2 B1 6 7 IOVDD R144 PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8 C122 C135 C145 C139 VCCA IOVDD 24 IOVDD VCCA VCCB 23 IOVDD DIR VCCB 22 A1 OE 21 A2 B1 20 B2 A3 19 U17 B3 A4 18 B4 A5 17 B5 A6 16 A7 B6 15 A8 B7 14 GND B8 13 GND GND 10k0 IOVDD R143 C146 R142 10k0 R149 IOVDD USBI_COUT [2,6] EI3_MCLKO [6] 49R9 49R9 SN74LVCH8T245DBR_8BITLVLSHFT 1 2 3 4 5 6 7 8 9 10 11 12 SN74LVC2T45DCTR_2BITLVLSHFT C120 10k0 JP6 C123 1 GND 8 Rev. 0 | Page 15 of 32 4 Figure 26. Schematic, Page 7—Level Shift and Clock Direction Control VCCB C142 EI3_IOVDD USBI_SCL [2,6] USBI_SDA [2,6] INTF_DLRCLK [5] INTF_DBCLK [5] Evaluation Board User Guide UG-564 11588-026 Rev. 0 | Page 16 of 32 [6] MR Figure 27. Schematic, Page 8—SDP Interface Connectors Schottky D9 [7] [7] [7] [7] R131 EI3_CLATCH_C EI3_CLATCH_B EI3_DSDATA2 EI3_DSDATA4 R133 49R9 OPEN J6 EI3_DSDATA8 J8 97 96 95 24 25 26 97 96 95 24 25 26 RESET_OUT' 76 75 74 73 72 71 70 69 68 67 66 65 45 46 47 48 49 50 51 52 53 54 55 56 RESET_OUT' 81 SDA0' SCL0' 40 77 76 75 74 73 72 71 70 69 68 67 66 65 45 46 47 48 49 50 51 52 53 54 55 56 EI3 1B 61 60 61 60 EI3 1A 62 59 62 59 63 58 63 64 78 44 79 80 43 42 58 [7] EI3_SCL 82 39 41 38 83 37 [7] [7] 84 85 86 87 88 89 90 91 92 93 57 [7] EI3_SDA SPORT3_D1 SPORT2_D1 SPORT3_CLK SPORT3_D0 SPORT3_FS SPORT2_FS SPORT2_D0 SPORT2_CLK [7] 36 35 34 [7] [7] 33 32 [7] EI3_DSDATA6 31 [7] [7] 30 [7] [7] 29 [7] 28 64 57 77 44 79 78 SDA0' SCL0' 43 42 80 41 EI3_COUT EI3_CCLK EI3_CDATA 82 84 EI3_CLATCH_A 83 81 SPI0_SEL_A SPI0_MOSI SPI0_MISO SPI0_CLK 40 39 38 37 85 EI3_DBCLK0 87 86 EI3_DSDATA1 EI3_DLRCLK0 EI3_DLRCLK1 88 89 90 EI3_DSDATA3 91 36 SPI0_SEL_B SPI0_SEL_C SPORT1_D1 SPORT0_D1 SPORT1_CLK SPORT1_D0 SPORT1_FS SPORT0_FS SPORT0_D0 SPORT0_CLK EI3_DBCLK1 92 93 35 34 33 32 31 30 29 28 94 98 23 98 23 HIROSE_FX8-120S-SV(21)_SOCKET 99 22 99 22 HIROSE_FX8-120S-SV(21)_SOCKET 100 21 100 21 27 101 20 94 102 19 102 101 20 27 103 18 103 19 18 106 104 17 104 17 107 105 16 105 16 108 15 106 15 109 14 107 14 110 13 108 13 111 12 109 12 112 11 110 11 113 10 111 10 114 9 112 8 113 7 114 115 6 9 116 5 8 117 4 7 118 3 115 119 2 6 120 1 116 OPEN 5 [7] R156 117 EI3_MCLK [7] 4 119 118 120 DAU_MCLK 2 3 1 5V0DD EI3_DBCLK2 EI3_DSDATA5 EI3_DLRCLK2 EI3_DLRCLK3 EI3_DSDATA7 EI3_DBCLK3 EI3_IOVDD [7] [7] [7] [7] [7] [7] C132 47uF + 11588-027 5V0DD EI3_IOVDD UG-564 Evaluation Board User Guide Figure 28. Schematic, Page 9—S/PDIF Receiver Rev. 0 | Page 17 of 32 C112 J1 CTP-021A-S-YEL 1 R6 75R0 1.0nF IOVDD 10nF 10nF 22nF C5 C6 C3 PU_RST [2,6] 5 2 C2 3k01 4 R5 6 3 S1 DPDT Slide C10 10uF C12 L3 2 GND + FILT RXN RXP0 9 RST 7 20 C U RCBL NV/RERR AUDIO 96KHZ OMCK 22 C11 19 18 17 14 15 16 25 26 SDOUT 28 OLRCK 27 OSCLK 24 RMCK TX 21 VL DGND CS8416 U2 23 VD AGND 10 RXSEL1 11 RXSEL0 12 TXSEL1 13 TXSEL0 3 RXP1 2 RXP2 1 RXP3 8 5 4 L4 6 VA L1 74 HC04 D- T U3 - B U3 - C 4 2Y PH DET RATE Norm Default High 47k5 RS7 47k5 R125 10k0 R20 74 HC04 D- T 2A 3 6 3Y 3A 5 U1 1 TORX147L(FT) OUT EMPH Off Default On 47k5 RS3 OMCK_FEED[6] R3 392R Red Diffused U3 - F IOVDD 12 6Y 6A 13 R4 10k0 D4 R2 392R 8 ERRORS NVERR Default RERR 47k5 RS1 Green Diffused 3 DVDD Error 74 HC04 D- T 10k0 U3 - D U3 - E 4Y 4A 9 10 5Y 5A 11 D3 R1 392R D2 1 RS6 47k5 SFSEL0 0 00 = LJ 24bit 01 = I2S 24bit 10 = RJ 24bit 11 = Direct AES SFSEL [1:0] 47k5 RS5 RMCK Freq 256xFs Default 128xFs 8416_SDATA[5] 8416_LRCLK[5] 8416_BCLK[5] 8416_MCLKI[6] |-------- SERIAL PORT Format -------| SFSEL1 0 Default 1 47k5 RS2 Default 150R R11 150R R12 150R R10 150R R21 74 HC04 D- T 74 HC04 D- T SERIAL PORT Control SLAVE Default MASTER RS4 47k5 Yellow Diffused U3- A R9 C110 >88kHz IOVDD Valid Audio 74 HC04 D- T 2 1Y 1A 1 3V3DD IOVDD IOVDD 11588-028 3V3DD Evaluation Board User Guide UG-564 C4 Rev. 0 | Page 18 of 32 J13 1 3 2 Figure 29. Schematic, Page 10—Power Supply GND TP88 TP2 +12VDC MAX D1 C1 +12VDC L2 600 Ohm @ 100 MHz 5V0DD L5 C107 47uF + 600 Ohm @ 100 MHz 3V3DD C105 + C118 47uF C106 68nF R120 1k15 C116 IN C104 390pF 2 + 5 6 7 8 U8 FB BIAS BOOST SWITCH 4 3 2 1 C109 0.47uF R121 10k2 402R R123 243R R124 32k4 R122 1 D8 L6 C119 47uF TP8 2 BAT54T1G 1N5819HW-7-F D7 + C117 22uH 3v3 Linear Supply 5v0 Switching Supply ADP3050ARZ COMP SD GND IN 10uF C115 1 3 LM317MDT OUT ADJ U9 C108 MSS12778-223MLB D5 3V3DD R13 C113 47uF C114 47uF TP9 Green Diffused 475R D6 R14 R18 475R 0R00 R15 5V0DD 0R00 Green Diffused TP15 TP14 TP60 TP86 TP92 TP5 AVDD IOVDD TP1 TP3 TP17 C152 TP6 C154 C143 TP4 TP13 TP56 TP23 TP94 TP36 TP106 TP105 TP102 TP104 C121 Plane decoupling UG-564 Evaluation Board User Guide 11588-029 UG-564 11588-030 Evaluation Board User Guide Figure 30. Top Assembly Rev. 0 | Page 19 of 32 Evaluation Board User Guide 11588-031 UG-564 Figure 31. Top Layer Copper Rev. 0 | Page 20 of 32 UG-564 11588-032 Evaluation Board User Guide Figure 32. L2 Ground Rev. 0 | Page 21 of 32 Evaluation Board User Guide 11588-033 UG-564 Figure 33. L3 Power Rev. 0 | Page 22 of 32 UG-564 11588-034 Evaluation Board User Guide Figure 34. Bottom Copper Rev. 0 | Page 23 of 32 Evaluation Board User Guide 11588-035 UG-564 Figure 35. Bottom Assembly Rev. 0 | Page 24 of 32 Evaluation Board User Guide UG-564 BILL OF MATERIAL Table 2. Qty 1 Reference U6 1 J12 1 U5 2 J6, J8 1 U1 1 U2 10 JP1, JP3 to JP9, JP11, JP21 1 U8 1 J11 1 U9 11 JP2, JP10, JP12 to JP20 Description Multibit SigmaDelta DAC 10-way shroud, polarized header 12.288 MHz, fixed SMD oscillator, 3.3 V to 5 V dc 120-pin socket, 0.6 mm 15 Mbps fiber optic receiving module with shutter 192 kHz dgtl rcvr, 28-TSSOP 2-pin header, unshrouded, jumper ,0.10"; use Tyco 881545-2 shunt 200 kHz, 1A, buck regulator 28-way, unshrouded 3-term adj voltage regulator DPAK 3-pos SIP header 1 JP22 3-pos T-header 1 J5 27 4 3 1 4 2 3 1 8-way, unshrouded, header dual row C9 to C10, C14, C16, C22, Alum electrolytic C32, C39,C49, C55, C62, capacitor, FC 105°, C74, C80, C83, C89, C91, SMD_B, 10 µF C93, C95, C11, C125 to C131, C133 to C134 C107, C118 to C119, Alum electrolytic C132 capacitor, FC 105°, 47 µF, SMD_D Buffer 3-state, U4, U14, U18 single gate Crystal, 12.288 MHz, Y1 SMT, 18 pF Chip ferrite bead, L1, L3 to L4, L7 600 Ω @ 100 MHz Chip ferrite bead, L2, L5 600 Ω @ 100 MHz Chip resistor, 1%, R1 to R3 100 mW, thick film, 0603, 392R Chip resistor, 1%, R5 100 mW thick film, 0603, 75R0 Manufacturer Analog Devices 3M Part Number ADAU1962AWBSTZ or ADAU1966AWBSTZ N2510-6002RB Digi-Key Vendor Order # ADAU1962AWBSTZ or ADAU1966AWBSTZ MHC10K-ND Cardinal Components CPPFX C 7 L T-A7 BR12.288MHz TS Cardinal Components CPPFX C 7 L T-A7 BR12.288MHz TS Hirose Electric FX8-120S-SV(21) Digi-Key H1219-ND Toshiba TORX147L(FT) Digi-Key TORX147LFT-ND Cirrus Logic CS8416-CZZ Digi-Key 598-1124-5-ND Sullins Electronics Corp PBC02SAAN or cut down PBC36SAAN Digi-Key S1011E-02-ND Analog Devices ADP3050ARZ Digi-Key ADP3050ARZ-R7CT-ND 3M PBC14DAAN, or cut down PBC36DAAN LM317MDT-TR Digi-Key S2011E-14-ND Digi-Key 497-1574-1-ND Digi-Key S1011E-03-ND Digi-Key Digi-Key S1011E-03-ND plus single pin S2011E-04-ND or cut down S2011E-36-ND PCE3995CT-ND ST Microelectronics Sullins Vendor Analog Devices Sullins Electronics Corp Panasonic EC PBC03SAAN or cut down PBC36SAAN PBC03SAAN or cut down PBC36SAAN PBC04DAAN or cut down PBC36DAAN EEE-FC1C100R Panasonic EC EEE-FC1C470P Digi-Key PCE4000CT-ND Texas Instruments SN74LVC1G125DRLR Digi-Key 296-18012-1-ND Abracon Corp ABM3B-12.288MHZ-10-1-U-T Digi-Key 300-8198-1-ND TDK Corp MMZ1005S601C Digi-Key 445-2162-1-ND Steward HZ0805E601R-10 Digi-Key 240-2399-1-ND Rohm MCR03EZPFX3920 Digi-Key RHM392HCT-ND Panasonic EC ERJ-3EKF75R0V Digi-Key P75.0HCT-ND Sullins Rev. 0 | Page 25 of 32 Digi-Key UG-564 Qty 2 Reference R13, R18 7 RS1 to RS7 1 R126 14 1 R4, R9, R20, R46, R127, R130, R134, R137 to R140, R144, R149, R157 R121 5 R10 to R12, R21, R49 1 R120 2 R56, R146 1 R50 1 R124 1 R122 5 R59, R62 to R63, R66, R141 3 R6, R111, R155 2 R25, R145 1 R123 16 R31, R33, R35, R37, R44, R51, R57, R64, R70, R76, R82, R88, R91, R93, R95, R97 R125 1 16 R8, R22, R26, R29, R45, R52, R58, R65, R71, R77, R83, R89, R100, R102 R104, R106 Evaluation Board User Guide Description Chip resistor, 1%, 475R, 125 mW, thick film, 0603 Chip resistor, 1%, 47k5, 125 mW, thick film, 0603 Chip resistor, 100k, 1%, 63 mW, thick film, 0402 Chip resistor, 1%, 10k0, 63 mW, thick film, 0402 Chip resistor, 1%, 10k2, 63 mW, thick film, 0402 Chip resistor, 1%, 150 R, 63 mW, thick film, 0402 Chip resistor, 1%, 1k15, 63 mW, thick film, 0402 Chip resistor, 1%, 1k50, 63 mW, thick film, 0402 Chip resistor, 1%, 1M00, 63 mW, thick film, 0402 Chip resistor, 1%, 243R, 63 mW, thick film, 0402 Chip resistor, 1%, 32k4, 63 mW, thick film, 0402 Chip resistor, 1%, 33R2, 63 mW, thick film, 0402 Chip resistor, 1%, 3K01, 63 mW, thick film, 0402 Chip resistor, 1%, 3k32, 63 mW, thick film, 0402 Chip resistor, 1%, 402R, 63 mW, thick film, 0402 Chip resistor, 1%, 475R, 63 mW, thick film, 0402 Manufacturer Panasonic EC Part Number ERJ-3EKF4750V Vendor Digi-Key Vendor Order # P475HCT-ND Panasonic EC ERJ-3EKF4752V Digi-Key P47.5KHCT-ND Rohm MCR01MZPF1003 Digi-Key RHM100KLCT-ND Rohm MCR01MZPF1002 Digi-Key RHM10.0KLCT-ND Vishay/Dale CRCW040210K2FKED Digi-Key 541-10.2KLCT-ND Rohm MCR01MZPF1500 Digi-Key RHM150LCT-ND Panasonic EC ERJ-2RKF1151X Digi-Key P1.15KLCT-ND Panasonic EC ERJ-2RKF1501X Digi-Key P1.50KLCT-ND Rohm MCR01MZPF1004 Digi-Key RHM1.00MLCT-ND Vishay/Dale CRCW0402243RFKED Digi-Key 541-243LCT-ND Vishay/Dale CRCW040232K4FKED Digi-Key 541-32.4KLCT-ND Panasonic EC ERJ-2RKF33R2X Digi-Key P33.2LCT-ND Rohm MCR01MZPF3011 Digi-Key RHM3.01KLCT-ND Vishay/Dale CRCW04023K32FKED Digi-Key 541-3.32KLCT-ND Vishay/Dale CRCW0402402RFKED Digi-Key 541-402LCT-ND Stackpole RMCF0402FT475R Digi-Key RMCF0402FT475RCT-ND Chip resistor, 1%, 47k5, 63 mW, thick film, 0402 Chip resistor, 1%, 49k9, 63 mW, thick film, 0402 Rohm MCR01MZPF4752 Digi-Key RHM47.5KLCT-ND Vishay/Dale CRCW040249K9FKED Digi-Key 541-49.9KLCT-ND Rev. 0 | Page 26 of 32 Evaluation Board User Guide Qty 15 1 Reference R24, R38, R42, R53, R128 to R129, R131 to R132, R142 to R143, R147 to R148, R150 to R152 R27 8 R67, R72 to R73, R78 to R79, R84 to R85, R90 18 2 R39, R43, R107, R117 to R119, R158 to R161, R170 to R177 R14 to R15 1 S1 48 3 R7, R19, R23, R28, R30, R32, R34, R36, R40 to R41, R47, to R48, R54 to R55, R60 to R61, R68 to R69, R74 to R75, R80 to R81, R86 to R87, R92, R94, R96, R98 to R99, R101, R103, R105, R108 to R110, R112 to R116, R162 to R169 R133, R156 TP7, TP10 to TP12, TP16, TP18 to TP19, TP22, TP24, TP37, TP40, TP42, TP47, TP49, TP52, TP55, TP65, TP68, TP70, TP73, TP75, TP77, TP87, TP89 to TP91, TP93, TP97 to TP101 D3, D5 to D6 1 U11 3 U13, U16 to U17 1 U15 1 U3 1 J13 32 TP1 to TP6, TP8 to TP9, TP13 to TP15, TP17, TP20 to TP21, TP23, TP25, TP27, TP36, TP38, TP44 to TP45, TP56, TP60, TP71, TP86, TP88, TP92, TP94, TP102, TP104 to TP106 2 32 UG-564 Description Chip resistor, 1%, 49R9, 63 mW, thick film, 0402 Manufacturer Rohm Part Number MCR01MZPF49R9 Vendor Digi-Key Vendor Order # RHM49.9LCT-ND Chip resistor, 1%, 562R, 63 mW, thick film, 0402 Chip resistor, 1%, 68R1, 63 mW, thick film, 0402 Chip resistor, 5%, 0R00, 100 mW, thick film, 0402 Chip resistor, 5%, 0R00, 125 mW, thick film, 0805 DPDT slide switch vertical Open Vishay/Dale CRCW0402562RFKED Digi-Key 541-562LCT-ND Rohm MCR01MZPF68R1 Digi-Key RHM68.1LCT-ND Panasonic ECG ERJ-2GE0R00X Digi-Key P0.0JCT-ND Panasonic EC ERJ-6GEY0R00V Digi-Key P0.0ACT-ND E-Switch EG2207 Digi-Key EG1940-ND Open Open Open Open Open Green diffused, 10 millicandela, 565 nm 1206 IC 2-bit, dual bus, TXRX 8-SSOP IC 8-bit, dual bus, TXRX 24-SSOP IC I2C bus, repeater 8-TSSOP IC inverter, hex TTL/LSTTL 14 SOIC Mini power jack, 0.08" R/A TH Mini test point, white .1" OD Lumex Opto SML-LX1206GW-TR Digi-Key 67-1002-1-ND Texas Instruments SN74LVC2T45DCTR DigiKey 296-16845-1-ND Texas Instruments SN74LVCH8T245DBR DigiKey 296-21067-1-ND NXP Semiconductor NXP Semiconductor Switchcraft, Inc. PCA9517DP-T DigiKey 568-1829-2-ND 74HC04D-T DigiKey 568-1384-1-ND RAPC722X Digi-Key SC1313-ND 5002 Digi-Key 5002K-ND Keystone Electronics Rev. 0 | Page 27 of 32 UG-564 Qty 2 Reference C113 to C114 44 C1, C4, C7, C11 to C12, C27, C33, C36 to C37, C40 to C42, C44, C47, C53, C65, C67 to C68, C71, C75, C77, C105, C108, C110 to C112, C116 to C117, C120 to C123, C135 to C140, C142 to C143, C145 to C146, C152, C154 C43, C45, C72, C76, C109 5 2 C5 to C6 1 C20 1 C2 2 C28, C124 3 C50, C52, C141 2 C29, C34 2 C17, C104 8 C56 to C58, C60, C63 to C64, C66, C70 1 C18 1 C3 16 1 C23 to C-26, C31, C38, C48, C54, C61, C73, C79, C82, C84 to C87 C106 1 C21 16 C8, C13, C15, C19, C30, C35, C46, C51, C59, C69, C78, C81, C88, C90, C92, C94 JP23 1 Evaluation Board User Guide Description Multilayer ceramic, 47 µF, 10 V, X5R, 1206 Multilayer ceramic, 0.10 µF, 16 V, X7R, 0402 Manufacturer Kemet Part Number C1206C476M8PACTU Vendor Digi-Key Vendor Order # 399-5508-6-ND Murata ENA GRM155R71C104KA88D Digi-Key 490-3261-1-ND Multilayer ceramic, 47 µF, 16 V, X7R, 0603 Multilayer ceramic, 10 nF, 25 V, NP0, 0603 Multilayer ceramic, 5.6 nF, 25 V, NP0, 0603 Multilayer ceramic, 22 nF, 25 V, NP0, 0805 Multilayer ceramic, 10 pF, 50 V, NP0, 0402 Multilayer ceramic, 2.2 pF, 50 V, NP0, 0402 Multilayer ceramic, 22 pF, 50 V, NP0, 0402 Multilayer ceramic, 390 pF, 50 V, NP0, 0402 Multilayer ceramic, 4.7 pF, 50 V, NP0, 0402 Multilayer ceramic, 2.2 nF, 50 V, NP0, 0603 Multilayer ceramic, 1.0 nF, 50 V, NP0, 0603 Multilayer ceramic, 2.7 nF, 50 V, NP0, 0603 Multilayer ceramic, 68 nF, 50 V, NP0, 1206 Multilayer ceramic, 39 nF, 50 V, X7R, 0805 10 µF, not fitted Taiyo Yuden EMK107B7474KA-T Digi-Key 587-1250-1-ND TDK Corp C1608C0G1E103J Digi-Key 445-2664-1-ND TDK Corp C1608C0G1E562J Digi-Key 445-2666-1-ND Murata ENA GRM21B5C1H223JA01L Digi-Key 490-1644-1-ND Kemet C0402C100J5GACTU Digi-Key 399-1011-1-ND Johanson Technology 500R07S2R2BV4T Digi-Key 712-1279-1-ND Murata ENC GRM1555C1H220JZ01D Digi-Key 490-1283-1-ND Murata ENA GRM1555C1H391JA01D Digi-Key 490-1296-1-ND Johanson Technology 500R07S4R7BV4T Digi-Key 12-1166-1-ND Murata Electronics GRM1885C1H222JA01D Digi-Key 490-1459-1-ND Panasonic EC ECJ-1VC1H102J Digi-Key PCC2151CT-ND Murata ENA GRM1885C1H272JA01D Mouser 81-GRM185C1H272JA01D Murata GCM31C5C1H683JA16L Digi-Key 490-5323-1-ND Panasonic EC ECJ-2VB1H393K Digi-Key PCC1835CT-ND Panasonic EC EEE-FC1C100R Digi-Key PCE3995CT-ND Sullins Electronics Corp PBC02SAAN or cut down PBC36SAAN Digi-Key S1011E-02-ND 2 jumper, not fitted Rev. 0 | Page 28 of 32 Evaluation Board User Guide Qty 1 1 Reference Q1 J1 1 D4 2 R135 to R136 2 J2, J4 1 L6 1 U12 1 D8 2 D9 to D10 1 D7 8 J3, J9 to J10, J14 to J18 1 D1 1 S2 1 D2 1 U10 Description PNP transistor RCA jack, PCB TH mount, R/A yellow Red diffused, 6.0 millicandela, 635 nm 1206 Resistor network, isolated 8 res, 33R0 SMA receptacle, straight PCB mount SMT power inductor, 22 µH Sngl bus, buff gate, 3ST SOP-5 Schottky 30 V, 0.2 A, SOD123 diode Schottky 30 V, 0.5 A, SOD123 diode Schottky 40 V, 1 A, SOD123 diode Sterero mini jack SMT TVS Zener 15 V, 600 W SMB Tact switch, 6 mm, gull wing, SPST-NO Yellow diffused, 4.0 millicandela, 585 nm 1206 Microprocessor voltage supervisor, logic low RESET output UG-564 Manufacturer Zetex, Inc. Connect-Tech Products Corp. Lumex Opto Part Number ZX5T953GTA CTP-021A-S-YEL Vendor Digi-Key Connect-Tech Vendor Order # ZX5T953GCT-ND CTP-021A-S-YEL SML-LX1206IW-TR Digi-Key 67-1003-1-ND CTS Corp. 741X163330JP Digi-Key 741X163330JPCT-ND Amp-RF Division 901-144-8RFX Digi-Key ARFX1231-ND Coilcraft MSS12778-223MLB Coilcraft MSS12778-223MLB Texas Instruments SN74LVC1G126DRLR DigiKey 296-18013-1-ND On Semiconductor BAT54T1G Digi-Key BAT54T1GOSCT-ND On Semiconductor MBR0530T1G Digi-Key MBR0530T1GOSCT-ND Diodes, Inc 1N5819HW-7-F Digi-Key 1N5819HW-FDICT-ND CUI, Inc. SJ-3523-SMT Digi-Key CP-3523SJCT-ND ON Semiconductor 1SMB15AT3G Digi-Key 1SMB15AT3GOSCT-ND Tyco/Alcoswitch FSM6JSMA Digi-Key 450-1133-ND CML Innovative Tech CMD15-21VYD/TR8 Digi-Key L62307CT-ND Analog Devices ADM811RARTZ-REEL7 Analog Devices ADM811RARTZ-REEL7 Rev. 0 | Page 29 of 32 UG-564 Evaluation Board User Guide NOTES Rev. 0 | Page 30 of 32 Evaluation Board User Guide UG-564 NOTES Rev. 0 | Page 31 of 32 UG-564 Evaluation Board User Guide NOTES I2C refers to a communications protocol developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. 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Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11588-0-7/13(0) Rev. 0 | Page 32 of 32