TS81001 High Efficiency Receiver Controller for Wireless Power Systems TRIUNE PRODUCTS Features Description • • Supports Qi®, PMA and proprietary charging applications Dual-mode Qi + PMA functionality using a single LC resonant circuit • Wireless power systems up to 40W+ • Compatible with variable voltage, variable frequency and variable duty cycle transmitters • Supports indirect (fixed voltage) and single/multi-cell battery charging applications (>2.0V) • Integrated controller and FLASH for communications and control • High precision data converter Low external component count The TS81001 is a power receiver communications and control unit for wireless charging applications. The TS81001 can support systems up to 40W+, and supports Qi® compliant, PMA compliant and proprietary applications. Applications • • • • • • • • • • • • • Qi® , PMA and non-standard wireless chargers for: Cell Phones and Smartphones GPS Devices Digital Cameras Tablets and eReaders Portable Lighting Toys Medical devices Industrial devices Description The TS81001 performs the necessary coding of packets to send commands to the transmitter to adjust the power level accordingly. Specification RISC-based controller core with flash and SRAM memory 12-bit A/D converter Two 16-bit timers 8-bit timer Auto-wakeup and watchdog timers 8 configurable analog general purpose IOs Charging LED output I2C interface 20 pin 3x3 QFN Typical Application Circuit TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 1 of 16 Semtech Pinout (Top View) TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 2 of 16 Semtech Pin Description Pin # Pin Name Pin Function Description 1 NRST Reset Reset input 2 SDA I2C Data I2C data 3 SCL I2C Clock I2C clock 4 VSS Power GND Power GND 5 VDD Input power Input power supply 6 EN_LOAD Load enable Output FET enable (some systems) 7 GPIO3 GPIO GPIO 3 8 LED LED output Charging LED control 9 GPIO6 GPIO GPIO 6 10 GPIO7 GPIO GPIO 7 11 GPIO8 GPIO GPIO 8 12 AMUX Analog GPIO AMUX input from TS51111 13 VREF Analog GPIO VREF input from TS51111 14 VACDET GPIO VACDET input from TS51111 15 GPIO5 Open-Drain GPIO True Open-Drain GPIO 5 16 GPIO4 Open-Drain GPIO True Open-Drain GPIO 4 17 EN_MOD GPIO EN_MOD output to TS51111 18 GPIO1 GPIO GPIO 1 19 GPIO2 GPIO GPIO 2 20 DEBUG Debug Debug interface TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 3 of 16 Semtech Functional Block Diagram TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 4 of 16 Semtech Absolute Maximum Ratings Over operating free–air temperature range unless otherwise noted(1, 2, 3) MIN MAX UNIT -0.3 4.0 V GPIO1, GPIO2, GPIO3, VACDET, VREF, SCL, SDA, EN_MOD, DEBUG, GPIO6, AMUX, EN_LOAD, GPIO7, LED, GPIO8, NRST VSS - 0.3 4.0 V GPIO4, GPIO5 VSS - 0.3 VDD + 4.0 V Operating Junction Temperature Range, TJ -40 125 °C Storage Temperature Range, TSTG -65 150 °C Electrostatic Discharge – Human Body Model ±2k V Lead Temperature (soldering, 10 seconds) 260 °C VDD, VSS Notes: (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD Input Operating Voltage 1.85 3.6 V FMCU Operating Frequency 2 16 MHz VDD Decoupling capacitor value 1 uF LDO Decoupling capacitor value 1 uF TA Operating Free Air Temperature -40 85 °C TJ Operating Junction Temperature -40 105 °C Communication Interfaces I2C or UART communication can only take place in the following cases: The Wireless Power Receiver is placed on the Wireless Power Transmitter and power transfer is taking place, or External power is applied, either through the system power supply or on the TS51111 USB pin In both cases, an internal voltage regulator inside the TS51111 provides 3.3V on the VCORE pin for the TS81001 to use. The Applications Processor can interrogate the TS81001 using the I2C or UART interfaces. The TS81001 acknowledges its I2C Slave Address only if it is powered. No ACK from the TS81001 after its slave address means that power transfer does not take place and power is not applied to the TS51111 USB pin. TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 5 of 16 Semtech I2C I2C Signal Pins • ALERT pin (GPIO pin) - optional: Driven high when an event is active in the internal STATUS register Driven low when all the internal events are cleared Note: The ALERT pin is provided to help with I2C communication, i.e. to signal events to the EC so the EC can interrogate the TS8100x via I2C. The use of the ALERT pin is not mandatory in the application. • SCL_TXD pin: Clock pin for the I2C interface. True open-drain. Needs external pull-ups. • SDA_RXD pin: Data pin for the I2C interface. True open-drain. Needs external pull-ups. I2C Protocol The TS81001 Wireless Power Receiver acts as an I2C slave peripheral to allow communication with an application microcontroller. The slave address (7 bit) is 0x49. The Embedded Controller is an I2C master and initiates every data transfer. The TS81001 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive parameters and return values using the I2C bus. Four transfer types are possible: • Write Register • Read Register • Run API Function • Read API Function Return Buffer Write Register Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Register n address (8 bits) Slave ACK Address of the first register. M[S Register n Data (8 bits) Slave ACK Write the first register. M[S Register n+1 Data (8 bits) Slave ACK Optionally write the following registers. ... M[S Register n+k Data (8 bits) STOP TS81001 Final Datasheet June 2, 2015 Slave ACK Stop of the I2C transfer. Rev 1.2 www.semtech.com 6 of 16 Semtech Read Register Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S Register n address (8 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0x92 as 8-bit). Slave ACK Address of the first register. START Repeated Start. M[S Slave Address (7 bits) S[M S[M 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). Register n Data (8 bits) Master ACK Read the first register. Register n+1 Data (8 bits) Master ACK Optionally read the following registers. Slave ACK The master should send a nACK after the last data byte was received. ... S[M Register n+k Data (8 bits) STOP Stop of the I2C transfer. Run API Function Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S API number (8 bits) M[S 0 (1 bit) API input buffer length m (8 bits) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Slave ACK API number. Slave ACK API input buffer length. Equal to 0 if no input buffer data is required by the API. M[S Input buffer data[0] (8 bits) Slave ACK First byte of the input buffer (optional). M[S Input buffer data[1] (8 bits) Slave ACK Second byte of the input buffer (optional). Slave ACK Last byte of the input buffer (optional). ... M[S Input buffer data[m-1] (8 bits) STOP Stop of the I2C transfer and execute the API function Read API Function Return Buffer Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S Register n address (8 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Slave ACK API number. START Repeated Start. M[S Slave Address (7 bits) S[M 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). API number (8 bits) Master ACK API number for the following return buffer. S[M API return buffer length n (8 bits) Master ACK API return buffer length. S[M Output buffer data[0] (8 bits) Master ACK Read the first byte in the output buffer. S[M Output buffer data[1] (8 bits) Master ACK Optionally read the following bytes. Master nACK The master should send a nACK after the last data byte was received. ... S[M Output buffer data[n-1] (8 bits) STOP TS81001 Final Datasheet June 2, 2015 Stop of the I2C transfer. Rev 1.2 www.semtech.com 7 of 16 Semtech Internal Registers Address Name Type Description 0x00 BOOTFW_REV_L R/W Bootloader Firmware Revision Low Register 0x01 BOOTFW_REV_H R/W Bootloader Firmware Revision High Register 0x02 FW_REV_L R/W Firmware Revision Low Register 0x03 FW_REV_H R/W Firmware Revision High Register 0x04 MODE_L R/W Operating Mode Low Register 0x05 MODE_H R/W Operating Mode High Register 0x06 RESET_L R/W Reset Low Register 0x07 RESET_H R/W Reset High Register 0x08 STATUS R Main Status Register 0x09 STATUS0 R Status0 Register 0x0A STATUS1 R Status1 Register 0x0B STATUS2 R Status2 Register 0x0C STATUS3 R Status3 Register 0x0D-0x7F RESERVED. Will be defined later. Bootloader Firmware Revision Low Register (BOOTFW_REV_L) Address: Reset value: 0x00 Minor version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_L[7:0] r r r r Bits 7:0 REV_L[7:0]: Bootloader Firmware Revision Low These bits contain the minor version number of the bootloader firmware. Bootloader Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x01 Major version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_H[7:0] r r r r Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the bootloader firmware. TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 8 of 16 Semtech Firmware Revision Low Register (FW_REV_L) Address: Reset value: 0x02 Minor version number of the user firmware 7 6 5 4 r r r r 3 2 1 0 r r r r REV_L[7:0] Bits 7:0 REV_L[7:0]: Firmware Revision Low These bits contain the minor version number of the user firmware. Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x03 Major version number of the user firmware 7 6 5 4 r r r r 3 2 1 0 r r r r REV_H[7:0] Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the user firmware. Operating Mode Low Register (MODE_L) Address: Reset value: 0x04 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 1 0 BOOTLDR Res r Bits 7:1 Reserved Bit 0 BOOTLDR: Bootloader mode 0: The user firmware is running 1: The controller is in bootloader mode Operating Mode High Register (MODE_H) Address: Reset value: 0x05 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 1 0 3 2 1 0 w w w Res Bits 7:0 Reserved Reset Low Register (RESET_L) Address: Reset value: 0x06 0x00 7 6 5 4 w w w w RESET_KEY_L[7:0] Bits 7:0 TS81001 Final Datasheet June 2, 2015 Rev 1.2 w RESET_KEY_L[7:0]: Reset Key 0x55: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. www.semtech.com 9 of 16 Semtech Reset High Register (RESET_H) Address: Reset value: 0x07 0x00 7 6 5 4 3 2 1 0 w w w RESET_KEY_H[7:0] w w w w w Bits 7:0 RESET_KEY_H[7:0]: Reset Key 0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. Main Status Register (STATUS) Address: Reset value: 0x08 0xC0 7 6 5 CTS CTS_API rw rw Bit 7 TS81001 Final Datasheet June 2, 2015 Rev 1.2 4 Res 3 2 1 0 STATUS3 STATUS2 STATUS1 STATUS0 rw rw rw rw CTS: Clear To Send This bit indicates if a new command can be issued to the controller. 0: The controller is busy processing a previous command. New commands should not be sent to the controller. 1: The controller can accept a new command over the communication interface. Bit 6 CTS_API: Clear to Send for API This bit indicates if a new API call can be issued to the controller. 0: The controller is busy processing a previous API call. New API calls should not be sent to the controller. 1: The controller can accept a new API call over the communication interface. Bits 5:4 Reserved Bit 3 STATUS3: STATUS3 Event Flag 0: No event is signaled in the STATUS3 register 1: An event is signaled in the STATUS3 register Bit 2 STATUS2: STATUS2 Event Flag 0: No event is signaled in the STATUS2 register 1: An event is signaled in the STATUS2 register Bit 1 STATUS1: STATUS1 Event Flag 0: No event is signaled in the STATUS1 register 1: An event is signaled in the STATUS1 register Bit 0 STATUS0: STATUS0 Event Flag 0: No event is signaled in the STATUS0 register 1: An event is signaled in the STATUS0 register www.semtech.com 10 of 16 Semtech API Functions API Number API Name Description 0x80 BOOTLOADER_UNLOCK_FLASH Allow changes to the FLASH memory 0x81 BOOTLOADER_WRITE_BLOCK Write a page into the FLASH memory 0x82 BOOTLOADER_CRC_CHECK Check the CRC of the user firmware 0x83-0xFE RESERVED. Will be defined later. 0xFF API_ERROR Value returned in the API field when a Read API Function Return Buffer command is issued and the API function called previously has generated an error. Bootloader Unlock Flash (BOOTLOADER_UNLOCK_FLASH) API number: Input buffer size: Output buffer size: 0x80 TBD 1 Buffer Parameter Input buffer TBD Return data buffer ERROR_CODE Length (bytes) Description 1 Bootloader Write Block (BOOTLOADER_WRITE_BLOCK) API number: Input buffer size: Output buffer size: 0x81 66 1 Buffer Input buffer Return data buffer Parameter Length (bytes) Block Number 2 Block Data 64 ERROR_CODE 1 Description Block index. The first block has an index of 0. Data to be written to the FLASH page. Bootloader CRC Check (BOOTLOADER_CRC_CHECK) API number: Input buffer size: Output buffer size: 0x82 0 1 Buffer Parameter Length (bytes) Return data buffer ERROR_CODE 1 Description API Error Codes Error Code Error Code Name Description 0x00 ERROR_GENERIC Generic error. 0x01 0x02 0x03 0x04 ERROR_OK ERROR_INVALID_CRC ERROR_FLASH_UNLOCK_FAILED ERROR_API_NOT_IMPLEMENTED 0x05 ERROR_API_DATA_OVERFLOW 0x06 0x07-0xFF ERROR_API_INVALID_PARAMETERS RESERVED. Will be defined later. Operation succeeded. This is not indicating an error. CRC error. FLASH unlocking has failed. The API number is not implemented. The API input buffer has been filled with more data than its length. At least one of the API parameters is invalid. TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 11 of 16 Semtech Application Schematic C2 VAC1 C7 100pF 50V 47nF 50V C9 68nF 50V C11 C6 22nF 50V 34 35 C10 22nF 50V 15 16 20 C12 100nF 50V 68nF 50V J2 GND 22 31 2 3 EN_MOD 1 VACDET 19 AMUX 30 25 VCORE SCL SDA 27 26 BST1 USB VAC1 VAC1 VAC1 PDC PDC PDC MOD1 MOD2 OVP VAC2 VAC2 VAC2 PACKS PACKP_K PACKP BST2 USB 7 13 14 PDC 21 EN_MOD PACKN VACDET PAD PGND PGND PGND PGND THERM AMUX VCORE VREF NC SCL SDA C3 10uF 25V R1 100 C4 10uF 25V C5 10uF 25V 4 5 6 PACKP C13 10uF 6.3V UART TXD RXD AGND 32 37 9 10 17 18 24 29 28 R2 GND PACKS 0.020 C14 10uF 6.3V GND D1 NP GND 1 2 J1 D2 5.6V GND VCORE GND AGND 33 C16 1uF 6.3V GND VCORE TP1 C17 100nF 10V AGND 10K (NP) D3 BAT54CW (NP) Out AGND VREF C15 10nF 10V + - GND TS51111_QFN36 R3 D4 5.1V (NP) RESET TP2 DEBUG TP3 SCL TP4 SDA TP5 TP6 VCORE GND C19 1uF 6.3V 6 5 4 U2 VDD LDO VACDET EN_MOD SCL SDA VREF AMUX VSS AGND GPIO4 GPIO5 2 3 7 RESET DEBUG 1 15 GPIO1 GPIO2 GPIO3 NRST DEBUG GPIO6 GPIO7 EN_LOAD LED 10 14 12 13 11 17 9 8 16 19 18 20 AGND VACDET EN_MOD SCL SDA VREF LEDR AMUX R4 C18 10K 2nF 10V LEDG LEDR AGND LEDG TS81000-QFN PDC TP7 AMUX TP8 USB TP9 VAC1 TP10 1 VAC2 36 D5 2 VAC1 U1 3 1 2 VAC2 8 11 12 4 COIL AC AC C8 1.8nF 50V 23 C1 100nF 50V R5 150 GND Figure 1: TS81001 Application Schematic TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 12 of 16 Semtech Package Dimensions TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 13 of 16 Semtech QFN Package (Top marking) Legend: Line 1 Marking: L151 Internal part code Line 2 Marking: SS Assembly site identifier LL Lot trace code D Assembly year WW Assembly week Y Additional marking o Pin 1 Identifier Line 3 Marking: TS81001 Final Datasheet June 2, 2015 Rev 1.2 www.semtech.com 14 of 16 Semtech Ordering Information Part Number Description TS81001-QFNR Bootloader programmed device RoHS and Reach Compliance Triune Systems is fully committed to environmental quality. All Triune Systems materials and suppliers are fully compliant with RoHS (European Union Directive 2011/65/EU), REACH SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level 3 materials declarations, and their subsequent amendments. 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