TS81000 High Efficiency Receiver Controller for Wireless Power Systems TRIUNE PRODUCTS Features Description • • The TS81000 is a power receiver communications and control unit for wireless charging applications. The TS81000 can support systems up to 40W+, and supports Qi® compliant, PMA compliant and proprietary applications. Supports Qi®, PMA and proprietary charging applications Dual-mode Qi + PMA functionality using a single LC resonant circuit • Wireless power systems up to 40W+ • Compatible with variable voltage, variable frequency and variable duty cycle transmitters • Supports indirect (fixed voltage) and multi-cell battery charging applications (>3.15V) • Integrated controller and FLASH for communications and control • High precision data converter Low external component count Applications • Qi® , PMA and non-standard wireless chargers for: Cell Phones and Smartphones GPS Devices Digital Cameras Tablets and eReaders Portable Lighting Toys Medical devices Industrial devices The TS81000 performs the necessary coding of packets to send commands to the transmitter to adjust the power level accordingly. Specification • • • • • • • • • RISC-based controller core with flash and SRAM memory 10-bit A/D converter Two 16-bit timers, advanced control and general purpose 8-bit timer Auto-wakeup and watchdog timers 8 configurable analog general purpose IOs Charging LED output I2C interface 20 pin 3x3 QFN Typical Application Circuit TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 1 of 16 Semtech Pinout (Top View) TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 2 of 16 Semtech Pin Description Pin # Pin Name Pin Function Description 1 NRST Reset Reset input 2 GPIO1 GPIO GPIO 1 3 GPIO2 GPIO GPIO 2 4 VSS Power GND Power GND 5 VCAP Filter Filter capacitor 6 VDD Input power Input power supply 7 GPIO3 GPIO GPIO 3 8 GPIO5 Open-Drain GPIO True Open-Drain GPIO 5 9 GPIO4 Open-Drain GPIO True Open-Drain GPIO 4 10 VACDET Analog GPIO VACDET input from TS51111 11 VREF Analog GPIO VREF input from TS51111 12 SCL I2C Serial Clock I2C Serial Clock 13 SDA I2C Serial Data I2C Serial Data 14 EN_MOD GPIO EN_MOD output to TS51111 15 DEBUG Debug Debug interface 16 GPIO6 GPIO GPIO 6 17 AMUX Analog GPIO AMUX input from TS51111 18 EN_LOAD Enable Load Enable an optional load switch 19 GPIO7 GPIO GPIO 7 20 LED Charging LED Charging LED output TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 3 of 16 Semtech TS8100 Version UNCTIONAL BLOCK DIAGRAM Functional Block Diagram MCU Programming TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 4 of 16 Semtech Absolute Maximum Ratings Over operating free–air temperature range unless otherwise noted(1, 2, 3) MIN MAX UNIT -0.3 6.5 V GPIO1, GPIO2, GPIO3, GPIO5, GPIO4, VAC_DET, VREF, SCL, SDA, EN_MOD, DEBUG, GPIO6, AMUX, EN_LOAD, GPIO7, LED VSS - 0.3 6.5 V NRST, VCAP VSS - 0.3 VDD + 0.3 V Operating Junction Temperature Range, TJ -40 125 °C Storage Temperature Range, TSTG -65 150 °C Electrostatic Discharge – Human Body Model ±2k V Lead Temperature (soldering, 10 seconds) 260 °C VDD, VSS Notes: (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD Input Operating Voltage 2.95 5.5 V FMCU Operating Frequency 0 16 MHz VDD Decoupling capacitor value 1 uF LDO Decoupling capacitor value 1 uF TA Operating Free Air Temperature -40 85 °C TJ Operating Junction Temperature -40 105 °C Communication Interfaces I2C or UART communication can only take place in the following cases: The Wireless Power Receiver is placed on the Wireless Power Transmitter and power transfer is taking place, or External power is applied, either through the system power supply or on the TS51111 USB pin In both cases, an internal voltage regulator inside the TS51111 provides 3.3V on the VCORE pin for the TS81000 to use. The Applications Processor can interrogate the TS81000 using the I2C or UART interfaces. The TS81000 acknowledges its I2C Slave Address only if it is powered. No ACK from the TS81000 after its slave address means that power transfer does not take place and power is not applied to the TS51111 USB pin. TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 5 of 16 Semtech I2C I2C Signal Pins • ALERT pin (GPIO pin) - optional: Driven high when an event is active in the internal STATUS register Driven low when all the internal events are cleared Note: The ALERT pin is provided to help with I2C communication, i.e. to signal events to the EC so the EC can interrogate the TS8100x via I2C. The use of the ALERT pin is not mandatory in the application. • SCL_TXD pin: Clock pin for the I2C interface. True open-drain. Needs external pull-ups. • SDA_RXD pin: Data pin for the I2C interface. True open-drain. Needs external pull-ups. I2C Protocol The TS81000 Wireless Power Receiver acts as an I2C slave peripheral to allow communication with an application microcontroller. The slave address (7 bit) is 0x49. The Embedded Controller is an I2C master and initiates every data transfer. The TS81000 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive parameters and return values using the I2C bus. Four transfer types are possible: • Write Register • Read Register • Run API Function • Read API Function Return Buffer Write Register Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Register n address (8 bits) Slave ACK Address of the first register. M[S Register n Data (8 bits) Slave ACK Write the first register. M[S Register n+1 Data (8 bits) Slave ACK Optionally write the following registers. ... M[S Register n+k Data (8 bits) STOP TS81000 Final Datasheet June 2, 2015 Slave ACK Stop of the I2C transfer. Rev 1.3 www.semtech.com 6 of 16 Semtech Read Register Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S Register n address (8 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0x92 as 8-bit). Slave ACK Address of the first register. START Repeated Start. M[S Slave Address (7 bits) S[M S[M 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). Register n Data (8 bits) Master ACK Read the first register. Register n+1 Data (8 bits) Master ACK Optionally read the following registers. Slave ACK The master should send a nACK after the last data byte was received. ... S[M Register n+k Data (8 bits) STOP Stop of the I2C transfer. Run API Function Operations Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S API number (8 bits) M[S 0 (1 bit) API input buffer length m (8 bits) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Slave ACK API number. Slave ACK API input buffer length. Equal to 0 if no input buffer data is required by the API. M[S Input buffer data[0] (8 bits) Slave ACK First byte of the input buffer (optional). M[S Input buffer data[1] (8 bits) Slave ACK Second byte of the input buffer (optional). Slave ACK Last byte of the input buffer (optional). ... M[S Input buffer data[m-1] (8 bits) STOP Stop of the I2C transfer and execute the API function Read API Function Return Buffer Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S Register n address (8 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Slave ACK API number. START Repeated Start. M[S Slave Address (7 bits) S[M 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). API number (8 bits) Master ACK API number for the following return buffer. S[M API return buffer length n (8 bits) Master ACK API return buffer length. S[M Output buffer data[0] (8 bits) Master ACK Read the first byte in the output buffer. S[M Output buffer data[1] (8 bits) Master ACK Optionally read the following bytes. Master nACK The master should send a nACK after the last data byte was received. ... S[M Output buffer data[n-1] (8 bits) STOP TS81000 Final Datasheet June 2, 2015 Stop of the I2C transfer. Rev 1.3 www.semtech.com 7 of 16 Semtech Internal Registers Address Name Type Description 0x00 BOOTFW_REV_L R/W Bootloader Firmware Revision Low Register 0x01 BOOTFW_REV_H R/W Bootloader Firmware Revision High Register 0x02 FW_REV_L R/W Firmware Revision Low Register 0x03 FW_REV_H R/W Firmware Revision High Register 0x04 MODE_L R/W Operating Mode Low Register 0x05 MODE_H R/W Operating Mode High Register 0x06 RESET_L R/W Reset Low Register 0x07 RESET_H R/W Reset High Register 0x08 STATUS R Main Status Register 0x09 STATUS0 R Status0 Register 0x0A STATUS1 R Status1 Register 0x0B STATUS2 R Status2 Register 0x0C STATUS3 R Status3 Register 0x0D-0x7F RESERVED. Will be defined later. Bootloader Firmware Revision Low Register (BOOTFW_REV_L) Address: Reset value: 0x00 Minor version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_L[7:0] r r r r Bits 7:0 REV_L[7:0]: Bootloader Firmware Revision Low These bits contain the minor version number of the bootloader firmware. Bootloader Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x01 Major version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_H[7:0] r r r r Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the bootloader firmware. TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 8 of 16 Semtech Firmware Revision Low Register (FW_REV_L) Address: Reset value: 0x02 Minor version number of the user firmware 7 6 5 4 r r r r 3 2 1 0 r r r r REV_L[7:0] Bits 7:0 REV_L[7:0]: Firmware Revision Low These bits contain the minor version number of the user firmware. Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x03 Major version number of the user firmware 7 6 5 4 r r r r 3 2 1 0 r r r r REV_H[7:0] Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the user firmware. Operating Mode Low Register (MODE_L) Address: Reset value: 0x04 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 1 0 BOOTLDR Res r Bits 7:1 Reserved Bit 0 BOOTLDR: Bootloader mode 0: The user firmware is running 1: The controller is in bootloader mode Operating Mode High Register (MODE_H) Address: Reset value: 0x05 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 1 0 3 2 1 0 w w w Res Bits 7:0 Reserved Reset Low Register (RESET_L) Address: Reset value: 0x06 0x00 7 6 5 4 w w w w RESET_KEY_L[7:0] w Bits 7:0 RESET_KEY_L[7:0]: Reset Key 0x55: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 9 of 16 Semtech Reset High Register (RESET_H) Address: Reset value: 0x07 0x00 7 6 5 4 3 2 1 0 w w w RESET_KEY_H[7:0] w w w w w Bits 7:0 RESET_KEY_H[7:0]: Reset Key 0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. Main Status Register (STATUS) Address: Reset value: 0x08 0xC0 7 6 5 CTS CTS_API rw rw 4 Res 3 2 1 0 STATUS3 STATUS2 STATUS1 STATUS0 rw rw rw rw Bit 7 CTS: Clear To Send This bit indicates if a new command can be issued to the controller. 0: The controller is busy processing a previous command. New commands should not be sent to the controller. 1: The controller can accept a new command over the communication interface. Bit 6 CTS_API: Clear to Send for API This bit indicates if a new API call can be issued to the controller. 0: The controller is busy processing a previous API call. New API calls should not be sent to the controller. 1: The controller can accept a new API call over the communication interface. Bits 5:4 Reserved Bit 3 STATUS3: STATUS3 Event Flag 0: No event is signaled in the STATUS3 register 1: An event is signaled in the STATUS3 register Bit 2 STATUS2: STATUS2 Event Flag 0: No event is signaled in the STATUS2 register 1: An event is signaled in the STATUS2 register Bit 1 STATUS1: STATUS1 Event Flag 0: No event is signaled in the STATUS1 register 1: An event is signaled in the STATUS1 register Bit 0 STATUS0: STATUS0 Event Flag 0: No event is signaled in the STATUS0 register 1: An event is signaled in the STATUS0 register TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 10 of 16 Semtech API Functions API Number API Name Description 0x80 BOOTLOADER_UNLOCK_FLASH Allow changes to the FLASH memory 0x81 BOOTLOADER_WRITE_BLOCK Write a page into the FLASH memory 0x82 BOOTLOADER_CRC_CHECK Check the CRC of the user firmware 0x83-0xFE RESERVED. Will be defined later. 0xFF API_ERROR Value returned in the API field when a Read API Function Return Buffer command is issued and the API function called previously has generated an error. Bootloader Unlock Flash (BOOTLOADER_UNLOCK_FLASH) API number: Input buffer size: Output buffer size: 0x80 TBD 1 Buffer Parameter Input buffer TBD Return data buffer ERROR_CODE Length (bytes) Description 1 Bootloader Write Block (BOOTLOADER_WRITE_BLOCK) API number: Input buffer size: Output buffer size: 0x81 66 1 Buffer Parameter Length (bytes) Block Number Input buffer 2 Block Data Return data buffer 64 ERROR_CODE Description Block index. The first block has an index of 0. Data to be written to the FLASH page. 1 Bootloader CRC Check (BOOTLOADER_CRC_CHECK) API number: Input buffer size: Output buffer size: 0x82 0 1 Buffer Parameter Return data buffer ERROR_CODE Length (bytes) Description 1t API Error Codes Error Code Error Code Name Description 0x00 ERROR_GENERIC Generic error. 0x01 0x02 0x03 0x04 0x05 0x06 0x07-0xFF ERROR_OK ERROR_INVALID_CRC ERROR_FLASH_UNLOCK_FAILED ERROR_API_NOT_IMPLEMENTED ERROR_API_DATA_OVERFLOW ERROR_API_INVALID_PARAMETERS RESERVED. Will be defined later. Operation succeeded. This is not indicating an error. CRC error. FLASH unlocking has failed. The API number is not implemented. The API input buffer has been filled with more data than its length. At least one of the API parameters is invalid. TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 11 of 16 Semtech Application Schematic Figure 1: TS81000 Application Schematic TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 12 of 16 Semtech Version 1.3 PACKAGE DIMENSIONS Package Dimensions Figure 46: 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) Table 53: 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data Dim. mm Min inches Typ Max Min Typ Max D 3.000 0.1181 E 3.000 0.1181 A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 0.152 0.0060 e 0.500 0.0197 L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.0059 L4 0.200 0.0079 b 0.180 Specifications subject to change 0.250 0.300 0.0071 WWW.TRIUNESYSTEMS.COM Triune Systems Proprietary and Confidential Information DOTS81000 NOT DUPLICATE www.semtech.com 15 Final Datasheet June 2, 2015 Rev 1.3 0.0098 0.0118 Copyright © 2013, Triune Systems, LLC 13 of 16 Semtech QFN Package (Top marking) Legend: Line 1 Marking: S033 Internal part code Line 2 Marking: SS Assembly site identifier LL Lot trace code D Assembly year WW Assembly week Y Additional marking o Pin 1 Identifier Line 3 Marking: TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 14 of 16 Semtech Ordering Information Part Number Description TS81000-QFNR Bootloader programmed device RoHS and Reach Compliance Triune Systems is fully committed to environmental quality. All Triune Systems materials and suppliers are fully compliant with RoHS (European Union Directive 2011/65/EU), REACH SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level 3 materials declarations, and their subsequent amendments. Triune Systems maintains certified laboratory reports for all product materials, from all suppliers, which show full compliance to restrictions on the following: • • • • • • • • • • • • Cadmium (Cd) Chlorofluorocarbons (CFCs) Chlorinate Hydrocarbons (CHCs) Halons (Halogen free) Hexavalent Chromium (CrVI) Hydrobromofluorocarbons (HBFCs) Hydrochlorofluorocarbons (HCFCs) Lead (Pb) Mercury (Hg) Perfluorocarbons (PFCs) Polybrominated biphenyls (PBB) Polybrominated Diphenyl Ethers (PBDEs) TS81000 Final Datasheet June 2, 2015 Rev 1.3 www.semtech.com 15 of 16 Semtech IMPORTANT NOTICE Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. 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