AT91SAM9M10-EKES
....................................................................................................................
User Guide
11029A–ATARM–11-Jan-10
1-2
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Section 1
Introduction .................................................................................................................1-1
1.1
Scope ................................................................................................................................. 1-1
1.2
Applicable Documents ....................................................................................................... 1-2
Section 2
Kit Contents ................................................................................................................2-1
2.1
Deliverables ....................................................................................................................... 2-1
2.2
Evaluation Board Specifications......................................................................................... 2-2
2.3
Electrostatic Warning ......................................................................................................... 2-2
Section 3
Power Up ....................................................................................................................3-1
3.1
Power Up the Board........................................................................................................... 3-1
3.2
Battery................................................................................................................................ 3-1
3.3
DevStart ............................................................................................................................. 3-1
3.4
Recovery Procedure .......................................................................................................... 3-1
3.5
Sample Code and Technical Support ................................................................................ 3-2
Section 4
Board Description .......................................................................................................4-1
4.1
4.2
Equipment on the Board .................................................................................................... 4-1
4.1.1
Interfaces ............................................................................................................. 4-1
4.1.2
Board Interface Connection ................................................................................. 4-2
4.1.3
Push Button Switches .......................................................................................... 4-2
4.1.4
Display LCD and LEDs ........................................................................................ 4-3
Hardware Layout and Configuration .................................................................................. 4-3
4.2.1
Processor............................................................................................................. 4-3
4.2.2
Clock Circuitry...................................................................................................... 4-3
4.2.3
Reset Circuitry ..................................................................................................... 4-4
4.2.4
Memory ................................................................................................................ 4-4
4.2.5
Power Supplies .................................................................................................... 4-7
4.2.6
Debug Interface ................................................................................................... 4-9
4.2.7
Audio Stereo Interface ....................................................................................... 4-14
4.2.8
TV-Out Extension .............................................................................................. 4-16
4.2.9
Software Controlled LEDs ................................................................................. 4-16
4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-17
4.2.11 Two Wire Interface (TWI)................................................................................... 4-18
4.2.12 SD/MMC Interface ............................................................................................. 4-18
4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20
4.2.14 Push Buttons ..................................................................................................... 4-22
AT91SAM9M10-EKES User Guide
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11029A–ATARM–11-Jan-10
4.2.15 Expansion Slot ................................................................................................... 4-22
Section 5
Configuration ..............................................................................................................5-1
5.1
JTAG/ICE Configuration..................................................................................................... 5-1
5.2
ETHERNET Configuration ................................................................................................. 5-1
5.3
Jumpers Configuration ....................................................................................................... 5-2
5.4
Miscellaneous Configuration Items .................................................................................... 5-3
5.5
PIO Configuration............................................................................................................... 5-3
5.5.1
Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3
5.5.2
Multiplexing on PIO Controller A (PIOA).............................................................. 5-4
5.5.3
Multiplexing on PIO Controller B (PIOB).............................................................. 5-5
5.5.4
Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6
5.5.5
Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7
5.5.6
Multiplexing on PIO Controller E (PIOE).............................................................. 5-8
Section 6
Connectors .................................................................................................................6-1
6.1
Power Supply ..................................................................................................................... 6-1
6.2
RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1
6.3
DBGU................................................................................................................................. 6-2
6.4
Ethernet.............................................................................................................................. 6-3
6.5
USB Host ........................................................................................................................... 6-3
6.6
USB Host/Device ............................................................................................................... 6-4
6.7
JTAG Debugging Connector .............................................................................................. 6-4
6.8
SD/MMC- MCI0.................................................................................................................. 6-6
6.9
SD/MMC- MCI1.................................................................................................................. 6-7
6.10 AC97 .................................................................................................................................. 6-7
6.11 Image Sensor - ISI ............................................................................................................. 6-8
6.12 Video .................................................................................................................................. 6-9
6.13 Display Devices.................................................................................................................. 6-9
6.13.1 LG TFT LCD LG/PHILIPS.................................................................................... 6-9
6.14 Large LCD Extension ....................................................................................................... 6-10
Section 7
Schematics .................................................................................................................7-1
7.1
Schematics......................................................................................................................... 7-1
Section 8
Revision History..........................................................................................................8-1
8.1
Revision History ................................................................................................................. 8-1
1-ii
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Section 1
Introduction
1.1
Scope
This User Guide introduces the SAM9M10 Evaluation Kit (SAM9M10-EKES) and describes its development and debugging capabilities.
Figure 1-1.
Board Photo
The Atmel® SAM9M10-EKES is a fully-featured evaluation platform for the Atmel SAM9M10-based
microcontroller. The evaluation kit allows users to extensively evaluate, prototype and create applicationspecific designs.
The SAM9M10-EKES includes many hardware peripherals such as:
Two high speed USB hosts and one high speed device port
An Ethernet 10/100 interface
Two high speed multimedia card interfaces
An LCD TFT display (480*RGB*272) with touch pannel
A composite video output
AT91SAM9M10-EKES User Guide
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11029A–ATARM–11-Jan-10
Introduction
A camera interface
Several communication peripherals such as:
– Universal Synchronous/Asynchronous Receiver Transmitter (USART)
– Serial Synchronous Controller (SSC)
– Two-Wire Interface (TWI)
The external memory block is made of 3 memory types:
1.2
DDR2-SDRAM
NAND Flash
NOR Flash
Applicable Documents
Table 1-1. Applicable Documents
Reference
6355A
1-2
11029A–ATARM–11-Jan-10
Title
SAM9M10 Preliminary Datasheet
Comments
This document describes the SAM9M10, which is part of the Atmel's
Smart ARM® Microcontrollers.
It is available from
http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf
AT91SAM9M10-EKES User Guide
Section 2
Kit Contents
2.1
Deliverables
The Atmel SAM9M10-EKES toolkit includes:
Board
– The SAM9M10-EKES board
Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
Cables
– One micro A/B-type USB cable
– One serial RS232 cable
A Welcome Letter
Figure 2-1.
Unpacked SAM9M10-EKES
Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
AT91SAM9M10-EKES User Guide
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11029A–ATARM–11-Jan-10
Kit Contents
2.2
Evaluation Board Specifications
Table 2-1. SAM9M10-EKES Specifications
2.3
Characteristics
Specifications
Clock speed
400 MHz PCK, 133 MHz MCK
Ports
Ethernet, USB, RS232, DBGU
Board supply voltage
5 VDC from connector
Temperature
- operating
- storage
-10° to +50° C
Relative humidity
0 to 90% (non condensing)
Dimensions
180 mm x 160 mm
RoHS status
Compliant
-40° to +85° C
Electrostatic Warning
The SAM9M10-EKES evaluation board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic
carpet, for example...). Avoid touching the component pins or any other metallic element on the board.
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11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Section 3
Power up
3.1
Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2
Battery
The SAM9M10-EKES ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and
time backup function of the SAM9M10 series devices when the board is switched off.
3.3
DevStart
The on-board NAND Flash contains a “SAM9M10-EKES DevStart”.
It is stored in the “SAM9M10-EKES DevStart” folder on the USB Flash disk available when the
SAM9M10-EKES is connected to a host computer.
Click the file “welcome.html” in this folder to launch SAM9M10-EKES DevStart.
SAM9M10-EKES DevStart guides you through installation processes of IAR™ EWARM, Keil™ MDK and
GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and
how to program it into the SAM9M10-EKES. Optionally, if you have a SAM-ICE™, instructions are also
given about how to debug the code.
We recommend that you backup the “SAM9M10-EKES DevStart” folder on your computer before
launching it.
AT91SAM9M10-EKES User Guide
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11029A–ATARM–11-Jan-10
Power up
3.4
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-EKES to the
state as it was when shipped by Atmel.
Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want
to recover from this situation.
3.5
Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical support from Atmel website
http://www.atmel.com/dyn/products/product_card.asp?part_id=4653
Figure 3-1.
3-2
11029A–ATARM–11-Jan-10
Atmel Website for SAM9M10 Series
AT91SAM9M10-EKES User Guide
Section 4
Board Description
4.1
Equipment on the Board
Figure 4-1.
Board Architecture
Main Memory
Multimedia cards
LCD TFT
Data
Flash
PARALLEL
FLASH
NPCS0
4 bits
interface
SD/MMC
Micro
MCI1
MCI1
EBI1 / 1.8v
EBI1 / 1.8v
Touch
Touch
Screen
Screen
Joystick
& P.B
Line Out
SPI0
SPI0
Led
Composite
video
CD
NCS0
NCS3
NCS1
8 bits
interface
SD/MMC
Codec
MCI0
MCI0
Multimedia Cards Interface
Multimédia Cards Interface
External Memory
External Memory
AC97
AC97
LCD Interface
LCD Interface
PWM
PWM
AT91SAM9M10
System Controller
System Controller
Image Sensor
Image
Sensor
Interface
Interface
TWI
TWI
ETHERNET
ETHERNET
10/100
MAC
10/100 MAC
USB
USB
USART
USART
Host A
Host A
Serial
Eeprom
Power /
Shdn
Host B
Device
Host B
Device
PIO
PIO
DEBUG
DEBUG
DBGU
JTAG/ICE
RS232
oooooooo
oooooooo
PHY RMII
oooooooo
oooooooo
VCC 5V
4.1.1
User I/O
Line In
NAND
FLASH
EBI0
EBI0
Audio
LCD TFT
LCD
TFT
480*272
480*272
DDR2
SDRAM
DDR2
SDRAM
Vidéo
ISI
oooooooo
oooooooo
Ethernet RMII/MII
RS232
USB Hub
High / Full
USB
Hub / Device
DBGU
JTAG/ICE
PIO
Interfaces
The board is equipped with a SAM9M10-CU chip (324-ball TFBGA package) together with the following
interfaces or peripherals:
DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory
External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND
Flash and NOR Flash (not populated))
AT91SAM9M10-EKES User Guide
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11029A–ATARM–11-Jan-10
Board Description
4.1.2
4.1.3
One TWI serial memory
One USB Host/Device multiplexed port interface
One USB Host port interface
One RS232 serial communication port
One DBGU serial communication port
One JTAG/ICE debug interface
One Ethernet 100-base TX with three status LEDs
One AC97 Audio DAC with headphone line out, line in and mono/stereo micro inputs
One TV interface (composite video output)
One 4.3" TFT LCD Module with touch screen and back light
One ISI connector (camera interface)
One Power red LED and two general-purpose green LEDs
Two user input push buttons
One joystick with 4-direction control and selector
One Wakeup input push button
One reset input push button
One DataFlash®/SD/SDIO/MMC plus card slot (4/8 bit interface)
One SD/SDIO/MMC card slot (4-bit interface)
One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)
Board Interface Connection
Ethernet using RJ45 connector (J15)
USB Host, support USB host using a type A connector (J12)
USB Host/Device, support USB host/device using a type micro AB connector (J14)
UART1 (Rx, Tx, Rts, Cts) connected to a 9-way male D-type RS232 connector (J11)
DBGU (Rx and Tx only) connected to a 9-way male D-type RS232 connector (J10)
JTAG, 20 pin IDC connector (J13)
SD/MMCplus connector (J5)
SD/MMC connector (J6)
Headphone (J7), line-in (J8) and microphone headset (J9)
Speaker output (JP15)
Image sensor connector (J17)
TFT LCD display (J16), with TouchScreen (J19) and BackLigth (J21)
Test points; various test points are located throughout the board
Main power supply (J2)
Push Button Switches
Reset, board reset (BP1)
Wake up, push button to bring processor out of low power mode (BP2)
Right and left click, user push button switches (BP4 and BP5)
Joystick (BP3)
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11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Board Description
Display LCD and LEDs
Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)
One surface-mounted power red LED, user interface (D8)
Two surface-mounted green LEDs, user interface (D6 and D7)
Three surface-mounted LEDs indicate Ethernet status (D9, D10, D11)
Board Layout Commented
20
30
Y2
8
2
J1
1
7
Y7
C199
TP5
R125
C192
BP3
MN2
RESET
BUTTON
C19
D5
R103
JP4
MN1
RR46
D3
C176
C178
1
Q1
MN4
BP1
BACKUP
BATTERY
J3
C220
R142
C221
R143
«RIGHT»
USER BUTTON
BP4
L18
BP5
Y6
RR34
RR36
TP2
2
1
J18
20
19
2
1
J23
RR35
40
39
J5
J6
SD/MMC 0
SLOT
L4
BP2
2
C193
MN13
L21
MN14
J17
R121
R119
R104
JP11
MN23
J20
C180 R108
R101
R100
JP16
L7
JP8
L6
L2
WAKE-UP
BUTTON
D2
JP7
C52
29
L5
L3
C171
Y4
R112
R92
C175
R93
Y5 R94 R95 C181
R10
JP6
JP13
R9 R3 R7
RR21
MN5
RR23
C48
RR19 RR25
RR9
RR11
MN8
MN9
TP6
RR13
Y3
Y1
C182
C173
RR44
C27
R25
C35
MN7
JP1
R32
R23
C54
C29
R26
R27
R28
C122
MN10
MN11
RR17
C129
C130
JP5
R33
C164
JP9
MN20 C165
1
C177
C172
C174
R109
R185
C113 C112
L24 C200
1
C146
C121
J7
USER
JOYSTICK
MN6
C36
C131
JP14
C196
VIDEO
OUTPUT
C128 R58
R72
MN16
JP15
HEADPHONES
HEADER
C137
C118
R71
C150
C151
J9
MN15
C144
R67
MICROPHONE
INPUT
R68
J8
C136
L22
LINE
INPUT
MN17
k D9
k D10
k D11
J15
JP12
1 2 3 4
C163
JP10
MN18
TP4
J2
TP1
19
R11
J13
k
2
1
k
1
Q2
D7
J11
D8
J10
POWER
ETHERNET
D6
J14
J12
JTAG
R107
R102
RS232
JP3
DBGU
HOST
HOST DEVICE
USB
USB
JP2
Figure 4-2.
k
4.1.4
LCD DISPLAY
LCD EXTENSION
CONNECTORS
TP3
«LEFT»
USER BUTTON
SD/MMC 1
SLOT
ISI/CAMERA
CONNECTOR
The major components of the SAM9M10-EKES board are shown in Figure 4-1.
4.2
Hardware Layout and Configuration
4.2.1
Processor
The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus.
For more information, refer to the last SAM9M10 datasheet available from http://www.atmel.com/
4.2.2
Clock Circuitry
The SAM9M10-EKES includes six clock sources:
AT91SAM9M10-EKES User Guide
4-3
11029A–ATARM–11-Jan-10
Board Description
Two are alternatives for the SAM9M10 main clock,
One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,
One crystal is used for the AC97 codec chip, and
One crystal or one crystal oscillator is used for the TV encoder.
Table 4-1. Main Components Associated with the Clock Systems
Quantity
4.2.3
Description
Component assignment
1
Crystal for Internal Clock, 12 MHz
Y1
1
Crystal for RTC Clock, 32.768 kHz
Y2
1
Oscillator for Ethernet Clock RMII, 50 MHz
Y4
1
Crystal for Ethernet Clock MII, 25 MHz
Y5
1
Crystal for AC91 Codec Clock, 24.576 MHz
Y3
1
Crystal for TV Encoder Clock, 13 MHz, or
Oscillator for TV Encoder, 13 MHz
Y7
Y6
Reset Circuitry
The reset sources are:
Power on reset
Push button reset
JTAG reset from an in-circuit emulator interface.
4.2.4
Memory
4.2.4.1
External Memories
The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit
interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The SAM9M10-EKES board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2SDRAM memory (Micron MT47H64M8B6-3 16Meg*8*4).
The External Bus Interface (EBI) is connected to three kinds of memory devices:
One Parallel Flash AT49SV322DT (not populated by default)
Two DDR2-SDRAM MT47H64M8B6-3
One NAND Flash MT29F2G16ABD (not populated by default) or MT29F2G08ABD (single footprint)
The chip select NCS0, NCS1 and CS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash memories, respectively. Furthermore, a dedicated jumper can disconnect each of these NCS0, NCS1, and
NCS3 signals, making them available for other functions.
4-4
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
AT91SAM9M10-EKES User Guide
DDR_W E
DDR_CAS
DDR_RAS
DDR_CS
DDR_CLK
DDR_NCLK
DDR_CKE
DDR_BA0
DDR_BA1
F3
NW E
G1
L3
L7
G8
G7
F7
CAS
RAS
E8
F8
CK
NCK
CS
F2
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
CKE
BA0
BA1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
MN6
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF - 3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
DDR_VREF
1V8
C75
100nF
100nF
100nF
100nF
100nF
C65
C67
C69
C71
C73
100nF
100nF
100nF
100nF
100nF
C63 100nF
C55
C57
C59
C61
DDR_DQM0
A1
E9
H9
L1
DDR_DQS0
B7
A8
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
B3
A2
C8
C2
D7
D3
D1
D9
B1
B9
NW E
CAS
RAS
CS
CK
NCK
CKE
BA0
BA1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
G1
L3
L7
F3
G7
F7
G8
E8
F8
F2
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
MN7
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF - 3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
A1
E9
H9
L1
B3
A2
B7
A8
C8
C2
D7
D3
D1
D9
B1
B9
DDR_VREF
1V8
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
C76
100nF
100nF
100nF
100nF
100nF
C66
C68
C70
C72
C74
100nF
100nF
100nF
100nF
100nF
C64 100nF
C56
C58
C60
C62
DDR_DQM1
DDR_DQS1
Figure 4-3.
DDR_A[0..13]
DDR_D[0..15]
Board Description
EBI0 - DDR2
11029A–ATARM–11-Jan-10
4-5
4-6
W E_EBI1
CAS_EBI1
RAS_EBI1
CS_EBI1
CLK_EBI1
NCLK_EBI1
CKE_EBI1
BA0_EBI1
BA1_EBI1
R_A[2..15]
R_D[0..15]
G8
G7
F7
F3
CS_EBI1
CAS_EBI1
RAS_EBI1
W E_EBI1
MN8
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
PC8
(RDY/BSY)
(NCS3)
(NANDCLE)
(NANDALE)
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF - 3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
PC5
PC4
EBI1_NANDOE
EBI1_NANDW E
PC14
EBI1_NAND_FSH_D[0..15]
G1
L3
L7
F2
E8
F8
CLK_EBI1
NCLK_EBI1
F9
G2
G3
CKE_EBI1
BA0_EBI1
BA1_EBI1
H8
EBI1_DDR_A2
H3
EBI1_DDR_A3
H7
EBI1_DDR_A4
J2
EBI1_DDR_A5
J8
EBI1_DDR_A6
J3
EBI1_DDR_A7
J7
EBI1_DDR_A8
K2
EBI1_DDR_A9
K8
EBI1_DDR_A10
K3
EBI1_DDR_A11
EBI1_DDR_A12 (SDA10) H2
K7
EBI1_DDR_A13
L2
EBI1_DDR_A14
L8
EBI1_DDR_A15
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
JP10
VREF1
1V8
1V8
1V8
C90
C92
C94
C96
C98
R41
R46
R44
R45
R42
R43
C101
100nF
100nF
100nF
100nF
100nF
R47
DNP
470K
470K
0R
1K
0R
0R
100nF
100nF
100nF
100nF
100nF
C88 100nF
C80
C82
C84
C86
DQM0_EBI1
A1
E9
H9
L1
DQS0_EBI1
B3
A2
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
B7
A8
C8
C2
D7
D3
D1
D9
B1
B9
WP
RB
RE
WE
CE
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
G5
C3
C8
D5
C4
D4
C7
C6
F2
VCC
VCC
VCC
VCC
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
G1
L3
L7
F3
G7
F7
G8
E8
F8
VSS
VSS
VSS
VSS
VF BGA- 63
MT29F2G08ABDHC:D
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
LOCK
WP
R/B
CLE
ALE NAND F L ASH
RE MT29F 2G08ABD
WE
CE
MN11
W E_EBI1
CAS_EBI1
RAS_EBI1
CS_EBI1
CLK_EBI1
NCLK_EBI1
CKE_EBI1
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
(SDA10) H2
K7
L2
L8
BA0_EBI1
BA1_EBI1
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
MN9
C5
F7
K3
K8
D3
G4
H8
J6
L9
L10
M1
M2
M9
M10
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
1V8
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
100nF
100nF
100nF
100nF
C102
100nF
100nF
100nF
100nF
100nF
C91
C93
C95
C97
C99
100nF
100nF
100nF
100nF
100nF
C89 100nF
C81
C83
C85
C87
Optional 16bits DATA BUS
With AT29F2G16ABD Micron
VREF1
1V8
DQM1_EBI1
A1
E9
H9
L1
DQS1_EBI1
B7
A8
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
B3
A2
C8
C2
D7
D3
D1
D9
B1
B9
C103
C104
C105
C106
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
DQ0
A0
DDR2 SDRAM
DQ1
A1
A2 MT47H64M8CF - 3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
DDR_VREF
EBI1_NCS0
EBI1_NRD/CFOE
1V8
EBI1_NW E/NW R0/CFW E
R39 100K
VREF1
JP9
1V8
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
DNP
VPP
CE
OE
RESET
WE
1V8
CBGA
GND
GND
VCC
I/00
A0
I/O1
A1
F L ASH
A2
I/O2
A3
I/O3
AT49SV322DT
A4
I/O4
A5
I/O5
A6
I/O6
A7
I/O7
A8
I/O8
A9
I/O9
A10
I/O10
A11
I/O11
A12
I/O12
A13
I/O13
A14
I/O14
A15
I/O15
A16
A17
A18
RDY/ BUSY
A19
A20
NC1
NC
MN10
R40 470K
B3
F1
G1
B4
A4
E1
D1
C1
A1
B1
D2
C2
A2
B5
A5
C5
D5
B6
A6
C6
D6
E6
B2
C3
D4
D3
H1
H6
G4
C4
F6
A3
E2
H2
E3
H3
H4
E4
H5
E5
F2
G2
F3
G3
F4
G5
F5
G6
1V8
C100
100nF
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
Figure 4-4.
1S
11029A–ATARM–11-Jan-10
H_A[1..21]
H_D[0..15]
Board Description
EBI1 - DDR2 + Flash
AT91SAM9M10-EKES User Guide
Board Description
4.2.5
Power Supplies
The SAM9M10 Board contains four regulated power supplies:
3.3 VDC Supply
1.8 VDC Supply
1.0 VDC Core Supply
1.0 VDC Core UTMI Supply, PLL
The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit
board.
The 3.3 VDC Supply is generated by an LTC1765-3.3 chip. It accepts VIN 5 VCC power and outputs a
regulated +3.3 V to most other circuits in the SAM9M10-VB.
The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an LT1765-1.8. It is powered by VIN
5 VCC power and outputs a regulated +1.8V.
The 1.0 VDC Core Supply (VDDCORE) is generated by a TPS60500 IC. It is powered by the VIN
5 VCC power.
The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by a CMOS
voltage regulator R1100D series. It is powered by the output of the 3.3 VDC Supply.
Note:
1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to
permit probing of these voltages.
AT91SAM9M10-EKES User Guide
4-7
11029A–ATARM–11-Jan-10
SHDN
1
2
10K
R4
2.1 MM SOCKET
3
J2
R5
10K
JP4
3
2
1
Si1563EDH
C11
15pF
Q1
FORCE
POWER
ON
D2
5V
4
5
6
R2
100K
5V
5V
3V3
5V
C18
2.2uF
C10
2.2uF
C2
2.2uF
7
10
15
11
3
4
7
10
15
11
3
4
NC1
NC2
NC3
SHDN
VIN1
VIN2
MN2
NC1
NC2
NC3
SHDN
VIN1
VIN2
MN1
14
1
5
14
LT1765-3.3
LT1765-1.8
MN4
EN
VIN
C1M
8
3
TPS60500
9
GND
C2P
4
C17
1uF
PG
FB
VOUT
C1P C2M
6
C16
1uF
12
6
5
2
10
7
C15
2.2nF
FB
SW 1
SW 2
12
6
5
C9
180nF
C6
2.2nF
FB
SW 1
SW 2
VC
2
BOOST
GND1
GND2
GND3
GND4
GND5
2
BOOST
SYNC
SYNC
D1
D4
2
C19
10pF
R8
220K
R6
68K
D5
STPS2L30A
2.2uH
L4 BAT20J
1
2
D3
STPS2L30A
2.2uH
L2 BAT20J
1
C22
22uF
1V
C12
10uF
1V8
C4
10uF
3V3
1V8
1V
3V3
C13
2.2uF
MN3
150mA
L3
150mA
R1100D101C
10uH
10uH
L1
2
VDD
1
C7
100nF
C3
100nF
J3
10uH
10uH
1
1
1
C25
100nF
1
1
150mA
L6
150mA
L5
C14
2.2uF
1V VDDUTMIC
C8
4.7uF
R3
1R
C5
4.7uF
R1
1R
OUT
1
8
17
9
16
GND1
GND2
GND3
GND4
GND5
1
8
17
9
16
13
VC
13
GND
3
5
3
3
1
JP6
JP5
J1-3
C24
4.7uF
R9
1R
C21
4.7uF
6
J1-2
R7
1R
3
JP3
JP2
3
J1-1
JP1
1
2
2
2
4-8
2
11029A–ATARM–11-Jan-10
2
7
3
3
JP7
C23
100nF
C20
100nF
4
2
8
3V3
VDDBU
3
J1-4
VDDUTMII
VDDBU
VDDIOM1
VDDIOM0
VDDCORE
VDDPLLA
VDDPLLUTMI
VDDUTMIC
VDDISI
VDDIOP2
VDDIOP1
VDDIOP0
VDDOSC
VDDANA
Figure 4-5.
2
C1
180nF
Board Description
Power Supply and Management Power Block
AT91SAM9M10-EKES User Guide
Board Description
4.2.6
Debug Interface
4.2.6.1
JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator.
Figure 4-6.
JTAG Interface
3V3
5
6
7
8
RR42
100K
J13
2
4
6
8
10
12
14
16
18
20
3V3
1
3
5
7
9
11
13
15
17
19
4
3
2
1
3V3
R84
DNP
R85
0R
0R
R86
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
R87
DNP
ICE INTERFACE
4.2.6.2
DBGU Com Port
This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).
Figure 4-7.
DBGU Com Port
3V3
SERIAL DEBUG PORT
MN18
16
VCC
15
GND
C153
100nF
MALE RIGHT ANGLE
C155
100nF
C160
100nF
6
1
V+
C1C2+
3
4
V-
C2-
5
C156
100nF
3V3
14
7
C158
100nF
T
11
T
10
13
R
12
8
R
9
10
11
1
6
2
7
3
8
4
9
5
2
C1+
R80
100K
R82
100K
PB13
PB12
R83
0R
J10
ADM3202ARNZ
AT91SAM9M10-EKES User Guide
4-9
11029A–ATARM–11-Jan-10
Board Description
4.2.6.3
User Serial Com Port
The USART1 is used as a user serial com port. This USART1 is buffered with an RS-232 Transceiver
(TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Software must
assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the
UART1 function.
User Serial Com Port
3V3
MN17
1
R79
100K
C152
100nF
R81
100K
PB4
PD16
PB5
PD17
C1+
3
4
C1C2+
5
C2-
C159
100nF
11
10
VCC
16
GND
15
RS232 COM PORT
C154
100nF
MALE RIGHT ANGLE
V+
2
V-
6
T
14
T
7
12
R
13
9
R
8
C157
100nF
1
6
2
7
3
8
4
9
5
C161
100nF
10
3V3
11
Figure 4-8.
J11
ADM3202ARNZ
Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs.
4.2.6.4
USB Port
The SAM9M10-EKES features USB communication ports:
Two Host Ports: Full speed OHCI and High speed EHCI
One Device Port: High speed.
USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is multiplexed with the USB device High speed and connected to the second UTMI port.
One USB high/full speed type standard A connector
One USB interface Host/Device Micro AB connector
Refer to the SAM9M10 datasheet for detailed programming information.
4-10
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Board Description
Figure 4-9.
USB Port
J12
292303-1
USB HOST INTERFACE
1
2
4
3
C162
100nF
HDMA
HDPA
6
5
5V
MN20
L15
8
BLM21PG221SN1x
7
C164
33 uF
16V
C163
100nF
6
L16
5
BLM21PG221SN1x
C165
33 uF
16V
ENA
OUTA
IN
FLGA
GNG
FLGB
OUTB
ENB
1
(ENA)
2
(FLGA)
3
(FLGB)
4
(ENB)
PD1
PD2
PD4
PD3
SP2526A-2
3V3
R88 47K
(VBUS)
C166
10pF
7
PB19
R89
68K
ZX62-AB-5P
DHS
6
J14
VBUS
DM
DP
ID
GND
1
2
3
4
5
R90
47K
(IDUSB)
HDMB
HDPB
PD28
USB HOST/DEVICE INTERFACE
C167
100nF
4.2.6.5
Ethernet 10/100 (EMAC) Port
The port is compatible with IEEE® Standard 802.3.
The SAM9M10-EKES is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical
Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as
defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment
(PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status
LEDs.
The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-Tx or
10Base-Tx. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as
described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the
table below.
AT91SAM9M10-EKES User Guide
4-11
11029A–ATARM–11-Jan-10
Board Description
Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name
Normal MII Mode
SAM9M10
Reduced MII Mode
DM9161
SAM9M10
DM9161
ETX0-ETX1
ETX[0:1] transmit data
TXD [0:1]
ETX[0:1]
TXD [0:1]
ETX2-ETX3
ETX[2:3] transmit data
TXD [2:3]
NC
NC
ETXEN
ETXEN: transmit enable
TXEN
ETXEN: transmit enable
TXEN
ETXER
ETXER: transmit error
TXER/TXD[4]
NC
NC
ETXCK/REFCK
ETXCK: transmit clock
TXCLK
REFCK: reference clock
REF_CLK
ERX0-ERX1
ERX[0:1]: receive data
RXD [0:1]
ERX[0:1]: receive data
RXD [0:1]
ERX2-ERX3
ERX[2:3]: receive data
RXD [2:3]
NC
NC
ERXER
ERXER: receive error
RXER/RXD[4]/
RPTR/NODE
ERXER: receive error
RPTR/NODE
ERXDV
ERXDV: receive valid data
RXDV
ECRSDV: carrier sense /
data valid
CRS DV
ERXCK
ERXCK: receive clock
RXCLK
NC
NC
ECOL
ECOL: collision detect
COL
NC
NC
ECRS
ECRS: carrier sense /
data valid
CRS (PHYAD[2:4]
NC
NC
EMDC
EMDC: management data clock
MDC
EMDC: management data
clock
MDC
EMDIO
EMDIO: management data
input / output
MDIO
EMDIO: management data
input / output
MDIO
NRST
NRST: microcontroller reset
RESET# XT1
(25 MHz)
NRST: microcontroller reset
RESET# XT1
(REF_CLK 50MHz)
4-12
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
PA18
PA19
PD15
PA30
PA29
PA27
PA16
PA28
PA15
PA9
PA8
PA13
PA12
PA7
PA6
PA11
PA10
PA14
R100
R101
R102
R103
R104
R107
(RXD3)
(RXD2)
(RXD1)
(RXD0)
(RX_CLK)
(RX_DV)
(TX_ER)
(RX_ER)
(COL)
(CRS)
(MDC)
(MDIO)
(MDINTR)
R98
R99
(TXD3)
(TXD2)
(TXD1)
(TXD0)
(TX_EN)
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
NRST
RR44
10K
8
7
6
5
1
2
3
4
(TX_CLK)
50 MHz
Y4
RR43
10K
3V3
3
4
8
7
6
5
RR45
10K
1
2
3
4
PA17
8
7
6
5
1
2
3
4
CFPS-39IB 50.0MHZ
2
EO
SSV
1
10K
JP16
3V3
R112
R114
0R
100nF
100nF
C180
C181
100nF
C179
0R
3V3
DNP
R95
1.5K
17
18
19
20
21
22
40
10
15
33
44
23
30
41
39
24
25
32
36
35
16
38
34
37
26
27
28
29
42
0R
R93
R94
C168
100nF
R108
R92
0R
3V3
3V3
C182
10uF
10V
RESET
PW RDW N
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
C170
18pF
R115
0R
GND_ETH
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
25MHz
2
1
REF_CLK/XT2
MN22
DNP
Y5
3
C169
18pF
4
45
48
31
11
12
13
14
47
C172 100nF
R109
6.8K
1%
0R
C178 100nF
C174 100nF
R185
AVDDT
5
6
46
9
2
1
4
3
8
7
43
C175
10uF
10V
3V3
L17
742792093
8
7
6
5
1
2
3
4
RR46
10K
GND_ETH
D11
D10
D9
C176
10uF
10V
AVDDT
C177
100nF
GREEN
GREEN
YELLOW
1K
1K
1K
R106
49R9
1%
C173
100nF
3V3
R113
R111
R110
2
3
5
6
8
7
4
J15
15
1
16
J00-0061NL
LINK&ACT
SPEED 100
FULL DUPLEX
RJ45 ETHERNET CONNECTOR
GND_ETH
GND_ETH
R97
49R9
1%
AVDDT
GND_ETH
R105
49R9
1%
R96
49R9
1%
C171
100nF
8
7
5
57
TC
-DR
CN
-XR
+DR
Fn1
6
+XR
TC
-DT
57 57
3
-XT
+DT
57
2
+XT
4
1
DDV
AT91SAM9M10-EKES User Guide
TUO
R91
Board Description
Figure 4-10. Ethernet Port
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.
11029A–ATARM–11-Jan-10
4-13
Board Description
4.2.7
Audio Stereo Interface
The SAM9M10-EKES includes an AD1981B AC97 SoundMAX® CODEC for digital sound input and output. This interface includes audio jacks for MIC input (J9), Line audio input (J8), Headphone line output
(J7) and a 2-point speaker output connector (JP15).
It is compliant with AC97 Component Specification V2.2.
4-14
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
OUT
OUT
IN
IN
PD8
NRST
PD6
PD7
PD9
PE31
22pF
C123
(AC97FS)
(AC97RX)
(AC97TX)
(AC97CK)
22pF
R60
Y3
24.576MHz
DNP
C122
10uF
10V
Local XTAL
Ext. BITCLK
Ext. BITCLK (Into XTAL-IN)
Ext. BITCLK (Into XTAL-IN)
C120
(EXT_CLK)
24.576 MHz
12.288 MHz
48.000 MHz
14.318 MHz
OUT
IN
OUT
IN
PRIMARY
SECONDARY
PRIMARY
PRIMARY
CLK FREQ
RB=1K CODEC ID
CLOCK SELECTION - PIN STRAPING TABLE
C144
10uF
10V
C124
100nF
5V
RB
RA
AGND_AC97
C146
47uF
6V3
AVDD_AC97
AGND_AC97
R65 2.2K
R63 2.2K
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
NC1
MN15
150mA
R73 0R
100nF
1
2
3
4
5
6
7
8
9
10
11
12
L13
10uH
C145
C125
100nF
3V3
R59 DNP
R58 DNP
(see table)
AVDD_AC97
48
47
46
45
44
43
42
41
40
39
38
37
AD1981B
C117
100nF
100nF
100nF
C142
10nF
AGND_AC97
C143
10nF
R70 100R
R69 100R
VREFOUT
DNP
DNP
R75
R77
270pF
270pF
270pF
270pF
R71
3.9K
C150
10uF
10V
R57
1K
AGND_AC97
R72
3.9K
R61 22K
R78
R76
R67
4.7K
-IN
MN16
R68
4.7K
R66
470R
470R
AVDD_AC97
4.7K
Av=1
Vo1
Vo2
742792093
C138
470pF
742792093
742792093
C147
470pF
L14
742792093
L12
L11
L10
AGND_AC97
7
GND
Bias
4.7K
SSM2211
R64
VDD
6 C126 100nF
C121
10uF
10V
C114
470pF
742792093
742792093
R62 22K
VDD/2
1 Shutdown
2 Bypass
3 +IN
4
AVDD_AC97
AGND_AC97
C135
100nF
R56
1K
AGND_AC97
L9
C113100uF 6V3
L8
C112100uF 6V3
C151
10uF
10V
C133 100nF
C132 100nF
AGND_AC97
C134
1uF
C128
C129
C130
C131
C127 100nF
3
DNP
OPTIONAL MIC BIASING FROM VREFOUT
C141
C140
1
JP14
C119
1uF
OPTIONAL VOICE
FILTER COMPONENTS
C137
1uF
VREFOUT
AVDD_AC97
C118
10uF
10V
36
35
34
33
32
31
30
29
28
27
26
25
C136
1uF
LINE_OUT_R
LINE_OUT_L
AVDD4
AVSS4
AFILT4
AFILT3
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
AGND_AC97
C116
100nF
SPDIF
EAPD
ID1
ID0
AVSS3
AVDD3
NC
HP_OUT_R
AVSS2
HP_OUT_L
AVDD2
MONO_OUT
AT91SAM9M10-EKES User Guide
PHONE_IN
AUX_L
AUX_R
JS1
JS0
CD_L
CD_GND_REF
CD_ R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
+
13
14
15
16
17
18
19
20
21
22
23
24
+
2
RA=1K
AGND_AC97
8
5
1
1
R74
0R
C149
470pF
AGND_AC97
C148
470pF
2
JP15
4
4
4
3.5 PHONEJACK STEREO
3 J9
5
C139
470pF
2
1
3.5 PHONEJACK STEREO
3 J8
5
C115
470pF
2
3.5 PHONEJACK STEREO
3 J7
5
DNP
MONO / STEREO
MICROPHONE INPUT
LINE-IN
SPEAKER OUTPUT
HEADPHONE
LINE-OUT
Board Description
Figure 4-11. Audio Stereo Interface
For more information about the AC97 codec device, refer to the Analog Devices AD1981B controller
manufacturer's datasheet.
11029A–ATARM–11-Jan-10
4-15
Board Description
4.2.8
TV-Out Extension
The Chrontel CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set by
converting LCD signals to TV signals.
The CH7024 is a TV encoder device which encodes the video signals and generates synchronization
signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433,
PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or Svideo.
Figure 4-12. TV-Out Extension Port
PE[0..30]
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPW R)
3V3
L18
742792093
MN23
1V8
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
PE3
PE4
PE5
PE6
39
40
41
20
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
VDDIO
DVDD
DGND
AVDD_PLL
AGND_PLL
AVDD
AGND
AVDD_DAC
AGND_DAC
V
H
XCLK
DE
ISET
CVBS
R122
C/CVBS
NC
34
DNP
Y6
1 OE
C193
10uF
10V
32
L20
742792093
C194
100nF
31
3V3
33
L21
742792093
C195
100nF
C196
10uF
10V
36
25
L22
742792093
C197
100nF
29
3V3
P-OUT
R116
30
R119
75R
26
J20
1.2K 1%
28
27
33pF
R121
3
L24
1.8uH
R120
75R
C199
100pF
C200
D13
270pF 1
2
BAT54SLT1G
75R
37
Composite Video Output
CH7024B-DF-TR
TP5
VDD 4
R125
0R
13 MHz
2 VSS
C192
10uF
10V
18
RESET
XO
24
3V3
35
23
NRST
Y
SPD
SPC
XI/FIN
21
22
742792093
C191
100nF
C198
R118 4.7K
(TW DO)
(TW CK0)
PA20
PA21
L19
C190
100nF
R117 4.7K
3V3
38
16
1
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
3
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
OUT 3
R124
DNP
Y7
SG-8002JC-13.0000M-PCB
DNP
4
C205
DNP
3
1
C207
10pF
2
13MHz
C206
10pF
The frequency accuracy must be +-20ppm or higher.
4.2.9
Software Controlled LEDs
Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their
control through either GPIO or PWM control.
LEDs D6 to D8 are software controlled by PIO pins.
LEDs D9 to D11 indicate Ethernet traffic and link status. These are automatically managed by on-chip
microcontroller hardware. See Section 7.1 ”Schematics” .
4-16
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Board Description
Table 4-3. Discrete LEDs
LED
Description
Comment
D6
Green LED
User software controlled
D7
Green LED
User software controlled
D8
Red LED
User software controlled
D9
Yellow LED
Indicates transmission or reception via Ethernet
D10
Green LED
Indicates speed 100
D11
Green LED
Is lit when a good link test has been detected
Figure 4-13. Software Controlled LEDs
USER INTERFACE
3V3
D6
3V3
R10
470R
R11
470R
PD0
GREEN
D7
PD31
GREEN
R12
470R
PB15
PB16
D8
RED
R15
470K
BP3
3
1
Q2
IRLML2402
PD30
1
2
3
4 UP
5 RIGHT
6 DOWN
JOYSTICK
PB17
2
POWER LED
4.2.10
LEFT
PUSH
PB14
PB18
C215
C216
C217
10nF
10nF
10nF
R141
100R
C218
C219
10nF
10nF
PB[14..18]
Serial Peripheral Interface Controller (SPI)
The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to
interface with the on-board serial EEPROM.
Figure 4-14. SPI
3V3
DNP
R53
470K
Test point
1
JP11
PB0
PB1
PB2
PB3
NRST
MN14
2
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
3V3
3
JP12
8
1
2
4
3
SO
SI
SCK
CS
RESET
VCC
GND
WP
6
C110
100nF
7
5
AT45D321D
SERIAL DATAFLASH
AT91SAM9M10-EKES User Guide
R55
DNP
W RITE PROTECT
NORMALLY OPEN
4-17
11029A–ATARM–11-Jan-10
Board Description
4.2.11
Two Wire Interface (TWI)
The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully compatible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the onboard Serial DataFlash, ISI and TV encoder interface.
Figure 4-15. TWI
3V3
R54
10K
MN13
PA21
PA20
6
5
(TW CK0)
(TW DO)
3V3
C111
100nF
8
4
SCL
SDA
A0
A1
A3
1
2
3
JP13
VCC
GND
WP
7
AT24C512BN-SH25-B
SERIAL EEPROM
4.2.12
SD/MMC Interface
The SAM9M10-EKES has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first
interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit
SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit
SD/MMC card slot.
The users must provide their own compatible cards for use with these connectors.
Please note that the power is connected to VCC, which is 3.3 volts.
4-18
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
PD10
PA[0..5]
R188
(MCI0_CK)
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
PA0
PA1
PA5
PA4
R189
R190
R191
R186
R187
(MCI0_DA1)
(MCI0_DA0)
PA3
PA2
(MCI0_CD)
RR41
68K
8
7
6
5
R52
10K
3V3
C109100nF
8
7
6
5
4
3
2
1
9
FPS009
J6
SD/MMC CARD INTERFACE - MCI0
27R
27R
27R
27R
27R
27R
R51
10K
12
11
10
PD29
PD11
PA[22..31]
PA27
PA28
PA29
PA30
PA22
PA26
PA25
PA31
PA24
PA23
(MCI1_DA4)
(MCI1_DA5)
(MCI1_DA6)
(MCI1_DA7)
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
(MCI1_CK)
(MCI1_DA1)
(MCI1_DA0)
(MCI1_W P)
(MCI1_CD)
R198
R199
R200
R201
27R
27R
27R
27R
R195 27R
R196 27R
R197 27R
R194 27R
R192 27R
R193 27R
68K
RR35
68K
3V3
C108
100nF
RR36
10K
8
7
6
5
4
3
2
1
9
7SDMM-B0-2211
J5
13
12
11
10
16
15
14
SD/MMCPlus CARD INTERFACE - MCI1
8
7
6
5
1
2
3
4
RR34
8
7
6
5
1
2
3
4
3V3
8
7
6
5
1
2
3
4
AT91SAM9M10-EKES User Guide
1
2
3
4
3V3
Board Description
Figure 4-16. SD/MMC0-MMC1
11029A–ATARM–11-Jan-10
4-19
Board Description
4.2.13
TFT LCD with Touch Panel
The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10EKES with a low power LCD display, back light unit and a touch panel, similar to that used on commercial PDAs.
The TFT LCD component is an LG®/PHILIPS®, model number LB043WQ1.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the
user to develop graphical user interfaces for a wide variety of end applications.
Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing
so may damage both units and is not covered by warranty.
The back light voltage is generated from a TPS61161 boost converter. It is powered directly by the VIN
5 VCC power (the control for the back light voltages is separated from the main board voltages due to
the specific voltage requirements of the LCD panel).
4-20
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
LG PHILIPS
1
R123
10R
FB
CTRL
COMP
2
5
MN25 TPS61161DRVT
6
VIN
22uH
L23
20mA MAX 9 LEDs Back Light
VLED-
C202
1uF
D12
STPS0540Z
VLED+
4
SW
LB043W Q1
4.3" 480x272
TFT LCD DISPLAY
THP
Z7
GND
3
PIN 45
C203
220nF
(LCDCC)
R137
10K
C201
2.2uF
5V
PIN 1
Conductors
on
TOP SIDE
AT91SAM9M10-EKES User Guide
7
PE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
C210
220K
YpLCD
XmLCD
YmLCD
XpLCD
C208
DNP
This Resistor
is intentionally mounted
in place of C210
pin45
pin44
pin43
pin42
pin41
pin40
pin39
pin38
pin37
pin36
pin35
pin34
pin33
pin32
pin31
pin30
pin29
pin28
pin27
pin26
pin25
pin24
pin23
pin22
pin21
pin20
pin19
pin18
pin17
pin16
pin15
pin14
pin13
pin12
pin11
pin10
pin9
pin8
pin7
pin6
pin5
pin4
pin3
pin2
pin1
(pinxx = display pin number )
XF2M45151A
J24
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
RR48A
RR48B
RR48C
RR48D
RR49A
RR49B
RR49C
RR49D
RR50A
RR50B
RR50C
RR50D
RR51A
RR51B
RR51C
RR51D
RR52A
RR52B
RR52C
RR52D
RR53A
RR53B
RR53C
RR53D
C211
DNP
0R
(AD2Yp)
(AD1Xm)
(AD3Ym)
(AD0Xp)
C189
10uF
10V
C188
100nF
0R
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
R180
10K
R50 27R
3V3
R130
0R
R132
R133
0R
R131
C209
DNP
YpLCD
XpLCD
YmLCD
XmLCD
VLED+
VLED-
PD22
PD21
PD23
PD20
3V3
(LCDDEN)
{3,12}
{3,12}
{3,12}
{3,12}
R174
R173
R172
R176
R175
R179
R178
R177
(LCDPW R)
0R
0R
0R
0R
0R
0R
0R
0R
PE9
PE8
PE7
PE16
PE15
PE25
PE24
PE23
BLUE3
DNP
0R
DNP
0R
DNP
0R
DNP
0R
R147
R146
R145
R144
R184
R183
R182
R181
RED6
RED5
RED4
RED3
RED7
DNP
0R
R149
R148
DNP
0R
DNP
0R
DNP
0R
DNP
0R
R153
R152
R155
R154
R157
R156
R151
R150
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
DNP
0R
DNP
0R
R163
R162
BLUE4
R159
R158
DNP
0R
R165
R164
BLUE5
GREEN7
DNP
0R
R167
R166
BLUE6
DNP
0R
DNP
0R
R169
R168
R161
R160
DNP
0R
R171
R170
BLUE7
R136
4.7K
PE6
PE8
PE10
PE9
PE11
PE10
PE12
PE11
PE13
PE12
PE14
PE13
PE17
PE14
PE18
PE15
PE19
PE16
PE20
PE17
PE21
PE18
PE22
PE20
PE26
PE21
PE27
PE22
PE28
PE23
PE29
PE24
PE30
R48 33R
R48 is placed near processor
{12} LCDDOTCK
PE0
LCDDOTCK
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(LCDPW R)
(LCDCC)
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
PE[0..30] {3,12}
Board Description
Figure 4-17. TFT LCD
11029A–ATARM–11-Jan-10
4-21
Board Description
4.2.14
Push Buttons
The SAM9M10-EKES is equipped with two system push buttons, two user push buttons and one joystick. The push buttons consist of momentary push button switches mounted directly to the board. When
any switch is depressed, a low (zero) appears at the associated input pin.
System push buttons:
– Reset, perform system reset
– Wakeup, perform system wake up
User push button:
– Right click
– Left click
Joystick:
– One touch, 5-way switching,
– Normally open momentary contacts,
– Push down to select in any position.
Figure 4-18.
Push Buttons
3V3
VDDBU
R13
100K
R14
1K
BP1
NRST
NRST
BP2
WAKE UP
WAKE UP
BP4
RIGHT CLICK
C220
10nF
PB7
R142
100R
BP5
LEFT CLICK
C221
10nF
4.2.15
PB6
R143
100R
Expansion Slot
GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23
All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17
Touch screen signals and analog I/O are connected to J18
This allows the developer to extend the features of the board by adding external hardware components
or boards.
4-22
11029A–ATARM–11-Jan-10
AT91SAM9M10-EKES User Guide
Board Description
Figure 4-19. Expansion Slot
CONNECTOR EXTENTION FOR LARGE LCD
J23
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
PE4
PE5
PE6
PE0
(GPIO1)
PD14
3V3
TSM-120-01-L-DV
2
PE7
4
PE9
6
PE11
8
PE13
10
PE15
12
PE17
14
PE19
16
PE21
18
PE23
20
PE25
22
PE27
24
PE29
26
PE3
28
30
32
PE2
34
PE1
36
(GPIO2)
38
40
PD15
DNP
J18
(AD1Xm)
(AD3Ym)
PD21
PD23
PD25
PD27
PD19
R128
DNP
3V3
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
(AD0Xp)
(AD2Yp)
PD20
PD22
PD24
PD26
PD18
R129
DNP
5V
3V3
DNP
TSM-110-01-L-DV
IMAGE SENSOR CONNECTOR
3V3
C186
100nF
C187
10uF
10V
C184
100nF
J17
VDDISI
PD12
(CTRL1)
PA21
PB21
PB23
PB25
PB27
PB9
PB11
AT91SAM9M10-EKES User Guide
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13
4-23
11029A–ATARM–11-Jan-10
Section 5
Configuration
5.1
JTAG/ICE Configuration
Table 5-1. JTAG/ICE Configuration
Designation
5.2
Default Setting
Feature
R84
Not populated
Disables the ICE NTRST input
R85
Soldered
Enables the ICE RTCK return. R87 must be opened
R86
Soldered
Enables the ICE NRST input
R87
Not populated
Disables TCK <-> RTCK local loop
ETHERNET Configuration
RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R92 and solder R93, R98 to R104, R107.
Two types of jumpers are used on the SAM9M10-EKES board:
2-pin jumpers with two possible settings:
– Fitted: the circuit is closed, and
– Not fitted: the circuit is open
3-pin jumpers with two possible positions, for which settings are presented in the following tables.
AT91SAM9M10-EKES User Guide
5-1
11029A–ATARM–11-Jan-10
Configuration
5.3
Jumpers Configuration
Table 5-2. Jumpers Configuration
Designation
J1
(combined
jumper array)
Default
Setting
Feature
Closed
J1-1
1-2
VDDUTMII
3V3
Closed
J1-2
3-4
VDDUTIMC
1V
Closed
J1-3
5-6
VDDCORE
1V
Closed
J1-4
7-8
VDDPLLUTMI
1V
1-2
VDDIOP0
3V3
1-2
JP1
2-3
External power to VDDIOP0
1-2
VDDIOP1
2-3
External power to VDDIOP1
1-2
VDDIOP2
2-3
External power to VDDIOP2
JP1
JP2
1-2
JP3
1-2
JP4
Opened
JP5
1-2
JP6
1-2
JP7
1-2
3V3 nominal
3V3
JP2
3V3 nominal
3V3
JP3
3V3 nominal
Forces power on.
To use the software shutdown control, JP4 must be opened.
3V battery backup must be present and JP7 jumper set in position 1-2
1-2
VDDIOM0
1V8
2-3
External power to VDDIOM0
1-2
VDDIOM1
2-3
External power to VDDIOM1
1-2
VDDBU
Lithium 3V Battery
2-3
VDDBU
3.3V from regulator
JP5
1V8 nominal
1V8
JP6
1V8 nominal
JP7
JP8
Opened
BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected
to NCS0
JP9
Closed
Enables chip select access, Boot on the NCS0 (MN10 Flash)
JP10
Closed
Enables chip select access, Boot on the NCS3 (MN12 NAND Flash)
JP11
Test point
JP12
Closed
Enables chip select access, Boot on the SPIO_NPCS0 (Serial Data Flash MN14)
JP13
Opened
Set address A0 low (MN13 Serial EEPROM), enable Boot access.
JP14
JP14.1 = Line_Out_L
JP15
JP16
JP11.1: SO
JP11.3: SCK
JP11.2: SI
JP14.3 = Line_Out_R
Used to connect a Loudspeaker
Closed
5-2
11029A–ATARM–11-Jan-10
DISMDIX (MN22)
AT91SAM9M10-EKES User Guide
Configuration
5.4
Miscellaneous Configuration Items
N.P = not populated
P = populated
Table 5-3. Miscellaneous Configuration
Designation
Default
Setting
R20
N.P
R21
P
Connect TSADVREF to VDDANA (may be used for specific filtering)
R22
P
Connect GNDANA to GND (may be used for specific filtering)
R24
P
Force TST pin to GND (chip is set in non-test mode = normal operation mode)
R47
N.P
Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND
Flash device)
R55
N.P
Write protect serial Data Flash (mount a 0-ohm resistor to write-protect the serial
Flash device)
R58, R59
N.P
Clock selection Audio AC97 (see mapping table in Section 7.1 ”Schematics” )
R60
N.P
External clock Audio AC97 (mount a 0-ohm resistor to connect it)
R75, R77
N.P
Change bias from VREFOUT (see Section 7.1 ”Schematics” )
Feature
JTAGSEL
R69, R70
Voice filter components
R84,R85
R86,R87
Configuration” )
ICE interface reset and clocking schemes (see Section 5.1 ”JTAG/ICE
R92, R93,
R94, R95,
R98, R99
R100, R101
R102,R103
R104,R107
R112
Y6, R122,
R124
Ethernet interface, MII mode (see Section 5.2 ”ETHERNET Configuration” )
N.P
External 13 MHz oscillator (option) for the on-board video composite encoder
TP1
GND Test point
TP2
GND Test point
TP3
GND Test point
TP4
GND Test point
5.5
PIO Configuration
5.5.1
Peripheral Signals Multiplexing on I/O Lines
The AT91SAMM10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be
assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs
define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
AT91SAM9M10-EKES User Guide
5-3
11029A–ATARM–11-Jan-10
Configuration
5.5.2
Multiplexing on PIO Controller A (PIOA)
"R.Select" = connection selectable via an on-board resistor (default not populated)
Table 5-4. PIO Multiplexing Port A
I/O
Peripheral A
PA0
MCI0_CK
TCLK3
MMCI0 Clock
VDDIOP0
PA1
MCI0_CDA
TIOA3
MMCI0 Command
VDDIOP0
PA2
MCI0_DA0
TIOB3
MMCI0 Data0
VDDIOP0
PA3
MCI0_DA1
TCKL4
MMCI0 Data1
VDDIOP0
PA4
MCI0_DA2
TIOA4
MMCI0 Data2
VDDIOP0
PA5
MCI0_DA3
TIOB4
MMCI0 Data3
VDDIOP0
PA6
MCI0_DA4
ETX2
Ethernet MII
VDDIOP0
PA7
MCI0_DA5
ETX3
Ethernet MII
VDDIOP0
PA8
MCI0_DA6
ERX2
Ethernet MII
VDDIOP0
PA9
MCI0_DA7
ERX3
Ethernet MII
VDDIOP0
PA10
ETX0
Ethernet RMII Transmit data 0
VDDIOP0
PA11
ETX1
Ethernet RMII Transmit data 1
VDDIOP0
PA12
ERX0
Ethernet RMII Receive data 0
VDDIOP0
PA13
ERX1
Ethernet RMII Receive data 1
VDDIOP0
PA14
ETXEN
Ethernet RMII Transmit enable
VDDIOP0
PA15
ERXDV
Ethernet RMII Receive data valid
VDDIOP0
PA16
ERXER
Ethernet RMII Receive Error
VDDIOP0
PA17
ETXCK
Ethernet RMII Transmit Clock
VDDIOP0
PA18
EMDC
Ethernet RMII Manag.Data Clock
VDDIOP0
PA19
EMDIO
Ethernet RMII Manag.Data In/Out
VDDIOP0
PA20
TWD0
Two Wire Interface Data
VDDIOP0
PA21
TWCK0
Two Wire Interface Clock
VDDIOP0
PA22
MCI1_CDA
SCK3
MMCI1 Command
VDDIOP0
PA23
MCI1_DA0
RTS3
MMCI1 Data0
VDDIOP0
PA24
MCI1_DA1
CTS3
MMCI1 Data1
VDDIOP0
PA25
MCI1_DA2
PWM3
MMCI1 Data2
VDDIOP0
PA26
MCI1_DA3
TIOB2
MMCI1 Data3
VDDIOP0
PA27
MCI1_DA4
ETXER
R.Select
MMCI1 Data4
Ethernet MII
VDDIOP0
PA28
MCI1_DA5
ERXCK
R.Select
MMCI1 Data5
Ethernet MII
VDDIOP0
PA29
MCI1_DA6
ECRS
R.Select
MMCI1 Data6
Ethernet MII
VDDIOP0
PA30
MCI1_DA7
ECOL
R.Select
MMCI1 Data7
Ethernet MII
VDDIOP0
PA31
MCI1_CK
PCK0
5-4
11029A–ATARM–11-Jan-10
Peripheral B
Function and Comments
MMCI1_clock
Power
VDDIOP0
AT91SAM9M10-EKES User Guide
Configuration
5.5.3
Multiplexing on PIO Controller B (PIOB)
Table 5-5. PIO Multiplexing Port B
I/O
Peripheral A
Peripheral B
PB0
SPI0_MISO
SPI Slave Out AT45DB642
VDDIOP0
PB1
SPI0_MOSI
SPI Slave In AT45DB642
VDDIOP0
PB2
SPI0_SPCK
SPI Serial Clock AT45DB642
VDDIOP0
PB3
SPI0_NPCS0
SPI Chip Select AT45DB642
VDDIOP0
PB4
TXD1
USART1 Transmit Data
VDDIOP0
PB5
RXD1
USART1 Receive Data
VDDIOP0
PB6
TXD2
User Push Button Right click
VDDIOP0
PB7
RXD2
User Push Button Left click
VDDIOP0
PB8
TXD3
ISI_D8
Image Sensor Data 8
VDDIOP2
PB9
RXD3
ISI_D9
Image Sensor Data 9
VDDIOP2
PB10
TWD1
ISI_D10
Image Sensor Data 10
VDDIOP2
PB11
TWCK1
ISI_D11
Image Sensor Data 11
VDDIOP2
PB12
DRXD
DBGU Receive Data
VDDIOP0
PB13
DTXD
DBGU Transmit Data
VDDIOP0
PB14
SPI1_MISO
Joystick Left
VDDIOP0
PB15
SPI1_MOSI
CTS0
Joystick Right
VDDIOP0
PB16
SPI1_SPCK
SCK0
Joystick Up
VDDIOP0
PB17
SPI1_NPCS0
RTS0
Joystick Down
VDDIOP0
PB18
RXD0
SPI0_NPCS1
Joystick Push
VDDIOP0
PB19
TXD0
SPI0_NPCS2
UsbVbus
VDDIOP0
PB20
ISI_D0
Image Sensor Data 0
VDDIOP2
PB21
ISI_D1
Image Sensor Data 1
VDDIOP2
PB22
ISI_D2
Image Sensor Data 2
VDDIOP2
PB23
ISI_D3
Image Sensor Data 3
VDDIOP2
PB24
ISI_D4
Image Sensor Data 4
VDDIOP2
PB25
ISI_D5
Image Sensor Data 5
VDDIOP2
PB26
ISI_D6
Image Sensor Data 6
VDDIOP2
PB27
ISI_D7
Image Sensor Data 7
VDDIOP2
PB28
ISI_PCK
Image Sensor Data Clock
VDDIOP2
PB29
ISI_VSYNC
Image Sensor Vertical Synchro
VDDIOP2
PB30
ISI_HSYNC
Image Sensor Horizontal Synchro
VDDIOP2
PB31
ISI_MCK
Image Sensor Reference Clock
VDDIOP2
PCK1
AT91SAM9M10-EKES User Guide
Function and Comments
Power
5-5
11029A–ATARM–11-Jan-10
Configuration
5.5.4
Multiplexing on PIO Controller C (PIOC)
Table 5-6. PIO Multiplexing Port C
I/O
Peripheral A
Peripheral B
Function and Comments
Power
PC0
DQM2
VDDIOM1
PC1
DQM3
VDDIOM1
PC2
A19
Add19 Flash AT49SV322
VDDIOM1
PC3
A20
Add20 Flash AT49SV322
VDDIOM1
PC4
A21/NANDALE
ALE Flash AT49SV322
VDDIOM1
PC5
A22/NANDCLE
CLE Flash AT49SV322
VDDIOM1
PC6
A23
VDDIOM1
PC7
A24
VDDIOM1
PC8
CFCE1
PC9
CFCE2
RTS2
VDDIOM1
PC10
NCS4/CFCS0
TCLK2
VDDIOM1
PC11
NCS5/CFCS1
CTS2
VDDIOM1
PC12
A25/CFRNW
VDDIOM1
PC13
NCS2
VDDIOM1
PC14
NCS3/NANDCS
PC15
NWAIT
VDDIOM1
PC16
D16
VDDIOM1
PC17
D17
VDDIOM1
PC18
D18
VDDIOM1
PC19
D19
VDDIOM1
PC20
D20
VDDIOM1
PC21
D21
VDDIOM1
PC22
D22
VDDIOM1
PC23
D23
VDDIOM1
PC24
D24
VDDIOM1
PC25
D25
VDDIOM1
PC26
D26
VDDIOM1
PC27
D27
VDDIOM1
PC28
D28
VDDIOM1
PC29
D29
VDDIOM1
PC30
D30
VDDIOM1
PC31
D31
VDDIOM1
5-6
11029A–ATARM–11-Jan-10
Ready/Busy NAND Flash
Chip select NAND Flash
VDDIOM1
VDDIOM1
AT91SAM9M10-EKES User Guide
Configuration
5.5.5
Multiplexing on PIO Controller D (PIOD)
Table 5-7. PIO Multiplexing Port D
I/O
Peripheral A
Peripheral B
PD0
TK0
PWM3
PD1
Function and Comments
Power
Command LED2
VDDIOP0
TF0
Output ENA USB Host
VDDIOP0
PD2
TD0
Input FLGA USB Host
VDDIOP0
PD3
RD0
Output ENB USB Host
VDDIOP0
PD4
RK0
Input FLGB USB Host
VDDIOP0
PD5
RF0
Int. Ethernet 10/100 MDINTR
VDDIOP0
PD6
AC97RX
AC97 Receive Signal
VDDIOP0
PD7
AC97TX
TIOA5
AC97 Transmit Signal
VDDIOP0
PD8
AC97FS
TIOB5
AC97 Frame Sync Signal
VDDIOP0
PD9
AC97CK
TCLK5
AC97 Clock Signal
VDDIOP0
PD10
TD1
Card Detect MMCI0 MCI0_CD
VDDIOP0
PD11
RD1
Card Detect MMCI1 MCI1_CD
VDDIOP0
PD12
TK1
CTRL1 Image Sensor Interface
VDDIOP0
PD13
RK1
CTRL2 Image Sensor Interface
VDDIOP0
PD14
TF1
GPIO1 Large LCD (connector)
VDDIOP0
PD15
RF1
GPIO2 Large LCD (connector)
VDDIOP0
PD16
RTS1
USART1 Request to Send
VDDIOP0
PD17
CTS1
USART1 Clear To Send
VDDIOP0
PD18
SPI1_NPCS2
IRQ
VDDIOP0
PD19
SPI1_NPCS3
FIQ
VDDIOP0
PD20
TIOA0
TSAD0
Touch screen X_Right
VDDANA
PD21
TIOA1
TSAD1
Touch screen X_Left
VDDANA
PD22
TIOA2
TSAD2
Touch screen Y_Up
VDDANA
PD23
TCLK0
TSAD3
Touch screen Y_Down
VDDANA
PD24
SPI0_NPCS1
PWM0
GPAD4
General purpose A/D4
VDDANA
PD25
SPI0_NPCS2
PWM1
GPAD5
General purpose A/D5
VDDANA
PD26
PCK0
PWM2
GPAD6
General purpose A/D6
VDDIOP0
PD27
PCK1
SPI0_NPCS3
GPAD7
General purpose A/D7
VDDIOP0
PD28
TSADTRG
SPI1_NPCS1
USB Plug-ID IDUSB
VDDIOP0
PD29
TCLK1
SCK1
MCI1_WP
VDDIOP0
PD30
TIOB0
SCK2
Command Power Led
VDDIOP0
PD31
TIOB1
PWM1
Command LED1
VDDIOP0
PCK0
AT91SAM9M10-EKES User Guide
5-7
11029A–ATARM–11-Jan-10
Configuration
5.5.6
Multiplexing on PIO Controller E (PIOE)
Table 5-8. PIO Multiplexing Port E
I/O
Peripheral A
PE0
LCDPWR
PE1
Peripheral B
Power
LCD Panel Pow.Enab.Ctrl
VDDIOP1
LCDMOD
LCD Modulation Signal
VDDIOP1
PE2
LCDCC
LCD Contrast Control
VDDIOP1
PE3
LCDVSYNC
LCD Vertical Synch.
VDDIOP1
PE4
LCDHSYNC
LCD Horizontal Synch.
VDDIOP1
PE5
LCDDOTCK
LCD Dot Clock
VDDIOP1
PE6
LCDDEN
LCD Data Enable
VDDIOP1
PE7
LCDD0
LCDD2
LCD-Red0
VDDIOP1
PE8
LCDD1
LCDD3
LCD-Red1
VDDIOP1
PE9
LCDD2
LCDD4
LCD-Red2
VDDIOP1
PE10
LCDD3
LCDD5
LCD-Red3
VDDIOP1
PE11
LCDD4
LCDD6
LCD-Red4
VDDIOP1
PE12
LCDD5
LCDD7
LCD-Red5
VDDIOP1
PE13
LCDD6
LCDD10
LCD-Red6
VDDIOP1
PE14
LCDD7
LCDD11
LCD-Red7
VDDIOP1
PE15
LCDD8
LCDD12
LCD-Green0
VDDIOP1
PE16
LCDD9
LCDD13
LCD-Green1
VDDIOP1
PE17
LCDD10
LCDD14
LCD-Green2
VDDIOP1
PE18
LCDD11
LCDD15
LCD-Green3
VDDIOP1
PE19
LCDD12
LCDD18
LCD-Green4
VDDIOP1
PE20
LCDD13
LCDD19
LCD-Green5
VDDIOP1
PE21
LCDD14
LCDD20
LCD-Green6
VDDIOP1
PE22
LCDD15
LCDD21
LCD-Green7
VDDIOP1
PE23
LCDD16
LCDD22
LCD-Blue0
VDDIOP1
PE24
LCDD17
LCDD23
LCD-Blue1
VDDIOP1
PE25
LCDD18
LCD-Blue2
VDDIOP1
PE26
LCDD19
LCD-Blue3
VDDIOP1
PE27
LCDD20
LCD-Blue4
VDDIOP1
PE28
LCDD21
LCD-Blue5
VDDIOP1
PE29
LCDD22
LCD-Blue6
VDDIOP1
PE30
LCDD23
LCD-Blue7
VDDIOP1
PE31
PWM2
AC97 External Clock
VDDIOP1
5-8
11029A–ATARM–11-Jan-10
PCK0
Function and Comments
PCK1
AT91SAM9M10-EKES User Guide
Section 6
Connectors
6.1
Power Supply
The AT91SAMM10-EKES evaluation board can be powered from a DC 5V power supply via the external
power supply jack (J2) shown in Figure 10 1. The positive pole must be on J2 center pin.
Figure 6-1.
Power Supply Connector J2
Table 6-1. Power Supply Connector J2 Signal Description
6.2
Pin
Mnemonic
Signal description
1
Center
+5 VCC
2
Gnd
RS232 Connector with RTS/CTS Handshake Support
Connector J11 is the COM1 connector.
Figure 6-2.
AT91SAM9M10-EKES User Guide
RS232 COM1 Connector J11
6-1
11029A–ATARM–11-Jan-10
Connectors
Table 6-2. Serial COM1 Connector J11 Signal Descriptions
Pin
1, 4, 6, 9
6.3
Mnemonic
Signal description
NC
NO CONNECTION
2
TXD TRANSMITTED DATA
RS232 serial data output signal
3
RXD RECEIVED DATA
RS232 serial data input signal
5
GND
GROUND
7
RTS READY TO SEND
Active-positive RS232 input signal
8
CTS CLEAR TO SEND
Active-positive RS232 output signal
DBGU
Connector J10 is the DBGU connector.
Figure 6-3.
RS232 DBGU Connector J10
Table 6-3. RS232 DBGU Connector J10 Signal Descriptions
Pin
1, 4, 6, 7, 8, 9
6-2
11029A–ATARM–11-Jan-10
Mnemonic
Signal description
NC
NO CONNECTION
2
TXD TRANSMITTED DATA
RS232 serial data output signal
3
RXD RECEIVED DATA
RS232 serial data input signal
5
GND
GROUND
AT91SAM9M10-EKES User Guide
Connectors
6.4
Ethernet
Connector J15 is the RJ-45 Ethernet Connector.
Figure 6-4.
Ethernet RJ45 Connector J15
Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions
Pin
6.5
Mnemonic
Pin
Mnemonic
1
TxData+ DIFFERENTIAL OUTPUT PLUS
2
Txdata- DIFFERENTIAL OUTPUT MINUS
3
RxData+ DIFFERENTIAL INPUT PLUS
4
Shield
5
Shield
6
RxData- DIFFERENTIAL INPUT MINUS
7
Shield
8
Shield
USB Host
Connector J12 is the USB Host connector.
Figure 6-5.
USB Host type A connector J12
Table 6-5. USB Host Type A Connector J12 Signal Descriptions
Pin
Mnemonic
Signal description
1
Vbus
5v power
2
DM
Data minus
3
DP
Data plus
4
Gnd
Ground
5
Shield
Shield
AT91SAM9M10-EKES User Guide
6-3
11029A–ATARM–11-Jan-10
Connectors
6.6
USB Host/Device
Connector J14 is the USB Host/Device connector.
Figure 6-6.
USB Host/Device Micro AB connector J14
Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions
Pin
6.7
Mnemonic
Signal description
1
Vbus
5v power
2
DM
Data minus
3
DP
Data plus
4
ID
On the Go Identification
5
Gnd
Ground
JTAG Debugging Connector
Connector J13 is the JTAG/ICE connector.
A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable.
Figure 6-7.
6-4
11029A–ATARM–11-Jan-10
JTAG/ICE Connector J13
AT91SAM9M10-EKES User Guide
Connectors
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target
has power, to create the logic-level reference for the input
comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility
with other equipment. Connect to VDD or leave open in target
system.
3
nTRST TARGET RESET - Active-low output
signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin
is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
4
GND
Common ground
5
TDI TEST DATA INPUT - Serial data output line,
sampled on the rising edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
6
GND
Common ground
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on
the target. Typically connected to TMS on target CPU. Output signal
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
8
GND
Common ground
9
TCK TEST CLOCK - Output timing signal, for
synchronizing test logic and control register
access.
JTAG clock signal to target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
10
GND
Common ground
11
RTCK - Input Return test clock signal from the
target.
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can
be used to dynamically control the TCK rate. SAM-ICE supports
adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
12
GND
Common ground
13
TDO JTAG TEST DATA OUTPUT - Serial data
input from the target.
JTAG data output from target CPU. Typically connected to TDO on
target CPU.
14
GND
Common ground
15
nSRST RESET
Active-low reset signal. Target CPU reset signal
16
GND
Common ground
17
RFU
This pin is not connected in SAM-ICE.
18
GND
Common ground
19
RFU
This pin is not connected in SAM-ICE
20
GND
Common ground
AT91SAM9M10-EKES User Guide
6-5
11029A–ATARM–11-Jan-10
Connectors
6.8
SD/MMC- MCI0
Connector J6 is the SD/MMC connector.
Figure 6-8.
SD/MMC0 Connector J6
Table 6-8. SD/MMC0 Connector J6 Signal Descriptions
6-6
11029A–ATARM–11-Jan-10
Pin
Mnemonic
Pin
Mnemonic
1
RSV/DAT3
2
CDA
3
GND
4
VCC
5
CLK
6
GND
7
DAT0
8
DAT1
9
DAT2
10
Card Detect
11
GND
12
AT91SAM9M10-EKES User Guide
Connectors
6.9
SD/MMC- MCI1
Connector J5 is the SD/MMC connector.
Figure 6-9.
SD/MMC1 Connector J5
Table 6-9. SD/MMC1 Connector J5 Signal Descriptions
6.10
Pin
Mnemonic
Pin
Mnemonic
1
RSV/DAT3
2
CMD
3
GND
4
VCC
5
CLK
6
7
DAT0
8
DAT1
9
DAT2
10
DAT3
11
DAT4
12
DAT5
13
DAT6
14
DAT7
AC97
Connector J7 is the Headphone connector.
Connector J8 is the Line In connector.
Connector J9 is the Line In connector.
Connector JP15 is the Speaker Output connector
Figure 6-10. Audio Connector J7, J8, J9
Table 6-10. J7, J8, J9 Signal Description
Pin
Mnemonic
Central pin
Signal
AT91SAM9M10-EKES User Guide
6-7
11029A–ATARM–11-Jan-10
Connectors
Table 6-11. Speaker JP15 Signal Descriptions
6.11
Pin
Mnemonic
1
Speaker bridge output A
2
Speaker bridge output B
Image Sensor - ISI
Connector J17 is the ISI connector.
Figure 6-11. ISI Connector J17
Table 6-12. ISI Connector J17 Signal Descriptions
6-8
11029A–ATARM–11-Jan-10
Pin
Mnemonic
Pin
Mnemonic
1
VCC 3v3
2
Gnd
3
VCC 3v3
4
Gnd
5
Ctrl1
6
Ctrl2
7
SCL
8
SDA
9
Gnd
10
ISI_MCK
11
Gnd
12
ISI_VSYNC
13
Gnd
14
ISI_HSYNC
15
Gnd
16
ISI_PCK
17
Gnd
18
ISI_Data0
19
ISI_Data1
20
ISI_Data2
21
ISI_Data3
22
ISI_Data4
23
ISI_Data5
24
ISI_Data6
25
ISI_Data7
26
ISI_Data8
27
ISI_Data9
28
ISI_Data10
29
ISI_Data11
30
Gnd
AT91SAM9M10-EKES User Guide
Connectors
6.12
Video
Connector J20 is the Video connector
Figure 6-12. Video Connector J20
Table 6-13. Video Connector J20 Signal Description
Pin
Mnemonic
Signal description
1
Center
Composite video signal output
6.13
Display Devices
6.13.1
LG TFT LCD LG/PHILIPS
Connector J24 is the TFT-LCD connector.
Figure 6-13. TFT LCD Connector J24
Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
Pin
Mnemonic
Pin
Mnemonic
1
GND
2
GND
3
VDD 3V3
4
VDD 3V3
5
R0
6
R1
7
R2
8
R3
9
R4
10
R5
AT91SAM9M10-EKES User Guide
6-9
11029A–ATARM–11-Jan-10
Connectors
Table 6-14. LG TFT LCD Connector J24 Signal Descriptions
6.14
Pin
Mnemonic
Pin
Mnemonic
11
R6
12
R7
13
G0
14
G1
15
G2
16
G3
17
G4
18
G5
19
G6
20
G7
21
B0
14
B1
23
B2
16
B3
25
B4
18
B5
27
B6
20
B7
29
GND
30
DCLK
31
DISPON
32
NO CONNECT
33
NO CONNECT
34
LCDEN
35
VDD PWR SEL
36
GND
37
X1
38
Y1
39
X2
40
Y2
41
GND
42
VLED-
43
VLED+
44
NO CONNECT
45
NO CONNECT
Large LCD Extension
Connectors J23 and J18 are for an optional large LCD extension (not populated).
Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin
6-10
11029A–ATARM–11-Jan-10
Mnemonic
Pin
Mnemonic
1
PE8
RED Data Signal
2
PE7
RED Data Signal (LSB)
3
PE10
RED Data Signal
4
PE9
RED Data Signal
5
PE12
RED Data Signal
6
PE11
RED Data Signal
7
PE14
RED Data Signal (MSB)
8
PE13
RED Data Signal
9
PE16
GREEN Data Signal
10
PE15
GREEN Data Signal (LSB
11
PE18
GREEN Data Signal
12
PE17
GREEN Data Signal
13
PE20
GREEN Data Signal
14
PE19
GREEN Data Signal
15
PE22
GREEN Data Signal (MSB)
16
PE21
GREEN Data Signal
17
PE24
BLUE Data Signal
18
PE23
BLUE Data Signal (LSB)
19
PE26
BLUE Data Signal
20
PE25
BLUE Data Signal
21
PE28
BLUE Data Signal
22
PE27
BLUE Data Signal
23
PE30
BLUE Data Signal (MSB)
24
PE29
BLUE Data Signal
AT91SAM9M10-EKES User Guide
Connectors
Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin
Mnemonic
Pin
Mnemonic
25
PE4
LCDHSYNC
26
PE3
LCDVSYNC
27
PE5
LCDDOTCK
28
GND
(0V)
29
GND
(0V)
30
NC
31
PE6
LCDDEN
32
PE2
LCDCC
33
PE0
DISPON
34
PE1
LCDMOD
35
PD14
GPIO1
36
PD15
GPIO2
37
GND
(0V)
38
GND
(0V)
39
VCC
+3V3 power source
40
NC
Table 6-16. Connector J18 Signal Description for a Large LCD Extension
Pin
Mnemonic
Pin
Mnemonic
1
XM
AD1XM
2
XP
AD0XP
3
YM
AD3YM
4
YP
AD2YP
5
GND
(0V)
6
GND
(0V)
7
PD25
PD25
8
PD24
PD24
9
PD27
PD27
10
PD26
PD26
11
PD19
PD19
12
PD18
PD18
13
GND
(0V)
14
GND
(0V)
15
GND
(0V)
16
17
GND
(0V)
18
GND
(0V)
19
VCC
+3V3 power source
20
VCC
+3V3 power source
AT91SAM9M10-EKES User Guide
+5V
6-11
11029A–ATARM–11-Jan-10
Section 7
Schematics
7.1
Schematics
This section contains the following schematics:
Top Level view, block architecture of the design
Power Supply
SAM Processor
Bus impedance adaptor
Main memory
EBI memory
MCI & TWI
Audio AC97
Serial interfaces
Ethernet
LCD
Video interfaces and LCD extension
AT91SAM9M10-EKES User Guide
7-1
11029A–ATARM–11-Jan-10
7
6
4
3
2
1
3V3
POWER SUPPLY
1V8
POWER
USER'S
INTERFACE
D
5
EBI0
EB0 DRR2 INTERFACE
1V
DDR2
128MB
5V
8
EB0 DRR2 INTERFACE
PIO
D
Sheet 5
DBGU
COM1
EB1 DRR2 INTERFACE
HOST
ICE
INTERFACE
PIO A,...E
ATMEL
ARM9 Processor
SAM9M10 or SAM9G45
(LFBGA324)
RJ 45
EB1 NANDFASH INTERFACE
EB1 BUS INTERFACE
Sheet 9
10/100 FAST
ETHERNET
EB1 FASH INTERFACE
EB1 ADRESSE INTERFACE
FLASH
HOST
DEVICE
EBI1
EB1 DATA INTERFACE
PIO
C
DDR2
128MB
RES.ARRAYS
EBI0_EBI1 ADAPTER
NAND
FLASH
HE 10
USB
RS232
Sheet 2
Sheet 4
PIO
Sheet 6
LCD INTERFACE
CARD
READER
4.3"
480x272
TFT
RCA
B
MIC
PIO
Sheet 3
IN
ISI
SERIAL
EEPROM
AUDIO
B
CAMERA
INTERFACE
SERIAL
DATA
FLASH
OUT
HE 15
TOUCH SCREEN
MMC SD
SDIO
CARD
READER
PIO A,...E
MMC SD
SDIO
HE 14
Sheet 10
PIO
CONNECTOR
C
Sheet 8
TV
INTERFACE
Sheet 7
Sheet 11 12
PIOA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
A
PIO MUXING
USAGE
PIOA
MCI0_CK
MCI0_CDA
MCI0_DA0
MCI0_DA1
(MCI0_DA2)
(MCI0_DA3)
TXD2
TXD3
RXD2
RXD3
TXD0
TXD1
RXD0
RXD1
TX_EN
RX_DV
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
USAGE
RX_ER
TX_CLK
MDC
MDIO
TW DO
TW CK0
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4 / TX_ER
MCI1_DA5 / RX_CLK
MCI1_DA6 / CRS
MCI1_DA7 / COL
MCI1_CK
PIOB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
USAGE
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
TXD1
RXD1
BP5_LEFT
BP4_RIGHT
ISI_D8
ISI_D9
ISI_D10
ISI_D11
DRXD
DTXD
BP3_LEFT
BP3_RIGHT
PIOB
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
USAGE
PIOC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
BP3_UP
BP3_DOW N
BP3_PUSH
VBUS
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
USAGE
NOT USED
NOT USED
A19
A20
NANDALE / A21
NANDCLE
NOT USED
NOT USED
RDY/BSY
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NCS3
NOT USED
PIOC
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
USAGE
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PIOD
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
USER_LED_D6
ENA
FLGA
ENB
FLGB
MDINTR
AC97RX
AC97TX
AC97FS
AC97CK
MCI0_CD
(MCI1_CD)
CTRL1
CTRL2
GPIO1
GPIO2
PIOD
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
RTS1
CTS1
J18_12
J18_11
AD0Xp
AD1Xm
AD2Yp
AD3Ym
J18_8
J18_7
J18_10
J18_9
IDUSB
(MCI1_W P)
POW ER LED
USER_LED_D7
PIOE
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
LCDPW R
LCDMOD
LCDCC
VSYNC
HSYNC
LCDDOTCK
LCDDEN
R0
R1
R2
R3
R4
R5
R6
R7
G0
PIOE
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
EXT_CLK
E
D
C
B
A
NOTE
AT91SAM9M10-EKES
AT91SAM9G45-EKES
"DNP" means the component is not populated by default
REV
INIT EDIT
MODIF.
SCALE
A
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
TOP LEVEL
8
VER.
1
1
12
8
7
6
5
4
3
2
1
3V3
BOOST
VIN1
VIN2
SHDN
D1
1
10uH
3V3
2.2uH
150mA
C4
10uF
2
VDDUTMII
R1
1R
C3
100nF
L3
10uH
150mA
C6
2.2nF
C7
100nF
1
3
3
4
VDDIOP2 {3,12}
2
1V8
C13
2.2uF
D5
STPS2L30A
R1100D101C
MN3
1V VDDUTMIC
3
1
C12
10uF
OUT
2.2uH
VDDISI
J1-2
4
8
3V3
6
C15
2.2nF
L5
10uH
C1M
5
C17
1uF
3
7
150mA
R7
1R
TPS60500
FB
1
B
EN
MN4
R126
10K
PG
GND
VDDPLLUTMI
{3}
C20
100nF
R9
1R
7
C19
10pF
C18
2.2uF
8
VDDPLLA {3}
150mA
1V
C2P
VOUT
J1-4
L6
10uH
4
C1P C2M
VIN
{3}
C
C21
4.7uF
C16
1uF
{3,12}
VDDUTMIC
C14
2.2uF
Si1563EDH
R5
10K
VDDIOP1 {3}
3
JP3
2
L4 BAT20J
2
1
2
VDD
BOOST
D4
1
GND
NC1
NC2
NC3
14
5V
VC
7
10
15
5
12
FB
LT1765-1.8
13
2
SHDN
6
5
SW 1
SW 2
GND1
GND2
GND3
GND4
GND5
10K
11
VIN1
VIN2
SYNC
R4
{3} SHDN
C11
15pF
MN2
1
8
17
9
16
C
C10
2.2uF
6
3
4
2
5V
Q1
VDDIOP0 {3}
3
JP2
3
JP4
1
2
JP1
1
C9
180nF
D
VDDOSC {3}
R3
1R
C8
4.7uF
FORCE
POWER
ON
{3}
VDDANA {3}
C5
4.7uF
D3
STPS2L30A
VC
1
L1
2
L2 BAT20J
12
FB
LT1765-3.3
14
NC1
NC2
NC3
6
5
SW 1
SW 2
13
7
10
15
R2
100K
2.1 MM SOCKET
11
MN1
GND1
GND2
GND3
GND4
GND5
3
D
C2
2.2uF
D2
5V
3
4
SYNC
5V
1
2
1
8
17
9
16
J2
2
C1
180nF
J1-1
R6
68K
10
2
R8
220K
C23
100nF
C24
4.7uF
C22
22uF
1V
5
9
J1-3
B
6
VDDCORE
{3}
1V8
1
GREEN
R11
D7
PD31 {3}
GREEN
R12
470R
A
R13
100K
R14
1K
ADHESIVE FEET
BP1
NRST
PB15
PB16
WAKE UP
PD30 {3}
LEFT
PUSH
1
2
3
BP3
RIGHT CLICK
4 UP
5 RIGHT
6 DOWN
C215
C216
C217
10nF
10nF
10nF
R141
100R
C220
Z2
11.1
11.1
Z3
Z4
Z5
11.1
11.1
11.1
PB7 {3}
C219
10nF
10nF
LEFT CLICK
C221
10nF
{3} PB[14..18]
3V3
J3
1
3
JP7
C25
100nF
VDDBU
VDDBU {3}
A
R142
100R
GND TEST POINT
BP5
C218
VDDIOM1 {3}
WAKE UP {3}
10nF
JOYSTICK
PB17
2
POWER LED
Z1
BP4
PB14
PB18
1
NRST {3,7,8,9,10,12}
BP2
R15
470K
3
Q2
IRLML2402
VDDBU
470R
VDDIOM0 {3}
3
JP6
3V3
PD0 {3}
2
3V3
470R
2
R10
1
2
3V3
D6
D8
RED
3
JP5
USER INTERFACE
TP1
TP2
TP3
E
D
C
B
A
TP4
PB6 {3}
R143
100R
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
7
6
5
4
3
2
DATE
REV.
SHEET
E
POW ER SUPPLY
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
VER.
1
2
12
{4} EBI0_CAS
{4} EBI0_RAS
{4} EBI0_WE
{5,6} DDR_VREF
{4} EBI0_DQM0
{4} EBI0_DQM1
{4} EBI0_DQS0
{4} EBI0_DQS1
H14
H17
J17
H15
A16
G14
H16
G18
G15
EBI0_DDR_CKE
EBI0_DDR_CLK
EBI0_DDR_NCLK
EBI0_DDR_CS
EBI0_DDR_CAS
EBI0_DDR_RAS
EBI0_DDR_W E
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
EBI1_RAS
EBI1_CAS
EBI1_SDW E
EBI1_SDA10
EBI1_SDCKE
EBI1_SDCK
EBI1_NSDCK
EBI0_DDR_VREF
EBI1_NCS0
EBI1_NCS1/SDCS
EBI0_DDR_DQM0
EBI0_DDR_DQM1
EBI1_NRD/CFOE
EBI1_NW E/NW R0/CFW E
EBI1_NBS1/NW R1/CFIOR
EBI1_NBS3/NW R3/CFIOW
EBI0_DDR_DQS0
EBI0_DDR_DQS1
EBI1_NANDOE
EBI1_NANDW E
PC14
{6} PC14
EBI1_D[0..15]
{4}
EBI1_A[1..18]
{4}
PC0/DQM2
PC1/DQM3
PC2/A19
PC3/A20
PC4/A21/NANDALE
PC5/A22/NANDCLE
PC6/A23
PC7/A24
PC8/CFCE1
PC9/CFCE2/RTS2
PC10/NCS4/CFCS0/TCLK2
PC11/NCS5/CFCS1/CTS2
PC12/A25/CFRNW
PC13/NCS2
PC14/NCS3/NANDCS
PC15/NW AIT
PC16/D16
PC17/D17
PC18/D18
PC19/D19
PC20/D20
PC21/D21
PC22/D22
PC23/D23
PC24/D24
PC25/D25
PC26/D26
PC27/D27
PC28/D28
PC29/D29
PC30/D30
PC31/D31
R7
T7
L8
V6
M8
V7
N8
U7
P8
R8
U8
T8
V8
L9
U9
M9
N9
V9
R9
T9
D2
E1
F1
G2
F2
G1
H1
H2
P9
L10
T10
L11
PD0/TK0/PW M3
PD1/TF0
PD2/TD0
PD3/RD0
PD4/RK0
PD5/RF0
PD6/AC97RX
PD7/AC97TX/TIOA5
PD8/AC97FS/TIOB5
PD9/97CK/TCLK5
PD10/TD1
PD11/RD1
PD12/TK1/PCK0
PD13/RK1
PD14/TF1
PD15/RF1
PD16/RTS1
PD17/CTS1
PD18/SPI1_NPCS2/IRQ
PD19/SPI0_NPCS3/FIQ
PD20/TIOA0
PD21/TIOA1
PD22/TIOA2
PD23/TCLK0
PD24/SPI0_NPCS1/PW M0
PD25/SPI0_NPCS2/PW M1
PD26/PCK0/PW M2
PD27/PCK1/SPI0_NPCS3
PD28/TSADTRG/SPI1_NPCS1
PD29/TCLK1/SCK1
PD30/TIOB0/SCK2
PD31/TIOB1/PW M1
PD[0..31]
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
{2,7,8,9,10,11,12}
G4
F4
G5
F5
G7
H5
G3
H6
G6
H7
H8
G8
J5
H4
J3
J4
J2
J6
J7
J1
J8
K1
K4
K2
K5
K6
K3
K7
K8
L3
L2
L4
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
MN5E
PE0/LCDPW R/PCK0
PE1/LCDMOD
PE2/LCDCC
PE3/LCDVSYNC
PE4/LCDHSYNC
PE5/LCDDOTCK
PE6/LCDDEN
PE7/LCDD0/LCDD2
PE8/LCDD1/LCDD3
PE9/LCDD2/LCDD4
PE10/LCDD3/LCDD5
PE11/LCDD4/LCDD6
PE12/LCDD5/LCDD7
PE13/LCDD6/LCDD10
PE14/LCDD7/LCDD11
PE15/LCDD8/LCDD12
PE16/LCDD9/LCDD13
PE17/LCDD10/LCDD14
PE18/LCDD11/LCDD15
PE19/LCDD12/LCDD18
PE20/LCDD13/LCDD19
PE21/LCDD14/LCDD20
PE22/LCDD15/LCDD21
PE23/LCDD16/LCDD22
PE24/LCDD17/LCDD23
PE25/LCDD18
PE26/LCDD19
PE27/LCDD20
PE28/LCDD21
PE29/LCDD22
PE30/LCDD23
PE31/PW M2/PCK1
D
C
VDDBU {2}
R16 39R
R17 39R
{9} HDPA
{9} HDMA
R18 39R
TP6
EBI1_A0
R19 39R
TESTPOINT
{9} HDPB
{9} HDMB
C38
18pF
C41
15pF
C45
15pF
B11
D11
A11
E11
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
A12
C11
F12
B9
B12
EBI1_RAS {4}
EBI1_CAS {4}
EBI1_SDWE {4}
EBI1_SDA10 {4}
EBI1_SDCKE {4}
A13
A14
EBI1_SDCK {4}
EBI1_NSDCK {4}
A10
F10
EBI1_NCS0 {6}
EBI1_NCS1/SDCS
{4}
{4}
{4}
{4}
{9}
{9}
{9}
{9}
{9}
{9}
{2,7,8,9,10,12}
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
T17
R17
V15
V16
U15
U16
U11
U12
{2} VDDOSC
C34
18pF
T18
R18
C32
100nF
V12
Y1
12 MHz
V11
C1
Y2
32.768 kHz
VDDBU
R20
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
{2} SHDN
DNP
D1
E4
N10
R10
P10
U10
R11
V10
M10
F3
MN5H
HFSDPA
HFSDMA
HHSDPA
HHSDMA
EBI1_NRD/CFOE {6}
EBI1_NWE/NWR0/CFWE
D10
E10
EBI1_NANDOE {6}
EBI1_NANDWE {6}
VDDPLLUTMI
VDDUTMIC
DFSDP/HFSDPB
DFSDM/HFSDMB
GNDUTMI
VDDUTMII
DHSDP/HHSDPB
DHSDM/HHSDMB
VDDIOP0
VDDIOP0
VDDOSC
GNDOSC
VDDIOP1
XIN
VDDIOP2
VDDCORE
VDDCORE
VDDCORE
VDDCORE
XOUT
XIN32
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
XOUT32
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
JTAGSEL
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
SHDN
{4}
F11
C9
D9
A9
VDDBU
GNDBU
VDDPLLA
TSADVREF
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOP
GNDIOP
{4} EBI0_CS
J16
J18
H18
EBI0_DDR_BA0
EBI0_DDR_BA1
EBI1_A0
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_A16
EBI1_A17
EBI1_A18
PC8
{6} PC8
MN5D
TST
{4} EBI0_CKE
{4} EBI0_CLK
{4} EBI0_NCLK
G17
G16
F13
F14
F18
F15
E14
F17
F16
E17
E15
E16
D18
D17
C18
B18
A18
B17
C10
B10
C17
1
VDDANA
GNDANA
D4
D3
C26 100nF
V13
U18
C27 100nF
C28 100nF
VDDPLLUTMI
VDDUTMIC
U17
VDDUTMII
V17
{2}
{2}
{2}
C29 100nF
K9
K10
VDDIOP0 {2}
C30 100nF
C31 100nF
H3
VDDIOP1 {2}
C33 100nF
V14
C35 100nF
E18
G12
G13
H11
C36
C37
C39
C40
100nF
100nF
100nF
100nF
K13
L12
L13
M14
C42
C43
C44
C46
100nF
100nF
100nF
100nF
D16
F6
G10
G11
C47
C48
C49
C50
100nF
100nF
100nF
100nF
P11
VDDIOP2 {2,12}
VDDCORE
{2}
VDDIOM0 {2}
B
VDDIOM1 {2}
VDDPLLA {2}
C51 100nF
E2
0R R21
E3
VDDANA {2}
C52
C53
100nF 100nF
C2
G9
H9
J9
J10
C16
H12
H13
J12
J13
K11
K12
H10
J11
{4} EBI0_BA0
{4} EBI0_BA1
EBI1_NBS0/A0
EBI1_NBS2/NW R2/A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_BA0/A16
EBI1_BA1/A17
EBI1_A18
EBI0_DDR_A0
EBI0_DDR_A1
EBI0_DDR_A2
EBI0_DDR_A3
EBI0_DDR_A4
EBI0_DDR_A5
EBI0_DDR_A6
EBI0_DDR_A7
EBI0_DDR_A8
EBI0_DDR_A9
EBI0_DDR_A10
EBI0_DDR_A11
EBI0_DDR_A12
EBI0_DDR_A13
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
PC2
PC3
PC4
PC5
MN5C
VBG
B
EBI0_DDR_D0
EBI0_DDR_D1
EBI0_DDR_D2
EBI0_DDR_D3
EBI0_DDR_D4
EBI0_DDR_D5
EBI0_DDR_D6
EBI0_DDR_D7
EBI0_DDR_D8
EBI0_DDR_D9
EBI0_DDR_D10
EBI0_DDR_D11
EBI0_DDR_D12
EBI0_DDR_D13
EBI0_DDR_D14
EBI0_DDR_D15
A17
D15
C15
B16
B15
D14
C14
A15
B14
D13
C13
E13
B13
E12
D12
C12
{4,6} PC[2..5]
A8
E9
B8
C8
F9
A7
D8
A6
E8
C7
B6
B7
A5
D7
F8
C6
E7
B5
D6
F7
A4
C5
B4
E6
D5
A3
C4
A1
A2
B2
B3
B1
E5
M17
L14
M18
L15
L16
L18
L17
K14
K15
K16
K18
K17
J14
J15
{4} EBI0_A[0..13]
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
2
{8,11,12} PE[0..31]
BMS
C
MN5F
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
V18
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
MN5G
{4} EBI0_D[0..15]
T4
V2
V3
U4
R5
V4
T5
U5
T12
N11
U13
M11
P6
R6
M7
V5
T6
U6
N7
P7
P12
T15
R12
T16
N12
M12
U14
M13
N13
R13
T13
P13
WKUP
R16
R15
T14
P15
P16
P17
R14
P14
N15
N16
P18
N17
N18
N14
M15
M16
MN5B
PB0/SPI0_MISO
PB1/SPI0_MOSI
PB2/SPI0_SPCK
PB3/SPI0_NPCS0
PB4/TXD1
PB5/RXD1
PB6/TXD2
PB7/RXD2
PB8/TXD3/ISI_D8
PB9/RXD3/ISI_D9
PB10/TW D1/ISI_D10
PB11/TW CK1/ISI_D11
PB12/DRXD
PB13/DTXD
PB14/SPI1_MISO
PB15/SPI1_MOSI/CTS0
PB16/SPI1_SPCK/SCK0
PB17/SPI1_NPCS0/RTS0
PB18/RXD0/SPI0_NPCS1
PB19/TXD0/SPI0_NPCS2
PB20/ISI_D0
PB21/ISI_D1
PB22/ISI_D2
PB23/ISI_D3
PB24/ISI_D4
PB25/ISI_D5
PB26/ISI_D6
PB27/ISI_D7
PB28/ISI_D8
PB29/ISI_VSYNC
PB30/ISI_HSYNC
PB31/ISI_MCK/PCK1
C3
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
MN5A
PA0/MCI0_CK/TCLK3
PA1/MCI0_CDA/TIOA3
PA2/MCI0_DA0/TIOB3
PA3/MCI0_DA1/TCKL4
PA4/MCI0_DA2/TIOA4
PA5/MCI0_DA3/TIOB4
PA6/MCI0_DA4/ETX2
PA7/MCI0_DA5/ETX3
PA8/MCI0_DA6/ERX2
PA9/MCI0_DA7/ERX3
PA10/ETX0
PA11/ETX1
PA12/ERX0
PA13/ERX1
PA14/ETXEN
PA15/ERXDV
PA16/ERXER
PA17/ETXCK
PA18/EMDC
PA19/EMDIO
PA20/TW D0
PA21/TW CK0
PA22/MCI1_CDA/SCK3
PA23/MCI1_DA0/RTS3
PA24/MCI1_DA1/CTS3
PA25/MCI1_DA2/PW M3
PA26/MCI1_DA3/TIOB2
PA27/MCI1_DA4/ETXER
PA28/MCI1_DA5/ERXCK
PA29/MCI1_DA6/ECRS
PA30/MCI1_DA7/ECOL
PA31/MCI1_CK/PCK0
3
T11
L1
M1
L5
N1
L6
M2
M3
M4
L7
N2
M5
P1
N3
P2
M6
N4
N5
N6
R1
P3
R2
P4
T1
P5
R3
T2
T3
U1
U3
U2
R4
V1
4
{2,7,9,12}
1
D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
5
PB[0..31]
2
{7,10,12} PA[0..31]
6
1
7
2
8
{6}
R22
0R
{2} WAKE UP
3V3
R24
10K
A
A
6.8K
JP8
R23
BOOT MODE SELECT
Opened = Internal ROM BOOT
Closed = NCS0
10pF
SUP1
C54
R25
4.7K
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
DNP
SG-BGA-CA89405MF
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
7
6
5
4
3
2
DATE
REV.
SHEET
E
SAM9 chip
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
VER.
1
3
12
8
7
6
EBI Bus Impedance Adaptor
DDR_D[0..15]
D
EBI0
EBI0_D0
2 RR4B
7
DDR_D0
EBI0_D1
4 RR2D
5
DDR_D1
EBI0_D2
2 RR2B
7
DDR_D2
EBI0_D3
1 RR4A
8
DDR_D3
EBI0_D4
3 RR4C
6
DDR_D4
EBI0_D5
4 RR4D
5
DDR_D5
EBI0_D6
1 RR2A
8
DDR_D6
EBI0_D7
3 RR2C
6
DDR_D7
EBI0_D8
2 RR6B
7
DDR_D8
EBI0_D9
4 RR8D
5
DDR_D9
EBI0_D10
4 RR6D
5
DDR_D10
EBI0_D11
2 RR8B
7
DDR_D11
1 RR8A
8
DDR_D12
EBI0_D13
3 RR6C
6
DDR_D13
EBI0_D14
1 RR6A
8
DDR_D14
EBI0_D15
3 RR8C
6
DDR_D15
EBI0_D12
C
B
1 RR10A
8
DDR_A0
EBI0_A1
2 RR10B
7
DDR_A1
EBI0_A2
3 RR10C
6
DDR_A2
EBI0_A3
3 RR12C
6
DDR_A3
EBI0_A4
4 RR10D
5
DDR_A4
EBI0_A5
2 RR12B
7
DDR_A5
EBI0_A6
1 RR12A
8
DDR_A6
EBI0_A7
4 RR14D
5
DDR_A7
EBI0_A8
3 RR14C
6
DDR_A8
EBI0_A9
2 RR14B
7
DDR_A9
EBI0_A10
4 RR12D
5
DDR_A10
EBI0_A11
1 RR14A
8
DDR_A11
EBI0_A12
2 RR16B
7
DDR_A12
EBI0_A13
1 RR16A
8
DDR_A13
3 RR26C
6
4 RR26D
5
{3} EBI0_CLK
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
{3} EBI0_NCLK
{3} EBI0_BA0
{3} EBI0_BA1
{3} EBI0_W E
{3} EBI0_CS
{3} EBI0_RAS
{3} EBI0_CAS
{3} EBI0_DQM0
{3} EBI0_DQM1
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
{5}
EBI1_D1
1 RR1A
8
EBI1_DDR_D1
1 RR9A
8
EBI1_FLASH_D0
EBI1_D2
2 RR1B
7
EBI1_DDR_D2
2 RR9B
7
EBI1_NAND_FSH_D0
1 RR11A
8
EBI1_FLASH_D1
EBI1_D3
3 RR1C
6
EBI1_D4
2 RR3B
7
2 RR11B
7
EBI1_NAND_FSH_D1
EBI1_DDR_D4
EBI1_D5
1 RR3A
8
EBI1_DDR_D5
4 RR11D
5
EBI1_FLASH_D2
3 RR11C
6
EBI1_NAND_FSH_D2
3 RR9C
6
EBI1_FLASH_D3
EBI1_D6
4 RR3D
5
EBI1_DDR_D6
4 RR9D
5
EBI1_NAND_FSH_D3
EBI1_D7
3 RR3C
6
EBI1_DDR_D7
1 RR13A
8
EBI1_FLASH_D4
2 RR13B
7
EBI1_NAND_FSH_D4
EBI1_D8
3 RR5C
6
EBI1_DDR_D8
3 RR13C
6
EBI1_FLASH_D5
4 RR13D
5
EBI1_NAND_FSH_D5
1 RR17A
8
EBI1_FLASH_D6
2 RR17B
7
EBI1_NAND_FSH_D6
3 RR17C
6
EBI1_FLASH_D7
4 RR17D
5
EBI1_NAND_FSH_D7
4 RR19D
5
EBI1_FLASH_D8
3 RR19C
6
EBI1_NAND_FSH_D8
2 RR21B
7
EBI1_FLASH_D9
1 RR21A
8
EBI1_NAND_FSH_D9
3 RR25C
6
EBI1_FLASH_D10
4 RR25D
5
EBI1_NAND_FSH_D10
2 RR23B
7
1 RR23A
8
EBI1_NAND_FSH_D11
1 RR25A
8
EBI1_FLASH_D12
2 RR25B
7
EBI1_NAND_FSH_D12
3 RR23C
6
EBI1_FLASH_D13
4 RR23D
5
EBI1_NAND_FSH_D13
4 RR21D
5
EBI1_FLASH_D14
3 RR21C
6
EBI1_NAND_FSH_D14
EBI1_FLASH_D11
2 RR19B
7
EBI1_FLASH_D15
1 RR19A
8
EBI1_NAND_FSH_D15
R29 27R
{3} EBI1_SDCKE
EBI1_DDR_D9
EBI1_D10
2 RR5B
7
EBI1_DDR_D10
EBI1_D11
4 RR7D
5
EBI1_DDR_D11
EBI1_D12
1 RR5A
8
EBI1_DDR_D12
EBI1_D13
3 RR7C
6
EBI1_D14
2 RR7B
7
EBI1_DDR_D14
EBI1_D15
4 RR5D
5
EBI1_DDR_D15
1 RR31A
8
BA0_EBI1 {6}
DDR_BA1 {5}
3 RR31C
6
BA1_EBI1 {6}
3 RR16C
6
DDR_W E {5}
2 RR33B
7
CS_EBI1 {6}
2 RR26B
7
1 RR33A
8
W E_EBI1 {6}
4 RR29D
5
DDR_CAS {5}
{3} EBI1_CAS
1 RR29A
8
DDR_DQM0 {5}
{3} EBI1_DQM0
2 RR29B
7
DDR_DQM1 {5}
{3} EBI1_DQM1
DDR_DQS0 {5}
{3} EBI1_DQS0
DDR_DQS1 {5}
3 RR28C
6
EBI1_FLASH_A3
4 RR30D
5
EBI1_DDR_A4
1 RR15A
8
EBI1_FLASH_A4
2 RR18B
7
EBI1_DDR_A5
3 RR18C
6
EBI1_FLASH_A5
2 RR20B
7
EBI1_DDR_A6
1 RR20A
8
EBI1_FLASH_A6
1 RR22A
8
EBI1_DDR_A7
2 RR22B
7
EBI1_FLASH_A7
1 RR30A
8
EBI1_DDR_A8
4 RR28D
5
EBI1_FLASH_A8
4 RR24D
5
EBI1_DDR_A9
1 RR28A
8
EBI1_FLASH_A9
3 RR20C
6
EBI1_DDR_A10
4 RR20D
5
EBI1_FLASH_A10
1 RR27A
8
EBI1_DDR_A11
2 RR27B
7
SDA10
3 RR22C
6
EBI1_A12
4 RR22D
5
EBI1_FLASH_A12
EBI1_A13
4 RR27D
5
EBI1_DDR_A13
3 RR27C
6
EBI1_FLASH_A13
3 RR15C
6
EBI1_DDR_A14
2 RR24B
7
EBI1_FLASH_A14
4 RR15D
5
EBI1_DDR_A15
3 RR24C
6
EBI1_FLASH_A15
EBI1_A16
2 RR31B
7
EBI1_FLASH_A16
EBI1_A17
4 RR31D
5
EBI1_FLASH_A17
EBI1_A18
EBI1_A6
EBI1_A8
EBI1_A9
{6}
EBI1_A14
7
3 RR33C
6
CAS_EBI1 {6}
{3}
4 RR33D
5
DQM0_EBI1 {6}
{3,6} PC4
1 RR32A
8
DQM1_EBI1 {6}
R35 27R
EBI1_DDR_A3
EBI1_A5
2 RR15B
R34 27R
{3} EBI1_DQS1
{3} EBI1_SDA10
EBI1_DDR_D13
{3} EBI1_A[1..18]
{3} EBI1_RAS
7
EBI1_A15
EBI1_A17
DDR_RAS {5}
EBI1_FLASH_A2
2 RR28B
NCLK_EBI1 {6}
EBI1_A16
6
8
EBI1_A11
DDR_BA0 {5}
3 RR29C
EBI1_DDR_A2
1 RR18A
EBI1_A10
8
{3} EBI1_SDW E
EBI1_FLASH_A1
5
EBI1_A4
CAUTION
Pin assignemts at
PCB layout time
5
{3} EBI1_NCS1/SDCS
6
4 RR18D
EBI1_A3
RAS_EBI1 {6}
{3}
PC2
PC3
EBI1_FLASH_A[1..21]
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
7
EBI1_A7
EBI1_FLASH_D[0..15]
{6}
3 RR30C
EBI1_A2
CLK_EBI1 {6}
R31 27R
{3} EBI1_NSDCK
8
1 RR26A
DDR_CS {5}
{6}
2 RR30B
EBI1_A1
CKE_EBI1 {6}
R30 27R
{3} EBI1_SDCK
1 RR7A
1
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
EBI1_DDR_D3
EBI1_D9
4 RR16D
R33 27R
{3} EBI0_DQS1
EBI1_D9
DDR_NCLK
R32 27R
{3} EBI0_DQS0
{5}
EBI1_D8
DDR_CLK {5}
R28 27R
EBI1_DDR_D[0..15]
EBI1_DDR_D0
{5}
EBI1_D1
DDR_CKE {5}
R27 27R
5
2
EBI1_NAND_FSH_D[0..15]
EBI1_D15
R26 27R
{3} EBI0_CKE
A
EBI0_A0
4 RR1D
3
EBI1_D[0..15]
EBI1_D0
DDR_A[0..13]
{3} EBI0_A[0..13]
4
EBI1_D0
{3}
{3} EBI0_D[0..15]
5
EBI1
EBI1_DDR_A[2..15]
6
EBI1_FLASH_A11
B
1 RR24A
8
EBI1_FLASH_A18
(A19)
2 RR32B
7
EBI1_FLASH_A19
(A20)
3 RR32C
6
EBI1_FLASH_A20
(A21)
4 RR32D
5
EBI1_FLASH_A21
A
E
D
C
B
A
DQS0_EBI1 {6}
DQS1_EBI1 {6}
AT91SAM9M10-EKES
AT91SAM9G45-EKES
SDA10
5
4
{6}
EBI1_DDR_A12 (SDA10)
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
3
2
VER.
DATE
REV.
SHEET
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
D
C
RES.ARRAYS-EBI0_EBI1
8
{6}
1
4
12
8
D
7
6
5
4
3
2
1
{4} DDR_D[0..15]
D
{4} DDR_A[0..13]
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
C
{4} DDR_BA0
{4} DDR_BA1
BA0
BA1
MN6
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0
BA1
F9
{4} DDR_CKE
{4} DDR_CLK
{4} DDR_NCLK
{4} DDR_CS
{4} DDR_CAS
{4} DDR_RAS
{4} DDR_W E
CKE
F2
CK
NCK
E8
F8
CS
G8
CAS
RAS
G7
F7
NW E
F3
ODT
VDDL
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK
CK
CS
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
G1
L3
L7
B
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RFU1
RFU2
RFU3
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
B7
A8
B3
A2
DDR_DQS0 {4}
DDR_DQM0 {4}
1V8
A1
E9
H9
L1
C55
C57
C59
C61
E1
C63 100nF
A9
C1
C3
C7
C9
C65
C67
C69
C71
C73
E2
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
F9
100nF
100nF
100nF
100nF
100nF
DDR_VREF
A3
E3
J1
K9
G2
G3
BA0
BA1
100nF
100nF
100nF
100nF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
C75
100nF
CKE
F2
CK
NCK
E8
F8
CS
G8
CAS
RAS
G7
F7
NW E
F3
A7
B2
B8
D2
D8
G1
L3
L7
MN7
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
BA0
BA1
ODT
CKE
CK
CK
CS
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
RFU1
RFU2
RFU3
E7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
B7
A8
B3
A2
DDR_DQS1 {4}
C
DDR_DQM1 {4}
1V8
A1
E9
H9
L1
C56
C58
C60
C62
E1
C64 100nF
A9
C1
C3
C7
C9
C66
C68
C70
C72
C74
E2
A3
E3
J1
K9
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
DDR_VREF
C76
100nF
A7
B2
B8
D2
D8
B
E7
1V8
L7
10uH 150mA
R36
1R
C77
100nF
C78
4.7uF
R37
1.5K
DDR_VREF
C79
100nF
DDR_VREF
{3,6}
R38
1.5K
A
A
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
EBI0_DDR2
8
VER.
1
5
12
8
7
6
5
4
3
2
1
{4} EBI1_FLASH_D[0..15]
{4} EBI1_FLASH_A[1..21]
{4} EBI1_DDR_D[0..15]
{4} EBI1_DDR_A[2..15]
MN8
H8
EBI1_DDR_A2
H3
EBI1_DDR_A3
H7
EBI1_DDR_A4
J2
EBI1_DDR_A5
J8
EBI1_DDR_A6
J3
EBI1_DDR_A7
J7
EBI1_DDR_A8
K2
EBI1_DDR_A9
K8
EBI1_DDR_A10
K3
EBI1_DDR_A11
EBI1_DDR_A12 (SDA10) H2
K7
EBI1_DDR_A13
L2
EBI1_DDR_A14
L8
EBI1_DDR_A15
D
{4} BA0_EBI1
{4} BA1_EBI1
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0_EBI1
BA1_EBI1
BA0
BA1
F9
{4} CKE_EBI1
{4} CLK_EBI1
{4} NCLK_EBI1
F2
CLK_EBI1
NCLK_EBI1
E8
F8
CS_EBI1
{4} CS_EBI1
C
CKE_EBI1
{4} CAS_EBI1
{4} RAS_EBI1
{4} W E_EBI1
ODT
CKE
CK
CK
G8
(NCS1)
CAS_EBI1
RAS_EBI1
G7
F7
W E_EBI1
F3
CS
CAS
RAS
WE
G1
L3
L7
RFU1
RFU2
RFU3
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
B7
A8
B3
A2
DQS0_EBI1 {4}
DQM0_EBI1 {4}
1V8
A1
E9
H9
L1
C80
C82
C84
C86
E1
C88 100nF
A9
C1
C3
C7
C9
C90
C92
C94
C96
C98
E2
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
BA0_EBI1
BA1_EBI1
100nF
100nF
100nF
100nF
G2
G3
F9
100nF
100nF
100nF
100nF
100nF
VREF1
A3
E3
J1
K9
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
(SDA10) H2
K7
L2
L8
C101
100nF
CKE_EBI1
F2
CLK_EBI1
NCLK_EBI1
E8
F8
CS_EBI1
G8
CAS_EBI1
RAS_EBI1
G7
F7
W E_EBI1
F3
A7
B2
B8
D2
D8
G1
L3
L7
MN9
C8
C2
D7
D3
D1
D9
B1
B9
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
BA0
BA1
B7
A8
B3
A2
VDD
VDD
VDD
VDD
ODT
VDDL
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK
CK
CS
WE
E7
C81
C83
C85
C87
E1
C89 100nF
A9
C1
C3
C7
C9
C91
C93
C95
C97
C99
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
R39 100K
1V8
VREF1
{3} EBI1_NRD/CFOE
C102
100nF
E1
D1
C1
A1
B1
D2
C2
A2
B5
A5
C5
D5
B6
A6
C6
D6
E6
B2
C3
D4
D3
B4
A4
1V8
{3} EBI1_NW E/NW R0/CFW E
B3
F1
G1
MN10
A0
I/00
A1
I/O1
FLASH
A2
I/O2
A3
I/O3
AT49SV322DT
A4
I/O4
A5
I/O5
A6
I/O6
A7
I/O7
A8
I/O8
A9
I/O9
A10
I/O10
A11
I/O11
A12
I/O12
A13
I/O13
A14
I/O14
A15
I/O15
A16
A17
A18
RDY/ BUSY
A19
A20
NC1
NC
RESET
WE
E2
H2
E3
H3
H4
E4
H5
E5
F2
G2
F3
G3
F4
G5
F5
G6
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
JP9
D
A3
C4
F6
1V8
VCC
VPP
CE
OE
CBGA
GND
GND
G4
C100
100nF
H1
H6
DNP
A7
B2
B8
D2
D8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RFU1
RFU2
RFU3
DQM1_EBI1 {4}
1V8
A3
E3
J1
K9
VSS
VSS
VSS
VSS
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
DQS1_EBI1 {4}
A1
E9
H9
L1
E2
VREF
CAS
RAS
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
C
R40 470K
1V8
{3} EBI1_NCS0
E7
VSSDL
{3,5} DDR_VREF
VREF1
{4} EBI1_NAND_FSH_D[0..15]
{3} PC5
{3,4} PC4
{3} EBI1_NANDOE
{3} EBI1_NANDW E
{3} PC14
B
{3}
PC8
(NANDCLE)
(NANDALE)
(NCS3)
(RDY/BSY)
JP10
1V8
1V8
R42
R43
0R
0R
R46
R44
R45
470K
0R
1K
R41
470K
R47
DNP
A
RE
WE
CE
D5
C4
D4
C7
C6
RB
C8
WP
C3
G5
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
MN11
CLE
ALE NAND FLASH
RE MT29F2G08ABD
WE
CE
R/B
WP
LOCK
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
B
Optional 16bits DATA BUS
With AT29F2G16ABD Micron
L9
L10
M1
M2
M9
M10
1V8
VCC
VCC
VCC
VCC
D3
G4
H8
J6
C103
C104
C105
C106
100nF
100nF
100nF
100nF
A
VSS
VSS
VSS
VSS
VFBGA-63
MT29F2G08ABDHC:D
C5
F7
K3
K8
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
EBI1_MEMORY
8
VER.
1
6
12
8
7
6
5
4
3
2
1
3V3
3V3
(MCI0_CD)
{3} PD10
{3} PA[0..5]
68K
PA3
PA2
(MCI0_DA1)
(MCI0_DA0)
R186
R187
27R
27R
PA0
(MCI0_CK)
R188
27R
PA1
PA5
PA4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
R189
R190
R191
27R
27R
27R
C109100nF
3V3
8
7
6
5
4
3
2
1
9
J6
8
7
6
5
(MCI1_W P)
(MCI1_CD)
{3} PD29
{3} PD11
{3,10} PA[22..31]
12
11
10
RR36
10K
1
2
3
4
R52
10K
1
2
3
4
RR41
68K
1
2
3
4
R51
10K
RR35
68K
1
2
3
4
8
7
6
5
RR34
8
7
6
5
D
8
7
6
5
D
PA24
PA23
(MCI1_DA1)
(MCI1_DA0)
R192 27R
R193 27R
PA31
(MCI1_CK)
R194 27R
PA22
PA26
PA25
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
R195 27R
R196 27R
R197 27R
PA27
PA28
PA29
PA30
(MCI1_DA4)
(MCI1_DA5)
(MCI1_DA6)
(MCI1_DA7)
R198
R199
R200
R201
8
7
6
5
4
3
2
1
9
3V3
FPS009
C108
100nF
27R
27R
27R
27R
16
15
14
J5
13
12
11
10
7SDMM-B0-2211
C
C
SD/MMCPlus CARD INTERFACE - MCI1
SD/MMC CARD INTERFACE - MCI0
3V3
3V3
DNP
Test point
1
R54
10K
{3,12} PA21
{3,12} PA20
6
5
(TW CK0)
(TW DO)
3V3
C111
100nF
8
4
MN13
SCL
SDA
VCC
GND
A0
A1
A3
WP
1
2
3
JP11
JP13
{3}
{3}
{3}
{3}
PB0
PB1
PB2
PB3
{2,3,8,9,10,12}
7
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
2
B
R53
470K
3
JP12
8
1
2
4
3
NRST
3V3
B
MN14
SO
SI
SCK
CS
RESET
VCC
GND
WP
6
C110
100nF
7
5
AT45D321D
SERIAL DATAFLASH
AT24C512BN-SH25-B
SERIAL EEPROM
R55
DNP
W RITE PROTECT
NORMALLY OPEN
A
A
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
MCI & TW I
8
VER.
1
7
12
7
6
5
4
3
C112100uF 6V3
OUT
IN
OUT
IN
24.576 MHz
12.288 MHz
48.000 MHz
14.318 MHz
PRIMARY
SECONDARY
PRIMARY
PRIMARY
Local XTAL
Ext. BITCLK
Ext. BITCLK (Into XTAL-IN)
Ext. BITCLK (Into XTAL-IN)
D
RA
AVDD_AC97
{3} PD7
{3} PD9
{3} PD6
{3} PD8
{2,3,7,9,10,12} NRST
C119
1uF
C125
100nF
22pF
1
2
3
4
5
6
7
8
9
10
11
12
(AC97TX)
(AC97CK)
(AC97RX)
(AC97FS)
R61 22K
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET
NC1
C121
10uF
10V
AVDD_AC97
AD1981B
AVDD_AC97
LINE_OUT_R
LINE_OUT_L
AVDD4
AVSS4
AFILT4
AFILT3
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
36
35
34
33
32
31
30
29
28
27
26
25
JP14
1
C128
C129
C130
C131
JP15
270pF
270pF
270pF
270pF
2 Bypass
C132 100nF
C134
1uF
C135
100nF
1 Shutdown
R64
C137
1uF
R66
C140
100nF
4.7K
4.7K
7
C141
R69 100R
100nF
C143
10nF
L11
3.5 PHONEJACK STEREO
3 J8
5
742792093
742792093
C138
470pF
2
LINE-IN
C139
470pF
1
L14
742792093
R71
3.9K
R72
3.9K
3.5 PHONEJACK STEREO
3 J9
5
742792093
C147
470pF
2
MONO / STEREO
MICROPHONE INPUT
C148
470pF
1
WARNING
R75
DNP
R76
470R
R77
DNP
R78
470R
TO BIAS FROM VREFOUT
CHANGE R71 and R72 to 3k 5%
DO NOT INSTALL R76, R78, C150, C151
C150
10uF
10V
VREFOUT MUST BE PROGRAMMED TO 3.7V
USING VREFH BIT (REG 76h)
R74
0R
AVDD_AC97
OPTIONAL MIC BIASING FROM VREFOUT
VREFOUT
4
C149
470pF
AGND_AC97
AGND_AC97
4
B
L12
R70 100R
C142
10nF
L10
AGND_AC97
R73 0R
A
Vo2
GND
R68
4.7K
AVDD_AC97
100nF
DNP
8
Bias
SSM2211
OPTIONAL VOICE
FILTER COMPONENTS
C146
47uF
6V3
Av=1
VDD/2
SPEAKER OUTPUT
C
C133 100nF
C136
1uF
B
150mA
5
Vo1
3 +IN
R67
4.7K
L13
4
C127 100nF
AGND_AC97
10uH
C145
1
AGND_AC97
R65 2.2K
C144
10uF
10V
C115
470pF
VDD
-IN
4
3
VREFOUT
6 C126 100nF
MN16
DNP
AGND_AC97
R63 2.2K
5V
HEADPHONE
LINE-OUT
R62 22K
48
47
46
45
44
43
42
41
40
39
38
37
MN15
C122
10uF
10V
C114
470pF
13
14
15
16
17
18
19
20
21
22
23
24
C
3V3
SPDIF
EAPD
ID1
ID0
AVSS3
AVDD3
NC
HP_OUT_R
AVSS2
HP_OUT_L
AVDD2
MONO_OUT
22pF
Y3
24.576MHz
C123
C124
100nF
2
742792093
AGND_AC97
AGND_AC97
DNP
PHONE_IN
AUX_L
AUX_R
JS1
JS0
CD_L
CD_GND_REF
CD_ R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
C120
R60
3.5 PHONEJACK STEREO
3 J7
5
742792093
R57
1K
1
D
C118
10uF
10V
C116
100nF
R59 DNP
(EXT_CLK)
R56
1K
C117
100nF
R58 DNP
RB
PE31
L9
C113100uF 6V3
(see table)
{3}
L8
+
CLK FREQ
2
OUT
OUT
IN
IN
RB=1K CODEC ID
+
CLOCK SELECTION - PIN STRAPING TABLE
RA=1K
2
AGND_AC97
8
AGND_AC97
A
C151
10uF
10V
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
AGND_AC97
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
AUDIO AC97
8
VER.
1
8
12
6
3V3
MALE RIGHT ANGLE
J10
MN18
VCC
15
C160
100nF
6
V+
C1C2+
V-
C2-
14
T
7
T
13
R
1
3
4
8
R
4
3
3V3
C156
100nF
R80
100K
5
R79
100K
R82
100K
11
PB13 {3}
2
C152
100nF
3V3
C158
100nF
C159
100nF
R81
100K
PB12 {3}
R83
9
3
4
10
12
{3} PB5
1
3V3
MN17
11
{3} PD16
12
1
5
{3} PB4
10
10
11
C1+
GND
2
C155
100nF
1
6
2
7
3
8
4
9
5
D
16
C153
100nF
SERIAL DEBUG PORT
5
C1+
VCC
GND
C1C2+
V+
C2-
V-
16
15
RS232 COM PORT
C154
100nF
2
MALE RIGHT ANGLE
C157
100nF
1
6
2
7
3
8
4
9
5
C161
100nF
6
14
T
7
T
D
0R
13
R
9
{3} PD17
ADM3202ARNZ
11
7
10
8
8
R
J11
ADM3202ARNZ
C
C
J12
292303-1
C162
100nF
USB HOST INTERFACE
1
2
HDMA {3}
4
3
HDPA {3}
RR42
100K
6
5
6
7
8
5
3V3
5V
L15
8
BLM21PG221SN1x
C164
33 uF
16V
6
L16
B
5
BLM21PG221SN1x
C165
33 uF
16V
C166
10pF
IN
VBUS
DM
DP
ID
GND
ENA
FLGA
GNG
FLGB
OUTB
ENB
1
(ENA)
PD1 {3}
2
(FLGA)
PD2 {3}
3
(FLGB)
PD4 {3}
4
(ENB)
PD3 {3}
R86
R84
DNP
R85
0R
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST {3}
TDI {3}
TMS {3}
TCK {3}
RTCK {3}
TDO {3}
NRST {2,3,7,8,10,12}
R87
DNP
B
ICE INTERFACE
3V3
(VBUS)
PB19 {3}
R89
68K
R90
47K
ZX62-AB-5P
SHD
7
OUTA
3V3
1
3
5
7
9
11
13
15
17
19
SP2526A-2
R88 47K
1
2
3
4
5
(IDUSB)
6
HDMB {3}
HDPB {3}
PD28 {3}
USB HOST/DEVICE INTERFACE
J14
A
7
C163
100nF
MN20
J13
2
4
6
8
10
12
14
16
18
20
4
3
2
1
3V3
C167
100nF
A
E
D
C
B
A
Take note of layout directive
"High speed USB platform design.PDF"
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
7
6
5
4
3
2
DATE
REV.
SHEET
E
SERIAL INTERFACES
8
VER.
1
9
12
8
7
6
D
5
3
2
1
D
3V3
4
C168
100nF
C169
18pF
CFPS-39IB 50.0MHZ
4
R92
0R
{3}
{3}
{3}
{3}
{3}
PA7
PA6
PA11
PA10
PA14
{3}
{3}
{3}
{3}
PA9
PA8
PA13
PA12
{3,7} PA28
{3} PA15
{3,7} PA27
{3} PA16
{3,7} PA30
{3,7} PA29
{3} PA18
{3} PA19
{3}
PD5
(TX_CLK)
DNP
R94
0R
42
DNP
17
18
19
20
21
22
R98
R99
DNP
DNP
(RXD3)
(RXD2)
(RXD1)
(RXD0)
R100
R101
DNP
DNP
26
27
28
29
(RX_CLK)
(RX_DV)
R102
DNP
34
37
(TX_ER)
(RX_ER)
R103
DNP
16
38
(COL)
(CRS)
R104
R107
DNP
DNP
36
35
R95
(MDC)
(MDIO)
(MDINTR)
R108
1.5K
24
25
32
39
8
7
6
5
8
7
6
5
8
7
6
5
3V3
JP16
RR43
10K
B
RR44
10K
1
2
3
4
1
2
3
4
1
2
3
4
3V3
C179
100nF
41
C180
100nF
30
C181
100nF
23
15
33
44
RR45
10K
R112
{2,3,7,8,9,12}
C171
100nF
GND_ETH
2
25MHz
(TXD3)
(TXD2)
(TXD1)
(TXD0)
(TX_EN)
3V3
1
C170
18pF
3
10
0R
40
NRST
MN22
REF_CLK/XT2
XT1
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
TX+
TX-
RX+
RX-
COL/RMII
CRS/PHYAD4
AVDDR
AVDDR
8
3
AVDDT
AGND
AGND
AGND
DVDD
4
TX+
1
2 TD-
TX-
2
3 RD+
RX+
3
RX-
6
C
6 RD-
1
C172 100nF
2
C174 100nF
AVDDT
DM9161AEP
DISMDIX
BGRESG
9
47
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
RESET
N.C
C175
10uF
10V
C178 100nF
48
31
11
12
13
14
R185
AVDDT
L17
742792093
C176
10uF
10V
R105
49R9
1%
R106
49R9
1%
3V3
0R
C173
100nF
GND_ETH
R109
6.8K
1%
75
1nF
4
75
8
7
8
RJ45 ETHERNET CONNECTOR
3V3
RR46
10K
D9
D10
45
75
J00-0061NL
GND_ETH
GND_ETH
75
7 NC
5
C177
100nF
5
6
46
DVDD
PW RDW N
J15
1 TD+
7
5 CT
TX_ER/TXD4
RX_ER/RXD4/RPTR
DGND
DGND
DGND
R97
49R9
1%
AVDDT
RX_CLK/10BTSER
RX_DV/TESTMODE
DVDD
R96
49R9
1%
4 CT
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
MDC
MDIO
MDINTR
43
16
{3} PA17
R93
Y5
15
VDD
50 MHz
2 VSS
OUT 3
8
7
6
5
1 OE
10K
Y4
1
2
3
4
R91
C
4
D11
YELLOW
1K
1K
GREEN
1K
GREEN
R110
FULL DUPLEX
R111
SPEED 100
R113
LINK&ACT
B
3V3
C182
10uF
10V
R114
0R
R115
0R
GND_ETH
A
A
Take note of layout directive
"DM9161-LG-V11-011401S.PDF"
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
REV.
E
RMII ETHERNET
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
VER.
1
DATE
SHEET
10
12
8
7
6
5
4
3
2
1
(pinxx = display pin number )
3V3
J24
D
Z7
LG PHILIPS
4.3" 480x272
TFT LCD DISPLAY
Conductors
on
TOP SIDE
PIN 45
C
pin45
pin44
pin43
pin42
pin41
pin40
pin39
pin38
pin37
pin36
pin35
pin34
pin33
pin32
pin31
pin30
pin29
pin28
pin27
pin26
pin25
pin24
pin23
pin22
pin21
pin20
pin19
pin18
pin17
pin16
pin15
pin14
pin13
pin12
pin11
pin10
pin9
pin8
pin7
pin6
pin5
pin4
pin3
pin2
pin1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN 1
LB043W Q1
VLED+
VLEDYpLCD
XpLCD
YmLCD
XmLCD
D
R180
10K
(LCDDEN)
PE6
(LCDPW R)
PE0
LCDDOTCK
PE[0..30] {3,12}
R50 27R
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
RR48A
RR48B
RR48C
RR48D
RR49A
RR49B
RR49C
RR49D
RR50A
RR50B
RR50C
RR50D
RR51A
RR51B
RR51C
RR51D
RR52A
RR52B
RR52C
RR52D
RR53A
RR53B
RR53C
RR53D
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
C188
100nF
C189
10uF
10V
R136
4.7K
R179
R178
R177
0R
0R
0R
PE25
PE24
PE23
R176
R175
0R
0R
PE16
PE15
R174
R173
R172
0R
0R
0R
R48 is placed near processor
PE9
PE8
PE7
{12} LCDDOTCK
3V3
R48 33R
XF2M45151A
BLUE7
R171
R170
DNP
0R
PE24
PE30
BLUE6
R169
R168
DNP
0R
PE23
PE29
BLUE5
R167
R166
DNP
0R
PE22
PE28
BLUE4
R165
R164
DNP
0R
PE21
PE27
BLUE3
R163
R162
DNP
0R
PE20
PE26
GREEN7
R161
R160
DNP
0R
PE18
PE22
GREEN6
R159
R158
DNP
0R
PE17
PE21
GREEN5
R157
R156
DNP
0R
PE16
PE20
GREEN4
R155
R154
DNP
0R
PE15
PE19
GREEN3
R153
R152
DNP
0R
PE14
PE18
GREEN2
R151
R150
DNP
0R
PE13
PE17
RED7
R149
R148
DNP
0R
PE12
PE14
RED6
R147
R146
DNP
0R
PE11
PE13
RED5
R145
R144
DNP
0R
PE10
PE12
RED4
R184
R183
DNP
0R
PE9
PE11
RED3
R182
R181
DNP
0R
PE8
PE10
B
D12
STPS0540Z
VLED+
CTRL
3
R123
10R
FB
THP
1
GND
VLED-
MN25 TPS61161DRVT
6
VIN
COMP
5
C201
2.2uF
(LCDCC)
2
C203
220nF
7
SW
4
C202
1uF
5V
L23
22uH
C208
DNP
YpLCD
XmLCD
YmLCD
XpLCD
PE2
R137
10K
C210
220K
20mA MAX 9 LEDs Back Light
C209
DNP
R130
0R
R132
R133
0R
R131
(AD2Yp)
(AD1Xm)
(AD3Ym)
(AD0Xp)
0R
0R
PD22
PD21
PD23
PD20
{3,12}
{3,12}
{3,12}
{3,12}
C211
DNP
This Resistor
is intentionally mounted
in place of C210
A
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
C
(LCDCC)
(LCDPW R)
B
A
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
REV.
E
LCD & ISI & VIDEO INTERFACE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
VER.
1
DATE
SHEET
11
12
8
7
6
5
4
3
2
1
CONNECTOR EXTENTION FOR LARGE LCD
{3,11} PE[0..30]
3V3
MN23
R49 is placed near processor
PE5
R49 33R
39
40
41
20
PE6
R118 4.7K
21
22
23
NRST
24
DGND
AVDD_PLL
AGND_PLL
AVDD
AGND
AVDD_DAC
AGND_DAC
V
H
XCLK
DE
ISET
CVBS
DNP
Y6
1 OE
13 MHz
2 VSS
C/CVBS
RESET
34
R122
Y
SPD
SPC
NC
VDD 4
OUT 3
R124
SG-8002JC-13.0000M-PCB
DNP
1V8
38
16
L19
C190
100nF
XO
(TW DO)
(TW CK0)
3V3
B
VDDIO
DVDD
35
{2,3,7,8,9,10}
PE3
PE4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
R117 4.7K
3V3
{3,7} PA20
{3,7} PA21
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
P-OUT
C191
100nF
C192
10uF
10V
742792093
{11} LCDDOTCK
C193
10uF
10V
PE6
PE0
(GPIO1)
{3} PD14
3V3
18
4
C205
DNP
Y7
1
C207
10pF
D
PD15 {3}
DNP
32
L20
C194
100nF
31
J18
742792093
3V3
33
L21
C195
100nF
36
25
L22
C197
100nF
29
27
R119
26
R121
75R
{3}
{3}
{3}
PD25
PD27
PD19
C196
10uF
10V
R128
DNP
3V3
2
4
6
8
10
12
14
16
18
20
(AD0Xp)
(AD2Yp)
PD20 {3,11}
PD22 {3,11}
PD24 {3}
PD26 {3}
PD18 {3}
R129
DNP
5V
C
3V3
DNP
TSM-110-01-L-DV
742792093
3V3
33pF
1.2K 1%
28
742792093
1
3
5
7
9
11
13
15
17
19
C198
R116
30
(AD1Xm)
(AD3Ym)
{3,11} PD21
{3,11} PD23
L24
1.8uH
R120
75R
C199
100pF
3
C200
D13
270pF 1
J20
2
BAT54SLT1G
75R
37
Composite Video Output
CH7024B-DF-TR
TP5
IMAGE SENSOR CONNECTOR
R125
0R
DNP
TSM-120-01-L-DV
2
PE7
4
PE9
6
PE11
8
PE13
10
PE15
12
PE17
14
PE19
16
PE21
18
PE23
20
PE25
22
PE27
24
PE29
26
PE3
28
30
32
PE2
34
PE1
36
(GPIO2)
38
40
1
C
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
J23
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
PE4
L18
742792093
XI/FIN
D
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPW R)
3
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
3V3
B
3
2
13MHz
C186
100nF
C206
10pF
C187
10uF
10V
J17
{3} PB[8..11]
The frequency accuracy must be +-20ppm or higher.
PB8
PB9
PB10
PB11
(ISI_D8)
(ISI_D09)
(ISI_D10)
(ISI_D11)
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
(ISI_D0)
(ISI_D1)
(ISI_D2)
(ISI_D3)
(ISI_D4)
(ISI_D5)
(ISI_D6)
(ISI_D7)
(ISI_PCK)
(ISI_VSYNC)
(ISI_HSYNC)
(ISI_MCK)
{2,3} VDDISI
{3} PD12
(CTRL1)
PA21
{3} PB[20..31]
A
C184
100nF
PB21
PB23
PB25
PB27
PB9
PB11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13 {3}
A
E
D
C
B
A
AT91SAM9M10-EKES
AT91SAM9G45-EKES
REV
INIT EDIT
MODIF.
SCALE
LN
PP
PP
PP
PP
DES.
03-sep-09
22-jun-09
02-DEC-08
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
DATE
1/1
REV.
E
LCD & ISI & VIDEO INTERFACE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
VER.
1
DATE
SHEET
12
12
Section 8
Revision History
8.1
Revision History
Table 8-1.
Document
Comments
11029A
First issue.
AT91SAM9M10-EKES User Guide
Change Request
Ref.
8-1
11029A–ATARM–11-Jan-10
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11029A–ATARM–11-Jan-10