Implementation of DDR2 on AT91SAM9G45

Implementation of DDR2 on AT91SAM9G45
Devices
1. Scope
The AT91SAM9G45 microprocessor features:
• One multi-port DDR2 controller that supports 16-bit DDR2 or 16-bit LP-DDR
memories only
• One single-port DDR2 controller that supports 16-bit DDR2, 16-bit LP-DDR, 16- or
32-bit SDR or LP-SDR memories through the EBI
The purpose of this document is to help the developer in the design of a system utilizing DDR2. Each DDR2 controller is described separately.
AT91 ARM
Thumb-based
Microcontrollers
Application Note
6492A–ATARM–22-Sep-09
2. Multi-Port DDR2 Controller Overview
The DDR2 controller (DDR2C) extends the memory capabilities of a chip by providing the interface to an external 16-bit
DDR2 device. The page size supports ranges from 2048 to 16384, and a number of columns from 256 to 4096. It supports
byte (8-bit) and half-word (16-bit) accesses.
The DDR2 controller supports a read or write burst length of four locations thanks to the 4-port architecture. It keeps track
of the active row in each bank, thus maximizing the DDR2 performance, e.g., the application may be placed in one bank
and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same
bank (Open Bank Policy).
The DDR2 controller only supports a CAS latency of 3; it optimizes the read access according to the operating frequency.
Self-refresh, power down and deep power down mode features allow to minimize the consumption of SDRAM device.
The multi-port DDR2 controller I/Os are powered by VDDIOM0. For DDR2, VDDIOM0 is set to 1.8V nominal.
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Application Note
6492A–ATARM–22-Sep-09
Application Note
3. Multi-Port DDR2 Controller Signals Definition
The DDR2 controller is capable of managing 4-bank DDR2 devices. The signals generated by
the controller are defined below.
Table 3-1.
DDR2 Controller Signals
DDR_D0 - DDR_D15
Data Bus
I/O
VDDIOM0
Pulled-up input at reset
DDR_A0 - DDR_A13
Address Bus
Output
VDDIOM0
0 at reset
DDR_CLK - #DDR_CLK
DDR2 Differential Clock
Input
Output
VDDIOM0
DDR_CKE
DDR2 Clock Enable
Output
High
VDDIOM0
DDR_CS
DDR2 Chip Select
Output
Low
VDDIOM0
DDR_WE
DDR2 Write Enable
Output
Low
VDDIOM0
DDR_RAS - DDR_CAS
Row and Column Signal
Output
Low
VDDIOM0
DDR_DQM[0..1]
Write Data Mask
Output
VDDIOM0
DDR_DQS[0..1]
Data Strobe
Output
VDDIOM0
DDR_BA0 - DDR_BA1
Bank Select
Output
VDDIOM0
DDR_VREF
Reference Voltage
Input
VDDIOM0
Where:
DDR_D0 - DDR_D15 are DDR2 controller data lines, respectively bounded to
[DDR_D15:DDR_D0] on the microcontroller.
DDR_A0 - DDR_A13 are DDR2 controller address lines, respectively bounded to [A0:A13] on
the microcontroller.
DDR_CLK - #DDR_CLK are the differential clock signals that feed the DDR2 device. All other
signals take those two signals as a reference.
To reach the 133 MHz speed on these pins loaded with a 10 pF equivalent capacitor, a dedicated high speed pin is necessary; it cannot be multiplexed on a PIO line (lower frequency).
DDR_CKE acts as an inhibit signal to the DDR device. DDR_CKE remains high during valid
DDR2 access (Read, Write, Prech). This signal goes low when the device is in power down
mode or in self-refresh mode; a self-refresh command can be issued by the controller (refer to
the DDR2 controller self-refresh mode).
DDR_CS: When the Chip Select (DDR_CS) is low, the command input is valid. When it is high,
the commands are ignored but the operation continues.
DDR_RAS - DDR_CAS, DDR_WE: The Row Address Strobe (DDR_RAS) and the Column
Address Strobe (DDR_CAS) will assert to indicate that the corresponding address is present on
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6492A–ATARM–22-Sep-09
the bus. The conjunction with Write Enable (DDR_WE) and chip select (SDCS), at the rising
edge of the clock (DDR_CK) or the falling edge of the #clock (#DDR_CK), determines the DDR2
operation.
DDR_DQM[0..1]: Data is accessed in 8 or 16 bits by means of DDR_DQM[1..0], which are
respectively the highest to lowest mask bit for the DDR2 data on the bus.
DDR_DQS[0..1]: Data strobe. The data is sampled on DDR_DQS edges.
DDR_BA0 - DDR_BA1 select the bank to address when a command is input. Read/write or precharge is applied to the bank selected by DDR_BA0 and DDR_BA1.
DDR_VREF is used by the input buffers of the DDR2 memories as well as the DDR2 controller
to determine logic levels. VREF is specified to be ½ the power supply voltage and is created
using a voltage divider constructed from two 1K Ω, 1% tolerance resistors.
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Application Note
6492A–ATARM–22-Sep-09
Application Note
4. EBI DDR2 Controller Overview
The EBI embeds a single-port DDR2 controller (DDR2SDRC) that extends the memory capabilities of a chip by providing the interface to 16-bit DDR2, 16-bit LP-DDR, 16-bit or 32-bit SDR or
LD-SDR external devices. The page size supports ranges from 2048 to 16384, and a number of
columns from 256 to 4096. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The DDR2 controller supports a read or write burst length of one location. It keeps track of the
active row in each bank, thus maximizing DDR2 performance, e.g., the application may be
placed in one bank and data in the other banks. So as to optimize performance, it is advisable to
avoid accessing different rows in the same bank (Open Bank Policy).
The DDR2 controller supports a CAS latency of 3 for DDR2, and 2 or 3 for SDR. It permits to
optimize the read access according to the frequency.
Self-refresh, power down and deep power down mode features allow to minimize the consumption of the SDRAM device.
The DDR2 controller I/Os are powered by VDDIOM1. For DDR2, VDDIOM1 is to be set to 1.8V
nominal.
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6492A–ATARM–22-Sep-09
5. EBI DDR2 Controller Signals Definition
The DDR2 controller is capable of managing four-bank DDR2 devices. The signals generated by
the controller are defined below (refer to the EBI Section on the product Datasheet).
Table 5-1.
EBI Controller Signals
D0 - D31
Data Bus
I/O
VDDIOM1
Pulled-up input at reset
A0 - A25
Address Bus
Output
VDDIOM1
0 at reset
SDCK - #SDCK
DDR2/SDRAM Differential Clock
Output
VDDIOM1
SDCKE
DDR2/SDRAM Clock Enable
Output
High
VDDIOM1
SDCS
DDR2/SDRAM Controller Chip Select
Output
Low
VDDIOM1
BA0 - BA1
Bank Select
Output
SDWE
DDR2/SDRAM Write Enable
Output
Low
VDDIOM1
RAS - CAS
Row and Column Signal
Output
Low
VDDIOM1
SDA10
SDRAM Address 10 Line
Output
VDDIOM1
DQS[0..1]
Data Strobe
Output
VDDIOM1
DQM[0..3]
Write Data Mask
Output
VDDIOM1
VDDIOM1
Where:
D0 - D31 are DDR2 controller data lines, respectively bounded to [D31:D0] on the
microcontroller.
A0 - A12 are DDR/SDR controller address lines, respectively bounded to [A2:A14] of the microcontroller except for A10 (SDA10) which is not bounded to A12.
A[12:0] lines allow to address up to 11 columns and 13 rows. A[25:13] lines are not used.
SDCK - #SDCK are the Differential Clock signals that feed the DDR2 device. All other signals
take those two signals as a reference. All SDRAM input signals are sampled on the positive
edge of SDCK.
SDCKE acts as an inhibit signal to the SDRAM device. SDCKE remains high during a valid
SDRAM access (Read, Write, Prech). This signal goes low when the device is in power down
mode or in self-refresh mode; a self-refresh command can be issued by the controller (refer to
the SDRAM controller self-refresh mode).
SDCS: When the chip select SDCS is low, the command input is valid. When it is high, the commands are ignored but the operation continues.
BA0 - BA1 selects the bank to address when a command is input. Read/write or precharge is
applied to the bank selected by BA0 and BA1.
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Application Note
6492A–ATARM–22-Sep-09
Application Note
RAS - CAS, SDWE: The row address strobe (RAS), column address strobe (CAS) will assert to
indicate that the corresponding address is present on the bus. The conjunction with write Enable
(SDWE) and chip select (SDCS) at the rising edge of the clock (SDCK) determines the SDRAM
operation.
SDA10 acts as a DDR/SDR address line but is also used as the auto-precharge command bit.
An AT91 product outputs a dedicated SDA10 signal.
DQS[0..1]: Data strobe. The data is sampled on DDR_DQS edges.
DQM[0..3]: Data is accessed in 8 or 16 bit by means of DDR_DQM[1:0] which are respectively
the highest to lowest mask bit for the DDR2 data on the bus. DQM[3:2] are used in case of an
SDR implementation.
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6492A–ATARM–22-Sep-09
6. DDR2 Connexion on AT91SAM9 Multi-Port Controller
The AT91SAM9G45 microprocessor supports 16-bit DDR2 devices on DDR/LPDDR Chip Select
area (0x70000000 memory zone). The user interface to configure the DDR2 controller is
mapped at address 0xFFFF E600.
Each DDR2 device must use sufficient decoupling to provide an efficient filtering on the power
supply rails.
6.1
6.1.1
16-bit Using 2 x 8-bit DDR2 Implementation
Hardware Configuration
DDR_D[0..15]
DDR_A[0..13]
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_CKE
DDR_CLK
DDR_NCLK
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
BA0
BA1
MN5
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8B6-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0
BA1
F9
ODT
CKE
F2
CKE
CK
NCK
E8
F8
CK
CK
CS
G8
CS
CAS
RAS
G7
F7
CAS
RAS
NWE
F3
G1
L3
L7
6.1.2
8
WE
RFU
RFU
RFU
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
B7
A8
DDR_DQS0
B3
A2
DDR_DQM0
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
1V8
A1
E9
H9
L1
C49
C51
C53
C55
VDDL
E1
C57 100NF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A9
C1
C3
C7
C9
C59
C61
C63
C65
C67
VDD
VDD
VDD
VDD
VREF
E2
VSS
VSS
VSS
VSS
A3
E3
J1
K9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
VSSDL
E7
VREF
C69
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
BA0
BA1
MN6
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8B6-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0
BA1
F9
ODT
CKE
F2
CKE
CK
NCK
E8
F8
CK
CK
CS
G8
CS
CAS
RAS
G7
F7
CAS
RAS
NWE
F3
WE
G1
L3
L7
RFU
RFU
RFU
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
B7
A8
B3
A2
DDR_DQS1
DDR_DQM1
1V8
A1
E9
H9
L1
C50
C52
C54
C56
VDDL
E1
C58 100NF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A9
C1
C3
C7
C9
C60
C62
C64
C66
C68
VDD
VDD
VDD
VDD
VREF
E2
VSS
VSS
VSS
VSS
A3
E3
J1
K9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
VSSDL
E7
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
100NF
VREF
C70
100NF
Software Configuration
The DDR2 initialization sequence is described in Section 11.1 “DDR2-SDRAM Initialization” on
page 13.
Application Note
6492A–ATARM–22-Sep-09
Application Note
7. DDR2 Connexion on AT91SAM9 EBI Controller
The AT91SAM9G45 microcontroller supports 16-bit DDR2 devices on one Chip Select area
(NCS1). The user interface to configure the DDR2 controller is mapped at
address 0xFFFF E400.
The 32-bit interface can be achieved by a single 32-bit SDRAM device or two 16-bit SDRAM
devices.
Each DDR2 device must use sufficient decoupling to provide an efficient filtering on the power
supply rails.
7.1
7.1.1
16-bit Using 2 x 8-bit DDR2 Implementation
Hardware Configuration
EBI1_DDR_D[0..15]
EBI1_DDR_A[2..15]
MN8
EBI1_DDR_A2
H8
EBI1_DDR_A3
H3
EBI1_DDR_A4
H7
EBI1_DDR_A5
J2
EBI1_DDR_A6
J8
EBI1_DDR_A7
J3
EBI1_DDR_A8
J7
EBI1_DDR_A9
K2
EBI1_DDR_A10
K8
EBI1_DDR_A11
K3
EBI1_DDR_A12 (SDA10) H2
EBI1_DDR_A13
K7
EBI1_DDR_A14
L2
EBI1_DDR_A15
L8
BA0_EBI1
BA1_EBI1
CKE_EBI1
CLK_EBI1
NCLK_EBI1
NCS1
CS_EBI1
CAS_EBI1
RAS_EBI1
WE_EBI1
BA0_EBI1
BA1_EBI1
G2
G3
BA0
BA1
F9
ODT
CKE_EBI1
F2
CKE
CLK_EBI1
NCLK_EBI1
E8
F8
CK
CK
CS_EBI1
G8
CS
CAS_EBI1
RAS_EBI1
G7
F7
CAS
RAS
WE_EBI1
F3
G1
L3
L7
7.1.2
MN9
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
WE
RFU1
RFU2
RFU3
C8
C2
D7
D3
D1
D9
B1
B9
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
B7
A8
DQS0_EBI1
B3
A2
DQM0_EBI1
1V8
VDD
VDD
VDD
VDD
A1
E9
H9
L1
C80
C82
C84
C86
VDDL
E1
C88 100nF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A9
C1
C3
C7
C9
C90
C92
C94
C96
C98
VREF
E2
VSS
VSS
VSS
VSS
A3
E3
J1
K9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
VSSDL
E7
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
VREF1
C101
100nF
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
(SDA10) H2
K7
L2
L8
BA0_EBI1
BA1_EBI1
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0
BA1
F9
ODT
CKE_EBI1
F2
CKE
CLK_EBI1
NCLK_EBI1
E8
F8
CK
CK
CS_EBI1
G8
CS
CAS_EBI1
RAS_EBI1
G7
F7
CAS
RAS
WE_EBI1
F3
WE
G1
L3
L7
RFU1
RFU2
RFU3
C8
C2
D7
D3
D1
D9
B1
B9
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
B7
A8
B3
A2
DQS1_EBI1
DQM1_EBI1
1V8
VDD
VDD
VDD
VDD
A1
E9
H9
L1
C81
C83
C85
C87
100nF
100nF
100nF
100nF
VDDL
E1
C89 100nF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A9
C1
C3
C7
C9
C91
C93
C95
C97
C99
VREF
E2
VSS
VSS
VSS
VSS
A3
E3
J1
K9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A7
B2
B8
D2
D8
VSSDL
E7
100nF
100nF
100nF
100nF
100nF
VREF1
C102
100nF
Software Configuration
The following configuration has to be performed:
• Assign the EBI CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip
Select Assignment Register located in the bus matrix memory space
• Initialize the DDR2 controller accordingly to the DDR2 device and the system bus frequency.
The Data Bus Width is to be programmed to 16 bits.
The DDR2 initialization sequence is described in Section 11.1 “DDR2-SDRAM Initialization” on
page 13.
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6492A–ATARM–22-Sep-09
8. DDR2 Signal Routing Considerations
The critical high speed signal is associated with the DDR2. The following are general guidelines
for designing a DDR2 interface with AT91SAM9 products with a targeted speed of 133 MHz on
SDCK/#SDCK:
• At first, position the DDR2 devices as close to the processor as possible. A longer trace will
increase the rise time and the fall time of the signals. The setup time of signals generated by
the AT91 Microcontroller will decrease with an increased trace length.
• Keep the DDR2 clocks and control lines as short as possible.
• Keep the DDR2 address and data lines as short as possible.
• For a proper DDR2 operation at 133 MHz, a bus impedance adaptation is necessary. 10 to
30 Ohms series resistors can be placed on all the switching signals to limit the current flow
into each outputs The resistor is to be located near the processor. The need for series
termination resistors and their specific value on the signals are better determined by
simulation, using IBIS models and the specific design PCB layout. On SAM9G45-EKES and
SAM9M10G45-EK, the adaptation is achieved with a 27-Ohm serial resistor.
• To support maximum speeds, reasonable DDR2 loading constraints must be followed. For
high-speed operation, the maximum load cannot exceed 30 pF on address and data buses,
and 10 pF on SDCK and #SDCK. The user must consider all the devices connected on the
different buses to calculate the system load.
• Use sufficient decoupling scheme for memory devices. It is recommended to use low ESR
0.01 µF and 0.1 µF decoupling capacitors in parallel. An additional 0.001 µF decoupling
capacitor is recommended to minimize ground bounce and to filter high frequency noise.
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Application Note
6492A–ATARM–22-Sep-09
Application Note
9. DDR2 Electromagnetic Compatibility Improvement
9.1
Simultaneous Switching
Simultaneous switching is the worst enemy of EMI at device operation level. The
AT91SAM9G45 microprocessor embeds Delay Controller on High Speed signals.
These delays are applied to address A[15:0] and Data D[15:0]. They are controlled in dedicated
registers in DDR2 controller, PIO controller and Static Memory controller respectively for DDR2
signal, High Speed MCI and EBI signals. Refer to the Product Datasheet for more details.
9.2
Over-Shoots
Over-shoots occur when the current driven is too high. The AT91SAM9G45 microprocessor
embeds drive control on memory signals. Refer to the Product Datasheet for more details.
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6492A–ATARM–22-Sep-09
10. DDR2 VREF Signal Considerations
DDR_VREF is used by the input buffers of the DDR2 memories and the DDR2 controller to
determine logic levels. VREF is specified to be 0.9V (½ the power supply voltage) and is created
using a voltage divider constructed from two 1.5 kOhm, 1% tolerance resistors.
DDR_VREF is not a high current supply, but it is important to keep it as quiet as possible with
minimal inductance.
1V8
L7
10uH 150mA
R36
1R
C77
100nF
R37
1.5K
C79
100nF
R38
1.5K
DDR_VREF
C78
4.7uF
12
DDR_VREF
Application Note
6492A–ATARM–22-Sep-09
Application Note
11. DDR2 Controller Configuration
11.1
DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized
by the following sequence:
(For a register description, see DDR2-SDRAM Initialization section on the AT91SAM9G45
Datasheet)
(For an example of initialization, see the “Appendix” )
1. Program the memory device type into the Memory Device Register.
2. Program the DDR2-SDRAM device features into the Timing Register (asynchronous
timing (TRC, TRAS, etc.)), and into the Configuration Register (number of columns,
rows, banks, CAS latency and output drive strength).
3. A NOP command is issued to the DDR2-SDRAM. Program the NOP command into the
Mode Register. The application must set Mode to 1 in the Mode Register and perform a
write access to any DDR2-SDRAM address to acknowledge this command. Now clocks
which drive DDR2-SDRAM device are enabled.
A minimum pause of 200 µs is provided to precede any signal toggle.
4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
the Mode Register. The application must set Mode to 1 in the Mode Register and perform a write access to any DDR2-SDRAM address to acknowledge this command. Now
CKE is driven high.
5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
precharge command into the Mode Register. The application must set Mode to 2 in the
Mode Register and perform a write access to any DDR2-SDRAM address to acknowledge this command.
6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high temperature operations. The application must set Mode to 5 in the Mode
Register and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
For example, with a 16-bit 128-MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank
address, the DDR2-SDRAM write access should be done at address 0x20800000*.
* This address is for example purposes only. The real address depends on the implementation in
the product.
7. An Extended Mode Register set (EMRS3) cycle is issued to set all registers to “0”. The
application must set Mode to 5 in the Mode Register and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so
that BA[1] is set to 1 and BA[0] is set to 1. For example, with a 16-bit 128-MB DDR2SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at address 0x20C00000.
8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The application must set Mode to 5 in the Mode Register and perform a write access to the DDR2SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] and BA[0] are set to 0. For example, with a 16-bit 128-MB DDR2-SDRAM (12
rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be
done at address 0x20800000 or 0x20400000.
An additional 200 cycles of clock are required for locking DLL.
9. Program DLL field into the Configuration Register to high (Enable DLL reset).
13
6492A–ATARM–22-Sep-09
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
Mode to 3 in the Mode Register and perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that BA[1:0] bits are
set to 0. For example, with a 16-bit 128-MB DDR2-SDRAM (12 rows, 9 columns, 4
banks) bank address, the SDRAM write access should be done at address
0x20000000.
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
precharge command into the Mode Register. The application must set Mode to 2 in the
Mode Register and perform a write access to any DDR2-SDRAM address to acknowledge this command.
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register. The application must set Mode to 4 in the Mode Register
and perform a write access to any DDR2-SDRAM location twice, to acknowledge these
commands.
13. Program DLL field into the Configuration Register to low (Disable DLL reset).
14. A Mode Register Set (MRS) cycle is issued to program the parameters of the DDR2SDRAM devices, in particular CAS latency, burst length, and to disable DLL reset. The
application must set Mode to 3 in the Mode Register and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so
that BA[1:0] are set to 0. For example, with a 16-bit 128-MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at address
0x20000000.
15. Program OCD field into the Configuration Register to high (OCD calibration default).
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The
application must set Mode to 5 in the Mode Register and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so
that BA[1] is set to 0 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at address 0x20400000.
17. Program OCD field into the Configuration Register to low (OCD calibration mode exit).
18. An Extended Mode Register Set (EMRS1) cycle is issued to enable OCD exit. The
application must set Mode to 5 in the Mode Register and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so
that BA[1] is set to 1and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at address or 0x20400000.
19. A Normal mode command is provided. Program the Normal mode into Mode Register.
Perform a write access to any DDR2-SDRAM address to acknowledge this command.
20. Perform a write access to any DDR2-SDRAM address.
21. Write the refresh rate into the count field in the Refresh Timer register (see page 32).
(Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a
refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh count will be
either (15.625 /100 MHz) = 1562, i.e. 0x061A, or (7.81 /100 MHz) = 781, i.e. 0x030d.
After initialization, the DDR2-SDRAM devices are fully functional.
11.2
Micron MT47H64M8
The Micron MT47H64M8 are 64 MB devices arranged as 16 Mbit x 8 x 4 banks with a CAS
latency of 3 at 133 MHz. These devices are featured on the AT91SAM9G45-EKES and
AT91SAM9M10G45-EK evaluation kits.
14
Application Note
6492A–ATARM–22-Sep-09
Application Note
The following table gives the delay in ns extracted from the DDR2-SDRAM datasheet, the corresponding number of cycles at 133 MHz, and the field to program these values accordingly.
Description
Register/Field
Value
800 MHz
PMC_PLLAR
0x20c73f03
400 / 133 MHz
PMC_MCKR
0x00001302
System Clock
DDR clock
enable
PMC_SCER
0x00000005
EBI Chip Select Assignment
DDR/SDR
EBI_CSA
System
PLL Frequency
Processor / Bus Clock
Value in
Datasheet
DDR2 Device
Value in
Datasheet
DDRSDRC Configuration Register
EBI_CS1A
0x2
Register/Field
Value
DDRSDRC_CR
0x3d
Number of Columns
10
10
NC
0x1
Number of Rows
14
14
NR
0x3
CAS Latency
3
3 cycles
CAS
0x3
Reset DLL
Disable
DLL
0x0
Output Driver Impedance control
Normal
DIC/DS
0x0
Disable DLL
No
DIS_DLL
0x0
Off-Chip Driver
(1)
OCD
0x0
not shared
DMQS
0x0
disabled
ENRDM
0x0
Number of
Cycles at
133 MHz
Register/Field
Value
DDRSDRC_T0PR
0x21128226
Mask Data is shared
Enable Read Measure
Delay in
Datasheet
(ns)
DDRSDRC Timing 0 Register
ACTIVATE to PRECHARGE time
45
6 cycles
TRAS
0x6
ACTIVATE to READ/WRITE time
15
2 cycles
TRCD
0x2
Last DATA-IN to PRECHARGE time
15
2 cycles
TWR
0x2
REFRESH to ACTIVATE time
55
8 cycles
TRC
0x8
PRECHARGE to ACTIVATE time
15
2 cycles
TRP
0x2
ACTIVE bankA to ACTIVE BankB
7.5
1 cycle
TRRD
0x1
Internal Write to Read Delay
7.5
1 cycle
TWTR
0x1
2 cycles
2 cycles
TMRD
0x2
DDRSDRC_T1PR
0x02c8100e
Load Mode Register Command to ACTIVE or REFRESH Command
DDRSDRC Timing 1 Register
Row Cycle delay
Exit Self Refresh Delay to Non-Read Command
105
14 cycles
TRFC
0xe
TRFC+10
16 cycles
TXSNR
0x10
15
6492A–ATARM–22-Sep-09
Description
Value
Exit Self Refresh Delay to Read Command
200 cycles
200 cycles
TXSRD
0xc8
Exit Power-down Delay to First Command
2 cycles
2 cycles
TXP
0x2
DDRSDRC_T2PR
0x00000107
2
2 cycles
TXARD
0x2
Exit Active Power Down Delay to Read Command (Slow Exit)
7 cycles
TXARDS
0x7
Row Precharge All Delay
0 cycle
TRPA
0x0
1 cycle
TRTP
0x1
DDRSDRC_MD
0x00000016
DDRSDRC Timing 2 Register
Exit Active Power Down Delay to Read Command (Fast Exit)
Read to Precharge
2 cycles
7.5
DDRSDRC Memory Device Register
Memory Device
DDR2SDRAM
MD
0x6
Data Bus Width
16 bits
DBW
0x1
7µs
SDRAMC_TR
0x410
SDRAM Refresh Timer Register - Timer Count
Note:
16
Register/Field
1. OCD is not supported, but it is a mandatory step in the DDR2 initialization phase.
Application Note
6492A–ATARM–22-Sep-09
Application Note
12. Appendix
Here is an example of the DDR2 initialization code, associated to the different steps introduced
in Section 11.1 “DDR2-SDRAM Initialization” on page 13:
//*---------------------------------------------------------------------------//* \fn
ddram_init
//* \brief Initialization of the DDR Controller
//*---------------------------------------------------------------------------int ddram_init(unsigned int ddram_controller_address, unsigned int ddram_address, struct
SDdramConfig *ddram_config)
{
volatile unsigned int i;
unsigned int cr = 0;
// Initialization Step 1: Program the memory device type
// Configure the DDR controller
write_ddramc(ddram_controller_address, HDDRSDRC2_MDR, ddram_config->ddramc_mdr);
// Program the DDR Controller
write_ddramc(ddram_controller_address, HDDRSDRC2_CR, ddram_config->ddramc_cr);
// Initialization Step 2: assume timings for 7.5 ns min clock period
write_ddramc(ddram_controller_address, HDDRSDRC2_T0PR, ddram_config->ddramc_t0pr);
// pSDDRC->HDDRSDRC2_T1PR
write_ddramc(ddram_controller_address, HDDRSDRC2_T1PR, ddram_config->ddramc_t1pr);
// pSDDRC->HDDRSDRC2_T2PR
write_ddramc(ddram_controller_address, HDDRSDRC2_T2PR, ddram_config->ddramc_t2pr);
// Initialization Step 3: NOP command -> allow to enable clk
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// Initialization Step 3 (must wait 200 µs) (6 core cycles per iteration, core is at 396 MHz:
// min 13,200 loops)
for (i = 0; i < 13300; i++) {
asm("
nop");
}
// Initialization Step 4: An NOP command is issued to the DDR2-SDRAM
// NOP command -> allow to enable cke
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 100; i++) {
asm("
nop");
}
17
6492A–ATARM–22-Sep-09
// Initialization Step 5: Set All Bank Precharge
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 6: Set EMR operation (EMRS2)
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x4000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 7: Set EMR operation (EMRS3)
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x6000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 8: Set EMR operation (EMRS1)
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x2000000)) = 0;
// wait 200 cycles min
for (i = 0; i < 10000; i++) {
asm("
nop");
}
// Initialization Step 9: enable DLL reset
cr = read_ddramc(ddram_controller_address, HDDRSDRC2_CR);
write_ddramc(ddram_controller_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
// Initialization Step 10: reset DLL
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
18
Application Note
6492A–ATARM–22-Sep-09
Application Note
// Initialization Step 11: Set All Bank Precharge
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 400 ns min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh
// command (CBR) into the Mode Register.
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Set 2nd CBR
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 13: Program DLL field into the Configuration Register to low (Disable
// DLL reset).
cr = read_ddramc(ddram_controller_address, HDDRSDRC2_CR);
write_ddramc(ddram_controller_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));
// Initialization Step 14: A Mode Register set (MRS) cycle is issued to program the parameters
// of the DDR2-SDRAM devices.
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// Initialization Step 15: Program OCD field into the Configuration Register to high (OCD
// calibration default).
cr = read_ddramc(ddram_controller_address, HDDRSDRC2_CR);
write_ddramc(ddram_controller_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_OCD_DEFAULT);
// Initialization Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default
// value.
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x2000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
19
6492A–ATARM–22-Sep-09
// Initialization Step 17: Program OCD field into the Configuration Register to low (OCD
// calibration mode exit).
cr = read_ddramc(ddram_controller_address, HDDRSDRC2_CR);
write_ddramc(ddram_controller_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_OCD_EXIT));
// Initialization Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD
// exit.
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x6000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 19, 20: A mode Normal command is provided. Program the Normal mode into
// Mode Register.
write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
//
//
//
//
Initialization Step 21: Write the refresh rate into the count field in the Refresh Timer
register. The DDR2-SDRAM device requires a refresh every 15.625 ¦µs or 7.81 ¦µs. With a
100MHz frequency, the refresh timer count register must to be set with (15.625 x 100 MHz) =
1562 i.e. 0x061A or (7.81 x 100MHz) = 781 i.e. 0x030d.
// Set Refresh timer
write_ddramc(ddram_controller_address, HDDRSDRC2_RTR, ddram_config->ddramc_rtr);
// OK, now we are ready to work on the DDRSDR
// wait for the end of calibration
for (i = 0; i < 500; i++) {
asm("
nop");
}
return 0;
}
20
Application Note
6492A–ATARM–22-Sep-09
Application Note
Revision History
Doc. Rev
Comments
6492A
First issue
Change
Request Ref.
21
6492A–ATARM–22-Sep-09
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6492A–ATARM–22-Sep-09