PIC24F04KA201 Family Silicon/Data Sheet Errata

PIC24F04KA201 FAMILY
PIC24F04KA201 Family
Silicon Errata and Data Sheet Clarification
The PIC24F04KA201 family devices that you have
received conform functionally to the current Device Data
Sheet (DS39937B), except for the anomalies described
in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC24F04KA201 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A1).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1.
2.
3.
4.
Using the appropriate interface, connect
the device to the MPLAB ICD 2
programmer/debugger or PICkit™ 3.
From the main menu in MPLAB IDE, select
Configure>Select Device and then select the
target part number in the dialog box.
Select
the
MPLAB
hardware
tool
(Debugger>Select Tool).
Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the development tool used, the part number and Device
Revision ID value appear in the Output window.
Note:
Data Sheet clarifications and corrections start on page 5,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The DEVREV values for the various PIC24F04KA201
family silicon revisions are shown in Table 1.
SILICON DEVREV VALUES
Part Number
Device ID(1)
Revision ID for Silicon
Revision(2)
A1
PIC24F04KA201
0B00h
PIC24F04KA200
0B02h
Note 1:
2:
01h
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program
memory. They are shown in hexadecimal in the format, “DEVID DEVREV”.
Refer to the “PIC24FXXKAXXX Flash Programming Specification” (DS39919) for detailed information on
Device and Revision IDs for your specific device.
 2011 Microchip Technology Inc.
DS80474B-page 1
PIC24F04KA201 FAMILY
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A1
Resets
BOR
1.
Inadvertent Reset when disabling/enabling BOR.
X
Core
Deep Sleep
2.
Failure to avoid Deep Sleep entry.
X
—
3.
Change in maximum VIOFF.
X
SPI
Comparator
Enhanced
Buffer mode
4.
Errors when polling SPITBF flag.
X
Core
Low-Voltage
BOR
5.
LPBOR configuration results in ambiguous Resets.
X
Comparator I/O Pins
6.
Enabling comparators disables some digital I/O ports.
X
Comparator
7.
Output polarity inversion also inverts edge-detect sensing.
X
8.
Instruction execution glitches following DOZE bit changes.
X
Core
Note 1:
—
Doze mode
Only those issues indicated in the last column apply to the current silicon revision.
DS80474B-page 2
 2011 Microchip Technology Inc.
PIC24F04KA201 FAMILY
2. Module: Core (Deep Sleep)
Silicon Errata Issues
Note:
Deep Sleep wake-up sources may be ignored if
they occur just prior to entry into Deep Sleep
mode. As a result, the device may enter Deep
Sleep mode when it should not.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
Work around
If possible, configure external Deep Sleep
wake-up sources to repeat themselves once. If
the device does enter Deep Sleep, the second
occurrence of the wake-up source will wake the
device.
1. Module: Resets (BOR)
A device Reset may occur if the BOR is disabled
and immediately re-enabled in software
(RCON<14> is cleared, and then immediately
set).
Alternatively, synchronize the entry into Deep
Sleep with external wake-up sources, where
possible.
Work around
Affected Silicon Revisions
It is recommended that several NOP instructions
be added to a BOR disable/enable sequence.
Alternatively, place several instructions or a
short routine between the instructions to disable
and enable the BOR.
A1
X
Affected Silicon Revisions
3. Module: Comparator
A1
The maximum value for the input offset voltage
(specification D300, VIOFF), shown in
Table 26-12 of the Device Data Sheet, has
changed for this silicon revision. The new value
is shown in Table 3 (changes in bold).
X
Work around
None.
Affected Silicon Revisions
A1
X
TABLE 3:
COMPARATOR DC SPECIFICATIONS (PARTIAL)
Param
Symbol
No.
VIOFF
Characteristics
Input Offset Voltage
 2011 Microchip Technology Inc.
Min
Typ
Max
Units
—
20
60
mV
Comments
DS80474B-page 3
PIC24F04KA201 FAMILY
4. Module: SPI (Enhanced Buffer Mode)
6. Module: Comparator (I/O Pins)
In Enhanced Buffer mode (SPI1CON2<0> = 1),
polling the SPI Transmit Buffer Full bit, SPITBF
(SPI1STAT<1>), may produce erroneous results.
This occurs only under two circumstances:
Certain I/O pins may not function correctly as
digital inputs or outputs after specific comparator
outputs have been enabled with the COE bit
(CMxCON<14> = 1). These are:
•
•
•
In Master mode, when the SPI divide clock
is 4 or greater.
In Slave mode, when the SPI sample clock
is slower than 1/4 of the CPU instruction
time (TCY).
•
For Master mode, this includes all combinations
of the primary prescale bits (SPI11CON1<1:0>)
and secondary prescale bits (SPI1CON1<4:2>)
that, when combined, create an SPI sample
clock divisor with a value of four or greater.
Work around
Instead of polling the SPITBF bit to test for an
empty buffer (SPI1STAT<1> = 0), implement a
SPI receive interrupt handler in software and
add to the SPI transmit buffer in this routine.
Alternatively, poll the SPI Receive Full bit,
SPIRBF (SPI1STAT<0>), or the Shift Register
Empty bit, SRMPT (SPI1STAT<7>), to determine
when to service the SPI transmit and transmit
buffers.
Affected Silicon Revisions
A1
X
5. Module: Core (Low-Power BOR)
When the low-power BOR is enabled
(FPOR<6:5> = 00), Brown-out Reset events
may result in a device Reset in which both the
BOR and POR bits are set.
RB14 (with Comparator 1)
RA6 (with Comparator 2)
This condition may continue, even after the comparator in question has been disabled using the
corresponding CON bit (CMxCON<15> = 0).
Work around
In addition to clearing the CON bit, also clear the
COE bit.
Affected Silicon Revisions
A1
X
7. Module: Comparator
When a comparator is programmed to trigger
on
certain
edge-detect
events
(CMxCON<7:6> = 10 or 01), setting the CPOL bit
(CMxCON<13> = 1) may cause the comparator to
flag the opposite edge-detect event (e.g., a
high-to-low edge instead of the programmed
low-to-high).
Work around
Leave CPOL = 0. In addition, use the opposite
setting of CMxCON<7:6> to achieve the correct
response (e.g., use ‘10’ for ‘01’).
Affected Silicon Revisions
A1
X
This differs from the expected behavior of simply
re-arming the POR circuit to ensure that a
Power-on Reset occurs when VDD drops below
the POR threshold.
Work around
None.
Affected Silicon Revisions
A1
X
DS80474B-page 4
 2011 Microchip Technology Inc.
PIC24F04KA201 FAMILY
8. Module: Core (Doze Mode)
Data Sheet Clarifications
Operations that immediately follow any manipulations of the DOZE<2:0> or DOZEN bits
(CLDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
The following typographic corrections and clarifications
are to be noted for the latest version of the Device Data
Sheet (DS39937B):
Note:
1. Module: Electrical Specifications
(DC Specifications)
Work around
Always insert a NOP instruction before and after
either of the following:
•
Table 26-5 (“BOR Trip Points”) has changed to
reflect the functionality of the LPBOR trip point
(BORV<1:0> = 00), and to make other typographic corrections. The minimum and
maximum values for the BOR trip points in
Table 26-5 have changed. The new version of
the table is shown below (changes in bold).
Enabling or disabling Doze mode by setting
or clearing the DOZEN bit
Before or after changing the DOZE<2:0> bits
•
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
Affected Silicon Revisions
A1
X
TABLE 26-5:
BOR TRIP POINTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
Param
Sym
No.
DC19
Note 1:
Characteristic
BOR Voltage on
VDD Transition
Max
Units
—
—
—
3
3.25
V
BORV = 10 2.63
2.7
2.92
V
BORV = 11 1.75
1.82 2.01
V
BORV = 00
Min
Typ
—
BORV = 01 2.92
Conditions
Note (1)
LPBOR re-arms the POR circuit, but does not cause a BOR.
 2011 Microchip Technology Inc.
DS80474B-page 5
PIC24F04KA201 FAMILY
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (6/2009)
Initial release of this document; issued for revision A1.
Includes silicon issues 1 (Resets – BOR), 2 (Core –
Deep Sleep), 3 (Comparator) and 4 (SPI – Enhanced
Buffer Mode).
Rev B Document (2/2011)
Adds new silicon issues 5 (Core – Low Power BOR),
6 and 7 (Comparators), and 8 (Core – Doze Mode) to
silicon revision A1.
Added data sheet clarification 1 (Electrical
Specifications – DC Specifications) to revision B of the
data sheet.
DS80474B-page 6
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
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MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
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ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
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All other trademarks mentioned herein are property of their
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© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-893-1
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2011 Microchip Technology Inc.
DS80474B-page 7
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DS80474B-page 8
 2011 Microchip Technology Inc.