SAM3U Microcontroller Series Schematic Check List 1. Introduction This Application Note is a schematic review check list for systems embedding Atmel’s SAM3U series of ARM® Cortex™-M3, Thumb®2-based microcontrollers. It gives requirements concerning the different pin connections that must be considered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the SAM3U Series. It does not consider PCB layout constraints. It also gives advice regarding low-power design constraints to minimize power consumption. This Application Note is not intended to be exhaustive. Its objective is to cover as many configurations of use as possible. AT91 ARM Thumb-based Microcontrollers Application Note The Check List table has a column reserved for reviewing designers to verify the line item has been checked. 11006B–ATARM–19-May-10 2. Associated Documentation Before going further into this application note, it is strongly recommended to check the latest documents for the SAM3U Series Microcontrollers on Atmel’s Web site. Table 2-1 gives the associated documentation needed to support full understanding of this application note. Table 2-1. 2 Associated Documentation Information Document Title User Manual Electrical/Mechanical Characteristics Ordering Information Errata SAM3U Series Product Datasheet Internal architecture of processor Thumb2 instruction sets Embedded in-circuit-emulator Cortex-M3 Technical Reference Manual (available from ARM Ltd.) Evaluation Kit User Guide SAM3U-EK Evaluation Board User Guide Application Note 11006B–ATARM–19-May-10 Application Note 3. Schematic Check List Single Power Supply Strategy VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.8V-3.6V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Single Power Supply Schematic Example: 3 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description VDDIN 1.8V to 3.6V Decoupling/Filtering capacitor (100 nF)(1)(2) Powers the voltage regulator. VDDIO 1.62V to 3.6V Decoupling/Filtering capacitors (100 nF and 4.7µF)(1)(2) Powers the peripheral I/Os Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDOUT Decoupling/Filtering capacitors (100 nF and 4.7µF)(1)(2) Output of the main voltage regulator. Decoupling/Filtering capacitors must be added to guarantee stability. VDDCORE Must be connected directly to VDDOUT pin. Decoupling capacitor (100 nF)(1)(2) VDDUTMI 3.0V to 3.6V Decoupling/Filtering RLC circuit (1R resistor and 4.7µF capacitor in parallel with a 100 nF capacitor, 10 µH inductor)(1)(2)(8) Powers the UTMI+ interface. VDDPLL 1.62V to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers PLLA, UPLL and 3-20 MHz oscillator. VDDANA 2.0V to 3.6V Decoupling/Filtering RLC circuit (1R resistor and 4.7µF capacitor in parallel with a 100 nF capacitor, 10 µH inductor)(1)(2)(8) ADC power supply VDDBU 1.62V to 3.6V VDDBU must be supplied before or at the same time as VDDIO and VDDCORE Powers the Slow Clock oscillator and a part of the System Controller. GND Ground Ground pins GND are common to VDDIO and VDDCORE. GNDBU Backup unit ground GNDBU pin is provided for VDDBU pin. GNDANA ADC ground GNDANA pin is provided for VDDANA pin. GNDPLL PLL ground GNDPLL pin is provided for VDDPLL pin. GNDUTMI UTMI+ ground GNDUTMI pin is provided for VDDUTMI pin. Core, embedded memories and peripherals power supply. Note: Restrictions With Main Supply < 2V, USB and ADC are not usable (please refer to the Datasheet Electrical Section). With Main Supply ≥ 2V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 4 Application Note 11006B–ATARM–19-May-10 Application Note Core externally supplied. VDDBU VDDUTMI VDDANA Main Supply (1.62V-3.6V) VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE Supply (1.62V-1.95V) VDDCORE VDDPLL Core externally supplied Schematic Example: Main Supply on VDDIO, VDDUTMI, VDDBU and VDDANA (1.62V to 3.6V). VDDCORE Supply is between 1.62V and 1.95V. Voltage regulator is OFF by connecting VDDIN to ground. 5 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description VDDIN Connected to GND The voltage regulator is OFF. VDDIO 1.62V to 3.6V Connected to Main Supply Decoupling/Filtering capacitors (100 nF and 4.7 µF)(1)(2) Powers the peripheral I/Os. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDOUT Unconnected Output of the main voltage regulator. Voltage regulator is OFF. VDDCORE 1.65V to 1.95V Connected to VDDCORE Supply Decoupling capacitor (100 nF)(1)(2) Core, embedded memories and peripherals power supply VDDUTMI 3.0V to 3.6V Connected to Main Supply Decoupling/Filtering RLC circuit (1R resistor and 4.7µF capacitor in parallel with a 100nF capacitor, 10 µH inductor)(1)(2)(8) Powers the UTMI+ interface. VDDPLL 1.62V to 1.95V Connected to VDDCORE Supply Decoupling capacitor (100 nF)(1)(2) Powers PLLA, UPLL and 3-20 MHz oscillator. VDDANA 2.0VV to 3.6V Connected to Main Supply Decoupling/Filtering RLC circuit (1R resistor and 4.7µF capacitor in parallel with a 100nF capacitor 10µH inductor)(1)(2)(8) ADC power supply VDDBU 1.62V to 3.6V Connected to Main Supply VDDBU must be supplied before or at the same time as VDDIO and VDDCORE. Powers the Slow Clock oscillator and a part of the System Controller. GND Ground Ground pins GND are common to VDDIO and VDDCORE GNDBU Backup unit ground GNDBU pin is provided for VDDBU pin. GNDANA ADC ground GNDANA pin is provided for VDDANA pin. GNDPLL PLL ground GNDPLL pin is provided for VDDPLL pin. GNDUTMI UTMI+ ground GNDUTMI pin is provided for VDDUTMI pin. Note: Restrictions With Main Supply < 2V, USB and ADC are not usable (please refer to the Datasheet Electrical Section). With Main Supply ≥ 2V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 6 Application Note 11006B–ATARM–19-May-10 Application Note Backup unit externally supplied FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Voltage Regulator Main Supply (1.8V-3.6V) VDDOUT VDDCORE VDDPLL 7 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description VDDIN 1.8V to 3.6V Decoupling/Filtering capacitor (100 nF)(1)(2) Powers the voltage regulator. VDDIO 1.62V to 3.6V Decoupling/Filtering capacitors (100 nF and 4.7 µF)(1)(2) Powers the peripheral I/Os. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDOUT Decoupling/Filtering capacitors (100 nF and 4.7µF)(1)(2) Output of the main voltage regulator. Voltage regulator is OFF VDDCORE 1.62V to 1.95V Decoupling capacitor (100 nF)(1)(2) Core, embedded memories and peripherals power supply VDDUTMI 3.0V to 3.6V Decoupling/Filtering RLC circuit (1R resistor and 4.7 µF capacitor in parallel with a 100 nF capacitor, 10 µH inductor)(1)(2)(8) Powers the UTMI+ interface. VDDPLL 1.62V to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers PLLA, UPLL and 3-20 MHz oscillator. VDDANA 2.0V to 3.6V Decoupling/Filtering RLC circuit (1R resistor and 4.7µF capacitor in parallel with a 100 nF capacitor, 10 µH inductor)(1)(2)(8) ADC power supply VDDBU 1.62V to 3.6V Connected to backup batteries. VDDBU must be supplied before or at the same time as VDDIO and VDDCORE. Powers the Slow Clock oscillator and a part of the System Controller. SHDN Connected to the main supply control pin. Shutdown pin Controls the main supply level. GND Ground Ground pins GND are common to VDDIO and VDDCORE GNDBU Backup unit ground GNDBU pin is provided for VDDBU pin. GNDANA ADC ground GNDANA pin is provided for VDDANA pin. GNDPLL PLL ground GNDPLL pin is provided for VDDPLL pin. GNDUTMI UTMI+ ground GNDUTMI pin is provided for VDDUTMI pin. Note: Restrictions With Main Supply < 2V, USB and ADC are not usable (please refer to the Datasheet Electrical Section). With Main Supply ≥ 2V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 8 Application Note 11006B–ATARM–19-May-10 Application Note ; Signal Name Recommended Pin Connection Description Clock, Oscillator and PLL Internal Equivalent Load Capacitance (CL): CL = 9.5 pF Crystal Load Capacitance, ESR, Drive Level and Shunt Capacitance to validate. AT91SAM3U CL Crystals between 3 and 20 MHz XIN XIN XOUT Capacitors on XIN and XOUT (crystal load capacitance dependant) Main Oscillator in Normal Mode 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz. XOUT 1K A 12 MHz crystal is mandatory to use the High Speed USB. GND 8 MHz CCRYSTAL CLEXT CLEXT The external load capacitance is calculated with the following formula: CLEXT=2*(Ccrystal-CL) Refer to the Crystal Oscillators Design Consideration Information section of the SAM3U Series datasheet. XIN XOUT Main Oscillator in Bypass Mode XIN: external clock source XOUT: can be left unconnected. A 12 MHz clock is mandatory to use the High Speed USB. 1.8V Square wave signal (VDDPLL) External Clock Source up to 50 MHz Duty Cycle: 40 to 60% 9 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description No internal load capacitance Crystal Load Capacitance, ESR, Drive Level and Shunt Capacitance to validate. . XIN32 XOUT32 32 kHz Crystal used SAM3 32.768 kHz Crystal Capacitors on XIN32 and XOUT32 (crystal load capacitance dependent) XIN32 CLEXT XOUT32 CLEXT Refer to the Crystal Oscillators Design Consideration Information section of the SAM3U Series datasheet. XIN32 XOUT32 32 kHz Oscillator in bypass mode XIN32 XOUT32 XIN32: external clock source XOUT32: can be left unconnected. 1.8V to 3.3V Square wave signal (VDDBU) External Clock Source up to 44 kHz Duty Cycle: 40 to 60% XIN32 and XOUT32 can be left unconnected. Crystal oscillator not required 10 Application Note 11006B–ATARM–19-May-10 Application Note ; Signal Name Recommended Pin Connection Description (3) Serial Wire and JTAG TCK/SWCLK Pull-up (100 kOhm)(1) No internal pull-up resistor. TMS/SWDIO (1) No internal pull-up resistor. TDI Pull-up (100 kOhm)(1) No internal pull-up resistor. TDO/ TRACESWO Floating Output driven at up to VVDDIO In harsh(4) environments, it is strongly recommended to tie this pin to GNDBU if not used or to add an external low resistor value (such as 1 kOhm). Internal pull-down resistor (15 kOhm). JTAGSEL Pull-up (100 kOhm) Must be tied to VVDDBU to enter JTAG Boundary Scan. Flash Memory Internal pull-down resistor (15 kOhm). ERASE In harsh(4) environments, it is strongly recommended to tie this pin to GNDBU if not used or to add an external low resistor value (such as 1 kOhm). Must be tied to VVDDBU to erase the General Purpose NVM bits (GPNVMx), the whole Flash content and the security bit (SECURITY) Minimum debouncing time is 220 ms. Reset/Test NRST is configured as an output at power up. NRST Application dependant. Can be connected to a push button for hardware reset. NRST is controlled by the Reset Controller (RSTC). An internal pull-up resistor to VVDDIO (100 kOhm) is available for User Reset and External Reset control. Application dependant. Can be connected to a push button for power-on reset. NRSTB(5) In harsh environments, it is recommended to add an external capacitor (10 nF) between NRSTB and VDDBU NRSTB is an asynchronous reset input always active. NRSTB pin integrates a permanent pull-up resistor (15 kOhm) and embeds an anti-glitch filter. To enter in FFPI mode NRSTB pin must be tied to VVDDIO. TST(5) In harsh(4) environments, it is strongly recommended to tie this pin to GND if not used or to add an external low resistor value (such as 1 kOhm). Internal pull-down resistor (15 kOhm). To enter in FFPI mode TST pin must be tied to VVDDIO. 11 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description Add a pull-up resistor (100 kOhms) if OFF Mode or FWUP functionality is used. FWUP(5) To enter in FFPI mode FWUP pin must be tied to VVDDIO. Force wake-up input No internal pull-up resistor If unused, tie this pin to GND SHDN 12 Application dependent. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies. This pin is a push-pull output. SHDN pin is driven low to GNDBU by the Shutdown Controller (SHDWC). Application Note 11006B–ATARM–19-May-10 Application Note ; Signal Name Recommended Pin Connection Description PIO PAx - PBx-PC(6) Application Dependant (Pulled-up on VVDDIO) At reset, all PIOs are configured as Schmitt trigger inputs with pull-up. To reduce power consumption, if not used, the concerned PIO can be configured as an output and driven at ‘0’ with internal pull-up disabled. Note: PA14, PB9 to PB16, PB25 to PB31 and PC20 to PC27 are not Shmitt triggered. 10-bit ADC ADVREF is a pure analog input. ADVREF 2.4V to VDDANA. Decoupling capacitor(s). AD0 to AD7 0V to VADVREF. To reduce power consumption, if ADC is not used, connect ADVREF to GND. ADx pins are multiplexed with PIOs. 12-bit ADC (ADC12B) AD12BVREF is a pure analog input. AD12BVREF 2.4V to VDDANA. Decoupling capacitor(s). AD12B0 to AD12B7 0V to VAD12BvREF. To reduce power consumption, if ADC is not used, connect AD12BVREF to GND. AD12Bx pins are multiplexed with PIOs. USB High Speed Device (UDPHS) Application dependent(7) DFSDP If USB Device is not used it can be left floating. Internal pull-down resistor Application dependent(7) DFSDM If USB Device is not used it can be left floating. Internal pull-down resistor Application dependent(7) DHSDP If USB Device is not used it can be left floating. Internal pull-down resistor Application dependent(7) DHSDM VBG If USB Device is not used it can be left floating. Application dependent(7) Internal pull-down resistor If USB Device is not used it must be left unconnected. 13 11006B–ATARM–19-May-10 ; Signal Name Recommended Pin Connection Description Static Memory Controller (SMC) D0-D15 A0-A23 Application dependent. Data Bus (D0 to D15) Note: Data bus lines are multiplexed with the PIOB controller. Their I/O line reset state is input with pull-up enabled. Application dependent. Address Bus (A0 to A23) Note: Data bus lines are multiplexed with the PIOB & PIOC controllers. Their I/O line reset state is input with pull-up enabled. NWAIT pin is an active low input. NWAIT Notes: Application dependent. Note: NWAIT is multiplexed with PC18. 1. These values are given only as a typical example. 2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin. 100nF VDDCORE 100nF VDDCORE 100nF VDDCORE GND 3. It is recommended to establish accessibility to a JTAG connector for debug in any case. 4. In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended. 5. See: Test Pin description in I/O Lines Considerations section of the SAM3U Series datasheet for more details on the different conditions to enter FFPI mode. 6. PB25 to PB31 and PCx is only available in 144-pin version 14 Application Note 11006B–ATARM–19-May-10 Application Note 7. Typical USB High Speed Device connection: As there is an embedded pull-up, no external circuitry is necessary to enable and disable the 1.5 kOhm pull-up. See: Typical Connection in USB High Speed Device Port section of the SAM3U Series datasheet for more details. PIO (VBUS DETECT) 15k Ω "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM 39 ± 5% Ω DFSDM Shell = Shield 22k Ω CRPB DHSDP 39 ± 5% Ω CRPB:1µF to 10µF DFSDP 6K8 ± 1% Ω VBG 10 pF GND 8. The filtering RLC circuit is given as an example. Depending on the application the user may only need a 100 nF decoupling capacitor. 15 11006B–ATARM–19-May-10 4. SAM3U Boot Program Hardware Constraints See AT91SAM Boot Program section of the SAM3U Series datasheet for more details on the boot program. 4.1 SAM-BA Boot The SAM-BA® Boot Assistant supports serial communication via the UART or USB device port: • UART Hardware Requirements: 3 to 8.9 MHz or 12 MHz or 19.7 to 20 MHz crystal. 1 to 8.9 MHz or 12MHz or 19.7 to 50 MHz external clock. • USB Device Hardware Requirements: 12 MHz Quartz or 12 MHz external clock on XIN. 12 MHz must be ±500 ppm and 1.8V Square Wave Signal in bypass mode. Table 4-1. 16 Pins driven during SAM-BA Boot Program execution Peripheral Pin PIO Line UART URXD PA11 UART UTXD PA12 Application Note 11006B–ATARM–19-May-10 Application Note Revision History Doc. Rev Date Comments 11006A 13-Oct-2009 First issue 1106B 12-Apr-2010 Change Request Ref. page 8 There are two FWUP pin descriptions. Remove the first FWUP line described by: 1.62V to 3.6V Connected to backup batteries 6953 page 10 If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected. 7154 17 11006B–ATARM–19-May-10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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