APPLICATION NOTE ATA6870 - Description of Evaluation Board and Control Software ATA6870 Introduction This document provides a description and details on using the Atmel® ATA6870 evaluation board for Li-Ion/NiMH Battery Management applications. The evaluation kit consists of two boards: ● ● Evaluation board with Atmel ATA6870 and external MOSFETs for charge balancing Controller board with the Atmel microcontroller ATmega128 For a comfortable control of the evaluation board, a graphical user interface is available. Figure 1. Li-Ion/NiMH Battery Stack Measurement and Monitoring Kit with Atmel ATA6870 9162E-AUTO-07/15 1. Evaluation System Figure 1-1. Evaluation Concept To ATA6870 above VDDHV MBAT7 PD_N DISCH6 Digital Level Shifter Cell 6: Reference ADC Cell Balancing Standby Control VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD 3.3V Internal Voltage Regulator DISCH1 Logic Cell 1: Reference ADC Cell Balancing Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 NTC NTC Interchip and Microcontroller Communication Interface Test Cell Temperature Measuring TEMP1 Digital Level Shifter TEMPREF TEMP2 TEMPVSS GND AVSS DVSS SCANMODE PWTST DTST CS_FUSE VDDFUSE ATST Evaluation Board with ATA6870 Controller Board ATmega128 Serial Port PC-GUI USB to Serial Converter 2 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 DVDD MFIRST MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK The Atmel® ATA6870 is designed for the measurement and monitoring of Li-ion and NiMH multicell battery stacks in hybrid electrical vehicles. Battery cell voltage and battery cell temperature are monitored in parallel by the related 12-bit ADC. The circuit also provides charge balancing capability for each battery cell by controlling the external discharge N-channel MOSFETs. To supply power to a microcontroller or other external components, a linear regulator is integrated in Atmel ATA6870. Levelshifters with current sources ensure a reliable communication between stacked ICs. Three to six battery cells can be connected to the Atmel ATA6870 and up to 16 ICs can be cascaded to one chain. The Atmel ATA6870 evaluation board is controlled by the Atmel ATmega128 controller board via a graphical user interface (GUI), see Figure 1-1 on page 2. A USB to serial converter is provided, in case a serial port is not available on the PC. 1.1 System Start To run the evaluation system, the following installation steps are necessary. 1.1.1 Hardware Installation ● ● Connect the Atmel ATA6870 evaluation board to the controller board at the pin header connectors X1 and X5 Apply a 12V power supply to the X3 controller board connector --> The lit red LED indicates the enabled status of the evaluation board ● Connect the battery cell stack to be measured or the enclosed emulator (see document “Battery_Emulator_ATA6870_71_v11.pdf”) to the green screw connectors on the evaluation board, see Figure 1-3 on page 4. ● ● In case of emulator use, apply a 48V power supply to the J22 power jack of the Atmel emulator board ATA6870-DK2. To control the evaluation board via Graphical User Interface, connect to the PC by serial interface, respectively USB to serial converter to the serial connector of the controller board. A “Digitus” USB to serial converter is included in the evaluation kit. Figure 1-2. Assigned USB Serial Port ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 3 1.1.2 Software Installation 1.1.2.1 USB to Serial Converter ● Install the corresponding driver software from the USB driver CD, enclosed with the USB to serial dongle. Attention: Don't let Windows® automatically install the driver. ● ● Check the assigned USB Serial Port number from the windows system device manager, see Figure 1-2 on page 3. Set the assigned COM port number in the “standard user” panel (upper right corner), as described in Figure 3-1 on page 11, as soon the Graphical User interface is installed and running. 1.1.2.2 Graphical User Interface (GUI) ● ● ● 1.1.3 Copy the folder “ATA6870 Battery Monitor Installer+exe” to a local drive on the PC Execute the “setup.exe” file to install all necessary support files Execute the file “ATA6870 Battery Monitor.exe” to run the Graphical User Interface (GUI) Communication Check To see whether the communication between PC and controller board is established or not, toggle the power down button PDN on the “standard user” panel (Figure 3-1 on page 11). A proper communication exists when the red LED (Figure 2-2 on page 6) on the evaluation board switches on/off. Figure 1-3. Evaluation Setup 4 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 2. Application Board 2.1 Controller Board Figure 2-1. Controller Board 2.1.1 On-board Features The controller board provides the following items: ● Atmel® ATmega128 QFN64 9x9 mm ● ● 8-bit AVR® microcontroller ● 16-MHZ system clock ● VCC regulator for 3.3V operation Connectors ● Pinheader interface X1 and X5 to Atmel ATA6870 Evaluation Board ● 6-pin ISP connector for In-System Programming using JTAGICEmkII ● Serial connector for PC communication ● Supply connector ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 5 2.2 Evaluation Board Figure 2-2. Evaluation Board with 3 Stacked Atmel ATA6870 2.2.1 On-board Features The evaluation board provides the following items: ● Atmel ATA6870 QFN 7x7 mm ● ● ● 6 ● 12-bit battery cell voltage measurement ● Simultaneous battery cells measurement in parallel ● Charge balancing capability ● Cell temperature measurement ● Undervoltage detection ● Integrated power supply for MCU ● Reliable communication between stacked ICs 18 external N-channel MOSFETs for balancing of battery cells On-board potentiometers as temperature emulation Connectors ● Pin header interface X1 and X5 to controller board ● Screw connectors for connecting up to 18 battery cells ● 16-pin connector for stacking several evaluation boards ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 2.2.2 Board Configuration for 3 IC Operation The evaluation board is assembled with 3 stacked devices of Atmel® ATA6870. The configuration regarding jumpers (J), optocouplers (O) and resistors (R) is as follows: Figure 2-3. Configuration for 3 IC Operation Atmel ATA6870 2.2.2.1 Board Definition Master/Slave Since several evaluation boards can be stacked to a string, the respective board has to be configured as master or slave. Single boards are configured as master board. Default: PD_N_OUT connected to GND (first) by Jumper J20 2.2.2.2 First Device The lowest device in a string is defined by MFIRST jumper J23. Default: set to first To pull up the MCU input pins MISO and IRQ on MCU high level, the VDD_PULL Jumper J27 has to be ON, if no external VDD_MCU supply is available. Default: J27 is OFF, when evaluation board is operated together with controller board. ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 7 2.2.2.3 Termination For the highest IC of the stack, the lines IRQ_IN, CLK_OUT, CS_N_OUT, SCK_OUT,MOSI_OUT, MISO_IN and VDDHVP need to be terminated. --> by default the jumpers J18, 19, 21, 22, 24-26 are set 2.2.2.4 Power Down/Enable The enable/disable of the 3 Atmel® ATA6870 on the evaluation board is executed by an optocoupler. Only the highest IC in the application needs to be switched on/off. The lower ICs are enabled/disabled via daisy chain. --> only optocoupler O2 is populated on the evaluation board By default, the GND connection of the optocoupler is set by jumper J31 (PD_N_OPTO_GND to GND). The evaluation board is automatically enabled by the controller board Pin “PD_N_OPTO_HI” of the X5 board interface connector. 2.2.2.5 Temperature Measurement IC1 Configuration - By default, the potentiometers R93 and R94 are populated at the temperature measuring inputs Temp1 and Temp2 to emulate the battery cell temperature, sensed by NTC1 and NTC2. Optional NTC resistors can be installed at the jumpers J51and J52. IC2 Configuration - a 3k3 voltage divider is realized at the inputs Temp1 and Temp2. Optional NTC resistors can be installed at the jumpers J4 and J5. In that case, the default 3k3 resistors R78 and R82 have to be removed. IC3 Configuration - a 3k3 voltage divider is realized at the inputs Temp1 and Temp2. Optional NTC resistors can be installed at the jumpers J16 and J17. In that case, the default 3k3 resistors R52 and R56 have to be removed. 2.2.2.6 Integrated Voltage Regulator To supply external components, e.g. MCU, an internal 3.3V voltage regulator is implemented in Atmel ATA6870. For the regulator activation, the POW_ENA Jumpers J3, J14 and 15 have to be set to ON. The regulator voltage is available at pin “VDDHVM” of the lowest stack IC. Default: POW_ENA Jumpers J3, J14 and J15 set to OFF 2.2.2.7 Battery Cell Connection The battery stack connection to the Atmel ATA6870 evaluation board has to be done in the described way: IC1 cells: connect the first 6 battery cells between clamp 1 and 7 of the lower connector to IC1. IC2 cells: connect the second 6 battery cells between clamp 1 and 7 of the middle connector to IC2. IC3 cells: connect the third 6 battery cells between clamp 1 and 7 of the upper connector to IC3. Clamp 7 of the first connector and clamp 1 of the second connector are connected together on the board, clamp 7 of the second connector and clamp 1 of the third connector as well. 2.2.2.8 Charge Balancing For each IC on the evaluation board, 6 external N-channel MOSFETs are populated to support the charge balancing of the connected battery cells, see Figure 2-2 on page 6. The activation of the respective MOSFET is controlled via the GUI, see Figure 3-2 on page 12. The populated 1k discharge resistors are in a 0603 package. The footprint of the resistors allows the use of resistors with higher power dissipation and package size up to 2512. 8 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 2.2.3 Board Configuration for 2 IC Operation - 12 Battery Cells To operate the evaluation board with only two ATA6870, modifications regarding termination and optocoupler have to be done (see Figure 2-4). ● Remove termination jumpers J18, J19, J21, J22, J24, J25, J26 from the 3 IC configuration ● ● ● ● Remove optocoupler O2 or resistor R51 Populate termination jumpers J6, J7, J8, J9, J10, J11, J12 Populate optocoupler O4 and resistor R77 (330) Connect the battery cells or an appropriate battery emulator to the two lower cell connectors of the board (see Figure 2-4). Figure 2-4. Configuration for 2 IC (12 Cell) Operation Atmel ATA6870 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 9 2.2.4 Board Configuration for 1 IC Operation - 6 Battery Cells To operate the evaluation board with only one Atmel® ATA6870, modifications regarding termination and optocoupler have to be done (see Figure 2-5). ● Remove termination jumpers J18, J19, J21, J22, J24, J25, J26 ● ● ● ● Remove optocoupler O2 or resistor R51 Populate termination jumpers J33, J35, J36, J37, J38, J40, J50 Populate optocoupler O1 and resistor R96 (330) Connect the battery cells or an appropriate battery emulator to the lowest connector of the board (see Figure 2-5) Figure 2-5. Configuration for 1 IC (6Cell) Operation Atmel ATA6870 10 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 3. Software Description To verify the functions of the application board, a graphical user face is provided. After the hardware setup and software installation, the GUI is started by executing the “ATA6870 Battery Monitor.exe” file. 3.1 Standard User With the “standard user” panel, the main functions of Atmel® ATA6870 can be tested. Figure 3-1. Standard User Control Panel 3.1.1 COM Box The USB to serial port number of the PC is selected 3.1.2 PDN The power-down button disables/enables the ICs on the evaluation board. 3.1.3 Select The data acquisition of chip1, chip2 or chip3 of the evaluation board can be selected. In addition, the data of all chips can be acquired by selecting “chip1…3” 3.1.4 Acquire The measurement data of the selected chips are acquired. ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 11 3.1.5 Draw The draw buttons select the chip, which measurement results are displayed on the screen, in case of “chip1…3” is selected. Otherwise the measurement results of selected chip is displayed automatically. 3.1.6 Measure The data can be acquired as single shot or in a permanent loop. In loop case, the measurement results are continuously drawn on the screen, see Figure 3-2. Figure 3-2. Standard User Panel with Loop Acquisition 3.1.7 Discharge The discharge buttons activate the on board N-channel MOSFET transistors for charge balancing of the corresponding battery cell, see Figure 3-3 on page 13. On the standard user panel the discharge function for 3 ICs (18 battery cells) is provided. On the “acquire data window” (see Figure 3-5 on page 15), which can be activated on the “standard user” and “advanced user” panel, the discharge matrix of up to 72 battery cells (12 ICs) is available for a stacked board configuration. 3.1.8 Loop The loop time for the acquisition cycles can be set. 3.1.9 Overvoltage A threshold can be defined to detect an overvoltage of the connected battery cells. 12 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 3.1.10 Undervoltage A threshold can be defined to detect an undervoltage of the connected battery cells. 3.1.11 Cell States The cell status of each connected battery cell is displayed for all chips. If an over- or undervoltage of a battery cell is detected, the corresponding cell color on the panel will change, see Figure 3-3. ● Green cell: battery cell voltage in the defined voltage range ● ● Red cell: battery cell voltage exceeds the undervoltage limit Yellow cell: battery cell voltage exceeds the overvoltage limit Figure 3-3. Standard User Panel with Over- and Undervoltage Detection ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 13 3.1.12 Data Logging To save the measurement values of the monitored battery cells, a log file can be generated. The data logging is enabled/disabled by the toggle menu Data logging/don't log data. The log file path can be written directly into the text box or set by a browser window, enabled by pushing the folder symbol. A format selection of csv (comma separated variable) or tab limited format of the saved data is available. Figure 3-4. Data Log File Generation The data log file generation for up to 72 battery cells (12 ICs) is available on the “acquire data window” (see Figure 3-5 on page 15), which can be activated on the “standard user” and “advanced user” panel. 3.1.13 Clear Graph Clears all displayed graphs from the window. 3.1.14 Stop All acquisitions are stopped. A second press of the stop button will halt the software, ready for closing. 3.1.15 Acquire Data Window By pushing the acquire data window button a new panel appears on the screen (see Figure 3-5 on page 15). The measurement values of up to 72 battery cells are displayed (12 ICs with 6 Cells per IC). The chip(s) acquire window shows the selected number of ICs to be measured in multi chip mode. The number can be inserted directly, or set by the provided slide bar. In single chip mode, only the cell values of the one selected IC are checked. For both, single chip and multi chip mode, the data logging function is provided. Also the discharge function of up to 72 battery cells is available by the discharge Chip/cell matrix. The data acquisition can be operated in once and loop mode. If the loop mode is running, press once to stop the continuous data acquisition. 14 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 Figure 3-5. Acquire Data Window ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 15 3.2 Advanced User For a more individual and detailed control of the evaluation system, the “advanced user” panel is provided. Single register can be controlled, and saved command files can be executed. Figure 3-6. Advanced User Panel Four command panels are at the user’s disposal. All of these are suitable to configure and execute commands. By default, the executed commands are displayed in the “standard” panel. Command files can be saved, respectively loaded to/from a folder by using the corresponding load and save buttons. The execute button starts the command transfer. A list box is provided to display the decimal ADC values of the acquired data for each battery cell of the selected IC. The decimal ADC values are available for V(MBATi+1), gain and offset. The calculated cell voltage VBATP is also displayed in this list box. To achieve a correct data transfer with the respective register, 5 read/write commands are available: ● Read/write8Bit - read/write operation with all 8 bit registers ● ● Read/write16Bit - read/write operation with all 16 bit registers Burst_read - reads back all channel values (6 voltage + 1 temperature) A register is addressed by selecting chip number (chip) and address (addr). Update SPI transfers the inserted data. 16 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 3.2.1 MOSI/MISO The transfer addresses and data are displayed for the respective write/read execution. 3.2.2 Clk ON The toggle button enables/disables system clock 3.2.3 SoftRSTN Resets Atmel® ATA6870 software. 3.2.4 Default Sets the controller board into default conditions. 3.2.5 CLK The system clock frequency is set. 3.2.6 SPI-clock The frequency of the serial data transfer is set. 3.2.7 Step Mode To execute a command stack in single steps, a step mode is provided, see Figure 3-7. The step button executes a single step, an auto once or an auto loop operation. Command panel 1 to panel 4 (Tab1 to Tab4) or a saved file represent the source for the step mode operation. The time interval between two steps is adjustable by the wait timer. Figure 3-7. Step Mode ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 17 4. Board Schematics and Layout 4.1 Schematic of 3 Stacked Atmel ATA6870 100nF 100nF C10 C32 J22 CS_OUT_HV 100nF 30V J25 CLK_OUT_HV J26 IRQ_IN_HV + C37 36 R55 33μF 35 121kΩ 34 33 32 R40 3.3kΩ 31 R57 3.3kΩ 30 29 28 27 26 GND 25 R66 100kΩ GND @5 GND 24 DVDD ATST DVSS C38 220nF 1 2 3 AVDD 23 R38 PD_N_OPTO_LO HCPL-181 37 PD_N VDDHVP 38 39 MISO_IN MOSI_OUT 40 SCK_OUT 41 43 44 45 46 47 42 CS_N_OUT CLK_OUT IRQ_IN VDDHV CLK T14 ZXMN2F34FH MBAT7 AVSS IRQ CS_N 100Ω TEMPVSS MBAT1 13 J39-3 R30 TEMP1 DISCH1 22 12 MBAT2 TEMP2 VDDFUSE 11 TEMPREF ATA6870 DISCH2 CS_FUSE 10 1kΩ BIASRES MBAT3 21 9 1kΩ R54 IC3 DISCH3 SCANMODE 8 PWTST 20 7 6 MBAT6 48 5 1kΩ R53 VDDHVM POW_ENA MBAT4 R51 330Ω J15 PD_N_OUT DISCH4 19 T13 1kΩ R47 DISCH5 MBAT5 DTST R41 0Ω 100Ω ZXMN2F34FH 4 18 J39-4 R31 3 2 MFIRST ZXMN2F34FH 1kΩ R46 17 0Ω T16 MISO R37 R32 100Ω 1 DISCH6 0Ω J39-5 1kΩ R45 MOSI R36 ZXMN2F34FH 1kΩ R58 SCK T17 14 100Ω 16 R59 15 R33 O2 POW_ENA ON OFF 0Ω J39-6 R50 270Ω J16 NTC6 100nF C11 J24 SCK_OUT_HV 3.3kΩ 100nF C12 MOSI_OUT_HV R52 100nF C13 R35 100nF T18 C14 R34 100Ω ZXMN2F34FH C15 J39-7 10μF 30V VDDHVP_HV MISO_OUT_HV J21 R56 + C1 J18 J19 3.3kΩ R47 10Ω/0.5W J17 NTC5 10Ω/0.5W PD_N_OPTO_HI VDDHVP_N_3 PD_N_3 MISO_IN_3 MOSI_OUT_3 SCK_OUT_3 CS_N_OUT_3 R4 CLK_OUT_3 IRQ_IN_3 GND_3 VSSA_3 Figure 4-1. Schematic of Atmel Evaluation Board ATA6870 0Ω J39-2 R29 GND_2 100Ω C33 10nF T15 R40 ZXMN2F34FH R98 0Ω 0Ω J39-1 R2 10μF 30V 100nF 100nF C5 C4 SCK_OUT_HV J9 CS_OUT_HV J11 CLK_OUT_HV J12 IRQ_IN_HV HCPL-181 AVDD + C46 36 R81 33μF 35 121kΩ 34 33 32 R75 3.3kΩ 31 R83 3.3kΩ 30 29 28 27 26 GND 25 R92 100kΩ GND @5 GND 24 DVDD DVSS ATST 23 R61 C47 220nF 1 2 3 37 VDDHVP 38 PD_N 39 MISO_IN MOSI_OUT 40 SCK_OUT 41 42 CS_N_OUT 43 CLK_OUT IRQ_IN VDDHV 44 45 47 46 MBAT7 CLK T20 ZXMN2F34FH DISCH6 AVSS IRQ CS_N 100Ω TEMPVSS MBAT1 13 J13-3 TEMP1 DISCH1 22 12 R18 MBAT2 TEMP2 VDDFUSE 11 TEMPREF ATA6870 DISCH2 CS_FUSE 10 1kΩ BIASRES MBAT3 21 9 1kΩ R80 IC2 DISCH3 SCANMODE 8 MBAT6 48 7 6 PWTST 20 T19 5 1kΩ R79 VDDHVM POW_ENA MBAT4 R77 330Ω J3 PD_N_OUT DISCH4 19 100Ω ZXMN2F34FH 1kΩ R73 MBAT5 DTST R60 0Ω 4 18 J13-4 R19 3 2 MFIRST ZXMN2F34FH 1kΩ R72 17 0Ω T22 DISCH5 MISO R48 R22 100Ω 1 MOSI 0Ω J13-5 1kΩ R71 SCK R43 ZXMN2F34FH 1kΩ R84 16 T23 14 100Ω 15 R85 O4 POW_ENA ON OFF 0Ω J13-6 R27 R76 270Ω J4 NTC4 100nF C6 J10 3.3kΩ 100nF C7 100nF 30V MOSI_OUT_HV R78 100nF R42 ZXMN2F34FH 100nF T24 C8 R28 100Ω C9 J13-7 C42 VDDHVP_HV MISO_OUT_HV J8 3.3kΩ + C2 J6 J7 R82 R70 10Ω/0.5W J5 NTC3 10Ω/0.5W 0Ω J13-2 R12 GND_1 100Ω C43 10nF T21 R62 ZXMN2F34FH R97 0Ω 0Ω J13-1 R39 J33 VDDHVP_HV J35 MISO_OUT_HV J36 MOSI_OUT_HV J38 SCK_OUT_HV J37 CS_OUT_HV C19 J40 CLK_OUT_HV 100nF 30V J50 IRQ_IN_HV 10Ω/0.5W R86 10Ω/0.5W + C3 10μF 30V 100nF 37 1 2 3 R90 0Ω 5.1kΩ ATA6870 [APPLICATION NOTE] VSSA_0 GND_0 R26 33 121kΩ R21 32 31 30 29 28 R23 3.3kΩ R13 27 3.3kΩ 26 100kΩ 2 1 J51 NTC2 3 1 2 SCK 10kΩ MIN R44 3 R93 25 10kΩ GND GND 24 DVDD 23 DVSS 22 VDDFUSE PD_N_OUT 34 J23 1 2 1 2 J52 NTC1 MAX D3 MISO VDD_MCU 35 first slave LED green C20 10nF J27 VDD_PULL 33μF R14 3kΩ J31 PD_N_OPTO_GND 1 2 0Ω J13-1 + C25 36 R94 VDDHVP 38 PD_N 39 MISO_IN MOSI_OUT 40 SCK_OUT 41 42 CS_N_OUT 43 CLK_OUT 44 IRQ_IN VDDHV 45 47 46 MBAT7 MBAT6 J20 1 2 3 GND R69 MOSI IRQ T9 ZXMN2F34FH 9162E–AUTO–07/15 R20 5.1kΩ ATST R1 100Ω 18 R17 5.1kΩ AVDD GND@5 0Ω J30-2 CLK 13 R68 ZXMN2F34FH AVSS IRQ CLK T8 TEMP1 TEMPVSS MBAT1 CS_N R6 100Ω VDD_MCU J30-3 TEMP2 DISCH1 CS_FUSE 12 MBAT2 21 11 ATA6870 DISCH2 SCANMODE 10 1kΩ TEMPREF 20 9 1kΩ R16 BIASRES MBAT3 19 8 VDDHVM PWTST IC1 DISCH3 C24 220nF POW_ENA MBAT4 1 2 first slave J14 PD_N_OUT DISCH4 DTST T7 6 18 R67 0Ω 100Ω ZXMN2F34FH 4 CS_N J30-4 0Ω T10 MFIRST 7 R8 1kΩ R15 100Ω 17 1kΩ R7 5 ZXMN2F34FH J30-5 DISCH5 MBAT5 MISO 1kΩ R5 3 MOSI 2 DISCH6 48 C16 C17 C18 C21 C22 1 SCK 0Ω R65 R9 1kΩ R3 16 R64 ZXMN2F34FH 1kΩ R24 15 T11 HCPL-181 VDD_HVM 14 100Ω C23 J30-6 R25 R96 330Ω POW_ENA ON OFF 0Ω R10 O1 1 2 3 100nF 100nF R63 ZXMN2F34FH 100nF T12 100nF R11 100Ω 100nF J30-7 R95 270Ω PD_N_OPTO_LO 15 13 11 9 7 5 3 1 WAN_16 VDD_MCU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X5 MA24-1-CAT MISO MOSI SCK CS_N CLK IRQ 1 WAN_16 16 14 12 10 8 6 4 2 X1 MA24-1-CAT VDD_HUM CLK GND_0 15 11 9 7 5 3 1 16 PD_N_OPTO_Hi MISO_IN_3 SCK_OUT_3 CLK_OUT_3 VSSA_3 GND_3 PD_N_OPTO_L0 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PD_N_OPTO_HI MOSI CS_N IRQ VDD_HUM PD_N_OUT 14 12 10 8 6 4 2 ST1 PD_N_OPTO_HI MOSI_OUT_3 CSN_OUT_3 IRQ_IN_3 VDD_HUP_3 PD_N_3 To upper BMS board MISO SCK CLK VSSA_0 GND_0 PD_N_OPTO_LO ST2 4.2 Interfaces to Controller Board and Additional Stacked Evaluation Boards Figure 4-2. Interfaces of the Atmel ATA6870 Evaluation Board AVR Board X1 AVR Board X5 To lower BMS board ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 19 4.3 Evaluation Board Layout and Component Placement Figure 4-3. Component Placement and Layout Top View 20 ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 Figure 4-4. Board Layout Bottom View ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 21 5. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 22 Revision No. History 9162E-AUTO-07/15 Put document in the latest template ATA6870 [APPLICATION NOTE] 9162E–AUTO–07/15 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9162E–AUTO–07/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Windows® is a registered trademark of Microsoft Corporation in the US and/or other countries.Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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