Features • • • • • • • • • • • • • • 12-bit Battery-cell Voltage Measurement Simultaneous Battery Cells Measurement in Parallel Cell Temperature Measurement Charge Balancing Capability – Parallel Balancing of Cells Possible Integrated Power Supply for MCU Undervoltage Detection Less than 10 µA Standby Current Low Cell Imbalance Current (< 10 µA) Hot Plug-in Capable Interrupt Timer for Cycling MCU Wake-ups Cost-efficient Solution Due to Cost-optimized 30V CMOS Technology Reliable Communication between Stacked ICs Due to Level Shifters with Current Sources and Checksum Monitoring of Data Daisy-chainable – Each IC Monitors up to 6 Battery Cells – 16 ICs (96 Cells) per String – No Limit on Number of Strings Package QFN48 7 mm × 7 mm Li-Ion, NiMH Battery Measuring, Charge Balancing and Power-supply Circuit Applications • Battery Measurement, Supply and Monitoring IC for Li-ion and NiMH Battery Systems in Electric (EV) and Hybrid Electrical (HEV) Vehicles Benefits • Highest Safety Level for Li-ion Battery Systems in Combination with ATA6871 • Cost Reduction Due to Integrated Measurement Circuit and High Voltage Power-supply ATA6870 Preliminary 1. Description The ATA6870 is a measurement and monitoring circuit designed for Li-ion and NiMH multicell battery stacks in hybrid electrical vehicles. The ATA6870 monitors the battery-cell voltage and the battery-cell temperature with a 12-bit ADC. The circuit also provides charge-balancing capability for each battery-cell. In addition, a linear regulator is integrated to supply a microcontroller or other external components. Reliable communication between stacked ICs is achieved by level-shifters with current sources. The ATA6870 can be connected to three, four, five or six battery-cells. Up to 16 circuits (96 cells) can be cascaded in one string. The number of strings is not limited. 9116B–AUTO–10/09 2. Block Diagram Figure 2-1. Block Diagram To ATA6870 above VDDHV MBAT7 Cell 6: Reference ADC Cell Balancing Standby Control Digital Level Shifter DISCH6 PD_N PD_N_OUT VDDHVP 3.3V Voltage Regulator MBAT6 POW_ENA VDDHVM AVDD 3.3V Internal Voltage Regulator DISCH1 Logic Cell 1: Reference ADC Cell Balancing Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 NTC NTC Cell Temperature Measuring Interchip and Microcontroller Communication Interface Test TEMP1 Digital Level Shifter TEMPREF TEMP2 TEMPVSS GND AVSS DVSS SCANMODE PWTST DTST CS_FUSE DVDD VDDFUSE MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MCU MFIRST ATST To ATA6870 below 2 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 3. Pin Configuration Table 3-1. 40 VDDHVP 41 MISO_IN 42 PD_N 43 SCK_OUT IRQ_IN 44 MOSI_OUT 45 CS_N_OUT 46 CLK_OUT 47 VDDHV 48 MBAT7 MBAT6 DISCH6 Pinning QFN48, 7 mm × 7 mm 39 38 37 DISCH5 1 36 MBAT5 2 35 PD_N_OUT DISCH4 3 34 POW_ENA VDDHVM MBAT4 4 33 PWTST DISCH3 5 32 BIASRES ATA6870 MBAT3 6 31 TEMPREF DISCH2 7 30 TEMP2 12 25 ATST 13 14 15 16 17 18 19 20 21 22 23 24 GND CLK DVDD AVDD DVSS AVSS 26 VDDFUSE 27 11 CS_FUSE 10 IRQ SCANMODE MBAT1 DTST TEMPVSS MFIRST TEMP1 28 MOSI 29 9 MISO 8 SCK MBAT2 DISCH1 CS_N Figure 3-1. Pin Description Pad Number Pad Name Exposed Pad Function Remark Heatslug 1 DISCH5 Output to drive external cell-balancing transistor 2 MBAT5 Battery cell sensing line 3 DISCH4 Output to drive external cell-balancing transistor 4 MBAT4 Battery cell sensing line 5 DISCH3 Output to drive external cell-balancing transistor 6 MBAT3 Battery cell sensing line 7 DISCH2 Output to drive external cell-balancing transistor 8 MBAT2 Battery cell sensing line 9 DISCH1 Output to drive external cell-balancing transistor 10 MBAT1 Battery cell sensing line 11 IRQ Interrupt output for MCU/ATA6870 below 12 CLK System clock 13 CS_N 14 SCK SPI clock input from MCU/ATA6870 below 15 MOSI Master Out Slave In input from MCU SPI data input 16 MISO Master In Slave Out output for MCU SPI data output 17 MFIRST Chip select input from MCU/ATA6870 below Select Master/Slave 3 9116B–AUTO–10/09 Table 3-1. 4 Pin Description (Continued) Pad Number Pad Name Function Remark 18 DTST Test-mode pin Keep pin open (output) 19 SCANMODE Test-mode pin Connected to VSSA 20 CS_FUSE Test-mode pin Connected to VSSA 21 VDDFUSE Test-mode pin Connected to VSSA 22 DVSS 23 DVDD Digital positive supply input (3.3V) 24 GND Ground 25 ATST Test-mode pin 26 AVDD 3.3V Regulator output Digital negative supply 27 AVSS 28 TEMPVSS 29 TEMP1 Temperature measuring input 1 30 TEMP2 Temperature measuring input 2 31 TEMPREF Reference voltage for temperature measuring 32 BIASRES Internal supply current adjustment 33 PWTST 34 POW_ENA Power regulator enable/disable 35 PD_N_OUT Power down output 36 VDDHVM Power regulator output to supply e.g. an external microcontroller 37 VDDHVP Power regulator supply voltage 38 PD_N Connected to AVDD Keep pin open (output) Analog negative supply Ground for temperature measuring Test - mode pin Keep pin open (output) Power down input 39 MISO_IN Master In Slave Out input from ATA6870 above 40 MOSI_OUT Master Out Slave In output for ATA6870 above 41 SCK_OUT SPI clock output for input of ATA6870 above 42 CS_N_OUT 43 CLK_OUT 44 IRQ_IN Interrupt input from ATA6870 above 45 VDDHV Supply voltage 46 MBAT7 Battery cell sensing line 47 DISCH6 Output to drive external cell-balancing transistor 48 MBAT6 Battery cell sensing line Chip select output for input of ATA6870 above System clock output for input of ATA6870 above ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 4. ATA6870 System Overview The ATA6870 can be stacked up to 16 times in one string. The communication with MCU is carried out on the lowest level through an SPI bus. The data on the SPI bus is transmitted to the 15 other ATA6870s using the communication interface implemented inside ATA6870. Figure 4-1. Battery Management Architecture with One Battery String ATA6870 ATA6870 ATA6870 ATA6870 MCU 5 9116B–AUTO–10/09 Figure 4-2. Battery Management Architecture with Several Battery Strings ATA6870 ATA6870 MCU OPTO ATA6870 ATA6870 MCU 6 To Battery Master Controller ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified all voltages to pin VSSA. Parameters Pin Symbol Min. Max. Unit Ambient temperature TA –40 +85 °C Junction temperature TJ –40 +125 °C TS –55 +150 °C VMBAT(i+1) VMBAT(i) –0.3 +5.5 V Storage temperature Battery cell voltage MBAT(i+1), MBAT(i) VVDDHV - VVMBAT7max VVDDHV - VVMBAT7 –5.5 +0.3 V MBAT1 VMBAT1 –0.3 +0.3 V VDDHVP VVDDHVP –0.3 +33.6 V VDDHV VVDDHV –0.3 +30 V Supply voltage DVDD (regulator is Off) DVDD VDVDD –0.3 +5.5 V Supply voltage AVDD (regulator is Off) AVDD VAVDD –0.3 +5.5 V Test-input VDDFUSE VVDDFUSE –0.3 +5.5 V Reference voltage for temperature measuring (regulator is Off) TEMPREF VTEMPREF –0.3 VDD+0.3 V Supply voltage VDDHVM (regulator is Off) VDDHVM V VDDHVM –0.3 +5.5 V Digital Ground DVSS VAVSS - VGND –0.3 +0.3 V Analog Ground AVSS VAVSS - VGND –0.3 +0.3 V AVSS, DVSS VAVSS - VDVSS –0.3 +0.3 V VMBAT1 Supply voltage power regulator Operating supply voltage Digital/Analog Ground Ground voltage for temperature measuring Input voltage for logic I/O pins Input voltage for analog I/O pins TEMPVSS VTEMPVSS –0.3 +0.3 V CLK, CS_N, SCK, MOSI, DTST, ATST, SCANMODE, MFIRST, POW_ENA, CS_FUSE, PWTST VCLK, VCS_N, VSCK, VMOSI, VDTST, VATST, VSCANMODE, VMFIRST, VPOW_ENA, VCS_FUSE, VPWTST –0.3 VDD + 0.3 V IRQ, MISO VIRQ, VMISO –0.3 +5.5 V –0.3 VDD + 0.3 V TEMP1, TEMP2, VTEMP1, VTEMP2, VBIASRES BIASRES Input voltage for digital high voltage input pins MISO_IN, IRQ_IN VMISO_IN, VIRQ_IN VDDHV – 0.3 VDDHV + 0.3 V Voltage at digital high voltage output pins MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT VMOSI_OUT, VSCK_OUT, VCS_N_OUT, VCLK_OUT VDDHV – 0.3 VDDHV + 0.3 V PD_N V PD_N VDDHV – 5.5 VDDHV + 0.3 V PD_N_OUT V PD_N_OUT –5.5 +0.3 V DISCH(i) VDISCH(i) VMBAT(i) – 0.3 VMBAT(i+1) + 0.3 V Input: PD_N Output: PD_N_OUT Voltage at cell balancing outputs 7 9116B–AUTO–10/09 5. Absolute Maximum Ratings (Continued) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified all voltages to pin VSSA. Parameters Pin Symbol HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Min. Max. Unit ±2 kV 500 V 750 V ±100 mA ESD 1, 12, 13, 24, 25, 36, 37, 48 Latch-up acc. to AECQ100-004, JESD78A LATCH-UP 6. Thermal Resistance Parameters Symbol Value Unit Max. thermal resistance junction-ambient(1) Rthjamax 20 K/W Max. thermal resistance junction-case RthjCmax TBD K/W Package. QFN48 7× 7 Note: 8 1. Package mounted on 4 large PCB (per JESD51-7) under natural convention as defined in JESD51-2. ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7. Circuit Description and Electrical Characteristics Unless otherwise specified all parameters in this section are valid for a supply voltage range of 6.9V < V D D H V < 30V and a battery cell voltage of V M B A T ( i + 1 ) – V M B A T ( i ) = 0V to 5V, –40°C < TA < 85°C. All values refer to pin VSSA, unless otherwise specified. 7.1 Operating Modes The ATA6870 has two operation modes. 1. Power-down Mode (PDmode) 2. Normal Mode (NORM Mode) 7.1.1 Power-down Mode In Power-down Mode all blocks of the IC are switched off. The circuit can be switched from Power-down to ON Mode or back via the PD_N input. If the pin is connected to VDDHV via an external optocoupler, for example, the circuit is in ON Mode. If several ATA6870 are stacked, the power-down signal must be only provided for the IC on the top level of the stack. The next lower IC receives this information from the PD_N_OUT output of its upper IC. The PD_N_OUT pin must be connected to either the PD_N pin of the next lower ATA6870 or to VSSA. 9 9116B–AUTO–10/09 Figure 7-1. Power-down VDDHV MBAT7 PD_N Digital Level Shifter Cell 6: Reference ADC Cell Balancing DISCH6 Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH1 Internal Biasing MBAT1 NTC Interchip and Microcontroller Communication Interface Test Cell Temperature Measuring TEMP1 NTC Digital Level Shifter TEMPREF TEMP2 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MFIRST VDDFUSE ATST DTST CS_FUSE PWTST SCANMODE DVSS GND TEMPVSS AVSS DVDD BIASRES Logic Digital Level Shifter MBAT2 VDDHV MBAT7 PD_N Digital Level Shifter Cell 6: Reference ADC Cell Balancing DISCH6 Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH1 Logic Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 TEMPREF NTC MCU MFIRST VDDFUSE ATST DTST CS_FUSE PWTST SCANMODE DVSS GND AVSS TEMPVSS 10 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK Test Cell Temperature Measuring TEMP1 NTC Interchip and Microcontroller Communication Interface Digital Level Shifter TEMP2 DVDD ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Table 7-1. Electrical Characteristics No. Parameters Pin Symbol Maximum allowed input current in Power-down 1.1 Mode (e.g., leakage current of an optocoupler) PD_N IPD_N 1.2 Input current in ON Mode PD_N IPD_N PD_N 1.3 Test Conditions Maximum voltage (pin PD_N left open) IPD_N = 0 to 50 µA Propagation delay time 1.4 from Power-down Mode to NORM Mode Min. Typ. Max. Unit Type* 50 µA A 5 mA A VVDDHV VPD_N 5 V A DVDD tVDDON 3 ms A DVDD tVDDOFF 10 ms A 2.5 min slope 1 mA I PD_N = -------------msec Propagation delay time 1.5 from NORM Mode to Power-down Mode *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.1.2 Normal Operating Mode (NORM Mode) The ATA6870 turns on when the PD_N signal is switched from low to high. The power supplies AVDD and DVDD as well as VDDHVM (if the input signal POW_ENA = high) are turned on. The configuration registers are set to their default values. In NORM Mode the ATA6870 can acquire analog data (voltage or temperature channels) upon request from the host microcontroller. When the host microcontroller orders an acquisition through the SPI bus, the IC starts digitizing all voltage and one temperature channel in parallel. The on-chip digital signal processor filters, in real time, the channel samples. When conversion and filtering are done, the data-ready interrupt to the host processor indicates the data availability. The MCU can now read the ADC result registers. The MCU reads the ATA6870’s status registers to check each IC and to acknowledge the interrupt. When ATA6870 is in NORM Mode, the MCU can be active or in idle mode. In order to wake-up the MCU by an interrupt, the Low Frequency Timer (LFT) can be activated in ATA6870. Interrupt is signaled with a high level on IRQ pin. The LFT is re-programmable on the fly and can be reset through SPI, but is not stoppable. Figure 7-2. ATA6870 in NORM Mode ASICs in NOMode Idle IRQ SPI MCU Acquisition Asserted ACQ Cmd Background task Send SPI Command Read status register Background task/Idle Interrupt Handling Idle Read data burst mode Background task Processing 11 9116B–AUTO–10/09 Table 7-2. Electrical Characteristics No. Parameters Test Conditions 2.1 Supply voltage 2.2 Current consumption IVDDHV (Normal Mode) Current consumption in Power-down mode 2.3 (PDmode) IVDDHV + IMBAT(i)max(1) VMBAT(i+1) – VMBAT(i) = 3.7V Pin Symbol Min. VDDHV VVDDHV 6.9 VDDHV IVDDHV Typ. VDDHV Imbalance from battery cell to battery cell in VMBAT(i+1) – 2.4 VMBAT(i) = 3.7V Power-down Mode (PDN Mode) MBAT(i+1) IMBAT(i+1) Max. Unit Type* 30 V A 15 mA A 10 µA A 10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Largest input current of the cell inputs MBAT(i) 7.2 Interface to Battery Cells Each input line MBAT(i) and the supply lines VDDHV, AVSS can be protected by additional resistors and a filter capacitor as shown below. Figure 7-3. External Components between ATA6870 and the Battery Cells R_VDDHV R_IN VDDHV MBAT(i+1) Discharge Resistor Battery cell(i) Cell(i) DISCH(i) R_IN R_VSS Battery cell Board MBAT(i) AVSS ATA6870 MBAT(i) are high impedance input (~2 MΩ). Thus, external components can be added to protect ATA6870 chip against current spikes and overvoltage at battery cell level. 12 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Table 7-3. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 3.1 R_IN MBAT(i) 1 kΩ D 3.2 R_VDDHV VDDHV 50 Ω D AVSS 50 Ω D 3.3 R_VSS *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.3 Reduced Number of Battery Cells Configuration It is possible for ATA6870 to operate with a reduced number of cells: 3, 4, 5, and 6 cell operation are possible. In these cases, the cell-chip inputs corresponding to the missing cells should be connected to the upper cell potential of the module. Connection with 4 Cells only VDDHV Figure 7-4. MBAT7 PD_N PD_N_OUT DISCH6 VDDHVP POW_ENA MBAT6 VDDHVM DISCH5 AVDD MBAT5 DVDD BIASRES DISCH4 MBAT4 ATA6870 MISO_IN DISCH3 MOSI_OUT MBAT3 SCK_OUT CS_N_OUT CLK_OUT DISCH2 IRQ_IN MBAT2 CS_N DISCH1 SCK MFIRST VDDFUSE ATST DVSS TEMPVSS GND TEMP1 AVSS TEMP2 DTST MISO CS_FUSE MOSI TEMPREF SCANMODE MBAT1 IRQ CLK Battery cell 1 (MBAT1, MBAT2) and battery cell 6 (MBAT6, MBAT7) must always be used for the lowest/highest cell. 13 9116B–AUTO–10/09 7.4 ATA6870 External MCU Supply The ATA6870 provides a 3.3V power-supply for external components such as the microcontroller unit (MCU). The input pin for this supply is pin VDDHVP, and the output pin is VDDHVM. This regulator is able to supply the MCU directly from the topmost battery cell of a string. The power regulators of all stacked ATA6870 are therefore put in serial configuration to avoid imbalance.The regulator can be disabled with the digital input pin POW_ENA. Table 7-4. Truth Table Pin Symbol POW_ENA VPOW_ENA Value Function Low Voltage regulator disabled High Voltage regulator enabled Logic levels: Low = VDVSS, High = VDVDD 14 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-5. MCU Supply with the Internal Power Supply VDDHV MBAT7 PD_N Digital Level Shifter Standby Control Cell 6: Reference ADC Cell Balancing DISCH6 PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH1 Logic Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 Cell Temperature Measuring TEMP1 Interchip and Microcontroller Communication Interface Test Digital Level Shifter TEMPREF TEMP2 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MFIRST VDDFUSE ATST DTST CS_FUSE SCANMODE PWTST DVSS GND TEMPVSS AVSS DVDD + VDDHV MBAT7 PD_N Standby Control Digital Level Shifter Cell 6: Reference ADC Cell Balancing DISCH6 PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH2 Logic Digital Level Shifter MBAT2 BIASRES TEMPREF Interchip and Microcontroller Communication Interface Digital Level Shifter Test Cell Temperature Measuring TEMP1 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MCU MFIRST VDDFUSE ATST DTST CS_FUSE SCANMODE PWTST DVSS GND TEMPVSS AVSS + Internal Biasing MBAT1 TEMP2 DVDD 15 9116B–AUTO–10/09 Table 7-5. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 33.3 V A 3.5 V A 4.1 Supply voltage VDDHVP VVDDHVP 6.9 4.2 Output voltage VDDHVM VVDDHVM 3.1 VDDHVM IVDDHVM 20 mA A VDDHVM IVDDHVM 50 mA A 4.3 DC output current 4.4 Peak output current (1) 3.3 (2) VDDHVM 30 33 µF D 4.6 Capacitor load(2) VDDHVM 200 220 nF D V A V A V C µA A 4.5 Capacitor load 0.7 × VDVDD 4.7 High level input voltage POW_ENA VPOW_ENA 4.8 Low level input voltage POW_ENA VPOW_ENA 4.9 Hysteresis POW_ENA VPOW_ENA 0.05 × VDVDD POW_ENA IPOW_ENA –1 4.10 Input current VPOW_ENA = 0V to VDVDD 0.3 × VDVDD +1 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Maximum current the power regulator can provide, time limited by thermal consideration only 2. These capacitors are mandatory 16 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-6. MCU Supply with an External Power Supply VDDHV MBAT7 PD_N Digital Level Shifter Standby Control Cell 6: Reference ADC Cell Balancing DISCH6 PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM MBAT6 AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH2 Logic Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 Cell Temperature Measuring TEMP1 Interchip and Microcontroller Communication Interface Test Digital Level Shifter TEMPREF TEMP2 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MFIRST VDDFUSE ATST DTST CS_FUSE PWTST SCANMODE AVSS DVSS TEMPVSS GND DVDD VDDHV MBAT7 PD_N Standby Control Digital Level Shifter Cell 6: Reference ADC Cell Balancing DISCH6 PD_N_OUT VDDHVP 3.3V Voltage Regulator MBAT6 POW_ENA VDDHVM AVDD ATA6870 3.3V Internal Voltage Regulator Cell 1: Reference ADC Cell Balancing DISCH2 Logic Digital Level Shifter MBAT2 BIASRES Internal Biasing MBAT1 Cell Temperature Measuring TEMP1 Interchip and Microcontroller Communication Interface Test Digital Level Shifter TEMPREF TEMP2 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MCU MFIRST VDDFUSE ATST DTST CS_FUSE PWTST SCANMODE AVSS DVSS TEMPVSS GND DVDD 17 9116B–AUTO–10/09 7.5 7.5.1 Analog Blocks Battery Voltage Measuring Figure 7-7. Block Diagram Battery Voltage Measurement External ATA6870 1.666V Reference DVDD gain MBAT(i+1) Cell i MBAT(i) 12 bits incremental ADC High voltage level shifter (digital) DISCH(i) Bitstream CLK MUX Disch(i) DVSS The battery voltage measurement block contains • a 3-input multiplexer • a voltage reference, • a 12-bit ADC • the upper part of digital voltage level shifters 7.5.1.1 Input Multiplexer The multiplexer has 3 inputs. Each of the functions are described in the table below: Table 7-6. Inputs of the Multiplexer Input Function V(MBAT(i+1), MBAT(i)) Input voltage measurement V(VREF(i)) Gain error acquisition of ADC V(MBAT(i), MBAT(i)) Offset error acquisition of ADC The multiplexer inputs are controlled by SPI. 18 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.1.2 12 Bits Incremental ADC The purpose of this cell is to convert an analog input into a 12-bit digital word. Table 7-7. Electrical Characteristics No. Parameters Test Conditions 5.1 Accuracy of voltage channel(1) Maximum input noise 0.5 mVrms Pin MBAT(i+1), MBAT(i) Accuracy of voltage channel(1)(2) Maximum input noise MBAT(i+1), 0.5 mVrms MBAT(i) VMBAT(i+1) – VMBAT(i) = 3.6V 5.3 Input voltage range MBAT(i+1), MBAT(i) 5.2 Symbol VMBAT(i+1), VMBAT(i) Min. Typ. Max. Unit Type* –10 +10 mV A –7 +7 mV A 0 5 V A 5.4 Input resolution (1 LSB) VLSB 1.5 mV A 5.5 Reference voltage VRef 1.667 V D 5.6 Offset voltage MBAT(i+1), MBAT(i) VMBAT(i+1), VMBAT(i) 410 LSB A 5.7 Gain voltage MBAT(i+1), MBAT(i) VMBAT(i+1), VMBAT(i) 655 LSB/V A kHz D 5.8 System clock CLK fCLK 5.9 SPI interface clock SCK fSCK (3) 12 tconv = (2 5.10 Conversion rate + 1) / fCLK MBAT(i+1), MBAT(i) 5.11 Input bandwidth 450 500 550 0.5 × fCLK D tconv 8.194 ms D fBW 50 Hz D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. The accuracy of the voltage channels is guaranteed with no external resistor in the MBAT(i), MBAT(i+1) lines. 2. Reduced temperature range (–20°C to + 65°C) 3. Conversion rate without readout times of SPI Figure 7-8. ADC output 3686D = 0.9D*212 Slope = (1502D - 410D)/1.667 = 655DLSB/V ADC (VREF) 1502D 410D = 0.1*212 0 0 VREF 5 Input Voltage (MBATi+1, MBATi) 19 9116B–AUTO–10/09 In order to correct offset and gain, MBATi and VREF are measured: adc ( VREF i ) – adc ( MBAT i ) Slope = ---------------------------------------------------------------------v ( VREFi ) (1) Offset = adc(MBATi) adc(MBATi+1) = Slope × v(MBATi+1, MBATi) + Offset adc ( MBATi+1 ) – adc ( MBAT i ) v ( MBAT i+1 MBAT i ) = ----------------------------------------------------------------------------- × v ( VREF i ) adc ( VREF i ) – adc ( MBATi ) Table 7-8. (2) Ideal ADC ADC Input Ideal ADC Output Code Comments 0V 410 0.1 × 212 VREF = 1.667V 1502 2.2V 1851 2.5V 2048 3V 2375 3.7V 2834 5V 3686 0.5 × 212 0.9 × 212 12 adc ( MBAT i+1 ) – 0.1 × 2 v ( MBAT i+1 MBAT i ) = 1.667 × ------------------------------------------------------------------12 1502 – 0.1 × 2 (3) v(MBATi+1, MBATi) = 1.52656 × 10–3 × (adc(MBATi+1) – 410) Using this equation, the round error is less than one mV. 5 = 1.5 mV LSB = -----------------------------------------------------12 12 0.9 × 2 – 0.1 × 2 Compensation with 1st Order Correction As the MCU cannot perform a division operation, 1 ---------------------------------------------------------------------- is approximated in a first order polynomial equation: adc ( VREF i ) – adc ( MBAT i ) [ adc ( VREF i ) – 1502 ] – [ adc ( MBAT i ) – 410 ] 1 --------------------------------- – ------------------------------------------------------------------------------------------------------------------2 ( 1502 – 410 ) ( 1502 – 410 ) 20 (4) ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] With equation (3) and (4) we get the formula for calculating the analog input voltage (without division): [ adc ( VREF i ) – 1502 ] – [ adc ( MBAT i ) – 410 ] 1 v ( MBAT i+1 , MBAT i ) = 1.667 × --------------------------------- – ------------------------------------------------------------------------------------------------------------------- × [ adc ( MBATi+1 ) – adc ( MBAT i ) ] 2 ( 1502 – 410 ) ( 1502 – 410 ) 7.5.1.3 Acquisition Time and Clocking The acquisition time depends on the number of ATA6870s to be addressed. Table 7-9. Electrical Characteristics Number of ATA6870 SCK Frequency (kHz) CLK Frequency (kHz) Conversion Time (ms) Total Acquisition Duration (ms)(1) 1 250 500 8.2 9.5 2 250 500 8.2 10.2 3 250 500 8.2 10.8 4 250 500 8.2 11.5 5 250 500 8.2 12.2 6 125 500 8.2 17.0 7 125 500 8.2 18.4 8 125 500 8.2 19.7 9 125 500 8.2 21.1 10 62.5 500 8.2 36.1 11 62.5 500 8.2 38.8 12 62.5 500 8.2 41.5 13 62.5 500 8.2 44.2 14 62.5 500 8.2 46.8 15 62.5 500 8.2 49.5 16 62.5 500 8.2 52.2 Notes: 1. The total acquisition time takes the following into account: - ADC conversion - Reading of voltage values in burst mode for all ATA6870 devices, - Reading of temperature values for all ATA6870 devices (only one temperature input is read). SPI clock (pin SCK) must a maximum of half the frequency of the system clock CLK. 21 9116B–AUTO–10/09 7.5.2 Battery Cell Discharge Each battery cell can be discharged with an external resistor and an NMOS transistor. Figure 7-9. External Circuit for Cell Balancing R_VDDHV R_IN VDDHV MBAT(i+1) Discharge Resistor Battery cell(i) Cell(i) DISCH(i) R_IN R_VSS Battery cell MBAT(i) AVSS Board ATA6870 The pin DISCH(i) (Discharge for battery cell i) is intended to switch on the external discharge resistor in parallel to the battery cell to bypass charge current for cell balancing reasons. The pin DISCH(i) is a digital output: No discharge: VDISCH(i) = VMBAT(i) Discharge: VDISCH(i) = VMBAT(i+1) Table 7-10. Electrical Characteristics No. Parameters Test Conditions 6.1 Operating voltage range Pin Symbol Min. MBAT(i) MBAT(i+1) – MBAT(i) 1.5 Typ. Max. Unit Type* 5 V A 6.2 High-level output voltage IDISCH(i) = –10 µA, MBAT(i+1) – MBAT(i) = 1.5V to 5V DISCH(i) VDISCH(i) – VMBAT(i) VMBAT(i+1) – 50 mV V A 6.3 High-level output voltage IDISCH(i) = –1 mA MBAT(i+1) – MBAT(i) = 3V to 5V DISCH(i) VDISCH(i) – VMBAT(i) VMBAT(i+1) – 0.6V V A kΩ A 6.4 Pull-down resistor(1) DISCH(i)MBAT(i) 60 140 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Integrated pull-down resistor between pins DISCH(i) and MBAT(i) 22 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.3 Temperature Channel The temperature sensors are based on a resistor divider using a standard resistor and an NTC resistor. This resistor divider is connected to the reference of the ADC for temperature measuring. As the ADC is sharing same reference value, the output of temperature measurement with ADC is ratio metric. Figure 7-10. Battery Cell Temperature Measurement AVDD TEMPREF RES_REF2 1.2V Reference RES_REF1 TEMP1 TEMP2 12 bits Incremental ADC OUT RES_NTC1 RES_NTC2 Operation Register TEMPVSS During one measuring cycle only one temperature input can be measured by the ADC. The channel can be selected in the Operation Register (0x02) by the TempMode bit (bit 3). The ADC output is equal to: RES_NTC(1) 8- – ----8-⎞ out = 2048 × ⎛ 1 + --------------------------------------------------------------------------------- × ----⎝ (RES_NTC(1) + RES_REF(1)) 15 10⎠ Table 7-11. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* TEMPREF VTEMPREF – VTEMPVSS 1.1 1.2 1.3 V A TEMPREF ITEMPREF 2 mA A 7.3 Input voltage range TEMP1 VTEMP1 0 VTEMPREF V A 7.4 Input voltage range TEMP2 VTEMP2 0 VTEMPREF V A 7.5 Resistor RES_REF RES_REF 1.2 7.6 Resistor RES_NTC RES_NTC 7.1 Reference voltage 7.2 Reference voltage output current Code output for 7.7 value(RES_NTCx) = value (RES_REFx) 22 kΩ D 800 kΩ D V(TEMPi, TEMPVSS) = 0.5 × V(TEMPREF, TEMPVSS) 931D 956D 981D A 7.8 Code output for value(RES_NTC) = 0 V(TEMPi, TEMPVSS) =0 385D 410D 435D A 7.9 Code output for V(TEMPi, TEMPVSS) value(RES_NTC) = infinite = V(TEMPREF) 1477D 1502D 1527D A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 23 9116B–AUTO–10/09 7.5.4 Internal Voltage Regulator The regulator output is pin AVDD. The pins AVDD and DVDD have to be connected together. An external filtering capacitor (10 nF recommended) is used to filter and stabilize the function. The regulator output can be used to supply outside functions at the price of power supply imbalance between battery cells. Table 7-12. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. VDDHV VVDDHV 6.9 8.2 Regulated output voltage AVDD VAVDD 3.1 8.3 Output current AVDD IAVDD 0 8.1 Supply voltage range 8.4 Cload (load capacitor) Cload 9 Typ. 3.3 Max. Unit Type* 30 V A 3.5 V A 5 mA A nF D 10 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.5.5 Central Biasing This block generates a precise bias current to supply internal blocks of the IC. Connection of any external loads to this pin is not allowed. Table 7-13. Electrical Characteristics No. Parameters Test Conditions 9.1 Biasing voltage Pin Symbol Unit Type* BIASRES VBIASRES 1.2 V A RRefbias 121 kΩ D +1 % D 50 pF D 9.2 External resistor ΔRRefbias 9.3 Tolerance Maximum external parasitic 9.4 capacitor BIASRES Min. –1 CExternal Typ. Max. *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Figure 7-11. Internal Bias Current Generation IBIAS Bandgap 1.2V BIASRES RREFBIAS 121 kΩ 24 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.6 RC Oscillator Table 7-14. Internal RC Oscillator Frequency No. Parameters Test Conditions Pin 10.1 Oscillator frequency Symbol Min. Typ. Max. Unit Type* fOsc 45 50 55 kHz A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.5.7 Power On Reset The Power On Reset is used to initialize the digital part at power-up. The Power On Reset circuit is functional when the voltage at pin DVDD is larger than VPOROP. There are two reset sources: System “hard reset” System hard reset occurs when the voltage at pin DVVD goes below the Power On Reset threshold. ATA6870 registers are set to their initial values. After t = tRESET, the MCU can access the ATA6870. Figure 7-12. Power On Reset VPOROFF VPORON VPOROP VDVDD VPOR Table 7-15. Electrical Characteristics No. Parameters Pin Symbol 11.1 Power On Reset Functional DVDD VPOROP 11.2 Power On Reset Off DVDD VPOROFF 1.5 DVDD VPOROFF – VPORON 0.03 11.3 Power On Reset Hysteresis 11.4 Power On Reset Time Test Conditions tRESET Min. Typ. Max. Unit Type* 0.8 V A 2.5 V A V C µs A 800 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 25 9116B–AUTO–10/09 7.6 7.6.1 Digital Part General Features The digital parts of the ATA6870 includes the following blocks: • 4-Wire-SPI Full Duplex Communication with External Host MCU • SPI System Protocol Management (Frames Decoding) and Configuration Registers Bank • Interrupt to MCU Management • Operations Decoding (Voltage and/or Temperature Acquisition) and Analog Part Control • Low Frequency Timer (50 kHz) for Wake-up Management 7.6.2 Host Interface Figure 7-13. Host Interface VDDMicrocontroller Unit CS_N VDVDD SCK SPI Master SPI MOSI MFIRST MISO MCU IRQ SPI Slave ATA6870 (1) The communication between ATA6870 (1) and its host MCU, as well as ATA6870 (n) and ATA6870(n-1) is based on a 4 wire serial/parallel SPI interface (CS_N, SCK, MISO, MOSI) and an interrupt line (IRQ). The SPI interface allows register read and write operations. The interrupt line indicates events that require host intervention. ATA6870(n)’s 4 wire-SPI bus inputs (CS_N, SCK, MOSI) are up-shifted through level shifters. They are internally connected to the outputs CS_N_OUT, SCK_OUT, MOSI_OUT and connected to ATA6870(n+1) (CS_N, SCK, MOSI). ATA6870(n)’s 4 wire-SPI bus output (MISO) and ATA6870(n)’s interrupt (IRQ) are down-shifted through level shifters and connected to ATA6870(n-1) (MOSI_IN, IRQ_IN) or host MCU (n = 1). 26 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.3 Interrupt In NORM Mode (Normal Mode), the reasons for an interrupt request are: • The availability of measured data (data ready) When a voltage measurement is completed, the dataRdy flag is set in the status register. The ATA6870 cannot decode any new incoming operation until the dataRdy flag is released. • The low frequency timer (LFT) elapses (wakeup) The wakeup flag is set in the status register when the LFT elapses. The LFT is controlled via the SPI interface. • A transmission error is flagged during the last SPI transaction (the commError bit is set in the status register). • If an undervoltage condition occurs. The undervoltage function is controllable via SPI interface. A mask bit in the irqMask register corresponds to each interrupt source. The MCU must read the ATA6870 status register before the interrupt is cleared. With each SPI access a 16-bit IRQ state is sent via MISO to the MCU with the interrupt state of all stacked ATA6870 (see Section 7.6.4.1 “SPI Transaction Fields” on page 27). In PDmode (Power Down), if the digital control part and MCU are not supplied, neither SPI command nor interrupt are transmitted over the interface. 7.6.4 SPI Interface The full duplex SPI interface block allows communication with the host MCU using four wires (MISO, MOSI, SCK and CS_N). SPI transactions are based on a byte-access MSB first protocol. 7.6.4.1 SPI Transaction Fields Most of the time, the SPI frame is defined by 4 distinct fields: IDENTIFICATION (2 bytes): 16-bit chip identification (MOSI), in parallel 16-bit IRQ state (MISO) CONTROL (1 byte): 7-bit register address + 1-bit read/write information (MOSI) DATA (k byte): k*8 bits data (MOSI or MISO depending on the access direction) CHKSUM (1 byte): 8 bits if the Chksum_ena bit is set in the Ctrl register (register 0x01, bit 4) 27 9116B–AUTO–10/09 Figure 7-14. SPI Transaction Fields Organization byte1 byte2 byte3 byte4 byte5 to n-1 MOSI ChipID1 ChipID0 CONTROL DATA .... MISO IRQID1 IRQID0 byte n CS_N CHKSUM (1) CHKSUM (1) SPI write access CS_N MOSI ChipID1 ChipID0 MISO IRQID1 IRQID0 CONTROL DATA .... SPI read access Note: 7.6.4.2 1. Only send if chksum_ena bit set to 1 in the Ctrl register Identification Field ATA6870 Chip Identification The two chip identification bytes are sent over MOSI to the ATA6870(n) in the chain. The ATA6870(n) checks the LSB. When LSB=1, the information is for this device. The SPI address will be decoded and the information processed. Independent from this the identification bytes are shifted by one bit to the right and transferred to the next ATA6870(n) in the chain. The 2 identification bytes allows the identification of up to 16 ATA6870s. . 28 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-15. Identification Field: Chip-ID Reception IDENTIFICATION FIELD CS_N ATA6870 (1) MOSI_IN 0x00 0x08 CONTROL DATA ATA6870 (2) MOSI_IN 0x00 0x04 CONTROL DATA ATA6870 (3) MOSI_IN 0x00 0x02 CONTROL DATA ATA6870 (4) MOSI_IN 0x00 0x01 CONTROL DATA ATA6870 (n>4) MOSI_IN 0x00 0x00 CONTROL DATA ATA6870 (1->3) identification field has lsb = 0 => device is not affected. ATA6870 (4) identification Shift it ”on the fly” once field has lsb = 1 => decode to the right SPI access. Shift it ”on the fly” once to the right 7.6.4.3 ATA6870 (>4) identification field has lsb = 0 => device is not affected. Shift it ”on the fly” once to the right ATA6870 IRQ Identification Figure 7-16. IRQ Propagation Scheme IRQ_IN IRQ irq_int ATA6870 (n) IRQ_IN IRQ irq_int ATA6870 (n-1) IRQ_IN IRQ irq_int MCU ATA6870 (1) 29 9116B–AUTO–10/09 ATA6870(n) IRQ output is connected to ATA6870(n-1) IRQ_IN input. ATA6870(n-1) IRQ output is a logic OR between IRQ_IN and its internal irq_int signal. ATA6870(1) IRQ output is connected to MCU. Figure 7-17. Identification Field: Interrupt State Emission CS_N ATA6870 (1) MISO 0x20 0x00 ATA6870 (2) MISO 0x40 0x00 ATA6870 (3) MISO 0x80 0x00 ATA6870 (16) MISO 0x00 0x00 Master SPI receives identification word = 0x2000 = 213 = 2m. This means ATA6870 number (16-m = 16-13) = 3 has IRQ pending. Others ATA6870s assert the MSB of the first byte to 0. Others bits are those coming from upper ATA6870, shifted once to the right. ATA6870 (3) IRQ is set. => ATA6870 (3) sets the MSB of the first byte to be shifted out. Others bits are those coming from upper ATA6870, shifted once to the right. Note: n = IC number m = bit number m = n -1 1 < = n < = 16 0 < = m < = 15 With each SPI access, a 16- bit IRQ state is send via MISO synchronous to the identification field to the MCU with the interrupt state of all stacked ATA6870. The MCU, interrupted by an ATA6870, has to send the identification field to check the IRQ levels (in that case the checksum is not considered). It is also possible to continue the transaction with CONTROL and DATA field. The MCU decodes the identification field shifted in MISO input. When bit m is set, ATA6870(16-m) is requesting interrupt. Figure 7-18. Identification Field CS_N SCK MOSI MISO 30 M(16) M(15) M(14) M(13) M(12) M(11) M(10) M(9) I(1) I(2) I(3) I(4) I(5) I(6) I(7) I(8) M(8) M(7) M(6) M(5) M(4) M(3) M(2) M(1) I(9) I(10) I(11) I(12) I(13) I(14) I(15) I(16) ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.4.4 CONTROL Field The CONTROL field defines the register to access and the direction (read/write). The size of the data (8, 16, or 112 bits) is defined by the address value in the CONTROL field. Table 7-16. Control Field CONTROL Field 7.6.4.5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 A6 A5 A4 A3 A2 A1 A0 W/Rd DATA Field The DATA field can be composed of 1, 2, or 14 bytes depending on the accessed register. Irrespective of the data direction, a byte is always transmitted with MSB first; a multi-byte word is transmitted with MSByte first. Figure 7-19. CONTROL and DATA Fields - 8-bits Register Write CS_N SCK MOSI A(6) A(5) A(4) MISO A(3) A(2) A(1) A(0) 1 D(7) D(6) Data not relevant D(5) D(4) D(3) D(2) D(1) D(0) D(1) D(0) Data not relevant Figure 7-20. CONTROL and DATA Fields - 8-bits Register Read CS_N SCK MOSI MISO A(6) A(5) A(4) A(3) A(2) A(1) Data not relevant A(0) 0 Data not relevant D(7) D(6) D(5) D(4) D(3) D(2) Figure 7-21. CONTROL and DATA Fields - 16-bits Register Write CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) MISO Data not relevant 1 D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8) Data not relevant D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Data not relevant 31 9116B–AUTO–10/09 Figure 7-22. CONTROL and DATA Fields - 16-bits Register Read CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) MISO 0 D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8) Data not relevant D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) In order to retrieve results from all channels in one ATA6870 without having to request for each channel, an SPI 112-bit read-only "burst access" (dataRd16Burst register; address = 0x7F) is implemented. When requested, the ATA6870 outputs its 6 voltage channels V6 to V1 and one of the two temperature channels T2 and T1 in sequence on the SPI bus. The diagrams below show the CONTROL and DATA fields of such an access. Figure 7-23. CONTROL and DATA Fields - 112-bits Register Read CS_N SCK MOSI 1 1 1 MISO 1 1 1 1 0 0 Data not relevant 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel V6 CS_N SCK MOSI MISO 0 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel V1 CS_N SCK MOSI MISO 0 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel temperature T1 or T2 32 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] One ATA6870 frame corresponds to the set of results obtained in one ATA6870. An ATA6870 frame is formatted as follows: Figure 7-24. SPI Access to dataRd16burst Register 0x7F Voltage channels Temp channel 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADCT Padding: 0x00 msb 12-bit ADC data lsb When reading data of chained ATA6870, data is transferred as follow: Figure 7-25. Example with two ATA6870 in a Chain CS_N SCK MOSI SPI Clock Rd Reg command chip1 MISO 7.6.4.6 SPI Clock Rd Reg command chip2 ATA6870 #1 Frame ATA6870 #2 Frame Communication Error Correct communication can be verified using various functions of the ATA6870. For internal synchronization, it is mandatory to keep CLK running during any SPI access; CLK must be set on 4 clock cycles (at least) before SPI access starts, and must be kept on 4 clock cycles (at least) after SPI access ends up. Keeping at least 4 CLK clock cycles between two consecutive SPI accesses is mandatory. If this is not the case, the ATA6870s will detect an error in communication. The CommError bit will be set in the Status Register 0x06). Figure 7-26. SPI Access and CLK Activity CLK OFF CLK ON 4 clk_ticks CLK_OFF 4 clk_ticks SPI ACCESS 4 clk ticks SPI ACCESS The ATA6870 verifies that complete bytes (8 bits long) are always transmitted. A transition starts when CS_N goes to low and it ends when CS_N goes to high. The number of clock cycles (signal CLK) is monitored during the transition. This number of clock cycles has to be modulo 8. If the CS_N length is not modulo 8 clock cycles, the bit CommError is set in the Status register. This will cause an interrupt to the MCU if the CommError is not masked by the commErrorMsk bit in the IrqMask register. 33 9116B–AUTO–10/09 7.6.4.7 CHKSUM Field The ATA6870 provides the possibility of verifying the transmitted data using a checksum. Setting chksum_ena bit to 1 in the Ctrl register (default = 0) activates the checksum feature. The chksum field is an 8-bit checksum computed from the proceeding data (control and data fields, byte 3 to byte n-1). It is based on the polynomial x8+x2+x1+1. The way it is computed is depicted below: Figure 7-27. LFSR-based Checksum Computation F0i serial bitstream MSB first F1i z-1 F2i z-1 F3i z-1 F4i z-1 F5i z-1 F6i z-1 F6o z-1 The checksum is calculated from the CONTROL field and DATA field by a polynomial division. The DATA field can consist of 1 byte up to 14 bytes (112-bit read-only “burst access”). The IDENTIFICATION field (2 bytes) is not used to generate the checksum. The checksum is always sent by the microcontroller, independent of read write mode. The checksum is in the LFSR (Linear Feedback Shift Register) when the complete bitstream (the whole fields of the transaction) followed by 0x00 have been shifted in the LFSR. The checksum verification on the complete data transmission was OK when the complete bitstream followed by the checksum have been shifted in the LFSR, and the content of the LFSR is 0x00. If this is not the case, the receiving ATA6870 will set the chkError bit in the status register. This will cause an interrupt to the MCU if the chkError is not masked by the chkErrorMsk bit in the IrqMask register. See the example below. The checksum is serially computed from the 8-bit value 0x57. So the bitstream 0x5700 is shifted in the LFSR. The resulting checksum is [f6o, f6i, f5i … f0i] at the last shift in cycle: Table 7-17. 5D 7D 0D 34 checksum = [f6o, f6i, ... f0i] = 0xA2 Input f01 f1i f2i f3i f4i f5i f6i f6o X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Table 7-17. checksum = [f6o, f6i, ... f0i] = 0xA2 (Continued) Input f01 f1i f2i f3i f4i f5i f6i f6o X 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0D 0x2 0xA During an SPI write access, the checksum is computed by the MCU and sent MSB first in the CHKSUM field. For an SPI read access, the checksum is computed by the ATA6870 and is checked by the MCU. During CHKSUM, MCU has to send 0x00 on MOSI, and must check that its own LFSR equals 0x00 at the end of CHKSUM field. 7.6.4.8 Device Position For the ATA6870 (1), this is the device on the lowest level, the SPI has to work as a standard logic CMOS interface to the MCU. The SPI’s between stacked ATA6870 have to work as level-shifters based on current sources. These different physical interfaces can be selected by the Pin MFIRST. Table 7-18. Device Position MFIRST Table 7-19. Configuration 0 ATA6870 (2) to ATA6870 (n) 1 ATA6870 (1) Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. 0.7 × DVDD 12.1 High level input voltage MFIRST MFIRST 12.2 Low level input voltage MFIRST MFIRST 12.3 Hysteresis MFIRST MFIRST 0.05 × DVDD MFIRST MFIRST –1 12.4 Input current VMFIRST = 0V to VDVDD Typ. Max. 0.3 × DVDD +1 Unit Type* V A V A V C µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 35 9116B–AUTO–10/09 7.6.5 Digital Inputs and Outputs 7.6.5.1 Digital Output Characteristics Digital Output Characteristics (MISO, IRQ) If the ATA6870 is configured as first IC (master) in a string (MFIRST = 1), these pins are configured as an open drain output. If the ATA6870 is configured to be a stacked IC (MFIRST = 0), the output signals MISO and IRQ coming from the upper IC need to be transferred to the MISO and IRQ outputs of the master in the string via the MISO_IN and IRQ_IN inputs. In this case the MISO and IRQ outputs act as level shifters based on current sources. Table 7-20. Electrical Characteristics No. Parameters Test Conditions 13.1 Low level output voltage IOUT = +5 mA MFIRST = 1 Pin MISO, IRQ Symbol Min. Typ. VMISO, VIRQ Max. Unit Type* 0.2 × VDD V A 13.2 Low level output current ±0.3V, MFIRST = 0 MISO, IRQ IMISO, IIRQ –13 –8 µA A 13.3 High level output current ±0.3V, MFIRST = 0 MISO, IRQ IMISO, IIRQ –65 –40 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Digital Output Characteristics (MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT) These outputs act as level shifters based on current sources. They transfer the input signals MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT to the next IC above. If the ATA6870 is the IC on the top level of a string, these outputs must be connected to VDDHV. Table 7-21. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. 14.1 Low level output current VDDHV + 1V to VDDHV + 2V (1) V(1) 14.2 High level output current VDDHV + 1V to VDDHV + 2V (1) V(1) Typ. Max. Unit Type* 25 55 µA A –1 +1 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT 36 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.5.2 Digital Input Characteristics Digital Input Characteristics (MISO_IN, IRQ_IN) Table 7-22. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. 15.1 Low level input current (VDDHV + 1.4V) ±0.3V MISO_IN, IRQ_IN IMISO_IN IIRQ_IN 13 15.2 High level input current (VDDHV + 1.4V) ±0.3V MISO_IN, IRQ_IN IMISO_IN IIRQ_IN Typ. Max. Unit Type* µA A µA A Max. Unit Type* DVDD V A 0.3 × DVDD V A V C 40 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Digital Input Characteristics (CS_N, SCK, MOSI, CLK) Table 7-23. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. 0.7 × DVDD Typ. 16.1 High level input voltage MFIRST = 1 (1) V(1) 16.2 Low level input voltage MFIRST = 1 (1) V(1) 16.3 Hysteresis MFIRST = 1 (1) V(1) 16.4 High level input current MFIRST = 1 I(1) 50 100 µA A 16.5 Low level input current MFIRST = 1 I(1) –130 –70 µA A 16.6 Low level input current MFIRST = 0, V(1) = 1V to 2V (1) I(1) –55 –35 µA A 16.7 High level input current MFIRST = 0 V(1) = 1V to 2V (1) I(1) –1 +1 µA A Max. Unit Type* 0.1 × DVDD *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. CS_N, SCK, MOSI, CLK Table 7-24. Propagation Delay Timing No. Parameters Test Conditions Pin Symbol Min. Typ. Propagation delay Upper IC to lower IC Rpull-up = 5.1 kΩ Load capacitor max. = 15 pF MFIRST = 0, 1 > 10% input to > 90% output (1) 110 ns A Propagation delay 17.2 Lower IC to upper IC Rpull-up = 5.1 kΩ Load capacitor max. = 15 pF MFIRST = 0, 1 > 10% input to > 90% output (2) 140 ns A 17.1 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. MISO_IN, IRQ_IN to MISO, IRQ 2. SCK, MOSI, CS_N, CLK to SCK_OUT, MOSI_OUT, CS_N_OUT, CLK_OUT 37 9116B–AUTO–10/09 7.6.5.3 Test-mode Pins The test-mode pins DTST, ATST, PWTST (outputs) have to be kept open in the application. The test-mode pins SCANMODE and CS_FUSE (inputs) have to be connected to VSSA. These inputs have an internal pull-down resistor. The test-mode pin VDDFUSE is a supply pin. It must also be connected to VSSA. Table 7-25. Input Characteristics Pins SCANMODE, CS_FUSE, VDDFUSE No. Parameters Test Conditions Pin Symbol SCANMODE, RSCANMODE, CS_FUSE RCS_FUSE 18.1 Pull-down resistor Min. Typ. 50 Max. Unit Type* 200 kΩ A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.7 7.7.1 Operations Voltage and Temperature Measurement At startup, the ATA6870 is supplied and is waiting for any operation request. The available operations are: • 6 channels voltage acquisition with a temperature acquisition – with voltage = V(MBATi+1, MBATi) (standard operation) and with voltage = V(TEMP1 or TEMP2, TEMPVSS) (standard operation) – with voltage = V(MBATi, MBATi) (offset calibration: CalOffset operation) and with voltage = V(TEMPVSS, TEMPVSS) (offset calibration: CalOffset operation) – with voltage = V(VREFi, MBATi) (gain calibration: CalGain operation) and with voltage = V(TEMPREF, TEMPVSS) (gain calibration: CalGain operation) Operation completion is flagged to the host MCU via the IRQ output in conjunction with dataRdy bit set in the status register. In order to retrieve the full results in a single access, the user has to access the dataRd16burst register (112 bits). Getting the results of a single channel (voltage or temperature) is also possible. For this, first select the channel to read through the ChannelReadSel register, then retrieve the channel value through the DataRd16 register. It is not possible to order a new operation until the previous operation has been acknowledged. The host MCU acknowledges the interrupt by reading the status register. This resets the dataRdy bit as well as the IRQ output, and enables the ATA6870 to start the next operation. Writing NoOp in the Operation register during an operation running aborts the current operation. In this case, the dataRdy bit is not set and interrupt is not requested to the host MCU. The Opstatus register flags whether operation is running, aborted, ended, or no operation is running. 38 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.7.2 Discharge Function Each channel is independently dischargeable. Discharge is activated or deactivated by the register ChannelDischSel. 7.7.3 Low Frequency Timer Function A low frequency timer (LFT), synchronous to internal 50 kHz oscillator provides the host MCU with a low power timer, which useful to either synchronize operations in the host MCU or monitor the ATA6870’s activity. The LFT elapsing asserts an interrupt to the host MCU if the corresponding mask bit in the IrqMask register is not set. Default is LFT not enabled. To enable the LFT, set the LFTimer_ena bit to 1 in the Ctrl register. LFT counting time is fully programmable in the register LFTimer. Changing the LFTimer register restarts the LFT if the new counting time is smaller than the current value of the LFT. Otherwise, LFT runs until it reaches the new end value. Asserting LFTRst bit in the Rstr register resets and restarts the LFT if the LFT is enabled. Otherwise, LFT is reset but not started. Each ATA6870 will assert its own interrupt when the timer elapses. Depending on how the timer is used, the host MCU may mask LFTdone interrupts in the whole ATA6870s chain, except the first one. As internal RC oscillators are not synchronized, this prevents the MCU from being interrupted each time one of the LFT elapses. 7.7.4 Undervoltage Detection A programmable undervoltage detection function is embedded in the ATA6870. After being digitalized, each of the 6 voltages is compared to a programmable threshold defined in the UdvThresh register. If one of the six channels is out of the range defined by the threshold, an interrupt is requested to the host MCU if the corresponding udv mask bit is not set in the IrqMask register. The default threshold is 1.5V. As soon as MCU has acknowledged, undervoltage information is no more available to MCU, because status register is cleared when MCU reads it out. As a consequence, the next undervoltage interrupt cannot occur until the ATA6870 leaves its current undervoltage state. 39 9116B–AUTO–10/09 7.8 Registers Registers are read and written through the SPI interface. Table 7-26. Register Address 40 Register Mapping Control Field Control Field Read Mode Write Mode Register Name Access Type Function 0x00 0x00 - RevID R 8 bits Revision ID/value Mfirst, pow_on 0x01 0x02 0x03 Ctrl RW 8 bits Control Register 0x02 0x04 0x05 Operation RW 8 bits Operation request 0x03 0x06 - OpStatus R 8 bits Operation status 0x04 - 0x09 Rstr W 8 bits Software reset 0x05 0x0A 0x0B IrqMask RW 8 bits Mask interrupt sources 0x06 0x0C - Status R 8 bits Status interrupt sources 0x08 0x10 - ChannelUdvStatus R 8 bits Channels undervoltage status 0x09 0x12 0x13 ChannelDischSel RW 8 bits Select channel to discharge 0x0A 0x14 0x15 ChannelReadSel RW 8 bits Select channel to read 0x0B 0x16 0x17 LFTimer RW 8 bits Low Frequency Timer control 0x0C 0x18 - CalibStatus R 8 bits Reserved 0x0D 0x1A 0x1B FuseCtrl RW 8 bits Reserved 0x10 0x20 0x21 UdvThresh RW 16 bits Undervoltage detection threshold 0x11 0x22 - DataRd16 R 16 bits Single access to selected channel value 0x12 0x24 0x25 ATA6870Test RW 16 bits Reserved 0x7F 0xFE - DataRd16Burst R 112 bits Burst Access to the whole channels (6 voltage and 1 temperature) ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1 7.8.1.1 Registers Content RevID Register Table 7-27. RevId Register Overview Register RevID Address 0x00 7 (msb) 6 5 4 3 x x x pow_en Mfirst Table 7-28. 2 1 0 (lsb) RevID Description RevID ATA6870 revision number, revision B: 0x02 Mfirst Status input pin MFIRST pow_en Status input pin POW_EN Ctrl Register Table 7-29. Ctrl Register Overview Register Ctrl Address 0x01 7 (msb) 6 5 x x x Table 7-30. 4 Reset Value 3 2 Chksum_ena LFTimer_ena TFMODE_ena 0x00 1 0 (lsb) x x Ctrl Register Content Bit Field 7.8.1.3 0x02 RevId Register Content Bit Field 7.8.1.2 Reset Value Description TFMode_ena 0: Prevent ATA6870 to switch to test mode 1: Not allowed for customer use LFTimer_ena 0: Disable internal Low Frequency Timer 1: Enable internal Low Frequency Timer Chksum_ena 0: Disable SPI transaction checksum computation/check 1: Enable SPI transaction checksum computation/check Operation Register Table 7-31. Operation Register Overview Register Operation Address 0x02 7 (msb) 6 x x 5 4 OpMode Reset Value 3 TempMode 2 0x02 1 VoltMode 0 (lsb) OpRqst 41 9116B–AUTO–10/09 Table 7-32. Operation Register Content Bit Field Description OpRqst 0: NoOp: No Operation, or abort current operation 1: AcqRqst: Start the analog to digital conversion An interrupt is generated when data is available in DataRd16/DataRd16Burst. VoltMode 00: Caloffset: select V(MBAT(i), MBAT(i)) as input of voltage channels. (offset calibration) 01: AcqV: select V(MBAT(i+1), MBAT(i)) as input of voltage channels (default) 10: Not allowed 11: Calgain: select V(vref(i)) as input of voltage channels. (gain calibration) 0: Select TEMP1 input pin as input of temperature channel 1: Select TEMP2 input pin as input of temperature channel TempMode 00: 6 voltage channels and temperature acquisition 01: No acquisition performed 10: No acquisition performed 11: No acquisition performed OpMode When a conversion operation is finished and the interrupt has been acknowledged by the MCU the Operation register is automatically reset to “NoOp”. Writing “NoOp” in the register when conversion operation is running, aborts the current operation. Other changes are not accepted during any operation. Figure 7-28. Typical Data Acquisition Flow ASIC3 (MFIRST = 0) ASIC2 (MFIRST = 0) ASIC1 (MFIRST = 1) Init State Opstatus = NoOP Status Cleared Init State Opstatus = NoOP Status Cleared Init State Opstatus = NoOP Status Cleared Runs Conversion Opstatus = Running Runs Conversion Opstatus = Running Runs Conversion Opstatus = Running Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY MCU ... Set Operation = ACQ*/CAL* Background Tasks/Idle ASIC3 Read/Check Opstatus Read/Check Status Opstatus = NoOP Status Cleared ASIC2 Read/Check Opstatus Read/Check Status Opstatus = NoOP Status Cleared Opstatus = NoOP IRQ Acknowledged Status Cleared ASIC1 Read/Check Opstatus Read/Check Status ASIC3 Burst Read Data ASIC2 Burst Read Data ASIC1 Burst Read Data ... 42 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.4 OpStatus Register Table 7-33. OpStatus Register Overview Register OpStatus Address 0x03 Reset Value 7 (msb) 6 5 4 3 2 x x x x x x Table 7-34. 0x00 1 0 (lsb) OpStatus OpStatus Register Content Bit Field Description OpStatus 00: No Operation 01: Operation is ongoing 10: Operation is finished, result is available 11: Operation is cancelled, result is not available Figure 7-29. Operation Status Register Management User reads Operation Status Register, Reset NO OP Users programs conversions operation Operation Running Users programs NoOp End of conversion Operation Aborted, Result not Available Operation Finished, Result Available User programs conversion operation or reads operation status register Status reg has been read and: User programs conversion operation or reads operation status register The OPStatus register is reset when read after a completed or aborted operation. Reading the register before starting an operation is not mandatory. Reading data conversion results or reading the OpStatus Register during an operation does not affect the OpStatus register. 43 9116B–AUTO–10/09 7.8.1.5 Rstr Register Table 7-35. Rstr Register Overview Register Rstr Address 0x04 Reset Value 0x00 7 (msb) 6 5 4 3 2 1 0 (lsb) x x x x x x LFTRst 0 Table 7-36. Rstr Register Content Bit Field Description 0: No reset 1: Low Frequency Timer software reset LFTRst LFTRst resets and restarts the low frequency timer if not disabled (LFTimer_ena = 0). 7.8.1.6 IrqMask Register Table 7-37. IrqMask Register Overview Register IrqMask Address 0x05 7 (msb) 6 5 x x x Table 7-38. 3 2 0x00 1 0 (lsb) chkErrorMask udvmask commErrorMask LFTdoneMask dataDryMask IrqMask Register Content Bit Field Description dataRdyMask Mask data ready interrupt when set to 1 WakeupMask Mask LFTdone interrupt when set to 1 commErrorMask udvMask chkErrorMask 44 4 Reset Value Mask commError interrupt when set to 1 Mask undervoltage detection interrupt when set to 1 Mask checksum error interrupt when set to 1 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.7 Status Register Table 7-39. Status Register Overview Register Status Address 0x06 Reset Value 0x10 7 (msb) 6 5 4 3 2 1 0 (lsb) x TFMdeOn por chkError udv commError LFTdone dataRdy Table 7-40. Status Register Content Bit Field Description dataRdy Conversion finished LFTdone Low frequency timer elapsed commError udv Bad SPI command detected (wrong length) Undervoltage detected chkError Error on checksum check Por Power on reset detected TFMdeOn Test mode on Any bit among {dataRdy, LFTdone, commError, udv, chkError} set in the status register requests an interrupt to the external MCU if the corresponding mask bit in the IrqMask register is 0. Reading the status register acknowledges the interrupt and resets its content. Por and TFMdeOn cause no interrupt. 45 9116B–AUTO–10/09 7.8.1.8 ChannelUdvStatus Register Table 7-41. ChannelUdvStatus Register Overview Register ChannelUdvStatus Address 0x08 7 (msb) 6 x x Table 7-42. 5 4 Reset Value 3 2 0x00 1 0 (lsb) chUdv6_stat chUdv5_stat chUdv4_stat chUdv3_stat chUdv2_stat chUdv1_stat ChannelUdvStatus Register Content Bit Field Description chUdv1_stat 1: Undervoltage detected on channel 1 0: No undervoltage detected on channel 1 chUdv2_stat 1: Undervoltage detected on channel 2 0: No undervoltage detected on channel 2 chUdv3_stat 1: Undervoltage detected on channel 3 0: No undervoltage detected on channel 3 chUdv4_stat 1: Undervoltage detected on channel 4 0: No undervoltage detected on channel 4 chUdv5_stat 1: Undervoltage detected on channel 5 0: No undervoltage detected on channel 5 chUdv6_stat 1: Undervoltage detected on channel 6 0: No undervoltage detected on channel 6 Undervoltage is detected when voltage decreases under the threshold value defined in udvThresh register. When undervoltage is detected on a channel, the ATA6870 requests an interrupt if the UDVmask bit in the IRQMask register is 0. 46 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.9 ChannelDischSel Register Table 7-43. ChannelDischSel Register Overview Register ChannelDischSel Address 0x09 7 (msb) 6 x x Table 7-44. 5 4 Reset Value 3 chV6_disch chV5_disch chV4_disch 2 0x00 1 0 (lsb) chV3_disch chV2_disch chV1_disch ChannelDischSel Register Content Bit Field Description chV1_disch 1: Enable voltage channel 1 discharge 0: Disable voltage channel 1 discharge chV2_disch 1: Enable voltage channel 2 discharge 0: Disable voltage channel 2 discharge chV3_disch 1: Enable voltage channel 3 discharge 0: Disable voltage channel 3 discharge chV4_disch 1: Enable voltage channel 4 discharge 0: Disable voltage channel 4 discharge chV5_disch 1: Enable voltage channel 5 discharge 0: Disable voltage channel 5 discharge chV6_disch 1: Enable voltage channel 6 discharge 0: Disable voltage channel 6 discharge The channels are dischargeable simultaneously. 7.8.1.10 ChannelReadSel Register Table 7-45. ChannelReadSel Register Overview Register ChannelReadSel Address 7 (msb) 0x0A 6 5 4 Reset Value 3 2 0x00 1 0 (lsb) ChannelReadSel 47 9116B–AUTO–10/09 Table 7-46. ChannelReadSel Register Content Bit Field Description 111: Value of the LFT is returned in DataRd16 register 110: Temperature channel available in DataRd16 register 101: Voltage channel6, value available in DataRd16 register 100: Voltage channel5, value available in DataRd16 register 011: Voltage channel4, value available in DataRd16 register 010: Voltage channel3, value available in DataRd16 register 001: Voltage channel2, value available in DataRd16 register 000: Voltage channel1, value available in DataRd16 register ChannelReadSel This register can be used to quickly read a single channel without using a full burst access. The value of the selected channel will be available in the DataRd16 register. The value will always be updated by writing a channel address to the ChannelReadSel register. Data in this register is not valid during ongoing data conversion. 7.8.1.11 LFTimer Register LFTimer Register Overview Register LFTimer Address 7 (msb) 0x0B 6 5 4 LFTPrescaler Table 7-47. Reset Value 3 2 0xF9 1 0 (lsb) LFTDelay LFTimer Register Content Bit Field Description LFTDelay Contains the present Low Frequency Timer delay value LFTPrescaler 0: PrescalerValue = 1 1: PrescalerValue = 6 The default timer value is 59.965s (0xF9) for fOSC = 50 kHz. Figure 7-30. Block Diagram LFTimer LFTprescaler 50 kHz /4096 /6 LFTdelay 7-bit counter Comp Delay Time elapsed clear Formula for Delay Time calculation: LFTprescaler D 1 Delay Time = ------------------------- × 4096 × ( 6 ) × ( LFTdelay D + 1 ) T OSC [Hz] 48 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] The LFT can be programmed to the following values (fOSC = 50 kHz): LFTprescaler = 0: LFTprescaler = 1: 0.082s <= duration <= 10.486s, Increment = 82 ms 492 ms <= duration <= 62.915s, Increment = 492 ms When LFT elapsed, an interrupt is requested unless LFTdoneMask bit is set in the IRQMask register. For details on the tolerances for the oscillator, see Section 7.5.6 “RC Oscillator” on page 25. Keeping at list 100 µs between two successive LFTimer register write accesses prevents internal metastability issues, which might result in bad LFTdelay decoding. 7.8.1.12 Test-Mode Register Table 7-48. Test-Mode Register 1 Overview Register TESTmode1 Address 0x0C Reset Value 0x03 7 (msb) 6 5 4 3 2 1 0 (lsb) 0 0 0 0 0 0 1 1 Table 7-49. Test-Mode Register 2 Overview Register TESTmode2 Address 0x0D Reset Value 0x07 7 (msb) 6 5 4 3 2 1 0 (lsb) 0 0 0 0 0 1 1 1 Table 7-50. Test-Mode Register 3 Overview Register UdvThresh Address 0x12 Reset value 0x0E00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 Test-Mode registers 1, 2, and 3 are reserved for the factory calibration process. They are not allowed for customer use. 49 9116B–AUTO–10/09 7.8.1.13 UdvThresh Register Table 7-51. UdvThresh Register Overview Register UdvThresh Address 0x10 15 14 13 12 x x x x Table 7-52. 11 10 9 Reset value 8 7 6 5 4 3 0x0570 2 1 0 udvThresh UdvThresh Register Content Bit Field Format Description udvThresh 12 bits Threshold for undervoltage detection Default value is 1.5V (0x0570, 1392D) 1.5V = VREF × (1392 – 410) / (1502 – 410) See also Section 7.5.1.2 “12 Bits Incremental ADC” on page 19. 7.8.1.14 DataRd16 Register Table 7-53. DataRd16 Register Overview Register DataRd16 Address 14 13 12 x x x x Table 7-54. 11 10 9 Reset value 8 7 6 5 4 3 0x0000 2 1 0 DataRd16 DataRd16 Register Content Bit Field DataRd16 50 0x11 15 Format Description 12 bits Return selected channel value (see Section 7.8.1.10 “ChannelReadSel Register” on page 47) ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.15 DataRd16burst Register Table 7-55. DataRd16burst Register Overview Register DataRd16Burst Address 0x7F 111 110 109 108 X X X x 95 94 93 92 x x x x 79 78 77 76 x x x x 63 62 61 60 x x x x 47 46 45 44 x x x x 31 30 29 28 x x x x 15 14 13 12 x x x x Table 7-56. 107 106 105 104 Reset value 103 102 101 0x0000 100 99 98 97 96 84 83 82 81 80 68 67 66 65 64 52 51 50 49 48 36 35 34 33 32 20 19 18 17 16 4 3 2 1 0 Channel6 data 91 90 89 88 87 86 85 Channel5 data 75 74 73 72 71 70 69 Channel4 data 59 58 57 56 55 54 53 Channel3 data 43 42 41 40 39 38 37 Channel2 data 27 26 25 24 23 22 21 Channel1 data 11 10 9 8 7 6 5 Temperature data DataRd16burst Register Content Bit Field Format Description DataRd16burst 112 bits Returns the values of all channels from one ATA6870, including temperature measurement 51 9116B–AUTO–10/09 Figure 7-31. Application 10Ω 1 kΩ 1.5 kΩ PD_N VDDHVP MISO_IN SCK_OUT MOSI_OUT CLK_OUT 100 nF CS_N_OUT IRQ_IN MBAT7 VDDHV MBAT6 1 kΩ DISCH6 100 nF VDDHVM + 33 µF DISCH5 PD_N_OUT MBAT5 POW_ENA 220 nF 1 kΩ 100 nF PWTST DISCH4 ATST MBAT4 BIASRES 1 kΩ 121 kΩ 100 nF ATA6870 DISCH3 TEMPVREF MBAT3 TEMP2 1 kΩ 100 nF DISCH2 + TEMP1 MBAT2 TEMPVSS NTC 1 kΩ 10 µF NTC 100 nF DVDD GND DVSS VDDFUSE AVSS CS_FUSE DTST MISO MOSI SCK CLK IRQ CS_N MBAT1 MFIRST DISCH1 1 kΩ SCANMODE 100 nF AVDD 10 nF 10Ω 10Ω 1 kΩ PD_N VDDHVP MISO_IN MOSI_OUT SCK_OUT CS_N_OUT 100 nF CLK_OUT IRQ_IN VDDHV MBAT7 MBAT6 1 kΩ DISCH6 100 nF VDDHVM + 33 µF DISCH5 PD_N_OUT MBAT5 POW_ENA 220 nF + 1 kΩ 10 µF 100 nF 100 nF PWTST DISCH4 ATST MBAT4 BIASRES 1 kΩ 121 kΩ 100 nF ATA6870 DISCH3 TEMPVREF MBAT3 TEMP2 1 kΩ 100 nF DISCH2 TEMP1 MBAT2 TEMPVSS NTC 1 kΩ NTC DVDD GND DVSS VDDFUSE AVSS CS_FUSE DTST MISO MOSI SCK CLK IRQ CS_N MBAT1 MFIRST DISCH1 1 kΩ SCANMODE 100 nF AVDD 10 nF 10Ω MISO MOSI SCK CSN CLK IRQ VDD OUT Microcontroller GND Figure 7-31 shows an application with 2 stacked ATA6870s. 52 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 8. Ordering Information Extended Type Number Package MOQ ATA6870-PLPW QFN48, 7 × 7 1,000 pieces ATA6870-PLQW QFN48, 7 × 7 4,000 pieces 9. Package Information Package: VQFN_7 x 7_48L Exposed pad 5.6 x 5.6 Dimensions in mm Bottom Not indicated tolerances ±0.05 5.6±0.15 Top 48 37 48 1 36 1 12 25 12 Pin 1 identification Z 7 24 13 0.2 0.5 nom. 5.5 Z 10:1 0.4±0.1 0.9±0.1 technical drawings according to DIN specifications Drawing-No.: 6.543-5130.01-4 Issue: 1; 21.03.06 0.23±0.07 9.1 Markings As a minimum, the devices will be marked with the following: • Date code (year and week number) • Atmel® part number (ATA6870) 53 9116B–AUTO–10/09 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History • • • • • • • • 9116B-AUTO-10/09 • • • • • • • • • • • • • 54 Table 3-1 “Pin Description” on page 4 changed Table 5 “Abs.Max.RAtings” changed Table 7-1 “Electrical Characteristics” on page 11 changed Table 7-5 “Electrical Characteristics” on page 16 changed Table 7-7 “Electrical Characteristics” on page 19 changed Table 7-9 on page 21 changed Table 7-11 “Battery Cell Temperature Measuring Characteristics” on page 23 changed Table 7-12 “Battery Cell Temperature Measuring Characteristics” on page 24 changed Section 7.5.7 “Power On Reset” on page 25 changed Table 7.15 “Battery Cell Temperature Measuring Characteristics” on page 25 changed Figure 7-13 “Host Interface” on page 26 changed Figure 7-14 “SPI Transaction Field Organization” on page 28 changed Section 7.6.4.7 “CHKSUM Field” on page 34 changed Table 7-19 “Electrical Characteristics” on page 35 changed Table 7-22 “Electrical Characteristics” on page 37 changed Table 7-23 “Electrical Characteristics” on page 37 changed Table 7-26 “Register Mapping” on page 40 changed Table 7-32 “Operation Register Content” on page 42 changed Section 7.8.1.5 “Rstr Register” on page 44 changed Table 7.55 “DataRd16burst Register Overview” on page 51 changed Figure 7-31 “Application” on page 52 changed ATA6870 [Preliminary] 9116B–AUTO–10/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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