Features • • • • • • • • • • • Overvoltage Monitoring Undervoltage Monitoring Cell Temperature Monitoring Self-diagnosis including – Comparator Functions – Communication Lines – Short and Open Measuring Lines Hot Plug-in Capable Less than 10 µA Stand-by Current Low Cell Imbalance Current (< 10 µA) Circuit Customization, e.g. for Over/Undervoltage Thresholds Possible for Adequate Volumes Cost-efficient Solution Due to Cost Optimized 30V CMOS Technology Daisy-chainable – Each IC Monitors 6 Battery Cells – 16 ICs (96 Cells) per String – No Limit on Number of Strings – Reliable Communication between Stacked ICs Due to Level Shifters with Current Sources Package SSO28 Applications • Backup Battery-Cell Monitoring System for Li-ion Batteries • Emergency Indicator in Li-ion Batteries • Monitoring System in Li-ion Batteries Li-ion Battery Management Monitoring Emergency and Backup Circuit ATA6871 Preliminary Benefits • Highest Safety Level for Li-ion Battery Systems • Circuit Customization, e.g. Over and Undervoltage Thresholds, Possible for Large Production Volumes 1. General Description The ATA6871 is a battery cell monitoring circuit designed to act as an emergency, safety, or backup circuit in Li-ion battery systems for electrical and hybrid electrical vehicles (EV/HEV). It monitors overvoltage, undervoltage, and the cell temperature in Li-ion batteries without the need of a microcontroller. The circuit has an advanced self-test functionality, which checks the proper functionality of the monitoring comparators as well as the communication lines. It can be used as a monitoring circuit as well as an emergency indicator or as a backup system in Li-ion battery management systems. The ATA6871 can monitor four, five, or six battery cells. Up to 16 IC’s can be cascaded. If one or more battery cells exceed the over or undervoltage thresholds for longer than 2 seconds, or if the temperature input exceeds the temperature limit for more than 2 seconds, a digital output signal is set to high. 9123B–AUTO–07/09 2. Block Diagram Figure 2-1. Top-level Block Diagram To ATA6871 above VDDHV PD_N MBAT7 6 Standby Control Debouncing > 2 sec MBAT6 Cell 6: Over-voltage Under-voltage Detection UV 6 Input OR OV RC-OSC PD_N_OUT STATUS_IN Self test STATUS 3.3V Internal Voltage Regulator BIASRES Cell 1: Over-voltage Under-voltage Detection UV 6 Input OR OV 6 Debouncing > 2 sec MBAT2 MBAT1 VDD Internal Biasing CHIPONE Chip Configuration VDD CHIPLAST CONF1 Overtemperature comparator TEMP_IN NTC Test VSSA SCANMODE CLK TEST_HV TEST_LV Debouncing > 2 sec CONF0 OROUT_IN 4 Input OR OROUT ENUV To ATA6871 below 2 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] 3. Pin Configuration Figure 3-1. Pinning SSO28 VDDHV 1 28 STATUS_IN MBAT7 2 27 OROUT_IN MBAT6 3 26 PD_N MBAT5 4 25 PD_N_OUT MBAT4 5 24 VDD MBAT3 6 23 VDD MBAT2 7 22 OROUT ATA6871 MBAT1 8 21 STATUS TEST_HV 9 20 SCANMODE TEST_LV 10 VSSA 11 Table 3-1. 19 CLK 18 ENUV BIASRES 12 17 TEMP_IN CHIPONE 13 16 CONF0 CHIPLAST 14 15 CONF1 Pin Description Pin Symbol Function 1 VDDHV Supply voltage 2 MBAT7 Battery monitoring line 3 MBAT6 Battery monitoring line 4 MBAT5 Battery monitoring line 5 MBAT4 Battery monitoring line 6 MBAT3 Battery monitoring line 7 MBAT2 Battery monitoring line 8 MBAT1 Battery monitoring line 9 TEST_HV Test-mode pin Keep pin open (output) 10 TEST_LV Test-mode pin Keep pin open (output) 11 VSSA 12 BIASRES Internal supply current adjustment 13 CHIPONE Indicates circuit position in battery string (first, middle, last) 14 CHIPLAST Indicates circuit position in battery string (first, middle, last) 15 CONF1 Programs how many cells will be monitored (4, 5, or 6 cells operating) 16 CONF0 Programs how many cells will be monitored (4, 5, or 6 cells operating) 17 TEMP_IN 18 ENUV Remark Negative supply voltage Input for battery-cell temperature monitoring Enable/Disable under-voltage detection 3 9123B–AUTO–07/09 Table 3-1. 4 Pin Description Pin Symbol Function Remark 19 CLK Test-mode pin Connected to VSSA 20 SCANMODE Test-mode pin Connected to VSSA 21 STATUS Status output 22 OROUT Output signal battery-cells in limits/out of limits 23 VDD Voltage regulator output 24 VDD Voltage regulator output 25 PD_N_OUT 26 PD_N 27 OROUT_IN Input for the OROUT signal of the upper ATA6871 circuit 28 STATUS_IN Input for the STATUS signal of the upper ATA6871 circuit Internally connected to pin 23 Power down output Power down input ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] 4. System Overview The ATA6871 can be stacked in one string up to 16 times. Figure 4-1. Battery Management Architecture with one Battery String ATA6871 ATA6871 ATA6871 ATA6871 2 Status/ Battery Cells OK, not OK 5 9123B–AUTO–07/09 Figure 4-2. Battery Management Architecture with Several Battery Strings ATA6871 ATA6871 OPTO ATA6871 2 ATA6871 6 2 Status/ Battery Cells OK, not OK ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified all voltages refer to pin VSSA. Logic Levels: 0 = VSSA, 1 = VDD. Parameters Pin Symbol Min. Max. Unit Ambient temperature TA –40 +85 °C Junction temperature TJ –40 +125 °C TS –40 +150 °C V(MBATi+1) - VMBATi –0.3 +5.5 V VVDDHV - VVMBAT7 –5.5 +0.3 V Storage temperature Battery cell voltage VVDDHV - VVMBAT7max VMBAT1 MBAT1 VMBAT1 –0.3 +0.3 V Supply voltage VDDHV VVDDHV –0.3 +30 V VDD VVDD –0.3 +5.5 V CHIPONE, CHIPLAST, CONF0, CONF1, SCANMODE, CLK, TEST_HV, TEST_LV, ENUV, OROUT VCHIPONE, VCHIPLAST, VCONF0, VCONF1, VSCANMODE, VCLK, VTEST_HV, VTEST_LV, VENUV, VOROUT –0.3 VDD + 0.3 V BIASRES, TEMP_IN VBIASRES, VTEMP_IN –0.3 VDD + 0.3 V Supply voltage (regulator is off) Input voltage for logic I/O pins Input voltage for analog low voltage input pins Input voltage for digital high voltage input pins OROUT_IN, STATUS_IN VOROUT_IN, VSTATUS_IN VDDHV – 0.3 VDDHV + 0.3 Logic output pin STATUS Input Output STATUS VSTATUS PD_N V PD_N PD_N_OUT V PD_N_OUT HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) –0.3 –5.5 Latch Up according to AECQ100-004 V V +0.3 V ±2 kV 500 V ESD 750 V LATCH-UP ±100 mA ESD VDDHV, CHIPLAST, CONF1, STATUS_IN +5.5 VDDHV – 5.5 VDDHV + 0.3 CDM ESD STM 5.3.1 CDM ESD STM 5.3.1 V 6. Thermal Resistance Parameters Symbol Value Unit Maximum thermal resistance junction-ambient Rthja max 49 K/W 7 9123B–AUTO–07/09 7. Circuit Description and Electrical Characteristics Unless otherwise specified, all parameters in this section are valid for a supply voltage range of 6.9V < V VDD HV < 30V and a battery cell voltage of V (MBATi+1) – V MBATi = 0V to 5V, –40°C < TA < 85°C, all values refer to pin VSSA, unless otherwise specified. 7.1 Operating Modes The ATA6871 has two operation modes: 1) Power-down Mode 2) ON Mode/Selfdiagnosis 7.1.1 Power-down Mode In Power-down Mode all blocks of the IC are switched off. The circuit can be switched from Power-down to ON Mode or back via the PD_N input. If the pin is connected to VDDHV, for example, via an external optocoupler the circuit is in ON Mode. If several ATA6871 are stacked, the power-down signal must be only provided for the IC on the top level of the stack. The next lower IC is getting this information from the PD_N_OUT output of it's upper IC. The PD_N_OUT pin must be connected either to the PD_N pin of the next lower ATA6871 or to VSSA. 8 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] Figure 7-1. Power-down VDDHV PD_N 6 Standby Control Debouncing > 2 sec MBAT6 OV Cell 1: Over-voltage Under-voltage Detection UV 6 Input OR MBAT7 PD_N_OUT RC-OSC Self test ATA6871 VDD 3.3V Internal Voltage Regulator 6 Debouncing > 2 sec MBAT1 OV Cell 6: Over-voltage Under-voltage Detection UV 6 Input OR MBAT2 Internal Biasing Chip Configuration TEMP_IN CHIPONE Debouncing > 2 sec Overtemperature comparator Test VSSA CHIPLAST 4 Input OR ENUV VDDHV PD_N MBAT7 6 Standby Control Debouncing > 2 sec MBAT6 Cell 1: Over-voltage Under-voltage Detection UV 6 Input OR OV PD_N_OUT RC-OSC Self test ATA6871 VDD 3.3V Internal Voltage Regulator 6 Debouncing > 2 sec MBAT1 OV Cell 6: Over-voltage Under-voltage Detection UV 6 Input OR MBAT2 Internal Biasing Chip Configuration TEMP_IN CHIPONE Debouncing > 2 sec Overtemperature comparator Test VSSA CHIPLAST 4 Input OR ENUV VDDHV PD_N MBAT7 6 Standby Control Debouncing > 2 sec MBAT6 Cell 1: Over-voltage Under-voltage Detection UV 6 Input OR OV PD_N_OUT RC-OSC Self test ATA6871 VDD 3.3V Internal Voltage Regulator 6 Debouncing > 2 sec MBAT1 OV Cell 6: Over-voltage Under-voltage Detection UV 6 Input OR MBAT2 Internal Biasing Chip Configuration TEMP_IN Test VSSA CHIPONE Debouncing > 2 sec Overtemperature comparator CHIPLAST 4 Input OR ENUV 9 9123B–AUTO–07/09 Table 7-1. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Maximum allowed input current in Power-down 1.1 Mode (e.g., leakage current of an optocoupler) PD_N IPD_N 1.2 Input current in ON Mode PD_N IPD_N Max. Unit Type* 50 µA A 5 mA A VMBAT(i+1) – VMBAT(i) = 3.7V 10 µA A Imbalance from battery cell VMBAT(i+1) – 1.4 to battery cell in VMBAT(i) = 3.7V Power-down Mode 10 µA A Current consumption in 1.3 Power-down Mode IVDDHV + IMBATi_max(1) Min. 2.5 Typ. PD_N VVDDHV – VPD_N 5 V A Propagation delay time 1.6 from Power-down Mode to CVDD = 10 nF ON Mode VDD tVDDON 1 ms A Propagation delay time 1.7 from ON Mode to Power-down Mode VDD tVDDOFF 11 ms A 1.5 Maximum input voltage (Power-down Mode) IPD_N = 0 to 50 µA CVDD = 10 nF *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 7.1.2 1. Largest input current of the inputs MBAT1 to MBAT7 ON Mode/Selfdiagnosis When the PD_N-signal goes from low to high, the self diagnosis of the ATA6871 starts. During this self diagnosis the following tests are performed: • Test if over/undervoltage or overtemperature comparators are able to switch or if they stuck to 0 or 1 • Test if pins OROUT_IN, OROUT in stacked ICs are able to switch or if they stuck to 0 or 1 and if the connection to next ATA6871 is available or not • Test if pins STATUS_IN, STATUS are able to switch or if they stuck to 0 or 1 and if the connection to next ATA6871/MCU is available or not • Detect open or shorted input pins MBAT1 to MBAT7 • Detect wrong setting of CONF0, CONF1 (e.g. 4 cell configuration programmed, 6 cells used) If self diagnosis fails, the STATUS of the lowest ATA6871 is constant low. If the self diagnosis succeeds, the STATUS of the lowest ATA6871 is toggling. 10 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] The circuit will suppress failures detected during the self test and provide only results from good tested comparators connections to pin OROUT. This enables the system to monitor the rest of the battery cells if one connection/comparator fails. If, for example, the connection of the OROUT signal between two ATA6871s is open, the OROUT_IN signal of the lower ATA6871 will be ignored, but all the cells of this ATA6871 and ICs below will be observed in the normal way. If the battery cell voltage exceeds 4.9V or is below 1.5V during the self-diagnosis, the affected comparator will be detected as defect, and the output of the affected comparator will be also suppressed until the next self diagnosis. If, after the self test has passed, one of the comparator in the stack detects under or overtemperature at a battery cell, the output OROUT switches from low to high. The battery cell undervoltage detection can be disabled with the digital input ENUV. Table 7-2. Electrical Characteristics No. Parameters 2.1 Supply voltage 2.2 Current consumption 2.3 Input current 2.4 2.5 Digital output signal Self diagnosis time Test Conditions No external load Self diagnosis ongoing or failed Self diagnosis passed successful Pin Symbol Min. VDDHV VVDDHV 6.9 VDDHV MBAT(i) STATUS i = number of stacked ICs Typ. Max. Unit Type* 30 V A IVDDHV 6 mA A IMBAT(i) 5 µA A Constant low VSTATUS 15 Toggle frequency 2+ 0.85 × i tselfdiag A 50 Hz A 8+ 2.2 × i ms B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.2 Battery Cell Over and Undervoltage Detection If, after the self diagnosis of the chip has passed, one of the monitored battery cell voltages V(MBATi+1) - VMBATi is above the overvoltage threshold or below the undervoltage threshold for t > tDebounce, the OROUT output goes high. The battery cell undervoltage detection can be disabled with the digital input ENUV. Table 7-3. Truth Table: PIN Symbol ENUV VENUV Value Function 0 Undervoltage detection disabled 1 Undervoltage detection enabled 11 9123B–AUTO–07/09 Table 7-4. Electrical Characteristics No. Parameters 3.1 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Overvoltage detection on threshold MBAT(i) V(MBAT(i+1)) – VMBAT(i) 4.3 4.45 4.6 V A 3.2 Overvoltage detection off threshold MBAT(i) V(MBAT(i+1)) – VMBAT(i) 4.2 4.35 4.5 V A 3.3 Overvoltage detection hysteresis MBAT(i) ΔV(MBAT(i+1)) – VMBAT(i) 70 mV A 3.4 Undervoltage detection on threshold MBAT(i) V(MBAT(i+1)) – VMBAT(i) 1.7 1.8 1.9 V A 3.5 Undervoltage detection off threshold MBAT(i) V(MBAT(i+1)) – VMBAT(i) 1.8 1.9 2.0 V A 3.6 Undervoltage detection hysteresis MBAT(i) ΔV(MBAT(i+1)) – VMBAT(i) 70 mV A 3.7 Debouncing time tDebounce 1 s A 3 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.3 Battery Cell Overtemperature Detection If the voltage at the input TEMP_IN is less than the half of VDD threshold for t > tDebounce, the OROUT output goes high. To disable this function, connect TEMP_IN to VDD. If the input is open (high impedance), an internal current will force the comparator to the overtemperature state and OROUT will switch to high. Figure 7-2. Overtemperature Detection VDD Rref TEMP_IN NTC ITEMP_IN VDD/2 Overtemp VSSA 12 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] Table 7-5. Electrical Characteristics No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 4.1 Overtemperature detection on threshold TEMP_IN VTEMP_IN VDD/2 – 100 mV VDD/2 VDD/2 + 100 mV V A 4.2 Overtemperature detection off threshold TEMP_IN VTEMP_IN VDD/2 – 50 mV VDD/2 + 50 mV VDD/2 + 150 mV V A 4.3 Overtemperature detection hysteresis TEMP_IN ΔVTEMP_IN 30 mV A 4.4 Resistor Divider RDivider = RNTC + RRref 3 1000 kΩ D 4.5 Input Current ITEMP_IN 0.4 0.6 µA A 4.6 Debouncing Time tDebounce 1 3 s A VTEMP_IN=1.65V TEMP_IN *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.4 7.4.1 ATA6871 Configuration Device Position The ATA6871 can be cascaded up to 16 times in one string. The input pins CHIPONE and CHIPLAST define the first and the last IC in a string. Table 7-6. 7.4.2 Device Position CHIPONE CHIPLAST Configuration 0 0 ICs between the first and the last IC (up to 14 ICs) 0 1 Last cascaded chip, connected to power down optocoupler 1 0 First chip in a string (master) 1 1 First and last chip: (if only one IC is used per string) Number of Cells Configuration The ATA6871 can work with either four, five, or six cells. This can be programmed with the input pins CONF0 and CONF1. When used with 5 cells, the inputs MBAT5 and 6 must be connected together, when used with 4 cells the inputs MBAT4, MBAT5 and MBAT6 must be connected together (see also Figure 7-3 to Figure 7-5). Table 7-7. Cells Configuration CONF1 CONF0 Configuration Notes 0 0 4 cells configuration Over/undervoltage comparators between MBAT4,5 and MBAT6 are disabled 0 1 5 cells configuration Over/undervoltage comparator between MBAT5 and MBAT6 is disabled 1 0 Do not use, reserved for test purposes 1 1 6 cells configuration 13 9123B–AUTO–07/09 Figure 7-3. 6 Cells Operation MBAT7 MBAT6 MBAT5 VDDHV VDD MBAT4 ATA6871 MBAT3 MBAT2 MBAT1 Figure 7-4. VSSA CONF1 CONF0 5 Cells Operation MBAT7 MBAT6 MBAT5 VDDHV VDD MBAT4 ATA6871 MBAT3 MBAT2 MBAT1 14 VSSA CONF1 CONF0 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] Figure 7-5. 4 Cells Operation MBAT7 MBAT6 MBAT5 VDDHV VDD MBAT4 ATA6871 MBAT3 MBAT2 MBAT1 VSSA CONF1 CONF0 15 9123B–AUTO–07/09 7.5 Supplies 7.5.1 Voltage Regulator The circuit includes a linear 3.3V voltage regulator, which supplies internal blocks as well as external components, e.g., the resistor divider for the over-temperature measurement. The regulator is supplied out of VDDHV. A load capacitor of 10 nF has to be used for stabilization purposes. Table 7-8. Electrical Characteristics No. Parameters 5.1 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Output voltage VDD VVDD 3.1 3.3 3.5 V A 5.2 Maximum output current for external components VDD IVDD –5 mA A 5.3 Load capacitor VDD Cload 8 nF D 10 12 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.5.2 Central Biasing This block generates a precise bias current to supply internal blocks of the IC. External load cannot be connected to this pin. Table 7-9. No. Electrical Characteristics Parameters 6.1 Biasing voltage 6.2 External resistor 6.3 Tolerance 6.4 Maximum external parasitic capacitor Test Conditions Pin BIASRES Symbol Unit Type* VBIASRES 1.2 V A RRefbias 121 kΩ D +1 % D 50 pF D ΔRRefbias BIASRES CExternal Min. –1 Typ. Max. *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] Figure 7-6. Internal Bias Current Generation IBIAS Bandgap 1.2V BIASRES RREFBIAS 121 kΩ VSSA 17 9123B–AUTO–07/09 7.6 7.6.1 Digital Inputs and Outputs Digital Output Characteristics If the ATA6871 is configured as first IC (master) in a string (CHIPONE = 1, CHIPLAST = 0 or 1), the output OROUT acts as a push-pull output, the output STATUS as an open drain output. If the ATA6871 is configured to be a stacked IC (CHIPONE = 0, CHIPLAST = 0 or 1), the output signals STATUS and OROUT coming from the upper IC need to be transferred to the STATUS and OROUT output of the master in the string via the STATUS_IN and OROUT_IN inputs. In this case the OROUT and STATUS outputs act as level shifters based on current sources. Table 7-10. Digital Output Characteristics (OROUT, STATUS) No. Parameters Test Conditions Pin Symbol Min. 7.1 High-level output voltage Iout = –5 mA CHIPONE = 1 OROUT VOROUT, 0.8 × VDD 7.2 Low-level output voltage Iout = +5 mA CHIPONE = 1 OROUT, STATUS VOROUT, VSTATUS 7.3 Low-level output current Vout = –0.3V to +0.3V, CHIPONE = 0 OROUT, STATUS IOROUT, ISTATUS 7.4 High-level output current Vout = –0.3V to +0.3V, CHIPONE = 0 OROUT, STATUS IOROUT, ISTATUS Typ. Max. Unit Type* V A 0.2 × VDD V A –13 –8 µA A –65 –44 µA A Unit Type* µA A µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.6.2 Digital Input Characteristics Table 7-11. No. Digital Input Characteristics (OROUT_IN, STATUS_IN) Parameters Test Conditions Pin Symbol Min. 15 8.1 Low-level input current (VDDHV + 1.4V) ±300 mV OROUT_IN, STATUS_IN IOROUT_IN, ISTATUS_IN 8.2 High-level input current (VDDHV + 1.4V) ±300 mV OROUT_IN, STATUS_IN IOROUT_IN, ISTATUS_IN Typ. Max. 42 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 18 ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] Table 7-12. No. 9.1 9.2 9.3 9.4 Digital Input Characteristics PINs CHIPONE, CHIPLAST, CONF0, CONF1, ENUV Parameters Test Conditions Pin Symbol Min. High-level input voltage CHIPONE, CHIPLAST, CONF0, CONF1, ENUV VCHIPONE, VCHIPLAST, VCONF0, VCONF1, VENUV 0.7 × VDD Low-level input voltage CHIPONE, CHIPLAST, CONF0, CONF1, ENUV VCHIPONE, VCHIPLAST, VCONF0, VCONF1, VENUV Hysteresis CHIPONE, CHIPLAST, CONF0, CONF1, ENUV VCHIPONE, VCHIPLAST, VCONF0, VCONF1, VENUV Input current CHIPONE, CHIPLAST, CONF0, CONF1, ENUV VCHIPONE, VCHIPLAST, VCONF0, VCONF1, VENUV Typ. Max. Unit Type* VDD V A 0.3 × VDD V A V C µA A 0.05 × VDD 1 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.6.3 Test-mode Pins The test-mode pins TEST_HV, TEST_LV (outputs) have to be kept open in the application. The test-mode pins CLK, SCANMODE (inputs) have to be connected to VSSA. These inputs have an internal pull-down resistor. Table 7-13. Digital Input Characteristics PINs SCANMODE, CLK No. Parameters 10.1 Pull-down resistor Test Conditions Pin Symbol Min. SCANMODE, CLK RSCANMODE, RCLK 50 Typ. Max. Unit Type* 200 kΩ A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 19 9123B–AUTO–07/09 8. Application Figure 8-1 shows an application with 3 stacked ATA6871s. The ATA6871 on the highest potential, is configured to monitor only four instead of six battery cells. Figure 8-1. Typical Application 50Ω Power Down 1 kΩ CHIPLAST CHIPONE MBAT7 100 nF 1 kΩ SCANMODE MBAT6 CLK 121 kΩ 1.5 kΩ BIASRES MBAT5 VDDHV VDD MBAT4 ATA6871 100 nF 1 kΩ MBAT3 OROUT MBAT2 PD_N_OUT PD_N 100 nF 1 kΩ STATUS_IN 100 nF 1 kΩ 10 nF 100 nF OROUT_IN MBAT1 TEMP_IN STATUS VSSA CONF1 CONF0 ENUV RREF NTC 50Ω 1 kΩ CHIPLAST CHIPONE MBAT7 100 nF 1 kΩ SCANMODE MBAT6 CLK 100 nF 1 kΩ VDDHV 100 nF 1 kΩ VDD MBAT4 ATA6871 100 nF 1 kΩ MBAT3 OROUT MBAT2 PD_N_OUT PD_N STATUS_IN 100 nF 1 kΩ 10 nF 100 nF OROUT_IN 100 nF 1 kΩ 121 kΩ BIASRES MBAT5 MBAT1 TEMP_IN STATUS VSSA CONF1 CONF0 ENUV RREF NTC 50Ω 1 kΩ CHIPLAST CHIPONE MBAT7 100 nF 1 kΩ SCANMODE MBAT6 CLK 100 nF 1 kΩ VDDHV 100 nF 1 kΩ VDD MBAT4 ATA6871 100 nF 1 kΩ OROUT_IN 10 nF ROROUT 51 kΩ To Emergency Relais PD_N 100 nF PD_N_OUT MBAT2 51 kΩ Microcontroller Supploy STATUS_IN 100 nF 1 kΩ 100 nF OROUT MBAT3 1 kΩ 121 kΩ BIASRES MBAT5 STATUS MBAT1 TEMP_IN VSSA CONF1 CONF0 ENUV Microcontroller RREF NTC 50Ω Note: 20 ROROUT can be used to check if the connection between the lowest ATA6871 and the emerging Relays is available. ATA6871 [Preliminary] 9123B–AUTO–07/09 ATA6871 [Preliminary] 9. Ordering Information Extended Type Number Package MOQ ATA6871-TLPW SSO28 1,000 pieces ATA6871-TLQW SSO28 4,000 pieces 10. Package Information The IC is packaged in a SSO28 package — green (lead-free/RoHS) package. 5.4±0.2 0.65±0.05 1.3±0.05 0.05+0.1 0.25±0.05 6.45±0.15 0.15±0.05 4.4±0.1 9.35-0.25 8.45±0.05 28 15 Package: SSO28 Dimensions in mm technical drawings according to DIN specifications 1 14 Drawing-No.: 6.543-5056.03-4 Issue: 1; 10.03.04 21 9123B–AUTO–07/09 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 22 Revision No. History 9123B-AUTO-07/09 • Table 5 “Absolute Maximum Ratings” on page 7 changed • Table 7-1 “Electrical Characteristics” on page 10 changed • Heading “ON-Mode/Selfdiagnosis” on page 10 changed • Table 7-4 “Electrical Characteristics” on page 12 changed • Table 7-8 “Electrical Characteristics” on page 16 changed • Table 7-10 “Digital Output Characteristics (OROUT, STATUS)” on page 19 changed • Table 7-11 “Digital Input Characteristics (OROUT_IN, STATUS_IN)” on page 19 changed • Table 7-12 “Digital Input Characteristics PINs CHIPONE, CHIPLAST, CONF0, CONF1, ENUV” on page 19 changed ATA6871 [Preliminary] 9123B–AUTO–07/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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