View detail for Implementation of SDRAM on SAMA5D2x Devices

APPLICATION NOTE
Implementation of SDRAM on SAMA5D2x Devices
Atmel | SMART SAMA5D2 Series
Scope
The Atmel® | SMART SAMA5D2 Series is a high-performance, power-efficient
embedded MPU based on the ARM® Cortex®-A5 processor.
The SAMA5D21, SAMA5D22, SAMA5D23, SAMA5D24, SAMA5D26, SAMA5D27
and SAMA5D28 eMPUs feature one multi-port DDR controller that supports 32-bit
DDR3(L)-SDRAM, 32-bit LPDDR3-SDRAM, 32-bit DDR2-SDRAM, 32-bit
LPDDR2-SDRAM and 32-bit LPDDR1-SDRAM memories. These memories are
called SDRAM in this document.
SAMA5D2x embeds a pad calibration feature that performs bus impedance
adaptation, improving signal integrity. This leads to a reduction of overshoots, of
Electromagnetic Interference (EMI), of power consumption on I/Os and eliminates
the need of serial resistors on data lines.
This application note helps the developer design a system using external
memory.
Reference Documents
Type
Title
Literature No.
Datasheet
SAMA5D2 Series Datasheet
11267
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
Table of Contents
1.
Multi-port DDR Controller Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.
Multi-Port DDR Controller Signals Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.
SDRAM Connection on SAMA5D2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.2
3.3
3.4
3.5
4.
Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
6.2
7.
General Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DDR2/LPDDR1 Bus Interface Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EBI Trace Routing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LPDDR2-SDRAM and LPDDR3-SDRAM Power-up and Power-off Considerations 14
5.1
5.2
6.
6
7
7
8
9
Layout and Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
5.
32-bit Using 2x16-bit DDR3(L)-SDRAM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-bit Using 2x16-bit DDR2-SDRAM Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR2-SDRAM and DDR3(L)-SDRAM VREF Signal Considerations . . . . . . . . . . . . . . . . . . . . . . . . .
32-bit Using 2x16-bit LPDDR2-SDRAM Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPDDR1-SDRAM, LPDDR2-SDRAM and LPDDR3-SDRAM VREF Signal Considerations. . . . . . . .
Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multi-port DDR Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.1
7.2
7.3
7.4
7.5
7.6
DDR3(L)-SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPDDR3-SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR2-SDRAM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPDDR2-SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPDDR1-SDRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micron® MT41K128M16JT DDR3L-SDRAM (MPDDRC Configuration Example). . . . . . . . . . . . . . .
17
17
17
17
17
17
Appendix A. DDR3(L)-SDRAM Initialization Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Appendix B. DDR2-SDRAM Initialization Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix C. LPDDR2-SDRAM Initialization Code Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
1.
Multi-port DDR Controller Overview
The Multi-port DDR-SDRAM Controller (MPDDRC) is a multi-port memory controller. It comprises eight slave AHB
interfaces. All simultaneous accesses (eight independent AHB ports) are interleaved to maximize memory
bandwidth and minimize transaction latency due to DDR-SDRAM protocol.
The MPDDRC extends the memory capabilities of a chip by providing the interface to the external 16-bit or 32-bit
DDR-SDRAM device. The page size supports ranges from 2048 to 16384 rows and from 256 to 4096 columns. It
supports dword (64-bit), word (32-bit), half-word (16-bit), and byte (8-bit) accesses.
The MPDDRC supports a read or write burst length of eight locations. This enables the command and address bus
to anticipate the next command, thus reducing the latency imposed by the DDR-SDRAM protocol and improving
the DDR-SDRAM bandwidth. Moreover, MPDDRC keeps track of the active row in each bank, thus maximizing
DDRSDRAM performance, e.g., the application may be placed in one bank and data in other banks. To optimize
performance, avoid accessing different rows in the same bank. The MPDDRC supports a CAS latency of 2, 3 or 6
and optimizes the read access depending on the frequency.
Self-refresh, Power-down and Deep Power-down modes minimize the consumption of the DDR-SDRAM device.
OCD (Off-chip Driver) and ODT (On-die Termination) modes are not supported.
The MPDDRC supports DDR3-SDRAM and DDR3L-SDRAM devices with DLL disabled, in DLL Off mode. In this
mode, according to JEDEC standard, the maximum clock frequency is 125 MHz. However, check with memory
suppliers for higher speed support. DDR3-SDRAM supports high capacity, 1 Gbit and more, and enables to
reduce power consumption with a 1.5V supply (DDR3-SDRAM) or a 1.35V supply (DDR3L-SDRAM). The DLL Off
mode sets the CAS Read Latency (CRL) and the CAS Write Latency (CWL) to 6. The latency is automatically set
by the controller.
The MPDDRC I/Os are powered by VDDIODDR. For DDR2-SDRAM and LPDDR1-SDRAM, VDDIODDR is set to
1.8V nominal; for DDR3-SDRAM, VDDIODDR is set to 1.50V nominal; for DDR3L-SDRAM, VDDIODDR is set to
1.35V nominal; for LPDDR2-SDRAM and LPDDR3-SDRAM, VDDIODDR is set to 1.2V nominal.
The DDR Chip Select enables to have 512 Mbytes of SDRAM, from address 0x2000 0000 to address
0x4000 0000 for standard accesses, and from address 0x4000 0000 to address 0x6000 0000 for AES encrypted
accesses.
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
3
2.
Multi-Port DDR Controller Signals Definition
The MPDDRC manages 4-bank and 8-bank SDRAM devices. The signals generated by the controller are defined
in Table 2-1.
Table 2-1.
SDRAM Controller Signals
Signal Name
Function
Type
Active
Level
DDR_RESETN
DDR3 Asynchronous Reset
Input
–
Description
Prevent illegal commands and/or unwanted states.
When Self-refresh mode is used, should be tied to
VDDIODDR using 100 KΩ, pull-up.
DDR_VREF
Reference Voltage
Input
–
Used by the input buffers of the DDR2 memories as
well as the DDR2 controller to determine logic
levels. VREF is specified to be ½ the power supply
voltage and is created using a voltage divider
constructed from two 1.5 KΩ, 1% tolerance resistors.
DDR_CAL
LPDDR2 Calibration
Reference
Input
–
Used to calibrate I/O. See Calibration section for
more details.
DDR_CK, DDR_CKN
DDR2 Differential Clock
Output
–
Differential clock signals that feed the SDRAM
device. All other signals take those two signals as a
reference.
DDR_CKE
DDR2 Clock Enable
Output
High
Acts as an inhibit signal to the DDR device.
DDR_CKE remains high during valid DDR2 access
(Read, Write, Prech). This signal goes low when the
device is in Power-down mode or in Self-refresh
mode; a self-refresh command can be issued by the
controller (refer to the DDR2 controller Self-refresh
mode).
DDR_CS
DDR2 Controller Chip Select
Output
Low
When the Chip Select (DDR_CS) is low, the
command input is valid. When it is high, the
commands are ignored but the operation continues.
DDR_BA[2..0]
Bank Select
Output
Low
Select the bank to address when a command is
input. Read/write or precharge is applied to the bank
selected by DDR_BA0, DDR_BA1, or DDR_BA2.
DDR_WE
DDR2 Write Enable
Output
Low
DDR_RAS - DDR_CAS
Row and Column Signal
Output
Low
DDR_A[13..0]
DDR2 Address Bus
Output
–
SDRAM controller address lines, respectively
bounded to [A0:A13] on the microcontroller.
DDR_D[31..0]
DDR2 Data Bus
I/O/-PD
–
SDRAM controller data lines, respectively bounded
to [DDR_D31:DDR_D0] on the microcontroller.
–
DDR_DQS[0..3]: Data Strobe. The data is sampled
on DDR_DQS edges.
DDR_DQSN[0..3]: Negative Data Strobe, for
LPDDR2-SDRAM. DQSN must be connected to
DDR_VREF for DDR2 memories.
DDR_DQS[3..0],
DDR_DQSN[3..0]
4
Differential Data Strobe
I/O/-PD
The Row Address Strobe (DDR_RAS) and the
Column Address Strobe (DDR_CAS) will assert to
indicate that the corresponding address is present
on the bus. The conjunction with Write Enable
(DDR_WE) and chip select (SDCS), at the rising
edge of the clock (DDR_CK) or the falling edge of
the #clock (#DDR_CK), determines the DDR2
operation.
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
Table 2-1.
SDRAM Controller Signals (Continued)
Signal Name
Function
DDR_DQM[3..0]
Write Data Mask
Type
Active
Level
Output
–
Description
Data is accessed in 32 bits by means of
DDR_DQM[3..0], which are respectively the highest
to lowest mask bits for the DDR2 data on the bus.
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
5
3.
SDRAM Connection on SAMA5D2x
The user interface to configure the MPDDR controller is mapped at address 0xF000 C000.
Each memory device must use sufficient decoupling to provide an efficient filtering on the power supply rails.
3.1
32-bit Using 2x16-bit DDR3(L)-SDRAM Implementation
3.1.1
Hardware Configuration
100 ohms differential trace
impedance
Routing top or bottom
100 ohms differential trace
impedance
Routing top or bottom
U8
U4
U6E
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
F12
C17
B17
B16
C16
G14
F14
F11
C14
D13
C15
A16
A17
G11
DDR_BA0
DDR_BA1
DDR_BA2
H12
H13
F17
DDR_RAS
DDR_CAS
F13
G12
DDR_CLK+
DDR_CLKDDR_CKE
E17
D17
F16
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_BA0
DDR_BA1
DDR_BA2
DDR_RAS
DDR_CAS
DDR_CLK
DDR_CLKN
DDR_CKE
R244
100K
DDR_CS
DDR_WE
G13
F15
E13
VDD_1V35
23.2K 1%
22pF
R251
C104
DDR_CS
DDR_WE
DDR_CAL
DDR_DQS0
DDR_DQSN0
R243
100K
DDR_DQS1
DDR_DQSN1
DDR_RESETN
E16
DDR_VREF
H16
D16
C98
100nF
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
C97
100nF
DDR_RESETN
DDR_DQS2
DDR_DQSN2
DDR_VREFB0
DDR_VREFCM
DDR_DQS3
DDR_DQSN3
B12
A12
C12
A13
A14
C13
A15
B15
G17
G16
H17
K17
K16
J13
K14
K15
B8
B9
C9
A9
A10
D10
B11
A11
J12
H10
J11
K11
L13
L11
L12
M17
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
C11
G15
C8
H11
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
B13
B14
DDR_DQS0+
DDR_DQS0-
J17
J16
DDR_DQS1+
DDR_DQS1-
C10
B10
DDR_DQS2+
DDR_DQS2-
L17
L16
DDR_DQS3+
DDR_DQS3-
DDR_RESETN
T2
DDR_CLK+
DDR_CLKDDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
J7
K7
K9
L2
J3
K3
L3
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR_DQS1+ C7
DDR_DQS1- B7
DDR_DQS0+ F3
DDR_DQS0- G3
DDR_DQM1 D3
DDR_DQM0 E7
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDD_1V35
J1
J9
L1
L9
RESET#
CK
CK#
CKE
CS#
RAS#
CAS#
WE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ODT
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
UDQS
UDQS#
LDQS
LDQS#
UDM
LDM
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
NC1
NC2
NC3
NC4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
SAMA5D27-CN
DDR_VREF
C89
100nF
M8
C70
100nF
H1
VREFCA
VREFDQ
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
R186
B2
G7
R9
K2
K8
N1
N9
R1
D9
VDD_1V35
DNP(1K)
0R
DDR_CLK+
DDR_CLKDDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
J7
K7
K9
L2
J3
K3
L3
VDD_1V35
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR_DQS3+ C7
DDR_DQS3- B7
DDR_DQS2+ F3
DDR_DQS2- G3
DDR_DQM3 D3
DDR_DQM2 E7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VDD_1V35
B1
B9
D1
D8
E2
E8
F9
G1
G9
A1
A8
C1
C9
D2
E9
F1
H2
H9
J1
J9
L1
L9
DDR_VREF
C143
100nF
L8
DDR_CLK+
T2
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
K1
R185
DDR_RESETN
C119
100nF
M8
H1
RESET#
CK
CK#
CKE
CS#
RAS#
CAS#
WE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ODT
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
UDQS
UDQS#
LDQS
LDQS#
UDM
LDM
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
NC1
NC2
NC3
NC4
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VREFCA
VREFDQ
ZQ
R239
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
R255
VDD_1V35
DNP(1K)
K1
R259
B2
G7
R9
K2
K8
N1
N9
R1
D9
0R
VDD_1V35
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
L8
R130
240R 1%
MT41K128M16JT-125:K
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
MT41K128M16JT-125:K
240R 1%
R160
DNP(100R 1%)
DDR_CLKVDDIODDR
L14 10uH_150mA
C81
4.7uF
R189
1R 1%
C55
4.7uF
VDD_1V35
C54
100nF
R188
6.8K 1%
C152
2.2uF
C96
2.2uF
C90
100nF
C111
100nF
C91
100nF
C148
100nF
C93
100nF
C94
100nF
C87
100nF
C74
100nF
C127
100nF
C124
100nF
C121
100nF
C147
100nF
C64
100nF
C113
100nF
C72
1nF
C80
1nF
C122
2.2uF
C92
100nF
C110
100nF
C115
100nF
C136
100nF
C151
100nF
C144
100nF
C149
100nF
C88
100nF
C114
100nF
C63
100nF
C76
100nF
C75
100nF
C85
100nF
C66
100nF
C65
1nF
C139
1nF
DDR_VREF
C53
100nF
R187
6.8K 1%
VDD_1V35
C150
2.2uF
Keep nets as short as possible, therefore, DDR devices have to be placed close as possible of SAMA5D27
The layout DDR should use controlled impedance traces of ZO= 50ohm characteristic impedance.
Address, control and data traces may not exceed 1.3 inches (33.0 mm).
Address, control and data traces must be length-matched to within 0.1 inch (2.54mm).
3.1.2
Software Configuration
Refer to Section 7.1 “DDR3(L)-SDRAM Initialization” for information on the DDR3 initialization sequence.
6
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
3.2
32-bit Using 2x16-bit DDR2-SDRAM Implementation
3.2.1
Hardware Configuration
{3} DDR_D[0..31]
{3} DDR_A[0..13]
MN8
{3}
{3}
{3}
DDR_BA0
DDR_BA1
DDR_BA2
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
VDDIODDR
R93 DNP
R94
{3}
DDR_CKE
{3}
{3}
DDR_CLK
DDR_CLKN
{3}
DDR_CS
{3}
{3}
DDR_CAS
DDR_RAS
{3}
DDR_WE
{3}
DDR_DQS1
0R
DDR_CKE
K2
DDR_CLK
DDR_CLKN
J8
K8
DDR_CS
L8
DDR_CAS
DDR_RAS
L7
K7
DDR_WE
K3
B7
A8
R98
{3}
DDR_DQS0
{3}
{3}
DDR_DQM1
DDR_DQM0
K9
R99
VREF
UDQS
UDQS
4.7K
F7
E8
MN9
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H128M16RT DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
A12
DQ12
DQ13
DQ14
BA0
DQ15
BA1
BA2
VDD
ODT
VDD
VDD
VDD
VDD
CKE
VDDL
CK
CK
VDDQ
VDDQ
VDDQ
CS
VDDQ
VDDQ
VDDQ
CAS
VDDQ
RAS
VDDQ
VDDQ
WE
VDDQ
LDQS
LDQS
VSS
VSS
VSS
VSS
VSS
4.7K
B3
F3
DDR_A13
A2
E2
R3
R7
R8
UDM
LDM
RFU1
RFU2
RFU3
RFU4
RFU5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
VDDIODDR
A1
E1
J9
M9
R1
C53
C55
C57
C59
C61
J1
100nF
100nF
100nF
100nF
100nF
C63 100nF
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
VDDIODDR
C65
C67
C69
C71
C73
C75
C77
C79
C81
C83
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
R91
DNP
R92
0R
K9
DDR_CKE
K2
DDR_CLK
DDR_CLKN
J8
K8
DDR_CS
L8
DDR_CAS
DDR_RAS
L7
K7
DDR_WE
K3
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H128M16RT DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
A12
DQ12
DQ13
DQ14
BA0
DQ15
BA1
BA2
VDD
ODT
VDD
VDD
VDD
VDD
CKE
VDDL
CK
CK
VDDQ
VDDQ
VDDQ
CS
VDDQ
VDDQ
VDDQ
CAS
VDDQ
RAS
VDDQ
VDDQ
WE
VDDQ
DDR_VREF
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
{3}
B7
A8
DDR_DQS3
C85
100nF
R100 4.7K
{3}
DDR_DQS2
{3}
{3}
DDR_DQM3
DDR_DQM2
F7
E8
VREF
UDQS
UDQS
LDQS
LDQS
VSS
VSS
VSS
VSS
VSS
R101 4.7K
B3
F3
DDR_A13
A2
E2
R3
R7
R8
UDM
LDM
RFU1
RFU2
RFU3
RFU4
RFU5
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
VDDIODDR
A1
E1
J9
M9
R1
C54
C56
C58
C60
C62
J1
C64 100nF
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
100nF
100nF
100nF
100nF
100nF
C66
C68
C70
C72
C74
C76
C78
C80
C82
C84
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
DDR_VREF
A3
E3
J3
N1
P9
C86
100nF
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
DDR2 SDRAM
3.2.2
Software Configuration
Refer to Section 7.1 “DDR3(L)-SDRAM Initialization” for information on the DDR2 initialization sequence.
3.3
DDR2-SDRAM and DDR3(L)-SDRAM VREF Signal Considerations
DDR_VREF, which is half the interface voltage, is provided by a voltage divider of VDDIODDR.

0.9V for 1.80V typical VDDIODDR for DDR2 Interface I/O lines

0.68V for 1.35V typical VDDIODDR for DDR3L Interface I/O lines

0.75V for 1.50V typical VDDIODDR for DDR3 interface I/O lines
DDR_VREF is not a high current supply, but it is important to keep it as noiseless as possible with minimal
inductance. DQSN[3:0] must be connected to DDR_VREF for DDR2-SDRAM and DDR3(L)-SDRAM memories.
Figure 3-1.
Example for DDR3L-SDRAM
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
7
3.4
32-bit Using 2x16-bit LPDDR2-SDRAM Implementation
3.4.1
Hardware Configuration
DDR_D[0..31]
LPDDR2 SDRAM
LPDDR2 SDRAM
U1A
C1
R1
49.9
DDR_CLK
R2
49.9
DDR_CLKN
100nF
DDR_RAS
DDR_CAS
DDR_WE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
AC6
AB6
AC7
AB8
AB9
W1
V2
U1
T2
T1
DDR_CKE
AC3
AC4
DDR_CLK
DDR_CLKN
VDDIODDR
1V2_VDD2
R3
0R
R4
0R
R5
0R
1V2_VDDCA
Y2
Y1
DDR_CS
AB3
AB4
DDR_DQS0
DDR_DQSN0
R23
P22
DDR_DQS1
DDR_DQSN1
J22
K23
1V2_VDDQ
AB18
AC19
B18
A19
DDR_DQM0
DDR_DQM1
N23
L23
AB20
B20
1V8_VDD1
1V2_VDD2
1V2_VDDCA
1V2_VDDQ
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C2
C8
C12
C13
C9
C16
C18
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C20
C21
C23
C24
C26
C28
C6
C7
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
B11
B21
C2
L22
R2
AA2
AB10
AB21
U2
W2
AC8
B13
B16
B19
D22
G22
K22
R22
V22
AA22
AB13
AB16
AB19
C38
C40
C42
C44
C46
C48
C50
C52
C54
C56
C58
C60
VREFCA
VREFDQ
CKE0
CKE1
CK
CK#
CS0#
CS1#
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
U2A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
AA23
Y22
W22
W23
V23
U22
T22
T23
H22
H23
G23
F22
E22
E23
D23
C22
AB12
AC13
AB14
AC14
AB15
AC16
AB17
AC17
B17
A17
A16
B15
B14
A14
A13
B12
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_RAS
DDR_CAS
DDR_WE
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
AC6
AB6
AC7
AB8
AB9
W1
V2
U1
T2
T1
DDR_CKE
AC3
AC4
DDR_CLK
DDR_CLKN
DDR_CS
R20
0R
ZQ
DDR_DQS3
DDR_DQSN3
J22
K23
AB18
AC19
B18
A19
P1
R6
DDR_DQM2
DDR_DQM3
240R 1%
P2
M22
A3
A4
A5
A7
A8
A10
B4
B6
B7
B9
D1
D2
E1
E2
G1
G2
H1
H2
K1
K2
L1
L2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDDCA
VDDCA
VDDCA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFCA
VREFDQ
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DNU13
DNU14
DNU15
DNU16
(NC)1
(NC)2
(NC)3
(NC)4
(NC)5
NC23
NC24
NC25
B5
B10
C1
F2
J2
M2
M23
AA1
AC5
AC9
A21
B8
R1
AB11
AC21
1V2_VDD2
1V2_VDDCA
V1
AB7
1V2_VDDQ
A12
A15
A18
C23
F23
J23
P23
U23
Y23
AC12
AC15
AC18
A1
A2
A22
A23
B1
B2
B22
B23
AB1
AB2
AB22
AB23
AC1
AC2
AC22
AC23
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C10
C11
C3
C14
C15
C17
C19
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C4
C22
C5
C25
C27
C29
C30
C31
B11
B21
C2
L22
R2
AA2
AB10
AB21
U2
W2
AC8
100nF C33
100nF C35
100nF C37
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
B13
B16
B19
D22
G22
K22
R22
V22
AA22
AB13
AB16
AB19
C39
C41
C43
C45
C47
C49
C51
C53
C55
C57
C59
C61
VREFCA
VREFDQ
A6
A9
F1
J1
AC10
M1
N1
AC11
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CKE0
CKE1
CK
CK#
CS0#
CS1#
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
AA23
Y22
W22
W23
V23
U22
T22
T23
H22
H23
G23
F22
E22
E23
D23
C22
AB12
AC13
AB14
AC14
AB15
AC16
AB17
AC17
B17
A17
A16
B15
B14
A14
A13
B12
P2
M22
A3
A4
A5
A7
A8
A10
B4
B6
B7
B9
D1
D2
E1
E2
G1
G2
H1
H2
K1
K2
L1
L2
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DQS3
DQS3#
DM0
DM1
DM2
DM3
ZQ
P1
MT42L128M16D1KL-25
U2B
A11
A20
B3
N2
N22
AC20
AB5
MT42L128M16D1KL-25
8
N23
L23
AB20
B20
1V8_VDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
AB3
AB4
R23
P22
DQS3
DQS3#
DM0
DM1
DM2
DM3
Y2
Y1
DDR_DQS2
DDR_DQSN2
MT42L128M16D1KL-25
U1B
A11
A20
B3
N2
N22
AC20
AB5
100nF C32
100nF C34
100nF C36
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDDCA
VDDCA
VDDCA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREFCA
VREFDQ
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
VSSCA
VSSCA
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DNU13
DNU14
DNU15
DNU16
(NC)1
(NC)2
(NC)3
(NC)4
(NC)5
NC23
NC24
NC25
MT42L128M16D1KL-25
B5
B10
C1
F2
J2
M2
M23
AA1
AC5
AC9
A21
B8
R1
AB11
AC21
V1
AB7
A12
A15
A18
C23
F23
J23
P23
U23
Y23
AC12
AC15
AC18
A1
A2
A22
A23
B1
B2
B22
B23
AB1
AB2
AB22
AB23
AC1
AC2
AC22
AC23
A6
A9
F1
J1
AC10
M1
N1
AC11
R7
240R 1%
3.4.2
Software Configuration
Refer to Section 7.4 “LPDDR2-SDRAM Initialization” for information on the LPDDR2 initialization sequence.
3.5
LPDDR1-SDRAM, LPDDR2-SDRAM and LPDDR3-SDRAM VREF Signal Considerations
DDR_VREF, which is half the interface voltage, is provided by a voltage divider of VDDIODDR.

0.9V for 1.80V typical VDDIODDR for LPDDR Interface I/O lines

0.6V for 1.20V typical VDDIODDR for LPDDR2 / LPDDR3 Interface I/O lines
DDR_VREF is not a high current supply, but it is important to keep it as noiseless as possible with minimal
inductance.
To reduce noise, two VREF pins are needed for LPDDR2-SDRAM: VREFCA and VREFDQ.
1V2_VDDCA
L1
10uH/150mA
VREFCA
R8
1R
C62
100nF
R9
1.5K 1%
R10
C63
4.7uF
C64
100nF
0R
C65
100nF
R11
1.5K 1%
C74
100nF
1V2_VDDQ
L2
10uH/150mA
VREFDQ
R14
1R
C66
100nF
R15
1.5K 1%
R16
C71
4.7uF
C72
100nF
R18
1.5K 1%
0R
C73
100nF
C75
100nF
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
9
4.
Layout and Design Constraints
4.1
General Considerations
This section provides routing guidelines for layout and design of a printed circuit board using high-speed
memories. The signal integrity rules for high-speed interfaces need to be considered. In fact, it is highly
recommended that the board design be simulated to determine optimum layout for signal integrity and quality.
Keep in mind that this document can only highlight the most important issues that should be considered when
designing a board with high-speed memories. The designer has to take into account the corresponding information
(specification, design guidelines, etc.) contained in the documentation for each interface that is to be implemented
on board.
The length difference between the data lane and the CK signal should not exceed 400 mils.
In each data lane (e.g. lane0 includes DQ[7:0]/DM0/DQS0), the length difference between each signal and the
respective DQS/DQSn signal should not exceed 100 mils.
The following rules should also be observed:
4.2

3W rule: keep the distance between two adjacent traces larger than 3 times the trace width.

Serpentine routing rule: when a design requires equal-length traces between the source and multiple loads,
some traces can be bent in order to match the trace lengths. However, improper trace bending affects signal
integrity and propagation delay. To minimize crosstalk, ensure that S ≥ 3 × H, where S is the spacing
between the parallel sections and H is the height of the signal trace above the reference plane.
DDR2/LPDDR1 Bus Interface Controller
Bus signals can be split in three groups:
1.
Differential Clock source, VREF middle voltage point for DDR2 reference voltage
̶
2.
3.
4.2.1
This first and most critical signal group is set up by the CK, NCK signals and the VREF reference
voltage only.
Bus, Strobe and Mask signals
̶
Data bus signals
̶
DQS signals
̶
DQM signals
Address, Control signals
̶
Address bus signals (DDR_Ax)
̶
DDR_BAx signals (Bank select signals)
̶
CKE signal, RAS, CAS, NWE and NCS control signals
Group 1 Signals
Group 1 signals are the most critical, and should be routed first. The clock is driven in Differential mode. Two
traces should be planned to drive those signals to DDR2 packages. The clock traces have the same impedance,
and therefore:

Both traces must be routed on the outer layer.

Both traces must be parallel.

Clock traces must use only two vias/traces.
Voltage reference VREF can be impacted by noise. Those voltage reference traces versus other traces must be
kept away from noisy digital traces (in three dimensions: above and below layers and on both sides): maintain a
15–20 mils clearance from other nets.
10
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
This net should be larger than other traces (like a small local voltage plane), and located on the layer closest to the
ground layer.
4.2.2
Group 2 Signals
Route Group 2 signals by keeping the propagation delay equal as first constraint:
4.2.3

Route each data group (DQ + DQS + DM) on the same layer to match propagation delays and minimize
skew between these signals.

Between signals DQ and DQM, keep a minimum space of 3 widths; between DQS (potentially impacted by
noise) and DQ/DQM, keep a minimum space of 4 widths.
Group 3 Signals
Group 3 signals should be routed by minimizing crosstalk with [DQ, DQS, DQM] ↔ [Addresses, CTRL Bus]:
maintain a gap between the two groups and do not interlace them.
Table 4-1.
Example of PCB Stackup
Layer
Type
Description
Layer 1 (Top)
Signal
Differential and critical signals: oscillators, quartz, clock, DDR_VREF,
DDR_CLK / DDR_NCLK, etc. address/data buses
Layer 2
GND
GND
Layer 3
Signal
Address/data buses, non-critical signal
Layer 4
Signal
Address/data buses, non-critical signal
Layer 5
Power plane
Non-critical signal
Layer 6 (Bottom)
Signal
Differential and critical signals: oscillators, quartz, clock, DDR_VREF,
DDR_CLK / DDR_NCLK, etc. address/data buses
4.3
EBI Trace Routing Guidelines
4.3.1
Topology About the EBI Bus
Bus impedance: maintain an impedance of 50Ω to ±10%.
4.3.2
Placement
Place the highest-speed/highest-current components as far from the I/O connections as possible.
4.3.3
Bypassing Capacitors
Keep all surface traces that run between the pads of the decoupling capacitors and their vias as short and wide as
possible. Use as small a body size for a decoupling capacitor as you can afford, and minimize the length of all
connections from the capacitor pads to the power and ground planes.
4.3.4
Trace Length
Keep the time delay of stubs less than 20% of the rise time of the fastest signals.
Route the shortest path between MPU and resistor networks dedicated to the memories.
4.3.5
Trace Spacing
For microstrip or stripline transmission lines, keep the spacing between adjacent signal paths at least twice the line
width.
Keep all traces at least five line widths from the edge of the board.
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
11
4.3.6
Vias
Use vias as large in diameter as practical when routing to power or ground planes.
4.3.7
Ground Plane(s)
Follow the return path of each signal and keep the width of the return path under each signal path at least as wide,
and preferably at least three times as wide, as the signal trace.
To avoid EMIs, avoid routing switching signals across splits or openings in ground planes. Routing around them is
preferable even if it results in longer paths.
4.3.8
4.3.9
Power Plane(s)

Minimize the loop inductance between the power and ground paths.

Allocate power and ground planes on adjacent layers with as thin a dielectric as possible.

Route the power and ground planes as close as possible to the surface where the decoupling capacitors are
mounted.

Supply voltages must be composed of planes only, not traces. Short connections (≈ 8 mils) are commonly
used to attach vias to planes. Any connections required from supply voltages to vias for device pins or
decoupling capacitors should be as short and as wide as possible to minimize trace impedance (20 mils
trace width).
General Considerations for High-Speed Differential Interfaces
The following is a list of suggestions for designing with high-speed differential signals.
12

Use controlled impedance PCB traces that match the specified differential impedance.

Keep the trace lengths of the differential signal pairs as short as possible.

The differential signal pair traces should be trace-length matched and the maximum trace-length mismatch
should not exceed the specified values. Match each differential pair per segment.

Maintain parallelism and symmetry between differential signals with the trace spacing needed to achieve the
specified differential impedance.

Maintain maximum possible separation between the differential pairs, any high-speed clocks/periodic
signals (CMOS/TTL) and any connector leaving the PCB (such as I/O connectors, control and signal
headers, or power connectors).

Route differential signals on the signal layer nearest the ground plane using a minimum of vias and corners.
This will reduce signal reflections and impedance changes. Use GND stitching vias when changing layers.

Route CMOS/TTL and differential signals on a different layer(s), which should be isolated by the power and
ground planes.

Avoid tight bends. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a
single 90° turn.

Do not route traces under crystals, crystal oscillators, clock synthesizers, magnetic devices or ICs that use,
and/or generate, clocks.

Stubs on differential signals should be avoided due to the fact that stubs will cause signal reflections and
affect signal quality.

Keep the length of high-speed clock and periodic signal traces that run parallel to high-speed signal lines at
a minimum to avoid crosstalk. Based on EMI testing experience, the minimum suggested spacing to clock
signals is 50 mils.

Use a minimum of 20 mils spacing between the differential signal pairs and other signal traces for optimal
signal quality. This helps to prevent crosstalk.

Route all traces over continuous planes (VCC or GND), avoiding to cross splits or openings in those planes.
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
DDR_A11
DDR_A12
DDR_A13
DDR_D0
DDR_D1
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQSN0
DDR_DQSN1
DDR_DQSN2
DDR_DQSN3
DDR_CS
DDR_CLK
DDR_CLKN
DDR_CKE
DDR_RAS
DDR_DATA
M8
DDR_A1
DDR_D0
DDR_A5
H17
H13
DDR_D1
DDR_D2
DDR_A6
DDR_A7
M3
M7
N2
N8
N3
N7
P2
G17
G16
H15
DDR_D3
DDR_D4
DDR_A8
DDR_A9
P8
P3
DDR_A10
DDR_A11
DDR_A12
M2
F17
G15
DDR_D5
DDR_D6
DDR_D7
F16
E17
DDR_D8
DDR_D9
DDR_A13
G14
E16
DDR_D10
DDR_D11
D17
DDR_D12
C18
DDR_D13
R8
R3
R7
L2
L3
L1
D16
DDR_D14
C17
B16
B18
C15
DDR_D15
DDR_D16
DDR_D17
DDR_D18
A18
DDR_D19
C16
C14
DDR_D20
DDR_D21
D15
B14
A15
A14
DDR_D22
DDR_D23
E12
A11
DDR_D26
DDR_D27
E3
J3
B11
F12
A10
E11
G12
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
N1
E15
B15
DDR_DQM1
DDR_DQM2
5
5
D2
D8
D12
E18
G18
B17
B13
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
5
5
5
DDR_DQS3
5
DDR_VREF
5
DDR_A2
DDR_D[0-31]
DDR_A3
DDR_A4
5
5
5
5
5
VDDIODDR
R50
R51
TP12
DDR_WE
DDR_WE#
5
DDR_BA0
DDR_BA1
E9
B6
DDR_BA0
DDR_BA1
DDR_BA2
5
5
C13
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
5
DDR_CK
GND
A
A0
A1
M8
DDR_A1
DDR_A3
H9
DDR_D3
DDR_D4
DDR_D5
F1
F9
DDR_D6
DDR_D7
DDR_A6
DDR_A7
M3
M7
N2
N8
N3
N7
P2
DQ8
DQ9
DQ10
DQ11
DQ12
C8
C2
DDR_D8
DDR_D9
DDR_A8
DDR_A9
P8
P3
D7
D3
D1
DDR_D10
DDR_A10
DDR_A11
DDR_A12
M2
DQ13
DQ14
DQ15
D9
B1
DDR_D13
DDR_D14
DDR_A13
B9
DDR_D15
LDQS
LDQS#/NU
UDQS
F7
R8
R3
R7
L2
L3
L1
UDQS#/NU
A8
A9
A10
A11
A12
RFU(A13)
K9
K2
CKE
J8
K8
CK
CK#
P9
A7
B2
B8
5
5
G8
DQ2
DQ3
DQ4
H7
H3
DQ5
DQ6
DQ7
VDD
VDDQ
VDDQ
VSS
VSSQ
VSSQ
VDDQ
VDDQ
DDR_DQS0
R72 0402
4k7
DDR_DQS1
R73 0402
4k7
B7
B3
VSSQ
VSSQ
VDDQ
VDDQ
F2
F8
H2
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDL
G7
G9
J1
H8
J7
VSSQ
VSSDL
VREF
J2
5
5
5
5
5
VDDIODDR
R52
0R
R53
DDR_BA0
DDR_BA1
DDR_BA2
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
DNP
0R
C48
C108
100n/10V
C77
100n/10V
C79
100n/10V
N1
DDR_CK#
A3
group 1AB
P9
100n/10V
A7
B2
B8
100n/10V
D2
D8
100n/10V
C53
100n/10V
C76
C56
100n/10V
C57
100n/10V
C112 100n/10V
C111 100n/10V
DDR_VREF
group 1AB
5
GND
DDR_CK#
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
B
DQ0
DQ1
G8
DDR_D16
G2
DDR_D17
DQ2
DQ3
DQ4
H7
H3
DDR_D18
H1
DDR_D20
DQ5
DQ6
DQ7
H9
DDR_D21
F1
F9
DDR_D22
DDR_D23
DQ8
DQ9
DQ10
DQ11
DQ12
C8
C2
DDR_D24
DDR_D25
D7
D3
D1
DDR_D26
DQ13
DQ14
DQ15
D9
B1
DDR_D29
DDR_D30
LDQS
LDQS#/NU
UDQS
F7
UDQS#/NU
A8
DDR_D27
DDR_D28
DDR_D31
B9
E8
R70
B7
R71
DDR_DQS2
4k7
0402
DDR_DQS3
4k7
0402
C60
100n/10V
F3
DDR_DQM2
5
B3
DDR_DQM3
5
NC
NC
A2
E2
VDDIODDR
VDD
VDD
A1
E1
J9
C46
100n/10V
C47
100n/10V
C50
C118
100n/10V
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
M9
R1
A9
C1
C3
C7
VSSQ
VSSQ
VDDQ
VDDQ
E7
VSSQ
VSSQ
VDDQ
VDDQ
C9
E9
G1
G3
F2
F8
H2
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDL
H8
J7
VSSQ
VSSDL
VREF
C117
C51
C54
200R
5
100n/10V
C113 100n/10V
100n/10V
G7
G9
J1
C59
100n/10V
C120 100n/10V
J2
DDR_VREF
C119 100n/10V
C61
100n/10V
GND
C62
group 1AB
100n/10V
top/bot
R13
200R
0402
0402
5
C64
1k5/1%
4u7/6V3/X5R
100n/10V
GND
R14
GND
GND
C65
100n/10V
GND
DDR_VREF
5
100n/10V
C58
BLM15AG121SN1D
R12
1k5/1%
100n/10V
C55
VDDIODDR
R11
GND
C116
100n/10V
100n/10V
C114 100n/10V
100n/10V
C115 100n/10V
L7
R10
5
UDM
5 Differential
5 100 ohms
GND
5
LDM
group 1AB
GND
L3 & L8
DDR_D19
MT47H128M16RT-3:C
group 1AB
DDR_CK
RFU
RFU
BA0
BA1
BA2
CK
CK#
E3
J3
GND
DDR_CK
RFU(A13)
CKE
100n/10V
5
A9
A10
A11
A12
J8
K8
C110
100n/10V
5
A8
K2
100n/10V
0402
A2
A3
A4
A5
A6
A7
K9
100n/10V
100n/10V
A0
A1
WE#
CAS#
RAS#
CS#
ODT
L7
K7
L8
C45
C52
5
E13
GND
5
DDR_CKE
5
R2
C44
C49
GND
1R
C63
5
P7
MT47H128M16RT-3:C
VDDIODDR
5
DDR_VREF
group 1AB
GND
DDR_A5
5
C109
A9
C1
C3
C7
E7
5
DDR_A4
0402
M9
R1
C9
E9
G1
G3
5
VDDIODDR
A1
E1
J9
VDDQ
VDDQ
5
DDR_DQM0
DDR_DQM1
A2
E2
VSSQ
VSSQ
DDR_A2
DDR_D11
DDR_D12
E8
F3
VDD
VDD
VSS
VSS
H1
UDM
VDD
VDD
VSS
VSS
G2
LDM
NC
NC
DDR_CK#
A3
DQ0
DQ1
group 2B
DDR_D[16-31]
U5
DDR_A0
A8
RFU
RFU
BA0
BA1
BA2
DDR_DATA
DDR_ADDR
DDR_A[0-13]
DDR_D0
DDR_D1
DDR_D2
A2
A3
A4
A5
A6
A7
WE#
CAS#
RAS#
CS#
ODT
L7
K7
L8
0402
DDR_VREF
DDR_BA0
DDR_BA1
DDR_BA2
0402
5
R2
group 1AB
top/bot
top/bot
5
C12
0R
5
DDR_CS#
DDR_CAS#
P7
DNP
0402
TP13
A5
B5
DDR_BA2
0R
0402
A12
DDR_CALN
DDR_CALP
5
5
DDR_D25
A17
A13
C8
B12
F9
DDR_CKE
5
DDR_D24
DDR_CKE
DDR_RAS#
SAMA5D3x
DDR_A0
group 2A
L3 & L8
DDR_D[0-15]
U4
D9 DDR_A12
A6 DDR_A13
H12
B7
G11
DDR_CAS
DDR_DATA
DDR_A[0-13]
B8 DDR_A9
F11 DDR_A10
A7 DDR_A11
D18
F18
minimizing crosstalk with [DQ, DQS, DQM]
DDR_ADDR
DDR_A7
0402
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
A8
GND
DDR_A9
DDR_A10
D10 DDR_A6
Zo=50 ohms
DQS-4w-DQ-3w-DQM-4w-DQS
Zo=50 ohms
keeping propagation delay equal
(between 2A & 2B too)
DDR_A8
C10 DDR_A8
L3 & L8
group 3AB
Data traces may not exceed 1.3 inches (33.0 mm).
Data traces must be length-matched to within 0.1 inch (2.54 mm).
Data traces must match the data group trace lengths to within
0.25 inches (6.35 mm).
B9 DDR_A4
E10 DDR_A5
A9 DDR_A2
D11 DDR_A3
Zo=50 ohms
C11 DDR_A1
DQS-4w-DQ-3w-DQM-4w-DQS
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
DDR_A[0-13]
keeping propagation delay equal
(between 2A & 2B too)
B10 DDR_A0
Keep nets as short as possible, therefore, DDR2/LPDDR2 devices have to be placed as close as possible to the MPU.
The layout EBI DDR2/LPDDR2 should use controlled impedance traces of Zo = 50 ohm characteristic impedance.
Trace width = 0.13mm (4 mil minimum, 6 mil nominal)
Trace space = 0.30 to 0.38 mm.
5
GND
SAMA5D2x-CM Memory Schematic
DDR_A0
Figure 4-1.
DDR_ADDR
U3-H
13
5.
LPDDR2-SDRAM and LPDDR3-SDRAM Power-up and Power-off
Considerations
5.1
Power-up Sequence
A specific sequence must be used to power up the LPDDR2-SDRAM or LPDDR3-SDRAM device. This procedure
is mandatory. Power-up and initialization by means other than those specified will result in undefined operation.
Refer to the LPDDR2-SDRAM or LPDDR3-SDRAM datasheet for full details and timings.
5.2
Power-off Sequence
A specific sequence must be used to power off the LPDDR2-SDRAM or LPDDR3-SDRAM device. This procedure
is mandatory. Power-off by means other than those specified will result in uncontrolled power-off.
The VDDIODDR power fail must be handled at system level (IRQ or FIQ). When this event occurs, the LPDDR2LPDDR3 power-off sequence is to be applied using the LPDDR2_LPDDR3_PWOFF bit (bit 3 in MPDDRC_LPR)
before the VDDIODDR power-off.
Uncontrolled power-off sequence can be applied only up to 400 times in the life of a LPDDR2-SDRAM or
LPDDR3-SDRAM device.
Refer to the LPDDR2-SDRAM or LPDDR3-SDRAM datasheet for full details and timings.
14
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
6.
Calibration Considerations
SAMA5D2x embeds a pad calibration feature that performs bus impedance adaptation, improving signal integrity.
This leads to:
6.1

reduction of overshoots,

reduction of Electromagnetic Interference (EMI),

reduction of power consumption on I/Os,

eliminating the need of a serial resistor on data lines.
Hardware
Calibration requires connecting a resistor on DDR_CAL to GND. The resistor value depends on the SDRAM type:

24 KΩ for LPDDR2/LPDDR3

23 KΩ for DDR3L

22 KΩ for DDR3

21 KΩ for DDR2/LPDDR1
Figure 6-1.
Example for DDR3L-SDRAM
6.2
Software
6.2.1
DDR3(L)-SDRAM, DDR2-SDRAM and LPDDR1-SDRAM Calibration
DDR3, DDR2 or LPDDR1 software calibration is to be done only once and requires the following steps:
1.
Set field RDIV in the MPDDRC_IO_CALIBR register, according to the board impedance.
2.
Calculate value TZQIO using the formula TZQIO = (DDRCLK × 20 ns) + 1.
3.
Set the TZQIO time in MPDDRC_IO_CALIBR.
4.
Activate calibration by setting the 5th bit in the High Speed Register (0xFFFFEA24).
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15
6.2.2
LPDDR2-SDRAM and LPDDR3-SDRAM Calibration
LPDDR2 and LPDDR3 software calibration is to be done only once and requires the following steps:
1.
Set field RDIV in the MPDDRC_IO_CALIBR register, according to the board impedance.
2.
Calculate value TZQIO using the formula TZQIO = (DDRCLK × 20 ns) + 1.
3.
Set the TZQIO time in MPDDRC_IO_CALIBR.
4.
Program Short Calibration Time with field ZQCS in LPDDR2_TIM_CAL according to the LPDDR2(3)SDRAM datasheet.
5.
Calculate the calibration pulse over Process Voltage Temperature (PVT) according to the refresh rate, the
temperature and voltage expected change, the temperature and voltage sensitivities defined in the
LPDDR2(3)-SDRAM datasheet, using the formula: COUNT_CAL = ZQCorrection / ((TSens × Tdriftrate) +
(VSens × Vdriftrate)).
6.
Set the value in field COUNT_CAL in the LPDDR23_CAL_MR4 register.
For example, if TSens = 0.75%/°C, VSens = 0.2%/mV, Tdriftrate = 1°C/sec and driftrate = 15mV/sec, then the
interval between ZQCS commands is calculated as 1.5 / ((0.75 × 1) + (0.2 × 15)) = 0.4 sec.
This LPDDR2-SDRAM device requires a calibration every 0.4s.
The value to be loaded depends on the average time between REFRESH commands, tREF.
For an LPDDR2-SDRAM with a time between refresh of 7.8 µs, the value of the Calibration Timer Count bit is
programmed (0.4/7.8 × 10-6) = 0xC852.
16
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7.
Multi-port DDR Controller Configuration
7.1
DDR3(L)-SDRAM Initialization
The DDR3(L)-SDRAM initialization sequence is described in Section “DDR3-SDRAM/DDR3L-SDRAM
Initialization” of the SAMA5D2 Series datasheet. For an example of initialization, see “DDR3(L)-SDRAM
Initialization Code Example”.
7.2
LPDDR3-SDRAM Initialization
The LPDDR3-SDRAM initialization sequence is described in Section “Low-power DDR3-SDRAM Initialization” of
the SAMA5D2 Series datasheet.
7.3
DDR2-SDRAM Initialization
The DDR2-SDRAM initialization sequence is described in Section “DDR2-SDRAM Initialization” of the SAMA5D2
Series datasheet. For an example of initialization, see “DDR2-SDRAM Initialization Code Example”.
7.4
LPDDR2-SDRAM Initialization
The LPDDR2-SDRAM initialization sequence is described in Section “Low-power DDR2-SDRAM Initialization” of
the SAMA5D2 Series datasheet. For an example of initialization, see “LPDDR2-SDRAM Initialization Code
Example”.
7.5
LPDDR1-SDRAM Initialization
The LPDDR1-SDRAM initialization sequence is described in Section “Low-power DDR1-SDRAM Initialization” of
the SAMA5D2 Series datasheet.
7.6
Micron® MT41K128M16JT DDR3L-SDRAM (MPDDRC Configuration Example)
Micron MT41K128M16JT devices are 256 MB DDR3L-SDRAM devices arranged as 16 Mbit × 16 × 8 banks with a
CAS latency of 5 at 166 MHz. These devices are featured on the SAMA5D2-XULT.
Table 7-1 gives the delay in ns extracted from the DDR3L-SDRAM datasheet, the corresponding number of cycles
at 166 MHz, and the field to program these values accordingly in a system running at 498 MHz for Processor Clock
and 166 MHz for System Clock.
Table 7-1.
MPDDRC Configuration Example with Micron MT41K128M16JT
System
Configuration
Description
Value in Number of Value in
Micron
Cycles at SAMA5D2
Datasheet 166 MHz Datasheet
Register
Bit or
Field
Register or
Field Value
System
PLL Frequency
Processor / Bus Clock
System Clock
996 MHz
–
–
–
CKGR_PLLAR
–
0x20523F01
498 / 166 MHz
–
–
–
PMC_MCKR
–
0x00001302
DDR clock
enable
–
–
–
PMC_SCER
–
0x00000005
DDR3L Device
(2)
MPDDRC Configuration Register
–
–
–
–
MPDDRC_CR
–
0x00D0055D
Number of Columns
–
10
–
10
MPDDRC_CR
NC
0x1
Number of Rows
–
14
–
14
MPDDRC_CR
NR
0x3<<2
CAS Latency
–
5
5
5 cycles
MPDDRC_CR
CAS
0x5<<4
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17
Table 7-1.
MPDDRC Configuration Example with Micron MT41K128M16JT (Continued)
Description
System
Configuration
Value in Number of Value in
Micron
Cycles at SAMA5D2
Datasheet 166 MHz Datasheet
Register
Bit or
Field
Register or
Field Value
Reset DLL
–
–
–
Disable
MPDDRC_CR
DLL
0x0<<7
Drive Strength (DDR2 only)
–
Normal
–
Normal
MPDDRC_CR
DIC_DS
0x1<<8
DLL OFF mode
–
–
–
DLL OFF
MPDDRC_CR
DIS_DLL
0x1<<9
Calibration (LPDD2/LPDDR3-SDRAM only)
–
–
–
Disabled
MPDDRC_CR
ZQ
0x0<<10
MPDDRC_CR
OCD
0x0<<12
Off-Chip Driver
–
–
–
(1)
Mask Data is shared
–
–
–
Not shared
MPDDRC_CR
DMQS
0x0<<16
Enable Read Measure
–
–
–
Disabled
MPDDRC_CR
ENRDM
0x0<<17
Number of banks
–
8
–
8
MPDDRC_CR
NB
0x1<<20
Not DQS (DDR2 only)
–
–
–
Disabled
MPDDRC_CR
NDQS
0x0<<21
Type of decoding
–
–
–
interleaved
MPDDRC_CR
DECOD
0x1<<22
Unaligned access allowed
–
–
–
Enabled
MPDDRC_CR
UNAL
0x1<<23
MPDDRC I/O Calibration Register(2)
–
–
–
–
MPDDRC_IO_
CALIBR
–
0x00876504
Resistor Divider
–
–
–
RZQ_60_R
ZQ_57_RZ
Q_55_RZQ
_52Ω
MPDDRC_IO_
CALIBR
RDIV
0x4
Calibration Enable
–
–
–
–
MPDDRC_IO_
CALIBR
EN_CALI
B
0x0<<4
IO calibration
–
–
–
–
MPDDRC_IO_
CALIBR
TZQIO
0x65<<8
Number of transistor P
–
–
–
–
MPDDRC_IO_
CALIBR
CALCOD
EP
0x7<<16
Number of transistor N
–
–
–
–
MPDDRC_IO_
CALIBR
CALCOD
EN
0x8<<20
MPDDRC Read Datapath Register(2)
–
–
–
–
MPDDRC_RD_DAT
A_PATH
–
0x00000002
Shift Sampling
–
–
–
2 cycles
MPDDRC Timing Parameter 0 Register(2)
–
–
–
–
MPDDRC_TPR0
ACTIVATE to PRECHARGE Time (delay)
–
28 ns
5
–
MPDDRC_TPR0
TRAS
0x5
ACTIVATE to READ/WRITE Time (delay)
–
11 ns
2
–
MPDDRC_TPR0
TRCD
0x2<<4
Last DATA-IN to PRECHARGE Time (delay)
–
4 CK in DLL
off mode
4
–
MPDDRC_TPR0
TWR
0x4<<8
REFRESH to ACTIVATE Time (delay)
–
49 ns
9
–
MPDDRC_TPR0
TRC
0x9<<12
PRECHARGE to ACTIVATE Time (delay)
–
14 ns
3
–
MPDDRC_TPR0
TRP
0x3<<16
ACTIVE BankA to ACTIVE BankB (delay)
–
Max of
7.5 ns or
4 CK
4
–
MPDDRC_TPR0
TRRD
0x4<<20
Internal Write to Read Delay
–
Max of
7.5 ns or
4 CK
4
–
MPDDRC_TPR0
TWTR
0x4<<24
18
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SHIFT_S
MPDDRC_RD_DAT
AMPLIN
A_PATH
G
0x2
0x44439425
Table 7-1.
MPDDRC Configuration Example with Micron MT41K128M16JT (Continued)
System
Configuration
Description
Value in Number of Value in
Micron
Cycles at SAMA5D2
Datasheet 166 MHz Datasheet
Register
Bit or
Field
Register or
Field Value
Load Mode Register Command to ACTIVE or
REFRESH Command (delay)
–
Max of
7.5 ns or
4 CK
4
–
MPDDRC_TPR0
TMRD
0x4<<28
MPDDRC Timing Parameter 1 Register
–
–
–
–
MPDDRC_TPR1
–
0x03001D1B
Row Cycle Delay
–
160 ns
27
–
MPDDRC_TPR1
TRFC
0x1B
Exit Self-Refresh Delay to Non-Read Command
–
TRFC +
10 ns
29
–
MPDDRC_TPR1
TXSNR
0x1D<<8
Exit Self Refresh Delay to Read Command (not
used in DDR3(L))
–
0 cycles
0
–
MPDDRC_TPR1
TXSRD
0x0<<16
Exit Power-down Delay to First Command
–
Max of 6 ns
or 3 CK
3
–
MPDDRC_TPR1
TXP
0x3<<24
MPDDRC Timing Parameter 2 Register(2)
–
–
–
–
MPDDRC_TPR2
Read to Precharge
–
Max of
7.5 ns or
4 CK
4
–
MPDDRC_TPR2
TRTP
0x4<<12
Four Active Windows
–
40 ns
7
–
MPDDRC_TPR2
TFAW
0x7<<16
MPDDRC Memory Device Register
–
–
–
–
MPDDRC_MD
Memory Device
DDR2-SDRAM
–
–
–
MPDDRC_MD
MD
0x4
Data Bus Width
32 bits
–
–
–
MPDDRC_MD
DBW
0x0<<4
166 MHz
7.8 µs
–
–
MPDDRC_RTR
COUNT
0x510
MPDDRC Refresh Timer Register - Timer
Count
Notes:
0x00074000
0x00000004
1. OCD is not supported, but it is a mandatory step in the DDR2 initialization phase.
2. Any bit or field of this register not listed in the table must remain unchanged.
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19
Appendix A. DDR3(L)-SDRAM Initialization Code Example
This appendix provides an example of the DDR3L initialization code, associated with the different steps of the
DDR3L-SDRAM initialization sequence. All defines are given in mpddrc.h or ddr.h.
int ddr3_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
/* Compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_very_loud(" ba_offset = %x ...\n", ba_offset);
/*
* Step 1: Program the memory device type in the MPDDRC Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program features of the DDR3-SDRAM device in the MPDDRC
* Configuration Register and in the MPDDRC Timing Parameter 0 Register
* /MPDDRC Timing Parameter 1 Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: A NOP command is issued to the DDR3-SRAM.
* Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
* The application must write a one to the MODE field in the MPDDRC_MR
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* The clock which drive the DDR3-SDRAM device are now enabled.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 4: A pause of at least 500us must be observed before a single toggle.
20
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*/
udelay(500);
/*
* Step 5: A NOP command is issued to the DDR3-SDRAM
* Program the NOP command in the MPDDRC_MR.
* The application must write a one to the MODE field in the MPDDRC_MR.
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* CKE is now driven high.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 6: An Extended Mode Register Set (EMRS2) cycle is issued to choose
* between commercial or high temperature operations. The application must
* write a five to the MODE field in the MPDDRC_MR and perform a write
* access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2] is set to 0,
* BA[1] is set to 1 and signal BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x2 << ba_offset))) = 0;
/*
* Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
* the Extended Mode Register to 0. The application must write a five
* to the MODE field in the MPDDRC_MR and perform a write access to the
* DDR3-SDRAM to acknowledge this command. The write address must be
* chosen so that signal BA[2] is set to 0, BA[1] is set to 1 and signal
* BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x3 << ba_offset))) = 0;
/*
* Step 8: An Extended Mode Register Set (EMRS1) cycle is issued to
* disable and to program O.D.S. (Output Driver Strength).
* The application must write a five to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2:1] is set to 0
* and signal BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/*
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21
* Step 9: Write a one to the DLL bit (enable DLL reset) in the MPDDRC
* Configuration Register (MPDDRC_CR)
/*
* Step 10: A Mode Register Set (MRS) cycle is issued to reset DLL.
* The application must write a three to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)ram_address) = 0;
udelay(50);
/*
* Step 11: A Calibration command (MRS) is issued to calibrate RTT and
* RON values for the Process Voltage Temperature (PVT).
* The application must write a six to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_DEEP_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 12: A Normal Mode command is provided.
* Program the Normal mode in the MPDDRC_MR and perform a write access
* to any DDR3-SDRAM address to acknowledge this command.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 13: Perform a write access to any DDR3-SDRAM address.
*/
*((unsigned int *)ram_address) = 0;
/*
* Step 14: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register (MPDDRC_RTR):
* refresh rate = delay between refresh cycles.
* The DDR3-SDRAM device requires a refresh every 7.81 us.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
return 0;
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Appendix B. DDR2-SDRAM Initialization Code Example
This appendix provides an example of the DDR2 initialization code, associated with the different steps of the
DDR2-SDRAM initialization sequence.
//*---------------------------------------------------------------------------//* \fn
ddram_init
//* \brief Initialization of the DDR Controller
//*---------------------------------------------------------------------------int ddram_init(unsigned int ddram_controller_address, unsigned int ddram_address, struct
SDdramConfig *ddram_config)
{
volatile unsigned int i;
unsigned int cr = 0;
// Initialization Step 1: Program the memory device type
// Configure the DDR controller
write_ddramc(ddram_controller_address, HMPDDRC_MDR, ddram_config->ddramc_mdr);
// Program the DDR Controller
write_ddramc(ddram_controller_address, HMPDDRC_CR, ddram_config->ddramc_cr);
// Initialization Step 2: assume timings for 7.5 ns min clock period
write_ddramc(ddram_controller_address, HMPDDRC_T0PR, ddram_config->ddramc_t0pr);
// pSDDRC->HMPDDRC_T1PR
write_ddramc(ddram_controller_address, HMPDDRC_T1PR, ddram_config->ddramc_t1pr);
// pSDDRC->HMPDDRC_T2PR
write_ddramc(ddram_controller_address, HMPDDRC_T2PR, ddram_config->ddramc_t2pr);
// Initialization Step 3: NOP command -> allow to enable clk
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// Initialization Step 3 (must wait 200 µs) (6 core cycles per iteration, core is at 536 MHz:
// min 17,733 loops)
for (i = 0; i < 17800; i++) {
asm("
nop");
}
// Initialization Step 4: A NOP command is issued to the DDR2-SDRAM
// NOP command -> allow to enable cke
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
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23
// Initialization Step 5: Set All Bank Precharge
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int*) ddram_address) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
// Initialization Step 6: Set EMR operation (EMRS2)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x4000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 7: Set EMR operation (EMRS3)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x6000000)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 8: Set EMR operation (EMRS1)
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ddram_address + 0x2000000)) = 0;
// wait 200 cycles min
for (i = 0; i < 10000; i++) {
asm("
nop");
}
// Initialization Step 9: enable DLL reset
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
// Initialization Step 10: reset DLL
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
24
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// Initialization Step 11: Set All Bank Precharge
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 400 ns min
for (i = 0; i < 250; i++) {
asm("
nop");
}
// Initialization Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh
// command (CBR) into the Mode Register.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Set 2nd CBR
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 13: Program DLL field into the Configuration Register to low (Disable
// DLL reset).
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));
// Initialization Step 14: A Mode Register set (MRS) cycle is issued to program the parameters
// of the DDR2-SDRAM devices.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_LMR_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// Initialization Step 15: Program OCD field into the Configuration Register to high (OCD
// calibration default).
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr | AT91C_DDRC2_OCD_DEFAULT);
// Initialization Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default
// value.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x2000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
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25
// Initialization Step 17: Program OCD field into the Configuration Register to low (OCD
// calibration mode exit). Write a 1 to DIC_DS field to use DDR2 weak drive strength.
cr = read_ddramc(ddram_controller_address, HMPDDRC_CR);
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr & (~AT91C_DDRC2_OCD_EXIT));
write_ddramc(ddram_controller_address, HMPDDRC_CR, cr |(AT91C_DDRC2_WEAKSTRENGTH));
// Initialization Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD
// exit.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*(((unsigned int*) (ddram_address + 0x6000000))) = 0;
// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm("
nop");
}
// Initialization Step 19, 20: A mode Normal command is provided. Program the Normal mode into
// Mode Register.
write_ddramc(ddram_controller_address, HMPDDRC_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(((unsigned volatile int*) ddram_address)) = 0;
// Initialization Step 21: Write the refresh rate into the count field in the Refresh Timer
// Register.
// Set Refresh timer
write_ddramc(ddram_controller_address, HMPDDRC_RTR, ddram_config->ddramc_rtr);
// OK, now we are ready to work on the DDRSDR
// wait for the end of calibration
for (i = 0; i < 500; i++) {
asm("
nop");
}
return 0;
}
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Appendix C. LPDDR2-SDRAM Initialization Code Example
This appendix provides an example of the LPDDR2 initialization code, associated with the different steps of the
LPDDR2-SDRAM initialization sequence.
void LPDDR2_MT42L128M16D1_Initialise( LPDDR2 psst_ddr2 )
{
/****************************************************************************************/
/****************************************************************************************/
// Initialization Step 1
// Program the memory device type into the Memory Device Register
/****************************************************************************************/
/****************************************************************************************/
// Memory device = LPDDR2 => MPDDRC_MD_MD_LPDDR2_SDRAM
// Data bus width = 32 bits => 0x0 (The system is in 64 bits, thus memory data bus width should
be 32 bits)
MPDDRC->MPDDRC_MD = MPDDRC_MD_MD_LPDDR2_SDRAM ;// LPDDR2
/****************************************************************************************/
/****************************************************************************************/
// Initialization Step 2
// Program the features of Low-power DDR2-SDRAM device into the Timing Register
// (asynchronous timing, trc, tras, etc.) and into the Configuration Register (number of
// columns, rows, banks, CAS latency and output drive strength) (see Section 8.3 on
// page 35, Section 8.4 on page 39 and Section 80.5 on page 41).
/****************************************************************************************/
/****************************************************************************************/
//////////////////////////MPDDRC Configuration Register//////////////////////////
// NC = 0x0. Number of collumn to address is 9 (extract from memory data sheet)
// NR = 0x2. Number of row to address is 13 (extract from memory data sheet)
// CAS latency = 3. FPGA platform runs at 30 MHz (depends on the frequency, check memory data
sheet)
// No DLL in LPDDR2 devices => DLL, DIS_DLL and DIC_DS = 0
// ZQ = 0. ZQ_INIT calibration will be performed later
// OCD = 0
// DQMS = 0. Bus isnt shared
// NB = 0.5 8 banks (extract from memory data sheet)
// NDQS = 0. LPDDR2 uses DQS and NDQS
// DECOD = 0. Sequential decoding is choosen (may changed after the initialization)
// UNAL = 1; Unaligned accesses will be performed
MPDDRC->MPDDRC_CR = (psst_ddr2.n_col|
psst_ddr2.n_row
// 9 col + 8 COl supported or not
|
// 14 row
MPDDRC_CR_CAS_3_LPDDR2
|
// CAS 3
MPDDRC_CR_NB_8) |
// 8 banks
MPDDRC_CR_UNAL_SUPPORTED|
// Unaligned accesses
MPDDRC_CR_ENRDM_ON;
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27
// Write the LPDDR2 drive strength according to the PCB. It should be set according to RDIV field
in MPDDRC I/O Calibration Register
// DS Write-only OP<3:0>
// 0000B: reserved
// 0001B: 34.3-ohm typical
// 0010B: 40-ohm typical (default)
// 0011B: 48-ohm typical
// 0100B: 60-ohm typical
// 0101B: reserved for 68.6-ohm typical
// 0110B: 80-ohm typical
// 0111B: 120-ohm typical (optional)
// All others: reserved
MPDDRC->MPDDRC_LPDDR2_LPR|=MPDDRC_LPDDR2_LPR_DS(0x3);
//////////////////////////MPDDRC Timing Parameter
MPDDRC->MPDDRC_TPR0
//////////////////////////
= \
MPDDRC_TPR0_TRAS(psst_ddr2.t_tras)
| /*03-TRAS tRAS Row active time*/
MPDDRC_TPR0_TRCD(psst_ddr2.t_trcd)
| /*04 -TRC tRCD RAS-to-CAS delay*/
MPDDRC_TPR0_TWR(psst_ddr2.t_twr)
| /*05 -TWR tWR WRITE recovery time */
MPDDRC_TPR0_TRC(psst_ddr2.t_trc)
\
\
\
|/*06 -TRC tRC ACTI-to-ACTIVT command period*/
MPDDRC_TPR0_TRP(psst_ddr2.t_trp) |/*07 -TRP tRPpb
Row precharge time
*/
\
\
MPDDRC_TPR0_TRRD(psst_ddr2.t_trrd) |/*08 -TRRD tRRD Active bank a to active bank b*/
\
MPDDRC_TPR0_TWTR(psst_ddr2.t_twtr) | /*09 -TWTR-tWTR Internal WRITE-to-READcommand delay*/
MPDDRC_TPR0_TMRD(psst_ddr2.t_tmrd)/*10 -TMRD-tMRD
MPDDRC->MPDDRC_TPR1
=
\
MPDDRC_TPR1_TRFC(psst_ddr2.t_trfc)
|/*11 -TRFC tRFCab Refresh cycle time
MPDDRC_TPR1_TXSNR(psst_ddr2.t_txsnr) | /*12 -TXSNR
MPDDRC_TPR1_TXSRD(psst_ddr2.t_txsrd)
=
*/ \
SELF REFRESH exit to next valid delay */\
| /*13-TXSRD Exit Self Refresh*/\
MPDDRC_TPR1_TXP(psst_ddr2.t_txp) /*14 -TXP-tXP Exit power-down */
MPDDRC->MPDDRC_TPR2
\
*/;
;
\
MPDDRC_TPR2_TXARD(psst_ddr2.t_txard) |/*15 TXARD-txARD
*/ \
MPDDRC_TPR2_TXARDS(psst_ddr2.t_tards) |/*16 TXARDS-txARDs */ \
MPDDRC_TPR2_TRPA(psst_ddr2.t_trpa)
|/*17 TRPA-tRPpab Row precharge time (all banks)
MPDDRC_TPR2_TRTP(psst_ddr2.t_trtp) |/*18 TRTP-tRTP */
*/
\
MPDDRC_TPR2_TFAW(psst_ddr2.t_tfaw) /*19TFAW--tFAW */;
MPDDRC->MPDDRC_LPR= 0x00000000; // Set low power register to normal mode
/****************************************************************************************/
/****************************************************************************************
// Initialization Step 3
// An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
28
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\
// command into the Mode Register, the application must set the MODE (MDDRC Command
// Mode) field to 1 in the Mode Register (see Section 8.1 on page 32). Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, clocks which drive Low-power DDR2-SDRAM devices are enabled.
// A minimum pause of 100 ns must be observed to precede any signal toggle.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_NOP_CMD;// NOP to ENABLE CLOCK output
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 100 ns)
/****************************************************************************************
***************************************************************************************
// Initialization Step 4
// An NOP command is issued to the Low-power DDR2-SDRAM. Program the NOP
// command into the Mode Register, the application must set MODE to 1 in the Mode
// Register (see Section 8.1 on page 32). Perform a write access to any Low-power
// DDR2-SDRAM address to acknowledge this command. Now, CKE is driven high.
// A minimum pause of 200 ìs must be satisfied before Reset Command.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_NOP_CMD;// NOP to drive CKE high
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 200 us)
/****************************************************************************************
****************************************************************************************
// Initialization Step 5
// A reset command is issued to the Low-power DDR2-SDRAM. Program
// LPDDR2_CMD in the MODE (MDDRC Command Mode) and MRS (Mode Register
// Select LPDDR2) field of the Mode Register, the application must set MODE to 7 and
// MRS to 63. (see Section 8.1 on page 32). Perform a write access to any Low-power
// DDR2-SDRAM address to acknowledge this command. Now, the reset command is issued.
// A minimum pause of 1 ìs must be satisfied before any commands.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_MR=MPDDRC_MR_MRS( 0x3F)| MPDDRC_MR_MODE_LPDDR2_CMD;/// Reset command. MODE =
0x7 and MRS = 0x3F
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
/***************************************************************************************
***************************************************************************************
// Initialization Step 6
// A Mode Register Read command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 0. (see Section 8.1 on
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29
// page 32). Perform a write access to any Low-power DDR2-SDRAM address to
// acknowledge this command. Now, the Mode Register Read command is issued.
// A minimum pause of 10 ìs must be satisfied before any commands.
****************************************************************************************
****************************************************************************************/
// Mode Register Read
command. MODE = 0x7 and MRS = 0x00
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x00);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
/****************************************************************************************
****************************************************************************************
// Initialization Step 7
A calibration command is issued to the Low-power DDR2-SDRAM. Program the type
of calibration into the Configuration Register, ZQ field, RESET value (see Section 8.3
”MPDDRC Configuration Register” on page 37). In the Mode Register, program the
MODE field to LPDDR2_CMD value, and the MRS field; the application must set
MODE to 7 and MRS to 10 (see Section 8.1 ”MPDDRC Mode Register” on page 34).
Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
this command. Now, the ZQ Calibration command is issued. Program the type of calibration
into the Configuration Register, ZQ field,
****************************************************************************************
***************************************************************************************/
MPDDRC->MPDDRC_CR&=~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR|=
// Mode Register Read
MPDDRC->MPDDRC_MR=
MPDDRC_CR_ZQ_RESET;
command. MODE = 0x7 and MRS = 0x0A
MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x0A);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Delay loop (at least 1 us)
MPDDRC->MPDDRC_CR&=~MPDDRC_CR_ZQ_Msk;
MPDDRC->MPDDRC_CR|=
MPDDRC_CR_ZQ_SHORT;
/****************************************************************************************
****************************************************************************************
// Initialization Step 8
// A Mode Register Write command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
// application must set MODE to 7 and must set MRS field to 0.5 (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular burst length. Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, the Mode Register Write command is issued.
****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 parameters MODE = 0x7 and MRS = 0x01
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x01);
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*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 9
// Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field in the Mode Register, the
// application must set MODE to 7 and must set MRS field to 2. (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular CAS latency. Perform a
// write access to any Low-power DDR2-SDRAM address to acknowledge this command.
// Now, the Mode Register Write command is issued.
****************************************************************************************
***************************************************************************************/
// Programm LPDDR2 CAS MODE = 0x7 and MRS = 0x02
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x02);
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 10
// A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 3. (see Section 8.1 on
// page 32). The Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular Drive Strength and Slew
// Rate. Perform a write access to any Low-power DDR2-SDRAM address to acknowledge
// this command. Now, the Mode Register Write command is issued.
****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 DS MODE = 0x7 and MRS = 0x03
MPDDRC->MPDDRC_MR= MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x03);//0x00000307;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 11
// A Mode Register Write Command is issued to the Low-power DDR2-SDRAM. Program
// LPPDR2_CMD in the MODE and MRS field of the Mode Register, the
// application must set MODE to 7 and must set MRS field to 16. (see Section 8.1 on
// page 32). Mode Register Write command cycle is issued to program the parameters
// of the Low-power DDR2-SDRAM devices, in particular Partial Array Self Refresh
// (PASR). Perform a write access to any Low-power DDR2-SDRAM address to
// acknowledge this command. Now, the Mode Register Write command is issued.
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31
****************************************************************************************
****************************************************************************************/
// Programm LPDDR2 PASR MODE = 0x7 and MRS = 0x10
MPDDRC->MPDDRC_MR=MPDDRC_MR_MODE_LPDDR2_CMD |MPDDRC_MR_MRS( 0x10);// 0x00001007;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Access to memory
Wait (0xFFFF);// Add a delay loop (not is the programmer datasheet)
/****************************************************************************************
****************************************************************************************
// Initialization Step 12
// Write the refresh rate into the COUNT field in the Refresh Timer register (see page
// 33). (Refresh rate = delay between refresh cycles). The Low-power DDR2-SDRAM
// device requires a refresh every 7.81 ìs. With a 100 MHz frequency, the refresh timer
// count register must to be set with (7.81/100 MHz) = 781 i.e. 0x030d.
****************************************************************************************
****************************************************************************************/
MPDDRC->MPDDRC_RTR&=~MPDDRC_RTR_COUNT_Msk;
MPDDRC->MPDDRC_RTR |=MPDDRC_RTR_COUNT(psst_ddr2.t_refresh);
//MPDDRC->MPDDRC_RTR|= MPDDRC_RTR_ADJ_REF ;// MR4 READ enabled
MPDDRC->MPDDRC_MR= 0x00000000;// Set Normal mode
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Perform
Wait (0xFFFF);
// Launch short ZQ calibration
MPDDRC->MPDDRC_CR&= ~
(MPDDRC_CR_ZQ_Msk);// Enable short calibration in the CR
MPDDRC->MPDDRC_CR |= (MPDDRC_CR_ZQ_SHORT);
MPDDRC->MPDDRC_CR |= MPDDRC_CR_DLL_RESET_ENABLED;
*(unsigned int *)DDR_CS_ADDR= 0x00000000;// Perform
// Calculate ZQS: search for tZQCS in the memory datasheet => tZQCS = 180 ns
MPDDRC->MPDDRC_LPDDR2_TIM_CAL =
MPDDRC_LPDDR2_TIM_CAL_ZQCS(psst_ddr2.t_tZQCS);
}
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Revision History
Table 7-2.
Implementation of SDRAM on SAMA5D2x Devices Revision History
Doc. Rev.
Date
Changes
44044A
07-Sep-15
First issue
Implementation of SDRAM on SAMA5D2x Devices [APPLICATION NOTE]
Atmel-44044A-ATARM-Implementation-of-SDRAM-on-SAMA5D2x-Devices-ApplicationNote_07-Sep-15
33
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